Mapping table double updating implementation method and device for DRAM-less solid state disk

Abstract

This application relates to a method, apparatus, computer device, and storage medium for implementing dual updates of the mapping table in a DRAM-less solid-state drive (SSD). The method includes: acquiring a write request and allocating a physical address for the write request; determining whether the mapping table corresponding to the write request has been loaded; if loaded, the newly generated mapping is recorded in both the temporary mapping cache and the mapping table, but the mapping table is not marked as dirty; if not loaded, the mapping table is recorded in a temporary mapping cache and it is determined whether the temporary mapping cache is full; if the temporary mapping cache is full, temporary mapping cache merging is triggered before writing data to the NAND flash; if the temporary mapping cache is not full, data is directly written to the NAND flash; acquiring a read request and determining whether the mapping table corresponding to the read request has been loaded; if not loaded, a mapping table fragment is loaded from the NAND flash and the temporary mapping cache is checked for emptiness. This invention improves the wide-range random mixed read / write performance of DRAM-less SSDs.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, and in particular to a method, apparatus, computer device, and storage medium for implementing dual updates of the mapping table in a DRAM-less solid-state drive. Background Technology

[0002] DRAM-less SSDs have a relatively small cacheable mapping table. When the dirty mapping table cache exceeds a threshold, dirty mappings need to be written to NAND to ensure that the system has enough clean mapping cache available. For large-scale random write scenarios, the mapping table that needs to be accessed cannot be fully loaded into RAM. In cases where the mapping table is not loaded, the newly generated mappings during the write process are usually temporarily cached. Then, the mapping fragments are loaded from NAND in batches and merged with the temporary mapping cache before being written back to NAND to reduce the amount of mapping table writes and improve the performance of large-scale random writes.

[0003] However, in existing technologies, for large-scale random read and write mixed scenarios, read commands will prematurely trigger the merging of mapping tables and generate dirty mapping tables, thereby causing the strategy of reducing the amount of mapping table writes by batch merging mappings and writing back to NAND to fail. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, computer device, and storage medium for implementing dual updates of the mapping table of a DRAM-less solid-state drive to address the aforementioned technical problems.

[0005] A method for implementing dual update of the mapping table of a DRAM-less solid-state drive, the method comprising: Obtain a write request and allocate a physical address for the write request; determine whether the mapping table corresponding to the write request has been loaded. If the mapping has been loaded, the newly generated mapping will be recorded in both the temporary mapping cache and the mapping table, but the mapping table will not be marked as dirty. If the mapping has not been loaded, the mapping table will be recorded in the temporary mapping cache. Then it is determined whether the temporary mapping cache is full. If the temporary mapping cache is full, the temporary mapping cache is merged and the data is written to NAND. If the temporary mapping cache is not full, the data is written to NAND directly. Obtain the read request and determine whether the mapping table corresponding to the read request has been loaded. If not loaded, load the mapping table fragments from NAND and check if the temporary mapping cache is empty; If the temporary mapping cache is empty, iterate through the temporary mappings, merge the temporary mappings that belong to the current mapping table shard, and do not delete the temporary mappings or mark the mapping shard as dirty.

[0006] In one embodiment, after the step of traversing the temporary maps if the temporary mapping cache is empty, merging the temporary maps belonging to the current mapping table shard, without deleting the temporary maps or marking the mapping shard as dirty, the method further includes: Query the mapping table to obtain the physical address and read the data from the NAND.

[0007] In one embodiment, the temporary mapping cache merging step triggered when the temporary mapping cache is full includes: Iterate through all temporary mappings and determine whether the corresponding mapping fragment has been loaded. If the corresponding mapping fragment has been loaded, mark the mapping fragment as dirty and delete all temporary mappings corresponding to the mapping fragment. If the corresponding mapping fragment is not loaded, load the corresponding mapping fragment from NAND, merge all temporary mappings belonging to the mapping fragment into the mapping fragment, delete the temporary mappings of the mapping fragment after the merging is complete, and mark the mapping fragment as dirty.

[0008] In one embodiment, the method further includes: If all mapped fragments are dirty, the dirty mapped fragments need to be stored in NAND first to release the clean mapped fragments.

[0009] A dual update implementation apparatus for the mapping table of a DRAM-less solid-state drive, the apparatus comprising: A write request processing module is used to obtain write requests and allocate physical addresses for the write requests, and determine whether the mapping table corresponding to the write request has been loaded; if it has been loaded, the newly generated mapping will be recorded in the temporary mapping cache and updated in the mapping table, but the mapping table will not be marked as dirty; if it has not been loaded, the mapping table is recorded in the temporary mapping cache; then it is determined whether the temporary mapping cache is full; if the temporary mapping cache is full, the temporary mapping cache is merged and the data is written to NAND; if the temporary mapping cache is not full, the data is directly written to NAND. The read request processing module is used to obtain read requests and determine whether the mapping table corresponding to the read request has been loaded. If it has not been loaded, the module loads the mapping table shard from NAND and checks whether the temporary mapping cache is empty. If the temporary mapping cache is not empty, the module traverses the temporary mappings and merges the temporary mappings belonging to the current mapping table shard, without deleting the temporary mappings or marking the mapping shard as dirty.

[0010] In one embodiment, the read request processing module is further configured to: Query the mapping table to obtain the physical address and read the data from the NAND.

[0011] In one embodiment, the apparatus further includes a mapping merging module, which is configured to trigger temporary mapping cache merging when the temporary mapping cache is full, including: Iterate through all temporary mappings and determine whether the corresponding mapping fragment has been loaded. If the corresponding mapping fragment has been loaded, mark the mapping fragment as dirty and delete all temporary mappings corresponding to the mapping fragment. If the corresponding mapping fragment is not loaded, load the corresponding mapping fragment from NAND, merge all temporary mappings belonging to the mapping fragment into the mapping fragment, delete the temporary mappings of the mapping fragment after the merging is complete, and mark the mapping fragment as dirty.

[0012] In one embodiment, the apparatus further includes a mapping release module, the mapping release module being used for: If all mapped fragments are dirty, the dirty mapped fragments need to be stored in NAND first to release the clean mapped fragments.

[0013] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.

[0014] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.

[0015] The aforementioned method, apparatus, computer device, and storage medium for dual-updating the mapping table of a DRAM-less solid-state drive effectively avoids the situation where the mapping table is prematurely merged with temporary mappings to generate a dirty mapping table in mixed read / write scenarios. For scenarios where the mapping table is already loaded, newly generated mappings are recorded in both the temporary cache and the mapping table, but the mapping table is not marked as dirty. Only when the temporary mapping cache is full is a complete mapping table merge operation performed. Dirty mapping table fragments are generated during this merge process, and all temporary mappings are deleted after the merge is complete. This significantly reduces the storage of the mapping table and greatly improves the performance of large-scale random read / write mixed operations. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a method for implementing dual updates of the mapping table of a DRAM-less solid-state drive in one embodiment. Figure 2 This is a flowchart illustrating a large-scale random write processing procedure in one embodiment. Figure 3 This is a flowchart illustrating a large-scale random read processing procedure in one embodiment. Figure 4 This is a flowchart illustrating the temporary mapping merging process in one embodiment; Figure 5 This is a structural block diagram of a dual update implementation device for the mapping table of a DRAM-less solid-state drive in one embodiment; Figure 6 This is a structural block diagram of a dual update implementation device for the mapping table of a DRAM-less solid-state drive in another embodiment; Figure 7 This is a structural block diagram of a dual update implementation device for the mapping table of a DRAM-less solid-state drive in another embodiment; Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] Currently, DRAM-less SSDs can cache a relatively small mapping table. For large-scale random write scenarios, not all mapping tables that need to be accessed can be loaded into RAM. In cases where the mapping table is not loaded, the newly generated mapping during the write process is usually cached temporarily. Then, the mapping table fragments are loaded from NAND in batches and merged with the temporary mapping before being written back to NAND to reduce the amount of mapping table writing and improve the performance of large-scale random writes.

[0019] However, in scenarios involving a wide range of random reads and writes, read commands may prematurely trigger the merging of temporary mappings and generate dirty mapping table fragments, causing the strategy of reducing the amount of mapping table writes by batch merging mapping fragments and writing back to NAND to reduce the amount of mapping table writes to fail.

[0020] Based on this, the present invention proposes a dual update implementation method for the mapping table of DRAM-less solid-state drives, which aims to improve the performance of DRAM-less SSDs in a wide range of random mixed read and write operations.

[0021] In one embodiment, such as Figure 1 As shown, a method for implementing dual update of the mapping table of a DRAM-less solid-state drive is provided, the method including: Step 102: Obtain the write request and allocate a physical address for the write request, and determine whether the mapping table corresponding to the write request has been loaded; Step 104: If the mapping has been loaded, the newly generated mapping will be recorded in the temporary mapping cache and updated in the mapping table, but the mapping table will not be marked as dirty. If the mapping has not been loaded, the mapping table will be recorded in the temporary mapping cache and it will be determined whether the temporary mapping cache is full. Step 106: If the temporary mapping cache is full, trigger the temporary mapping cache merging and then write the data to NAND; if the temporary mapping cache is not full, write the data directly to NAND. Step 108: Obtain the read request and determine whether the mapping table corresponding to the read request has been loaded; Step 110: If not loaded, load the mapping table fragment from NAND and check if the temporary mapping cache is empty; Step 112: If the temporary mapping cache is empty, traverse the temporary mappings and merge the temporary mappings that belong to the current mapping table shard. At the same time, do not delete the temporary mappings or mark the mapping shard as dirty.

[0022] In this embodiment, a dual update implementation method for the mapping table of a DRAM-less solid-state drive is proposed. In a large-scale random mixed read and write scenario, for a scenario where the mapping table has been loaded, the newly generated mapping will be recorded in the mapping temporary cache and updated in the mapping table, but the mapping table will not be marked as dirty.

[0023] For scenarios that require loading a mapping table, after the mapping table is loaded and merged with the temporary cache, the temporary mapping cache is not deleted, nor is the merged mapping shard marked as dirty.

[0024] Furthermore, for mapping table shards that are merged with temporary mappings in advance, since a copy of the mapping information is also stored in the temporary mapping, these mapping table shards can remain in a clean state and can be directly reallocated and used without writing to NAND.

[0025] A full map merge operation is only performed when the temporary map cache is full. During this merge, dirty map table fragments are generated and written to the NAND flash memory. After the merge is complete, all temporary maps are deleted. In scenarios with a wide range of random reads and writes, the frequent writing of the map table to the NAND flash memory due to excessive dirty map tables will not occur before the temporary map cache is full, thus significantly improving the performance of mixed random reads and writes.

[0026] Specifically, the method includes a large-scale random write processing flow and a large-scale random read processing flow: refer to Figure 2 The flowchart shown illustrates the large-scale random write processing procedure, which includes the following steps: Step 2.1: Allocate physical addresses.

[0027] Step 2.2: Check if the mapped fragment corresponding to the logical address is loaded. If not, go to step 2.4.

[0028] Step 2.3: Update the mapping table (without marking it as dirty).

[0029] Step 2.4: Record the mapping to the temporary mapping cache.

[0030] Step 2.5: If the temporary mapping cache is full, trigger the temporary mapping cache merging.

[0031] Step 2.6: Write the data into NAND.

[0032] In one embodiment, after the step of traversing the temporary mappings if the temporary mapping cache is empty, merging the temporary mappings belonging to the current mapping table fragment, without deleting the temporary mappings or marking the mapping fragment as dirty, the method further includes: querying the mapping table to obtain the physical address and reading data from the NAND.

[0033] Specifically, refer to Figure 3 The flowchart shown illustrates the large-scale random read processing procedure, which includes the following steps: Step 3.1: Check if the mapped fragment corresponding to the logical address is loaded. If it is loaded, goto step 3.5.

[0034] Step 3.2: Load the mapped fragments from NAND.

[0035] Step 3.3: Check if the temporary mapping cache is empty. If it is empty, goto step 3.5.

[0036] Step 3.4: Merge temporary mappings belonging to this mapping fragment (but do not delete the temporary mappings or mark the mapping fragment as dirty).

[0037] Step 3.5: Query the mapping table to obtain the NAND address.

[0038] Step 3.6: Read data from NAND.

[0039] In the above embodiments, the situation where the mapping table is prematurely merged with temporary mappings to generate a dirty mapping table in mixed read / write scenarios can be effectively avoided. For scenarios where the mapping table is already loaded, newly generated mappings are recorded in both the temporary cache and updated in the mapping table, but the mapping table is not marked as dirty. Only when the temporary mapping cache is full is a complete mapping table merge operation performed. Dirty mapping table fragments are generated during this merge process, and all temporary mappings are deleted after the merge is complete. This significantly reduces the storage of the mapping table and greatly improves the performance of large-scale random read / write mixed scenarios.

[0040] In one embodiment, a method for implementing dual update of the mapping table of a DRAM-less solid-state drive is provided, the method further comprising: Iterate through all temporary mappings and determine whether the corresponding mapping fragment has been loaded. If the corresponding mapping fragment has been loaded, mark the mapping fragment as dirty and delete all temporary mappings corresponding to the mapping fragment. If the corresponding mapping slice is not loaded, load the corresponding mapping slice from NAND, merge all temporary mappings belonging to the mapping slice into the mapping slice, delete the temporary mappings of the mapping slice after the merging is completed, and mark the mapping slice as dirty. If all mapped fragments are dirty, the dirty mapped fragments need to be stored in NAND first to release the clean mapped fragments.

[0041] For specific details, please refer to Figure 4 The flowchart shown below illustrates the temporary mapping merging process, which includes the following implementation steps: Traverse all temporary mappings. If the corresponding mapping fragment has been loaded, mark the mapping fragment as dirty and delete all temporary mappings corresponding to that mapping fragment. Otherwise, load the corresponding mapping fragment, merge it with all temporary mappings belonging to it, delete the corresponding temporary mapping, and mark the mapping fragment as dirty.

[0042] If all mapped shards are dirty during the process, the dirty mappings need to be saved to NAND first, and the clean mapped shards need to be released.

[0043] In this embodiment, a complete mapping table merge operation is only performed when the temporary mapping cache is full. Dirty mapping table fragments are generated during this merge process, and all temporary mappings are deleted after the merge is completed, thereby improving the wide range of random mixed read and write performance of DRAM-less SSD.

[0044] It should be understood that, although Figures 1-4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0045] In one embodiment, such as Figure 5As shown, a dual update implementation apparatus 500 for the mapping table of a DRAM-less solid-state drive is provided, the apparatus comprising: The write request processing module 501 is used to obtain write requests and allocate physical addresses for the write requests, and determine whether the mapping table corresponding to the write request has been loaded; if it has been loaded, the newly generated mapping will be recorded in the temporary mapping cache and updated in the mapping table, but the mapping table will not be marked as dirty; if it has not been loaded, the mapping table is recorded in the temporary mapping cache and it is determined whether the temporary mapping cache is full; if the temporary mapping cache is full, the temporary mapping cache is merged and the data is written to NAND; if the temporary mapping cache is not full, the data is directly written to NAND. The read request processing module 502 is used to obtain a read request and determine whether the mapping table corresponding to the read request has been loaded. If it has not been loaded, the module loads the mapping table shard from NAND and checks whether the temporary mapping cache is empty. If the temporary mapping cache is empty, the module traverses the temporary mappings and merges the temporary mappings belonging to the current mapping table shard, without deleting the temporary mappings or marking the mapping shard as dirty.

[0046] In one embodiment, the read request processing module 502 is further configured to: Query the mapping table to obtain the physical address and read the data from the NAND.

[0047] In one embodiment, such as Figure 6 As shown, a dual update implementation device 500 for the mapping table of a DRAM-less solid-state drive is provided. This device further includes a mapping merging module 503, used for: Iterate through all temporary mappings and determine whether the corresponding mapping fragment has been loaded. If the corresponding mapping fragment has been loaded, mark the mapping fragment as dirty and delete all temporary mappings corresponding to the mapping fragment. If the corresponding mapping fragment is not loaded, load the corresponding mapping fragment from NAND, merge all temporary mappings belonging to the mapping fragment into the mapping fragment, delete the temporary mappings of the mapping fragment after the merging is complete, and mark the mapping fragment as dirty.

[0048] In one embodiment, such as Figure 7 As shown, a dual update implementation device 500 for the mapping table of a DRAM-less solid-state drive is provided. This device further includes a mapping release module 504, used for: If all mapped fragments are dirty, the dirty mapped fragments need to be stored in NAND first to release the clean mapped fragments.

[0049] For specific limitations on the implementation device of dual update of mapping table for DRAM-less solid-state drives, please refer to the limitations on the implementation method of dual update of mapping table for DRAM-less solid-state drives above, which will not be repeated here.

[0050] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 8 As shown, the computer device includes a processor, memory, and a network interface connected via a device bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores operating devices, computer programs, and a database. The internal memory provides an environment for the operation of the operating devices and computer programs stored in the non-volatile storage medium. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a dual-update mapping table implementation method for a DRAM-less solid-state drive.

[0051] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0052] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.

[0053] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.

[0054] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0055] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for implementing dual update of the mapping table of a DRAM-less solid-state drive, the method comprising: Obtain a write request and allocate a physical address for the write request; determine whether the mapping table corresponding to the write request has been loaded. If the mapping has been loaded, the newly generated mapping will be recorded in both the temporary mapping cache and the mapping table, but the mapping table will not be marked as dirty. If the mapping has not been loaded, the mapping table will be recorded in the temporary mapping cache. Then it is determined whether the temporary mapping cache is full. If the temporary mapping cache is full, the temporary mapping cache is merged and the data is written to NAND. If the temporary mapping cache is not full, the data is written to NAND directly. Obtain the read request and determine whether the mapping table corresponding to the read request has been loaded. If not loaded, load the mapping table fragments from NAND and check if the temporary mapping cache is empty; If the temporary mapping cache is empty, iterate through the temporary mappings, merge the temporary mappings that belong to the current mapping table shard, and do not delete the temporary mappings or mark the mapping shard as dirty.

2. The mapping table double update implementation method of DRAM-less solid state disk according to claim 1, characterized in that, After the step of iterating through the temporary mappings if the temporary mapping cache is empty, merging the temporary mappings belonging to the current mapping table shard, without deleting the temporary mappings or marking the mapping shard as dirty, the following is also included: Query the mapping table to obtain the physical address and read the data from the NAND.

3. The mapping table double update implementation method of DRAM-less solid state disk according to claim 2, characterized in that, The temporary mapping cache merging step triggered when the temporary mapping cache is full includes: Iterate through all temporary mappings and determine whether the corresponding mapping fragment has been loaded. If the corresponding mapping fragment has been loaded, mark the mapping fragment as dirty and delete all temporary mappings corresponding to the mapping fragment. If the corresponding mapping fragment is not loaded, load the corresponding mapping fragment from NAND, merge all temporary mappings belonging to the mapping fragment into the mapping fragment, delete the temporary mappings of the mapping fragment after the merging is complete, and mark the mapping fragment as dirty.

4. The mapping table double update implementation method of DRAM-less solid state disk according to claim 3, characterized in that, The method further includes: If all mapped fragments are dirty, the dirty mapped fragments need to be stored in NAND first to release the clean mapped fragments.

5. A mapping table double update implementation device of a DRAM-less solid state disk, characterized in that, The device includes: A write request processing module is used to obtain write requests and allocate physical addresses for the write requests, and determine whether the mapping table corresponding to the write request has been loaded; if it has been loaded, the newly generated mapping will be recorded in the temporary mapping cache and updated in the mapping table, but the mapping table will not be marked as dirty; if it has not been loaded, the mapping table is recorded in the temporary mapping cache; then it is determined whether the temporary mapping cache is full; if the temporary mapping cache is full, the temporary mapping cache is merged and the data is written to NAND; if the temporary mapping cache is not full, the data is directly written to NAND. The read request processing module is used to obtain read requests and determine whether the mapping table corresponding to the read request has been loaded. If it has not been loaded, the module loads the mapping table shard from NAND and checks whether the temporary mapping cache is empty. If the temporary mapping cache is not empty, the module traverses the temporary mappings and merges the temporary mappings belonging to the current mapping table shard, without deleting the temporary mappings or marking the mapping shard as dirty.

6. The apparatus for implementing dual update of the mapping table of a DRAM-less solid-state drive according to claim 5, characterized in that, The read request processing module is also used for: Query the mapping table to obtain the physical address and read the data from the NAND.

7. The mapping table dual update implementation apparatus of a DRAM-less solid state disk according to claim 6, wherein, The apparatus further includes a mapping merging module, which is used to trigger temporary mapping cache merging when the temporary mapping cache is full, including: Iterate through all temporary mappings and determine whether the corresponding mapping fragment has been loaded. If the corresponding mapping fragment has been loaded, mark the mapping fragment as dirty and delete all temporary mappings corresponding to the mapping fragment. If the corresponding mapping fragment is not loaded, load the corresponding mapping fragment from NAND, merge all temporary mappings belonging to the mapping fragment into the mapping fragment, delete the temporary mappings of the mapping fragment after the merging is complete, and mark the mapping fragment as dirty.

8. The mapping table dual update implementation apparatus of a DRAM-less solid state disk according to claim 7, wherein, The device further includes a mapping release module, which is used for: If all mapped fragments are dirty, the dirty mapped fragments need to be stored in NAND first to release the clean mapped fragments.

9. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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