Communication circuit, mainboard and server

Abstract

This disclosure relates to a communication circuit, a motherboard, and a server. The communication circuit includes an interconnect fork mode determination module, at least one central processing unit (CPU), at least one first connector, and at least one second connector. The interconnect fork mode determination module is used to: obtain a first signal from a network interface card (NIC), obtain a second signal from the second connector, determine, based on the first and second signals, a PCIe interface on the CPU that can communicate with the NIC, and a communication path between the PCIe interface and the NIC; determine a target fork mode from the PCIe fork modes supported by the NIC; output a third signal indicating the target fork mode to the NIC; and output a fourth signal indicating the target fork mode to the CPU. When the communication circuit of this embodiment is installed on the motherboard, the PCIe fork mode of the motherboard can be flexibly adjusted, enabling the motherboard to be compatible with more types of PCIe fork modes, improving the motherboard's reusability, and reducing server costs.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, and in particular to a communication circuit, motherboard, and server. Background Technology

[0002] With the development of the server industry, more and more servers are using network interface cards (NICs) from the Open Compute Project (OCP). Existing OCP NIC cards support various combinations of high-speed peripheral component interconnect (PCIe) branching methods, such as supporting PCIe 1x8, PCIe 1x16, PCIe 2x8, PCIe 4x4, and so on.

[0003] The OCP NIC card communicates with the server's motherboard via PCIe and receives PCIe signals from the central processing unit (CPU) on the motherboard. Existing motherboards typically lack flexibility in supporting various PCIe branching methods. For example, if the motherboard uses PCIe 1x16 but the OCP NIC card only supports PCIe 1x8, 1x8 PCIe signals on the OCP NIC card side will be wasted. Conversely, if the motherboard uses PCIe 1x8 or PCIe 2x8 but the OCP NIC card only supports PCIe 1x16, the actual effective PCIe signals remain at 1x8, failing to utilize the OCP NIC card's maximum speed. To optimize server functionality, current technologies often require custom motherboards based on the PCIe branching methods supported by the OCP NIC card, increasing server costs.

[0004] Therefore, how to make motherboards flexibly compatible with various PCIe fork methods, improve motherboard reuse rate, and reduce server costs has become a research hotspot in this field. Summary of the Invention

[0005] This disclosure proposes a communication circuit, a motherboard, and a server. When the communication circuit of the embodiments of this disclosure is set on the motherboard, the PCIe branching mode of the motherboard can be flexibly adjusted, so that the motherboard can be compatible with more types of PCIe branching modes, improve the reusability of the motherboard, and reduce the cost of the server.

[0006] According to one aspect of this disclosure, a communication circuit is provided, including an interconnect fork mode determination module, at least one central processing unit (CPU), at least one first connector, and at least one second connector. The interconnect fork mode determination module and the second connector communicate with a network interface card (NIC) via a third connector. The first connector is connected to a high-speed peripheral component interconnect (PSI) interface of the corresponding CPU. When the first connector is connected to the second connector via a cable and the cable is in place, the first connector communicates with the second connector via the cable. The interconnect fork mode determination module is configured to: acquire a first signal from the NIC, the first signal indicating the presence of the NIC and the high-speed peripheral component interconnect (PSI) supported by the NIC. A high-speed peripheral component interconnect (PSI) fork mode is defined; a second signal is obtained from the second connector, the second signal indicating a high-speed PSI interface on the central processing unit that can communicate with the second connector; based on the first signal and the second signal, a high-speed PSI interface on the central processing unit that can communicate with the network card, and a communication path between the high-speed PSI interface and the network card are determined; based on the first signal and the communication path, a target fork mode is determined from the high-speed PSI fork modes supported by the network card, a third signal indicating the target fork mode is output to the network card, and a fourth signal indicating the target fork mode is output to the central processing unit.

[0007] In one possible implementation, determining the high-speed peripheral component interconnect interface on the central processing unit that can communicate with the network card based on the first signal and the second signal includes: when the first signal indicates that the network card is in place, determining the high-speed peripheral component interconnect interface on the central processing unit corresponding to the second signal as the high-speed peripheral component interconnect interface that can communicate with the network card.

[0008] In one possible implementation, determining the high-speed peripheral component interconnect (PSI) interfaces on the central processing unit (CPU) that can communicate with the network interface card (NIC), and the communication path between the PSI interfaces and the NIC, based on the first signal and the second signal, includes: for each PSI interface on the CPU that can communicate with the NIC, determining the communication path between each PSI interface and the NIC based on a first connector connected to each PSI interface, a second connector that receives a second signal corresponding to each PSI interface, and the third connector.

[0009] In one possible implementation, the first connector is connected to the power supply voltage via pull-up resistors corresponding to each high-speed peripheral component interconnect (PSI) interface, and connected to ground via pull-down resistors corresponding to each PSI interface. The pull-up and pull-down resistors for any two PSI interfaces are different. When the PSI interfaces on the central processing unit are connected to the first connector, the signal levels transmitted to the first connector through any two PSI interfaces are different. On the first connector, the initial state of the fifth signal is high. On the second connector, the fifth signal remains low. When the fifth signal on the first connector changes to a low state, it indicates that the cable connecting the first and second connectors is in place. When the fifth signal on the first connector remains high, it indicates that the cable connecting the first and second connectors is not in place.

[0010] In one possible implementation, the second signal includes an identifier of a high-speed peripheral component interconnect (HS-IP) interface, an identifier of each H-IP interface on each central processing unit, and a correspondence between the signal levels transmitted by each H-IP interface to a corresponding first connector, stored in the first connector. The first connector is configured to query the stored correspondence based on the received signal level from the H-IP interface, and generate the second signal based on the queried identifier. When the first connector is connected to the second connector via a cable and the cable is in place, the second signal is sent to the second connector.

[0011] In one possible implementation, the interconnect fork mode determination module is further configured to: when the first signal indicates that the network card is not in place, set the high-speed peripheral component interconnect interface on the central processing unit corresponding to the second signal to a power-saving state.

[0012] In one possible implementation, the interconnection branching mode determination module is further configured to: obtain the fifth signal from the first connector, the fifth signal indicating whether the cable connected to the first connector is in place; when the cable connected to the first connector is not in place, set the high-speed peripheral component interconnection interface on the central processing unit corresponding to the first connector to the power-saving state.

[0013] In one possible implementation, determining the target fork mode from the high-speed peripheral component interconnection fork modes supported by the network card based on the first signal and the communication path includes: determining the target fork mode that matches the user's needs from the high-speed peripheral component interconnection fork modes supported by the network card based on the first signal, the communication path, and the user's needs.

[0014] According to one aspect of this disclosure, a motherboard is provided, including the communication circuit described above.

[0015] According to one aspect of this disclosure, a server is provided, including the motherboard described above.

[0016] According to the communication circuit of this disclosure embodiment, an interconnect fork mode determination module, at least one central processing unit (CPU), at least one first connector, and at least one second connector are provided. The interconnect fork mode determination module and the second connector communicate with the network card (NIC) through a third connector. The first connector is connected to the high-speed peripheral component interconnect interface (PSBI) of the corresponding CPU. When the first connector is connected to the second connector via a cable and the cable is in place, the first connector communicates with the second connector via the cable. The interconnect fork mode determination module obtains a first signal from the NIC and a second signal from the second connector. The first signal indicates the presence of the NIC, and the second signal indicates the high-speed PBI interconnect interface on the CPU that can communicate with the second connector. Therefore, based on the first and second signals, the high-speed PBI interconnect interface on the CPU that can communicate with the NIC, as well as the communication path between the high-speed PBI interconnect interface and the NIC, can be determined, thus clarifying the range of high-speed PBI interconnect fork modes that the motherboard can support. The first signal also indicates the high-speed PBI interconnect fork modes supported by the NIC. Therefore, based on the first signal and the communication path, the target fork mode is determined from the high-speed PBI interconnect fork modes supported by the NIC, thereby completing the selection of high-speed PBI interconnect fork modes that can be supported by both the motherboard and the NIC. The interconnection fork mode determination module outputs a third signal indicating the target fork mode to the network card and a fourth signal indicating the target fork mode to the central processing unit (CPU), thus configuring the high-speed peripheral component interconnection fork mode between the CPU and the network card. The placement of the first and second connectors allows for more possibilities in the communication path between the high-speed peripheral component interconnection interface on the CPU and the network card. Based on this, when the communication circuit of this embodiment is mounted on the motherboard, the high-speed peripheral component interconnection fork mode of the motherboard can be flexibly adjusted, enabling the motherboard to be compatible with more types of high-speed peripheral component interconnection fork modes, improving the motherboard's reusability, and reducing server costs.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0019] Figure 1 This illustrates an example of a PCIe forking method in the prior art.

[0020] Figure 2 This illustrates an example of a PCIe forking method in the prior art.

[0021] Figure 3 This illustrates an example of a PCIe forking method in the prior art.

[0022] Figure 4 Exemplary application scenarios of communication circuits according to embodiments of this disclosure are shown.

[0023] Figure 5 A schematic diagram showing the structure of a communication circuit 100 according to an embodiment of the present disclosure is provided.

[0024] Figure 6a An exemplary workflow of an interconnect fork determination module according to an embodiment of this disclosure is shown.

[0025] Figure 6b An exemplary workflow of an interconnect fork determination module according to an embodiment of this disclosure is shown.

[0026] Figure 7 A schematic diagram showing another structure of the communication circuit 100 according to an embodiment of the present disclosure is provided.

[0027] Figure 8 An exemplary connection method between a first connector and a resistor according to an embodiment of this disclosure is shown.

[0028] Figure 9 This diagram illustrates a high-speed peripheral component interconnection branching method configured according to an embodiment of the present disclosure on the motherboard side and the network card side.

[0029] Figure 10 This diagram illustrates a high-speed peripheral component interconnection branching method configured according to an embodiment of the present disclosure on the motherboard side and the network card side.

[0030] Figure 11 This diagram illustrates a high-speed peripheral component interconnection branching method configured according to an embodiment of the present disclosure on the motherboard side and the network card side.

[0031] Figure 12 This diagram illustrates a high-speed peripheral component interconnection branching method configured according to an embodiment of the present disclosure on the motherboard side and the network card side.

[0032] Figure 13 A block diagram of a server 1900 according to an embodiment of the present disclosure is shown. Detailed Implementation

[0033] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0034] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0035] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0036] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0037] Existing OCP NIC cards support various combinations of high-speed peripheral component interconnect express (PCIe) branching methods, such as supporting PCIe 1x8, PCIe 1x16, PCIe 2x8, PCIe 4x4, etc. Figures 1-3 Examples of existing PCIe forking methods are shown below.

[0038] like Figure 1 As shown, when the motherboard supports single host, the PCIe branching method can be PCIe 1x16. CPU0 acts as the host, and the motherboard and OCP NIC card are connected via a primary connector. One x16 PCIe signal generated by CPU0 is directly transmitted to the OCP NIC card through the primary connector.

[0039] like Figure 2As shown, when the motherboard supports single host, the PCIe branching method can be PCIe 2x8. CPU0 acts as the host, and the motherboard and OCP NIC card are connected via a primary connector. The two x8 PCIe signals generated by CPU0 are directly transmitted to the OCP NIC card through the primary connector.

[0040] like Figure 3 As shown, when the motherboard supports quad-host configuration, the PCIe branching method can be PCIe 4x4. CPU0 through CPU3 are all considered master hosts, and the motherboard and OCP NIC card are connected via a primary connector and a secondary connector. One x4 PCIe signal generated by CPU0 and one x4 PCIe signal generated by CPU1 are directly transmitted to the OCP NIC card through the primary connector, while one x4 PCIe signal generated by CPU2 and one x4 PCIe signal generated by CPU3 are directly transmitted to the OCP NIC card through the secondary connector.

[0041] Existing motherboards typically lack flexibility in supporting various PCIe fork configurations. For example, if a motherboard uses PCIe 1x16 but the OCP NIC card only supports PCIe 1x8, eight PCIe signals on the OCP NIC card side will be wasted. Conversely, if a motherboard uses PCIe 1x8 or PCIe 2x8 but the OCP NIC card only supports PCIe 1x16, the actual effective PCIe signal is still 1x8, failing to utilize the OCP NIC card's maximum speed. To optimize server functionality, current technologies often require custom motherboards based on the PCIe fork configurations supported by the OCP NIC card, increasing server costs.

[0042] In view of this, the present disclosure proposes a communication circuit, a motherboard, and a server. When the communication circuit of the embodiments of the present disclosure is set on the motherboard, the PCIe branching mode of the motherboard can be flexibly adjusted, so that the motherboard can be compatible with more types of PCIe branching modes, improve the reusability of the motherboard, and reduce the cost of the server.

[0043] Figure 4 Exemplary application scenarios of communication circuits according to embodiments of this disclosure are shown.

[0044] like Figure 4As shown, the communication circuit of this embodiment can be mounted on the motherboard, which can be connected to the network card via a third connector. The network card can be the OCP NIC card described above. When the network card is present, the devices in the communication circuit on the motherboard can communicate with the network card via the third connector; when the network card is not present, the devices in the communication circuit on the motherboard cannot communicate with the network card.

[0045] In a large form factor (LFF) configuration, there can be two third connectors: the primary connector and the secondary connector, as described above. Alternatively, the third connector can be a single connector in a small form factor (LFF) configuration, namely the primary connector mentioned above.

[0046] When the network interface card (NIC) is in place, the communication circuit can obtain a signal indicating the PCIe forking mode supported by the NIC (i.e., the first signal described below) from the NIC. Combined with the communication path between the high-speed peripheral interconnect interface on the central processing unit (CPU) and the NIC, it determines the target forking mode, such as a forking mode that maximizes the resource utilization of the motherboard and the NIC. The signal indicating the target forking mode (i.e., the third signal described below) is then transmitted to the NIC to configure the NIC's PCIe forking mode. Simultaneously, the PCIe forking mode on the motherboard side is configured according to the target forking mode. In this case, starting the PCIe training process allows for the adjustment of the PCIe forking modes on both the motherboard and NIC sides.

[0047] The communication circuit of the present disclosure embodiment is described below.

[0048] In one possible implementation, this disclosure proposes a communication circuit including an interconnect fork mode determination module, at least one central processing unit (CPU), at least one first connector, and at least one second connector. The interconnect fork mode determination module and the second connector communicate with a network interface card (NIC) via a third connector. The first connector is connected to the high-speed peripheral component interconnect interface of the corresponding CPU. When the first connector is connected to the second connector via a cable and the cable is in place, the first connector communicates with the second connector via the cable.

[0049] The interconnect fork method determination module is used for:

[0050] Obtain the first signal from the network card, which indicates the presence of the network card and the high-speed peripheral component interconnection branching method supported by the network card;

[0051] A second signal is obtained from the second connector, the second signal indicating the high-speed peripheral component interconnect interface on the central processing unit that is communicative with the second connector;

[0052] Based on the first and second signals, determine the high-speed peripheral component interconnect interface on the central processing unit that can communicate with the network card, and the communication path between the high-speed peripheral component interconnect interface and the network card;

[0053] Based on the first signal and the communication path, the target fork mode is determined from the high-speed peripheral component interconnection fork modes supported by the network card, and a third signal indicating the target fork mode is output to the network card, and a fourth signal indicating the target fork mode is output to the central processing unit.

[0054] Figure 5 A schematic diagram showing the structure of a communication circuit 100 according to an embodiment of the present disclosure is shown, as follows: Figure 5 As shown, the communication circuit 100 is mounted on the motherboard MB and includes an interconnection branch mode determination module 10, a central processing unit CPU 0, a first connector A0, and a second connector B0. The interconnection branch mode determination module 10 and the second connector B0 communicate with the network card 200 through a third connector C0. The third connector C0 can be the primary connector described above, and the network card 200 can be the OCP NIC card described above.

[0055] The first connector A0 corresponds to the central processing unit (CPU0) and connects to the CPU0's high-speed peripheral interconnect interface (PCIe interface). The first connector A0 can obtain PCIe signals from the CPU0 through the PCIe interface connected to the CPU0. The CPU may include multiple PCIe interfaces; when the first connector is connected to different PCIe interfaces, the obtained PCIe signal levels are different, allowing the first connector to identify which CPU's PCIe interface the obtained PCIe signal originates from. For example... Figure 5 In the example, when the first connector A0 is connected to the PCIe interface K0 of the central processing unit CPU0, the level of the PCIe signal P[e] obtained through the PCIe interface K0 can be used to determine that the PCIe signal comes from the PCIe interface K0 of the central processing unit CPU0.

[0056] In this embodiment, the first connector A0 can be connected to the second connector B0 via a cable. The presence of the cable affects the communication status of the objects connected at both ends of the cable. When the cable is in place, the objects connected at both ends of the cable can communicate; when the cable is not in place, the objects connected at both ends of the cable cannot communicate. After the first connector A0 determines that the received PCIe signal comes from the PCIe interface K0 of the central processing unit CPU0, when the first connector A0 is connected to the second connector B0 via a cable and the cable is in place, the first connector A0 outputs the PCIe signal P[e] from the PCIe interface K0 to the second connector B0, and also outputs the second signal PCIe_PORT_ID_[n:0], which can indicate the PCIe interface K0, to the second connector B0. For example, the second signal PCIe_PORT_ID_[n:0] can include an identifier indicating the PCIe interface on the central processing unit CPU0 that can communicate with the second connector B0. In this case, the second signal PCIe_PORT_ID_[n:0] can be used to determine the communication status of the PCIe interface of the central processing unit CPU0 and the second connector B0.

[0057] The principle by which the first connector A0 achieves the above functions is given below.

[0058] The second connector B0 is connected to the interconnection branch mode determination module 10. When the interconnection branch mode determination module 10 acquires the second signal PCIe_PORT_ID_[n:0], the second connector B0 outputs the second signal PCIe_PORT_ID_[n:0] to the interconnection branch mode determination module 10.

[0059] The second connector B0 connects to the network card 200 through the third connector C0, and can output the PCIe signal P[e] to the network card 200 through the third connector C0.

[0060] The network interface card (NIC) 200 is equipped with a first signal PRSNTB[3:0]. The state of the first signal PRSNTB[3:0] is determined by the PCIe fork mode supported by the NIC 200 and the presence of the NIC 200. For example, when the first signal PRSNTB[3:0] is 0000, it indicates that the NIC 200 is not present. When the first signal PRSNTB[3:0] is 0001, it indicates that the NIC 200 is present and supports PCIe fork modes including PCIe 1x8 and PCIe 2x8. When the first signal PRSNTB[3:0] is 0010, it indicates that the NIC 200 is present and supports PCIe fork modes including PCIe 1x8 and PCIe 4x4, and so on. Therefore, the first signal PRSNTB[3:0] can be used to determine the communication status of the NIC 200 and the second connector B0, as well as the PCIe fork modes supported by the NIC 200. When the interconnection fork mode determination module 10 acquires the first signal PRSNTB[3:0], the network card 200 outputs the first signal PRSNTB[3:0] to the interconnection fork mode determination module 10.

[0061] The interconnection branching method determination module 10 can be implemented using a complex programmable logic device (CPLD). Figure 6a An exemplary workflow of an interconnect fork determination module according to an embodiment of this disclosure is shown.

[0062] See Figure 5 and Figure 6a For the interconnection fork mode determination module 10, step S61 can be executed to obtain the first signal PRSNTB[3:0] from the network card, and step S62 can be executed to obtain the second signal PCIe_PORT_ID_[n:0] from the second connector. The first signal PRSNTB[3:0] indicates the presence of the network card 200 and can be used to determine the communication status of the network card 200 and the second connector B0. The second signal PCIe_PORT_ID_[n:0] indicates the high-speed peripheral component interconnection interface on the central processing unit CPU0 that can communicate with the second connector B0. The interconnection fork mode determination module 10 executes step S63, and can determine the high-speed peripheral component interconnection interface on the central processing unit CPU0 that can communicate with the network card 200, as well as the communication path between the high-speed peripheral component interconnection interface and the network card 200, based on the obtained first signal PRSNTB[3:0] and second signal PCIe_PORT_ID_[n:0]. An exemplary implementation can be found in the further description below.

[0063] The first signal PRSNTB[3:0] also indicates the high-speed peripheral component interconnection fork mode supported by the network card. In this case, the interconnection fork mode determination module 10 executes step S64. Based on the first signal PRSNTB[3:0] and the communication path, the target fork mode can be determined from the high-speed peripheral component interconnection fork modes supported by the network card 200. The third signal BIF[2:0] indicating the target fork mode is output to the network card, and the fourth signal W0 indicating the target fork mode is output to the central processing unit CPU0. The method for selecting the target fork mode is given later.

[0064] When the central processing unit (CPU0) can recognize the third signal BIF[2:0], the fourth signal W0 can be the same as the third signal BIF[2:0]. When the central processing unit (CPU0) cannot recognize the third signal BIF[2:0], the interconnection branching method determination module 10 can generate the fourth signal W0 that the central processing unit (CPU) can recognize according to the communication specifications followed by the central processing unit (CPU0).

[0065] After executing step S64, other operating parameters on the motherboard side (such as the data transfer rate between the motherboard and the memory) can be configured. Then, the high-speed peripheral component interconnection training process (PCIe training process) is started to adjust the PCIe branching method on the motherboard side and the network card side.

[0066] The first signal PRSNTB[3:0], the second signal PCIe_PORT_ID_[n:0], and the third signal BIF[2:0] in this embodiment are all signals supported by the existing OCP NIC design specifications. Therefore, the communication circuit, motherboard, and server in this embodiment are all compatible with the OCP NIC design specifications.

[0067] exist Figure 5 In the example provided, the communication circuit includes only one central processing unit (CPU), one first connector, and one second connector. Those skilled in the art will understand that in practical applications, the communication circuit may include more CPUs, first connectors, and second connectors, such that each first connector corresponds to one CPU, and each second connector is connected to at least one first connector via a cable. This disclosure does not limit the number of CPUs, first connectors, and second connectors included in the communication circuit.

[0068] According to the communication circuit of this disclosure embodiment, an interconnect fork mode determination module, at least one central processing unit (CPU), at least one first connector, and at least one second connector are provided. The interconnect fork mode determination module and the second connector communicate with the network card (NIC) through a third connector. The first connector is connected to the high-speed peripheral component interconnect interface (PSBI) of the corresponding CPU. When the first connector is connected to the second connector via a cable and the cable is in place, the first connector communicates with the second connector via the cable. The interconnect fork mode determination module obtains a first signal from the NIC and a second signal from the second connector. The first signal indicates the presence of the NIC, and the second signal indicates the high-speed PBI interconnect interface on the CPU that can communicate with the second connector. Therefore, based on the first and second signals, the high-speed PBI interconnect interface on the CPU that can communicate with the NIC, as well as the communication path between the high-speed PBI interconnect interface and the NIC, can be determined, thus clarifying the range of high-speed PBI interconnect fork modes that the motherboard can support. The first signal also indicates the high-speed PBI interconnect fork modes supported by the NIC. Therefore, based on the first signal and the communication path, the target fork mode is determined from the high-speed PBI interconnect fork modes supported by the NIC, thereby completing the selection of high-speed PBI interconnect fork modes that can be supported by both the motherboard and the NIC. The interconnection fork mode determination module outputs a third signal indicating the target fork mode to the network card and a fourth signal indicating the target fork mode to the central processing unit (CPU), thus configuring the high-speed peripheral component interconnection fork mode between the CPU and the network card. The placement of the first and second connectors allows for more possibilities in the communication path between the high-speed peripheral component interconnection interface on the CPU and the network card. Based on this, when the communication circuit of this embodiment is mounted on the motherboard, the high-speed peripheral component interconnection fork mode of the motherboard can be flexibly adjusted, enabling the motherboard to be compatible with more types of high-speed peripheral component interconnection fork modes, improving the motherboard's reusability, and reducing server costs.

[0069] Figure 6b An exemplary workflow of an interconnect fork determination module according to an embodiment of this disclosure is shown.

[0070] like Figure 6b As shown, in one possible implementation, determining the high-speed peripheral component interconnection interface on the central processing unit that is communicative with the network card based on the first signal and the second signal (step S63) includes:

[0071] When the first signal indicates that the network card is in place, the high-speed peripheral component interconnect interface on the central processing unit corresponding to the second signal is identified as the high-speed peripheral component interconnect interface that can communicate with the network card.

[0072] For example, when the network card is not present, no PCIe interface on the motherboard can communicate with it. Therefore, the interconnect fork determination module can first determine whether the network card is present based on the first signal. Determining the high-speed peripheral component interconnect interface on the CPU that can communicate with the network card can be a step performed when the first signal indicates that the network card is present. The second signal indicates the high-speed peripheral component interconnect interface on the CPU that can communicate with the second connector. Therefore, when the first signal indicates that the network card is present, the high-speed peripheral component interconnect interface on the CPU corresponding to the second signal is determined as the high-speed peripheral component interconnect interface that can communicate with the network card based on the indication of the second signal.

[0073] This method avoids unnecessary exploration of the communication path between the high-speed peripheral component interconnect interface and the network card when the network card is not in place, thus reducing data processing costs.

[0074] like Figure 6b As shown, in one possible implementation, the interconnect fork method determination module is also used for:

[0075] When the first signal indicates that the network card is not in place, the high-speed peripheral component interconnection interface on the central processing unit corresponding to the second signal is set to power-saving mode.

[0076] For example, when the network card is not in place, the high-speed peripheral component interconnect interface on the central processing unit (CPU) corresponding to the second signal will not function properly. In this case, this interface can be set to power-saving mode. Other high-speed peripheral component interconnect interfaces on the CPU may not be connected to the first connector, but rather to other devices or components; they will still function properly when the network card is not in place, thus not changing the interface state.

[0077] This method makes the communication circuits more energy-efficient, thereby reducing the energy consumption of the motherboard and server.

[0078] After setting the high-speed peripheral component interconnect interface corresponding to the second signal on the central processing unit to power-saving mode, other operating parameters on the motherboard side (such as the data transfer rate between the motherboard and memory) can be configured, and then the high-speed peripheral component interconnect training process (PCIe training process) can be started. This allows for the adjustment of the PCIe fork method on the motherboard side.

[0079] like Figure 6b As shown, in one possible implementation, the high-speed peripheral component interconnect interface on the central processing unit that can communicate with the network card, and the communication path between the high-speed peripheral component interconnect interface and the network card are determined based on the first signal and the second signal (step S63), including:

[0080] For each high-speed peripheral component interconnect interface on the central processing unit that can communicate with the network card, the communication path between each high-speed peripheral component interconnect interface and the network card is determined based on the first connector connected to each high-speed peripheral component interconnect interface, the second connector that obtains the second signal corresponding to each high-speed peripheral component interconnect interface, and the third connector.

[0081] For example, in Figure 5 In the example, the central processing unit where the PCIe interface K0 is located is the central processing unit CPU0, and the central processing unit CPU0 corresponds to the first connector A0. Therefore, the PCIe interface K0 is connected to the first connector A0. This information is fixed in the communication circuit and can be pre-stored in the interconnection branching method determination module 10.

[0082] Based on the first signal PRSNTB[3:0] and the second signal PCIe_PORT_ID_[n:0], the interconnection branching mode determination module 10 can determine that the high-speed peripheral component interconnection interface on the central processing unit CPU0 that can communicate with the network card 200 is the PCIe interface K0. The interconnection branching mode determination module obtains the second signal PCIe_PORT_ID_[n:0] corresponding to the PCIe interface K0 from the second connector B0. Therefore, the communication path from the PCIe interface K0 to the network card 200 can be determined as follows: PCIe interface K0 — first connector A0 — second connector B0 — third connector C0 — network card 200.

[0083] Figure 7 A schematic diagram showing another structure of the communication circuit 100 according to an embodiment of the present disclosure is provided.

[0084] like Figure 7 As shown, the communication circuit 100 includes an interconnection branching mode determination module 10, a central processing unit (CPU0-CPU3), first connectors A0-A3, and second connectors B0-B3. The interconnection branching mode determination module 10 and the second connectors B0-B3 communicate with the network interface card (NIC) 200 through a third connector C0. The third connector C0 can be the primary connector described above, and the NIC 200 can be the OCP NIC card described above.

[0085] Each first connector has a corresponding central processing unit (CPU), which connects to the corresponding CPU's high-speed peripheral component interconnect interface (PCIe interface). Figure 7In the example, the first connector A0 corresponds to CPU0 and is connected to PCIe interface K0 on CPU0. The first connector A1 corresponds to CPU1 and is connected to PCIe interface K1 on CPU1. The first connector A2 corresponds to CPU2 and is connected to PCIe interface K2 on CPU2. The first connector A3 corresponds to CPU3 and is connected to PCIe interface K3 on CPU3.

[0086] First connector A0 is connected to second connector B0 via a cable; first connector A1 is connected to second connector B1 via a cable; first connector A2 is connected to second connector B2 via a cable; and first connector A3 is connected to second connector B3 via a cable. All cables are in place.

[0087] Then in Figure 7 In the example, based on the first signal PRSNTB[3:0] and the second signal (not shown) obtained from the second connector B0 corresponding to the PCIe interface K0, the interconnection branching method determination module 10 can determine that the high-speed peripheral component interconnection interface on the central processing unit CPU0 that can communicate with the network card 200 is the PCIe interface K0. The communication path from the PCIe interface K0 to the network card 200 is determined as follows: PCIe interface K0 — first connector A0 — second connector B0 — third connector C0 — network card 200.

[0088] Based on the first signal PRSNTB[3:0] and the second signal (not shown) obtained from the second connector B1 corresponding to the PCIe interface K1, the interconnection branching method determination module 10 can determine that the high-speed peripheral component interconnection interface on the central processing unit CPU1 that can communicate with the network card 200 is the PCIe interface K1. The communication path from the PCIe interface K1 to the network card 200 is as follows: PCIe interface K1 — first connector A1 — second connector B1 — third connector C0 — network card 200.

[0089] Based on the first signal PRSNTB[3:0] and the second signal (not shown) obtained from the second connector B2 corresponding to the PCIe interface K2, the interconnection branching method determination module 10 can determine that the high-speed peripheral component interconnection interface on the central processing unit CPU2 that can communicate with the network card 200 is the PCIe interface K2. The communication path from the PCIe interface K2 to the network card 200 is as follows: PCIe interface K2 — first connector A2 — second connector B2 — third connector C0 — network card 200.

[0090] Based on the first signal PRSNTB[3:0] and the second signal (not shown) obtained from the second connector B3 corresponding to the PCIe interface K3, the interconnection branching method determination module 10 can determine that the high-speed peripheral component interconnection interface on the central processing unit CPU1 that can communicate with the network card 200 is the PCIe interface K3. The communication path from the PCIe interface K3 to the network card 200 is as follows: PCIe interface K3 — first connector A3 — second connector B3 — third connector C0 — network card 200.

[0091] In this way, as long as the network card is in place, the interconnect branching method determination module can determine the communication path between the interface and the network card by acquiring the first and second signals. This allows it to determine the interconnect branching methods of the high-speed peripheral components supported by the motherboard.

[0092] The communication circuit of this disclosure is compatible with the OCP NIC design specification. That is, the network card can support various PCIe branching methods, such as PCIe 1x32, PCIe 1x16, PCIe 2x16, PCIe 1x8, PCIe 2x8, PCIe 4x8, PCIe 1x4, PCIe 2x4, PCIe 4x4, PCIe 8x4, etc. The motherboard supports single host, dual host, and quad host configurations; it supports setting 1 upstream socket, 2 upstream sockets, 4 upstream sockets, and 8 upstream sockets; and it supports 1 link, 2 links, 4 links, and 8 links.

[0093] The following is combined with Figure 7 This invention introduces an exemplary method for determining the interconnect fork mode using an interconnect fork mode determination module according to embodiments of the present disclosure.

[0094] In one possible implementation, based on the first signal and the communication path, the target forking method is determined from the high-speed peripheral component interconnection forking methods supported by the network card (step S64), including:

[0095] Based on the first signal, communication path, and user requirements, a target forking method matching the user requirements is determined from the high-speed peripheral component interconnection forking methods supported by the network card.

[0096] In one example, assuming the first signal PRSNTB[3:0] is 1111, it indicates that the network card supports PCIe 1x8, PCIe 2x8, and PCIe 4x8 branching modes. Based on the first signal PRSNTB[3:0] and the second signal PCIe_PORT_ID_[n:0], the communication path between the high-speed peripheral component interconnect interface and the network card 200 can be determined as follows: Figure 7As shown. At this time, the motherboard has 4 communication paths, that is, it communicates with the outside world through 4 communication paths.

[0097] User requirements can be entered into the interconnect fork method determination module via code. User requirements can include maximizing the resource utilization of the motherboard and network card. It can be seen that the motherboard's PCIe fork method adapts to the PCIe 4x8 fork method, resulting in the highest resource utilization of the motherboard and network card, followed by the PCIe 2x8 fork method, while the PCIe 1x8 fork method has the lowest resource utilization.

[0098] because Figure 7 In the example, each CPU on the motherboard side can act as a master. Therefore, as long as each CPU outputs a x8 PCIe signal through the PCIe interface connected to the corresponding first connector, the motherboard side can achieve a PCIe 4x8 branching method.

[0099] In this case, the interconnect fork method determination module can determine that the target fork method matching the user's needs is the PCIe 4x8 fork method.

[0100] In another example, assuming the first signal PRSNTB[3:0] is 1010, it indicates that the network card supports PCIe 1x8 and PCIe 2x8 branching modes. Based on the first signal PRSNTB[3:0] and the second signal PCIe_PORT_ID_[n:0], the communication path between the high-speed peripheral component interconnect interface and the network card 200 can be determined as follows: Figure 7 As shown. At this time, the motherboard has 4 communication paths, that is, it communicates with the outside world through 4 communication paths.

[0101] User requirements can be entered into the interconnect fork method determination module via code. User requirements can include maximizing the resource utilization of the motherboard and network card. It can be seen that the resource utilization of the motherboard and network card is highest when the motherboard's PCIe fork method is adapted to a PCIe 2x8 fork method, followed by the PCIe 1x8 fork method.

[0102] because Figure 7 In the example, each CPU on the motherboard side can act as a master. Therefore, as long as any two CPUs output a PCIe signal through the PCIe interface connected to the corresponding first connector, the motherboard side can achieve the PCIe 2x8 branching method.

[0103] Those skilled in the art should understand that Figure 7In the example, each CPU shows only one PCIe interface connected to the corresponding first connector, but in reality there may be more than one. For example, if there are two PCIe interfaces connected to the corresponding first connector on CPU0, it is also possible to select only CPU0 to output two x8 PCIe signals to support the PCIe 2x8 branching method.

[0104] In this case, the interconnect fork method determination module can determine that the target fork method matching the user's needs is the PCIe 2x8 fork method.

[0105] Those skilled in the art will understand that users may have more options, such as prioritizing an nx8 branching method (n = 1 / 2 / 4 / ...), and this disclosure does not limit this.

[0106] In this way, the determined target branching method is matched with user needs, thereby improving the user experience.

[0107] like Figure 6b As shown, in one possible implementation, the interconnection fork method determination module 10 is further used for:

[0108] A fifth signal is obtained from the first connector, which indicates whether the cable connected to the first connector is in place;

[0109] When the cable connected to the first connector is not in place, the high-speed peripheral component interconnection interface on the central processing unit corresponding to the first connector and connected to the first connector is set to power-saving state.

[0110] For example, with Figure 5 For example, the first connector A0 may also be equipped with a fifth signal, Cable_PRSNT_[a]#, to indicate whether the cable connected to the first connector A0 is in place. When the interconnection branch mode determination module 10 obtains the fifth signal, Cable_PRSNT_[a]#, the first connector A0 outputs the fifth signal, Cable_PRSNT_[a]#, to the interconnection branch mode determination module 10.

[0111] exist Figure 5In the example, the cable connects the first connector A0 and the second connector B0. Therefore, the fifth signal obtained from the first connector A0 can be used to determine the communication status of the first connector A0 and the second connector B0. If the cable connected to the first connector A0 is not in place, the interconnection branch mode determination module 10 can determine that the PCIe interfaces on the CPU0 corresponding to the first connector A0 cannot communicate with the second connector B0. At this time, regardless of whether the network card is in place, the PCIe interfaces on the CPU0 corresponding to the first connector A0 cannot communicate with the network card, and this part of the PCIe interfaces will not work properly. In this case, this part of the interface can be set to power-saving mode.

[0112] In other examples, the first connector connects to a cable, but the other object connected to the cable may not be the second connector, but rather a device such as a memory. It is also possible to make the fifth signal indicate the object to which the cable is connected. In this case, when the fifth signal indicates that the cable connected to the first connector is in place, the PCIe interface on the central processing unit corresponding to the first connector can also be set to power-saving mode when the cable connected to the fifth connector is the second connector.

[0113] exist Figure 6b In the example, the step of obtaining the fifth signal from the first connector and setting the high-speed peripheral component interconnect interface on the central processing unit corresponding to the first connector to a power-saving state when the cable connected to the first connector is not in place is executed before step S61. Those skilled in the art should understand that the execution of this step does not affect the execution of steps S61-S64, and the embodiments of this disclosure do not limit the execution order of the step of obtaining the fifth signal from the first connector.

[0114] In this way, the energy consumption of communication circuits can be further reduced.

[0115] The following describes the principle by which the first connector can distinguish the source of the PCIe signal based on the received PCIe signal, and the principle by which the fifth signal indicates whether the cable connected to the first connector is in place.

[0116] Figure 8 An exemplary connection method between a first connector and a resistor according to an embodiment of this disclosure is shown.

[0117] In one possible implementation, the first connector is connected to the power supply voltage via pull-up resistors corresponding to each high-speed peripheral component interconnect interface, and connected to ground via pull-down resistors corresponding to each high-speed peripheral component interconnect interface. The pull-up and pull-down resistors for any two high-speed peripheral component interconnect interfaces are different.

[0118] When the high-speed peripheral component interconnect interface on the central processing unit is connected to the first connector, the signal levels transmitted to the first connector through any two high-speed peripheral component interconnect interfaces are different;

[0119] On the first connector, the initial state of the fifth signal is a high level.

[0120] On the second connector, the fifth signal remains at a low level.

[0121] When the fifth signal on the first connector changes to a low level, it indicates that the cable connecting the first connector and the second connector is in place.

[0122] When the fifth signal on the first connector remains high, it indicates that the cable connecting the first connector and the second connector is not in place.

[0123] For example, such as Figure 8 As shown, assume that the central processing unit (CPU0) corresponding to the first connector A0 includes N (N is a positive integer) PCIe interfaces. Each PCIe interface may communicate with the network card (not shown) through the first connector A0, the second connector B0, and the third connector (not shown). To distinguish which PCIe interface the PCIe signal obtained by the first connector A0 from the CPU0 comes from, N pull-up resistors (R1, R2, ..., RN) and N pull-down resistors (R-1, R-2, ..., RN) can be set, with each PCIe interface corresponding to one pull-up resistor and one pull-down resistor.

[0124] The first connector A0 is connected to the power supply voltage VCC via pull-up resistors and to ground via pull-down resistors. The pull-up resistors for any two PCIe interfaces can be different, and the pull-down resistors for any two PCIe interfaces can also be different. This ensures that when the PCIe interfaces on the CPU0 are connected to the first connector A0, the levels of the PCIe signals transmitted to the first connector A0 through any two PCIe interfaces will be different. This allows the first connector A0 to distinguish the source of the PCIe signal based on its received signal level and generate a second signal indicating the corresponding PCIe interface.

[0125] like Figure 8 As shown, the first connector A0 is also connected to the power supply voltage VCC through a pull-up resistor R0 corresponding to the fifth signal, so that the initial state of the fifth signal on the first connector A0 is a high level. The second connector B0 can also be configured to be connected to ground through a pull-down resistor R-0 corresponding to the fifth signal, so that the fifth signal on the second connector B0 remains a low level.

[0126] If the first connector A0 is connected to the second connector B0 via a cable and the cable is in place, the level of the fifth signal on the first connector A0 side will be pulled down by the level of the fifth signal on the second connector B0 side, changing it to a low level. In other words, when the fifth signal on the first connector changes to a low level, it indicates that the cable connecting the first and second connectors is in place. If the first connector A0 is connected to the second connector B0 via a cable and the cable is not in place, the level of the fifth signal on the second connector B0 side cannot affect the level of the fifth signal on the first connector A0 side, and the fifth signal on the first connector A0 side remains at a high level. In other words, when the fifth signal on the first connector remains at a high level, it indicates that the cable connecting the first and second connectors is not in place. When the interconnection branching mode determination module 10 obtains the fifth signal from the first connector A0, it can determine whether the cable connected to the first connector A0 is in place based on the level of the fifth signal.

[0127] In this way, the first connector can distinguish the source of the PCIe signal based on the level of the received PCIe signal, and the fifth signal can indicate whether the cable connected to the first connector is in place, thereby improving the capability of the first connector.

[0128] In one possible implementation, the second signal includes an identifier for a high-speed peripheral component interconnect (PSI) interface, an identifier for each PSI interface on each central processing unit, and a correspondence between the signal levels transmitted from each PSI interface to the corresponding first connector, stored in the first connector.

[0129] The first connector is used to query the stored correspondence based on the level of the signal received from the high-speed peripheral component interconnection interface, and generate a second signal based on the queried identifier;

[0130] When the first connector is connected to the second connector via a cable and the cable is in place, a second signal is sent to the second connector.

[0131] For example, the first connector receives a PCIe signal from the PCIe interface, can generate a second signal based on the PCIe signal, and then transmit the PCIe signal and the second signal to the second connector.

[0132] For example, the first connector may store a correspondence between the signal level of each PCIe interface it is connected to and the identifier of that interface. Therefore, when the first connector receives a signal level from a PCIe interface, it can determine which PCIe interfaces it is communicating with by looking up the stored correspondence. Based on the determined PCIe interface identifier, a second signal is generated and sent to the second connector when the first connector is connected to the second connector via a cable and the cable is in place.

[0133] In this way, the first connector is able to transmit information from the high-speed peripheral component interconnect interface that it can communicate with as a second signal to the second connector. Therefore, when the subsequent interconnection branching mode determination module obtains the second signal from the second connector, it can determine the communication status between the high-speed peripheral component interconnect interface and the second connector, and thus determine the transmission path between the high-speed peripheral component interconnect interface and the network card.

[0134] PCIe signals may include configuration information about the network interface card's (NIC) operating mode, such as data transfer rates and other operating parameters. This disclosure does not limit the specific information transmitted by the PCIe signals.

[0135] Figures 9-12 Schematic diagrams are shown of the high-speed peripheral component interconnection branching methods configured according to embodiments of the present disclosure on the motherboard side and the network card side.

[0136] like Figure 9 As shown, the high-speed peripheral component interconnection between the motherboard side and the network card side after configuration can be a PCIe 4x4 branching method. CPU0-CPU3 are the central processing units, A0-A3 are the first connectors, and B0-B3 are the second connectors. Each central processing unit transmits one x4 PCIe signal to the corresponding first connector. Each first connector is connected to a second connector via a cable, and the cable is in place. The one x4 PCIe signal received by each first connector is transmitted to the connected second connector via the cable, and then transmitted by the second connector to the network card through the primary connector.

[0137] like Figure 10 As shown, the high-speed peripheral component interconnection between the motherboard side and the network card side after configuration can be a PCIe 4x8 branching method. CPU0-CPU3 are the central processing units, A0-A3 are the first connectors, and B0-B3 are the second connectors. Each central processing unit transmits one x8 PCIe signal to the corresponding first connector. Each first connector is connected to a second connector via a cable, and the cable is in place. The x8 PCIe signal received by each first connector is transmitted to the connected second connector via the cable. Second connectors B0 and B1 transmit the received PCIe signals to the network card through the primary connector. Second connectors B2 and B3 transmit the received PCIe signals to the network card through the secondary connector.

[0138] like Figure 11As shown, the high-speed peripheral component interconnection between the motherboard side and the network card side after configuration can be a PCIe 2x8 branching method. CPU0 is the central processing unit, A0 is the first connector, and B0 is the second connector. According to existing technology, CPU0 directly transmits one x8 PCIe signal to the network card through the primary connector. CPU0 also transmits one x8 PCIe signal to the corresponding first connector A0. The first connector A0 is connected to the second connector B0 via a cable, and the cable is in place. The x8 PCIe signal received by the first connector A0 is transmitted to the connected second connector B0 via the cable. The second connector B0 transmits the received PCIe signal to the network card through the primary connector.

[0139] like Figure 12 As shown, the high-speed peripheral component interconnection between the motherboard side and the network card side after configuration can be a PCIe 2x8 branching method. CPU0 and CPU1 are central processing units (CPUs), A0 and A1 are first connectors, and B0 is a second connector. According to existing technology, CPU0 directly transmits one x8 PCIe signal to the network card through the primary connector. CPU1 also transmits one x8 PCIe signal to the corresponding first connector A0. However, the cable between first connector A0 and second connector B0 is not in place, therefore there is no signal transmission between them. First connector A1 is connected to second connector B0 via a cable, and the cable is in place. The x8 PCIe signal received by first connector A1 is transmitted to the connected second connector B0 via the cable. Second connector B0 transmits the received PCIe signal to the network card through the primary connector.

[0140] Those skilled in the art will understand that the forking methods shown above are merely examples, and this disclosure supports many more forking methods. This disclosure does not limit the selectable forking methods.

[0141] This disclosure also proposes a motherboard including the communication circuit described above. Exemplarily, the motherboard may also include a non-volatile memory express (NVMe) or a PCIe expansion card (Card Electromechanical, CEM), etc. This disclosure does not limit the specific types of devices installed on the motherboard.

[0142] This disclosure also proposes a server, including the motherboard described above.

[0143] Figure 13 A block diagram of a server 1900 according to an embodiment of the present disclosure is shown. (Refer to...) Figure 13Server 1900 includes processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, processing component 1922 is configured to execute instructions to perform the methods described above.

[0144] Server 1900 may also include a power supply component 1926 configured to perform power management of server 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output (I / O) interface 1958. Server 1900 can operate on an operating system stored in memory 1932, such as Microsoft Windows Server operating system. TM Apple's graphical user interface-based operating system (Mac OS X) TM ), a multi-user, multi-process computer operating system (Unix) TM Linux is a free and open-source Unix-like operating system. TM ), the open-source Unix-like operating system (FreeBSD) TM (or similar.)

[0145] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of a server 1900 to perform the above-described method.

[0146] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0147] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0148] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0149] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A communication circuit, characterized by, The device includes an interconnect fork mode determination module, at least one central processing unit (CPU), at least one first connector, and at least one second connector. The interconnect fork mode determination module and the second connector communicate with the network interface card (NIC) via a third connector. The first connector is connected to the high-speed peripheral component interconnect interface of the corresponding CPU. When the first connector is connected to the second connector via a cable and the cable is in place, the first connector communicates with the second connector via the cable. The interconnection fork method determination module is used for: A first signal is obtained from the network card, the first signal indicating the presence of the network card and the high-speed peripheral component interconnection fork mode supported by the network card; A second signal is obtained from the second connector, the second signal indicating a high-speed peripheral component interconnect interface on the central processing unit that is communicative with the second connector; Based on the first signal and the second signal, determine the high-speed peripheral component interconnect interface on the central processing unit that can communicate with the network card, and the communication path between the high-speed peripheral component interconnect interface and the network card; Based on the first signal and the communication path, a target fork mode is determined from the high-speed peripheral component interconnection fork modes supported by the network card, a third signal indicating the target fork mode is output to the network card, and a fourth signal indicating the target fork mode is output to the central processing unit. The step of determining the high-speed peripheral component interconnect interface on the central processing unit that can communicate with the network card, and the communication path between the high-speed peripheral component interconnect interface and the network card, based on the first signal and the second signal, includes: for each high-speed peripheral component interconnect interface on the central processing unit that can communicate with the network card, determining the communication path between each high-speed peripheral component interconnect interface and the network card based on the first connector connected to each high-speed peripheral component interconnect interface, the second connector that obtains the second signal corresponding to each high-speed peripheral component interconnect interface, and the third connector; When the communication circuit is mounted on the motherboard, the interconnection and branching method of the motherboard's high-speed peripheral components can be flexibly adjusted.

2. The circuit of claim 1, wherein, The step of determining the high-speed peripheral component interconnection interface on the central processing unit that can communicate with the network card based on the first signal and the second signal includes: When the first signal indicates that the network card is in place, the high-speed peripheral component interconnect interface on the central processing unit corresponding to the second signal is identified as a high-speed peripheral component interconnect interface that can communicate with the network card.

3. The circuit of claim 1, wherein, The first connector is connected to the power supply voltage via pull-up resistors corresponding to each high-speed peripheral component interconnect interface, and connected to ground via pull-down resistors corresponding to each high-speed peripheral component interconnect interface. The pull-up and pull-down resistors for any two high-speed peripheral component interconnect interfaces are different. When the high-speed peripheral component interconnect interface on the central processing unit is connected to the first connector, the signal levels transmitted to the first connector through any two high-speed peripheral component interconnect interfaces are different. On the first connector, the initial state of the fifth signal is a high level. On the second connector, the fifth signal remains at a low level; When the fifth signal on the first connector changes to a low level, it indicates that the cable connecting the first connector and the second connector is in place. When the fifth signal on the first connector remains at a high level, it indicates that the cable connecting the first connector and the second connector is not in place.

4. The circuit of claim 3, wherein, The second signal includes an identifier for a high-speed peripheral component interconnect (PSI) interface, an identifier for each PSI interface on each central processing unit, and a correspondence between the signal levels transmitted by each PSI interface to the corresponding first connector, stored in the first connector. The first connector is used to query the stored correspondence based on the level of the signal received from the high-speed peripheral component interconnection interface, and generate the second signal based on the queried identifier; When the first connector is connected to the second connector via a cable and the cable is in place, the second signal is sent to the second connector.

5. The circuit of claim 1, wherein, The interconnection fork method determination module is also used for: When the first signal indicates that the network card is not in place, the high-speed peripheral component interconnection interface on the central processing unit corresponding to the second signal is set to power saving state.

6. The circuit of claim 3, wherein, The interconnection fork method determination module is also used for: The fifth signal is obtained from the first connector, the fifth signal indicating whether the cable connected to the first connector is in place; When the cable connected to the first connector is not in place, the high-speed peripheral component interconnection interface on the central processing unit corresponding to the first connector and connected to the first connector is set to power-saving state.

7. The circuit of claim 1, wherein, The step of determining the target fork method from the high-speed peripheral component interconnection fork methods supported by the network card based on the first signal and the communication path includes: Based on the first signal, the communication path, and the user's requirements, a target fork method matching the user's requirements is determined from the high-speed peripheral component interconnection fork methods supported by the network card.

8. A main board, characterized by, The communication circuit includes any one of claims 1-7.

9. A server, characterized by Includes the motherboard as described in claim 8.

Images