A method and emulator for chip simulation

Abstract

The specification discloses a chip simulation method and a simulator. The simulator receives chip data of a chip to be simulated. Then, in response to a selection operation of a user, at least one target chip interface is determined from a plurality of chip interfaces of different interface types. Next, a logic level signal sent by the target chip interface is received, and a power-on reset signal corresponding to the logic level signal is determined. Finally, the chip to be simulated is reset based on the power-on reset signal, and after the reset is completed, data communication between the chip to be simulated and the target chip interface is simulated according to the chip data. The method can determine at least one target chip interface from a plurality of chip interfaces of different interface types, and simulate data communication between the chip to be simulated and the target chip interface according to the chip data, thereby improving the efficiency of development and testing of a chip with a plurality of chip interfaces of different interface types.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a method and simulator for chip emulation. Background Technology

[0002] As the application functions of chips continue to expand, solutions based on multi-interface chips are being supported and promoted by many manufacturers. A multi-interface chip is a chip that integrates multiple different types of chip interfaces. It can simultaneously support multiple different communication protocols and interface standards, thus providing greater flexibility and compatibility. Multi-interface chips can be embedded in any mobile device and applied in fields such as payment, transportation, electronic ticketing, and cryptographic services.

[0003] Currently, to verify the correctness and feasibility of multi-interface chip designs, the concurrent processing capabilities of different types of interfaces within the chip are typically tested after its manufacture to identify design flaws or logical problems. However, this method is costly and results in a long chip development cycle.

[0004] Therefore, how to simulate multi-interface chips to improve the efficiency of their development and testing is an urgent problem to be solved. Summary of the Invention

[0005] This specification provides a method, simulator, electronic device, and machine-readable storage medium for chip emulation to improve the efficiency of multi-interface chip development and testing.

[0006] The following technical solution is adopted in this specification:

[0007] This specification provides a method for chip emulation, including:

[0008] Receive chip data from the chip to be simulated;

[0009] In response to the user's selection operation, at least one target chip interface is determined from multiple chip interfaces of different interface types;

[0010] Receive the logic level signal sent by the target chip interface, and determine the power-on reset signal corresponding to the logic level signal;

[0011] The chip to be simulated is reset based on the power-on reset signal, and after the reset is completed, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data.

[0012] Optionally, the plurality of interface types include: 7816 interface, SWP interface, SPI interface, and I2C interface.

[0013] Optionally, the power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface;

[0014] The chip to be simulated is reset based on the power-on reset signal, and after the reset is completed, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data, including:

[0015] If the global power-on reset signal is detected to change from high level to low level, a hard reset is performed on the chip to be simulated, and the data communication between the interface between the chip to be simulated and the target chip is terminated before the hard reset is completed.

[0016] If the global power-on reset signal is detected to change from low to high, it is determined that the hard reset of the chip to be simulated is complete. After the hard reset is complete, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data.

[0017] Optionally, the power-on reset signal further includes a partial power-on reset signal corresponding to the 7816 interface, and the method further includes:

[0018] Determine whether the target chip interface includes the 7816 interface; if not, detect the global power-on reset signal and the local power-on reset signal is high, perform a cold reset on the chip to be simulated, and after the cold reset is completed, simulate the data communication between the chip to be simulated and the target chip interface based on the chip data;

[0019] If so, upon detecting the local power-on reset signal, a thermal reset is performed on the chip to be simulated. After the thermal reset is completed, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data.

[0020] Optionally, receiving the logic level signal sent by the target chip interface includes:

[0021] The system receives a logic level signal sent by the target chip interface based on a reference voltage; wherein, if the input voltage of the target chip interface is greater than a threshold corresponding to the reference voltage, the logic level signal sent by the target chip interface is determined to be high; if the input voltage of the target chip interface is not greater than the threshold corresponding to the reference voltage, the logic level signal sent by the target chip interface is determined to be low.

[0022] Optionally, the power supply voltage signal includes a first power supply voltage and a second power supply voltage, wherein the first power supply voltage is used to represent the power supply voltage corresponding to interfaces other than the 7816 interface, and the second power supply voltage is used to represent the power supply voltage corresponding to the 7816 interface;

[0023] Receiving the logic level signal transmitted by the target chip interface based on a reference voltage includes:

[0024] Determine whether the target chip interface includes the 7816 interface. If not, use the first power supply voltage as the reference voltage for the logic level signal and receive the logic level signal sent by the target chip interface based on the first power supply voltage. If yes, use the second power supply voltage as the reference voltage for the logic level signal and receive the logic level signal sent by the target chip interface based on the second power supply voltage.

[0025] This manual provides a simulator, including:

[0026] The chip module is used to receive chip data from the chip to be simulated.

[0027] The selection module is used to determine at least one target chip interface from multiple interface types of chip interfaces in response to the user's selection operation.

[0028] The power-on module is used to receive the logic level signal sent by the target chip interface and determine the power-on reset signal corresponding to the logic level signal;

[0029] The reset module is used to reset the chip to be simulated based on the power-on reset signal, and after the reset is completed, to simulate the data communication between the interface between the chip to be simulated and the target chip based on the chip data.

[0030] Optionally, the plurality of interface types include: 7816 interface, SWP interface, SPI interface, and I2C interface.

[0031] Optionally, the power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface;

[0032] The reset module is configured to perform a hard reset on the chip to be simulated if the global power-on reset signal changes from high to low, and terminate the data communication between the interface between the chip to be simulated and the target chip before the hard reset is completed; if the global power-on reset signal changes from low to high, determine that the hard reset of the chip to be simulated is complete, and after the hard reset is complete, simulate the data communication between the interface between the chip to be simulated and the target chip based on the chip data.

[0033] Optionally, the power-on reset signal also includes a partial power-on reset signal corresponding to the 7816 interface, and the emulator further includes:

[0034] An interface control module is used to determine whether the target chip interface includes the 7816 interface; if not, it detects the global power-on reset signal and the local power-on reset signal is high, performs a cold reset on the chip to be simulated, and after the cold reset is completed, simulates the data communication between the chip to be simulated and the target chip interface based on the chip data; if yes, it detects the local power-on reset signal, performs a hot reset on the chip to be simulated, and after the hot reset is completed, simulates the data communication between the chip to be simulated and the target chip interface based on the chip data.

[0035] This specification provides an electronic device, including a communication interface, a processor, a memory, and a bus, wherein the communication interface, the processor, and the memory are interconnected via the bus;

[0036] The memory stores machine-readable instructions, and the processor executes the chip emulation method described above by calling the machine-readable instructions.

[0037] This specification provides a machine-readable storage medium storing machine-readable instructions, which, when called and executed by a processor, implement the above-described chip emulation method.

[0038] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects:

[0039] In the chip simulation method provided in this specification, the simulator receives chip data from the chip to be simulated. Next, in response to a user selection operation, at least one target chip interface is determined from multiple interface types. Then, a logic level signal sent by the target chip interface is received, and a power-on reset signal corresponding to the logic level signal is determined. Finally, the chip to be simulated is reset based on the power-on reset signal, and after the reset is complete, the data communication between the chip to be simulated and the target chip interface is simulated based on the chip data. This method can determine at least one target chip interface from multiple interface types and simulate the data communication between the chip to be simulated and the target chip interface based on the chip data, thereby improving the efficiency of chip development and testing for chips with multiple interface types. Attached Figure Description

[0040] The accompanying drawings, which are included to provide a further understanding of this specification and form part of this specification, illustrate exemplary embodiments and their descriptions, serving to explain this specification and do not constitute an undue limitation thereof.

[0041] In the picture:

[0042] Figure 1 This is a flowchart illustrating a method for chip emulation, as shown in an exemplary embodiment.

[0043] Figure 2 This is a schematic diagram of an emulator shown in an exemplary embodiment;

[0044] Figure 3 This is a schematic diagram of another simulator shown in an exemplary embodiment;

[0045] Figure 4 This is an exemplary embodiment illustrating the structure of an electronic device in which a simulator is located;

[0046] Figure 5 This is a block diagram of an emulator shown in an exemplary embodiment. Detailed Implementation

[0047] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0048] It should be noted that the steps of the corresponding methods are not necessarily performed in the order shown and described in this specification in other embodiments. In some other embodiments, the methods may include more or fewer steps than described in this specification. Furthermore, a single step described in this specification may be broken down into multiple steps in other embodiments; and multiple steps described in this specification may be combined into a single step in other embodiments.

[0049] To enable those skilled in the art to better understand the technical solutions in the embodiments of this specification, the relevant technologies involved in the embodiments of this specification will be briefly described below.

[0050] A multi-interface chip is a chip that integrates multiple different types of chip interfaces. It can simultaneously support multiple different communication protocols and interface standards, thus providing greater flexibility and compatibility.

[0051] ISO 7816 is a standardized contact smart card communication protocol used for reading and writing contact smart cards. This protocol defines the physical characteristics, electrical signals, transmission protocols, and application command formats and rules of the smart card, ensuring efficient data exchange. The 7816 interface is a half-duplex serial communication interface.

[0052] SWP (Single Wire Protocol) is an interface protocol for transmitting information between a SIM card and the Near Field Communication (NFC) chip in a cellular phone. The SWP interface is a communication interface that implements full-duplex communication over a single wire.

[0053] The SPI (Serial Peripheral Interface) bus system is a synchronous serial peripheral interface used to handle the exchange of communication information between chips and various peripheral devices in a serial manner. It operates in a master-slave mode, which typically has one master device and one or more slave devices, performing full-duplex serial data transmission.

[0054] I2C (Inter-Integrated Circuit) is a bidirectional two-wire synchronous serial bus. It requires only two wires to transmit information between devices connected to the bus.

[0055] In practical applications, to verify the correctness and feasibility of a multi-interface chip design, it is usually necessary to manufacture the multi-interface chip based on the design, and then test the concurrent functionality of different types of interfaces in the multi-interface chip to discover defects or logic problems in the chip design. However, this method is costly and has a long chip development cycle.

[0056] Based on this, this specification proposes a technical solution to determine at least one target chip interface from multiple interface types of chip interfaces, and to simulate the data communication between the chip to be simulated and the target chip interface based on the chip data.

[0057] The technical solutions provided in the various embodiments of this specification are described in detail below with reference to the accompanying drawings.

[0058] Figure 1 This is a flowchart illustrating a chip emulation method as an exemplary embodiment, specifically including the following steps:

[0059] S100: Receives chip data from the chip to be simulated.

[0060] S102: In response to the user's selection operation, determine at least one target chip interface from multiple interface types of chip interfaces.

[0061] In the embodiments of this specification, the chip emulation method is applied to an emulator for emulating chips mounted on an electronic device, and the execution subject can be the emulator. The physical carrier of the emulator can be an electronic device, including servers, server clusters, etc. For ease of description, the chip emulation method provided in this specification will be described below using only the emulator as the execution subject.

[0062] In practical applications, testing the concurrent processing capabilities of multi-interface chips requires manually selecting which chip interfaces to use for concurrent processing via DIP switches or jumpers. However, this manual selection necessitates technicians adjusting the multi-interface chips for each test, which is cumbersome and results in low efficiency for testing the concurrent processing capabilities of multi-interface chips.

[0063] Based on this, the emulator can respond to the user's selection operation and determine which chip interfaces to process concurrently from multiple interface types of chip interfaces.

[0064] In the embodiments described in this specification, the emulator can receive chip data from the chip to be emulated.

[0065] Then, in response to the user's selection, the emulator can determine at least one target chip interface from multiple interface types of chip interfaces.

[0066] Specifically, in response to the user's selection operation, the simulator outputs an interface selection signal to represent at least one chip interface. Based on the interface selection signal, at least one target chip interface is determined from multiple chip interfaces of various interface types.

[0067] For example, an interface management interface is displayed to the user, from which the user can select at least one chip interface, and an interface selection signal is output to indicate that at least one chip interface is selected. Based on the interface selection signal, at least one target chip interface is determined from multiple chip interfaces of different interface types.

[0068] Among them, multiple interface types can include: 7816 interface, SWP interface, SPI interface, I2C interface, etc.

[0069] For example, multiple interface types can include: 7816 interface, SWP interface, SPI interface, and I2C interface. The target chip interface can be any one of the 7816 interface, SWP interface, SPI interface, and I2C interface; any two of the 7816 interface, SWP interface, SPI interface, and I2C interface; any three of the 7816 interface, SWP interface, SPI interface, and I2C interface; or all four of the 7816 interface, SWP interface, SPI interface, and I2C interface.

[0070] S104: Receive the logic level signal sent by the target chip interface, and determine the power-on reset signal corresponding to the logic level signal.

[0071] In the embodiments described in this specification, the emulator can receive the logic level signal sent by the target chip interface and determine the power-on reset signal corresponding to the logic level signal.

[0072] Specifically, it receives logic level signals transmitted by the target chip interface based on the power supply voltage. If the input voltage of the target chip interface is within the high-level range corresponding to the power supply voltage, the logic level signal transmitted by the target chip interface is determined to be high. If the input voltage of the target chip interface is within the low-level range corresponding to the power supply voltage, the logic level signal transmitted by the target chip interface is determined to be low.

[0073] It should be noted that different digital circuit standards or devices specify specific ranges or definitions of logic levels. For example, in the Transistor-Transistor Logic (TTL) standard, a high level is defined as a voltage between 2.4V and 5V, and a low level is defined as a voltage between 0V and 0.8V. In the Complementary Metal-Oxide-Semiconductor (CMOS) standard, a high level is defined as a voltage close to the supply voltage, and a low level is defined as close to 0V.

[0074] For example, when the power supply voltage is 5V, the high-level range can be 2.4V to 5V, and the low-level range can be 0V to 0.8V. If the input voltage of the target chip interface is between 2.4V and 5V, the logic level signal sent by the target chip interface is determined to be high. If the input voltage of the target chip interface is between 0V and 0.8V, the logic level signal sent by the target chip interface is determined to be low.

[0075] In practical applications, the power supply voltage required for the 7816 interface differs from that required for the SWP, SPI, and I2C interfaces. Therefore, when the target chip interface includes the 7816 interface, a power supply voltage compatible with the 7816 interface must be used to power the chip. Because the power supply voltage changes, the corresponding high-level and low-level ranges will also change.

[0076] Based on this, the simulator can determine whether the target chip interface includes a 7816 interface, and thus determine which power supply voltage to use to send logic level signals.

[0077] In the embodiments of this specification, the power supply voltage signal includes a first power supply voltage and a second power supply voltage. The first power supply voltage is used to represent the power supply voltage corresponding to interfaces other than the 7816 interface, and the second power supply voltage is used to represent the power supply voltage corresponding to the 7816 interface.

[0078] Determine whether the target chip interface includes a 7816 interface. If not, receive the logic level signal sent by the target chip interface based on the first power supply voltage. If yes, receive the logic level signal sent by the target chip interface based on the second power supply voltage.

[0079] S106: The chip to be simulated is reset based on the power-on reset signal, and after the reset is completed, the data communication between the interface between the chip to be simulated and the target chip is simulated according to the chip data.

[0080] In practical applications, resetting is a crucial step in chip simulation. Resetting refers to restoring the chip to its initial state when it starts up or is in an abnormal state. During chip simulation, it's crucial to determine whether the chip can correctly initialize its various modules and registers under different reset conditions. After resetting, it's essential to verify whether the chip can enter normal operating mode as expected and run stably without causing abnormalities or errors. This allows for the discovery of reset-related defects or logic problems in the chip design.

[0081] Based on this, the simulator can reset the chip to be simulated and then simulate the data communication after the reset is complete in order to discover defects or logic problems in the chip design.

[0082] In the embodiments described in this specification, the emulator can reset the chip to be simulated based on the power-on reset signal, and after the reset is completed, simulate the data communication between the interface between the chip to be simulated and the target chip based on the chip data.

[0083] In practical applications, a hard reset is a reset method triggered by physical circuitry or signals. A hard reset can reset the entire system or device to its initial state, clearing all data in registers and memory, and restarting the device. Therefore, during a hard reset, the instability of voltage and signals within the circuitry puts the circuit in an uncertain state. This can lead to errors, loss, or damage in data communication.

[0084] Therefore, in order to avoid errors, loss or damage in data communication, data communication is usually required after a hard reset is completed.

[0085] In the embodiments described in this specification, the power-on reset signal includes a global power-on reset signal corresponding to at least one target chip interface.

[0086] If the global power-on reset signal is detected to change from high to low, a hard reset is performed on the chip to be simulated, and data communication between the interface between the chip to be simulated and the target chip is terminated before the hard reset is completed.

[0087] If the global power-on reset signal changes from low to high, it is determined that the hard reset for the chip to be simulated is complete. After the hard reset is complete, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of an emulator shown in an exemplary embodiment. The emulator may include: a chip module, a selection module, a power-on module, and a reset module.

[0088] exist Figure 2 In the process, the chip module receives chip data from the chip to be simulated to simulate the chip. The selection module, responding to the user's selection operation, determines at least one target chip interface from multiple interface types and sends a logic level signal from the target chip interface to the power-on module. The power-on module receives the logic level signal from the target chip interface, determines the corresponding power-on reset signal, and sends the corresponding power-on reset signal to the reset module. The reset module receives the corresponding power-on reset signal and resets the chip simulated by the chip module based on the power-on reset signal. After the reset is complete, the data communication between the chip simulated by the chip module and the target chip interface is simulated based on the chip data.

[0089] In practical applications, a cold reset signal is generally caused by a memory fault and is used to trigger a cold reset. A cold reset refers to restoring the entire reset system and memory to their initial power-on state, which can be achieved by powering on and off. A hot reset signal is generally caused by a non-memory fault and is used to trigger a hot reset. A hot reset refers to resetting a specific module or unit during the reset process of the reset system. Among various interface types, the SWP, SPI, and I2C interfaces do not have cold and hot resets; only the 7816 interface has both. Therefore, the emulator needs to perform cold or hot resets for the 7816 interface during chip emulation.

[0090] Based on this, when it is determined that the target chip interface includes the 7816 interface, it is determined whether to perform a cold reset or a hot reset on the chip to be simulated.

[0091] In the embodiments described in this specification, the power-on reset signal also includes a partial power-on reset signal corresponding to the 7816 interface.

[0092] Determine whether the target chip interface includes a 7816 interface. If not, ensure that the local power-on reset signal is high. When the global power-on reset signal is detected, perform a cold reset on the chip to be simulated. After the cold reset is completed, simulate the data communication between the interface between the chip to be simulated and the target chip based on the chip data.

[0093] If so, when a partial power-on reset signal is detected, a thermal reset is performed on the chip to be simulated. After the thermal reset is completed, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data.

[0094] Please see Figure 3 , Figure 3 This is a schematic diagram of another emulator shown as an exemplary embodiment. The emulator may also include an interface control module.

[0095] exist Figure 3 In the process, the chip module receives chip data from the chip to be simulated to simulate the chip. The selection module, responding to the user's selection operation, determines at least one target chip interface from multiple interface types and sends the logic level signal from the target chip interface to the power-on module. The power-on module receives the logic level signal from the target chip interface, determines the corresponding global power-on reset signal, and sends the corresponding global power-on reset signal to the reset module.

[0096] The interface control module communicates with the target chip interface in the selection module to determine whether the target chip interface includes a 7816 interface. If not, it determines that the local power-on reset signal is high. When the global power-on reset signal is detected, it performs a cold reset on the chip simulated by the chip module. After the cold reset is completed, it simulates the data communication between the chip simulated by the chip module and the target chip interface based on the chip data.

[0097] If so, when a partial power-on reset signal is detected, the chip simulated by the chip module is thermally reset, and after the thermal reset is completed, the data communication between the chip simulated by the chip module and the target chip interface is simulated based on the chip data.

[0098] As can be seen from the above method, the emulator receives chip data from the chip to be simulated. Next, in response to the user's selection operation, at least one target chip interface is determined from multiple interface types. Then, the logic level signal sent by the target chip interface is received, and the corresponding power-on reset signal is determined. Finally, the chip to be simulated is reset based on the power-on reset signal, and after the reset is complete, the data communication between the chip to be simulated and the target chip interface is simulated based on the chip data. This method can determine at least one target chip interface from multiple interface types and simulate the data communication between the chip to be simulated and the target chip interface based on the chip data, thereby improving the efficiency of development and testing of chips with multiple interface types.

[0099] Please see Figure 4 , Figure 4 This is a structural diagram of an electronic device housing an emulator, as illustrated in an exemplary embodiment. At the hardware level, the device includes a processor 402, an internal bus 404, a network interface 406, memory 408, and non-volatile memory 410, and may also include other necessary hardware. One or more embodiments of this specification can be implemented in software, for example, the processor 402 reads the corresponding computer program from the non-volatile memory 410 into memory 408 and then runs it. Of course, besides software implementation, one or more embodiments of this specification do not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. That is to say, the execution entity of the following processing flow is not limited to individual logic units, but can also be hardware or logic devices.

[0100] Please see Figure 5 , Figure 5 This is a block diagram illustrating an exemplary embodiment of a simulator. This simulator can be applied to, for example... Figure 4 The electronic device shown implements the technical solution of this specification. The simulator may include:

[0101] Chip module 500 is used to receive chip data from the chip to be simulated.

[0102] Selection module 502 is used to determine at least one target chip interface from multiple interface types of chip interfaces in response to a user's selection operation.

[0103] The power-on module 504 is used to receive the logic level signal sent by the target chip interface and determine the power-on reset signal corresponding to the logic level signal.

[0104] The reset module 506 is used to reset the chip to be simulated based on the power-on reset signal, and after the reset is completed, to simulate the data communication between the interface between the chip to be simulated and the target chip based on the chip data.

[0105] Optional, multiple interface types include: 7816 interface, SWP interface, SPI interface, and I2C interface.

[0106] Optionally, the power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface. The reset module 506 is specifically used to perform a hard reset on the chip to be simulated if the global power-on reset signal is detected to change from high level to low level, and to terminate the data communication between the chip to be simulated and the target chip interface before the hard reset is completed; if the global power-on reset signal is detected to change from low level to high level, to determine that the hard reset for the chip to be simulated is completed, and after the hard reset is completed, to simulate the data communication between the chip to be simulated and the target chip interface based on the chip data.

[0107] Optionally, the power-on reset signal also includes a partial power-on reset signal corresponding to the 7816 interface, and the emulator further includes:

[0108] An interface control module is used to determine whether the target chip interface includes the 7816 interface; if not, it detects the global power-on reset signal and the local power-on reset signal is high, performs a cold reset on the chip to be simulated, and after the cold reset is completed, simulates the data communication between the chip to be simulated and the target chip interface based on the chip data; if yes, it detects the local power-on reset signal, performs a hot reset on the chip to be simulated, and after the hot reset is completed, simulates the data communication between the chip to be simulated and the target chip interface based on the chip data.

[0109] Optionally, the power-on module 504 is specifically used to receive a logic level signal sent by the target chip interface based on the power supply voltage; wherein, if the input voltage of the target chip interface is within the high-level range corresponding to the power supply voltage, the logic level signal sent by the target chip interface is determined to be high; if the input voltage of the target chip interface is within the low-level range corresponding to the power supply voltage, the logic level signal sent by the target chip interface is determined to be low.

[0110] Optionally, the power supply voltage includes a first power supply voltage and a second power supply voltage. The first power supply voltage represents the power supply voltage corresponding to interfaces other than the 7816 interface, and the second power supply voltage represents the power supply voltage corresponding to the 7816 interface. The power-on module 504 is specifically used to determine whether the target chip interface includes the 7816 interface. If not, it receives a logic level signal sent by the target chip interface based on the first power supply voltage; if yes, it receives a logic level signal sent by the target chip interface based on the second power supply voltage.

[0111] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0112] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0113] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0114] In a typical configuration, a computer includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0115] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0116] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0117] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0118] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0119] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0120] The terminology used in one or more embodiments of this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of one or more embodiments of this specification. The singular forms “a,” “described,” and “the” as used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0121] It should be understood that although the terms first, second, third, etc., may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of one or more embodiments of this specification, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "in response to a determination," or "when," or "in the event of a determination."

[0122] The above description is merely a preferred embodiment of one or more embodiments of this specification and is not intended to limit the scope of one or more embodiments of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the protection scope of one or more embodiments of this specification.

Claims

1. A method for chip emulation, characterized in that, include: Receive chip data from the chip to be simulated; In response to the user's selection operation, at least one target chip interface is determined from multiple chip interfaces of different interface types; Receive the logic level signal sent by the target chip interface based on the power supply voltage, and determine the power-on reset signal corresponding to the logic level signal according to the level range of the input voltage of the target chip interface corresponding to the power supply voltage; The chip to be simulated is reset based on the determined power-on reset signal, and after the reset is completed, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data. The step of determining the power-on reset signal corresponding to the logic level signal based on the input voltage of the target chip interface being within the level range corresponding to the power supply voltage includes: If the input voltage of the target chip interface is within the high-level range corresponding to the power supply voltage, the logic level signal is determined to be high, and then the power-on reset signal corresponding to the high level is determined. If the input voltage of the target chip interface is within the low level range corresponding to the power supply voltage, the logic level signal is determined to be low, and then the power-on reset signal corresponding to the low level is determined.

2. The method as described in claim 1, characterized in that, The various interface types include: 7816 interface, SWP interface, SPI interface, and I2C interface.

3. The method as described in claim 2, characterized in that, The power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface; The chip to be simulated is reset based on the determined power-on reset signal. After the reset is completed, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data, including: If the global power-on reset signal is detected to change from high level to low level, a hard reset is performed on the chip to be simulated, and the data communication between the interface between the chip to be simulated and the target chip is terminated before the hard reset is completed. If the global power-on reset signal is detected to change from low to high, it is determined that the hard reset of the chip to be simulated is complete. After the hard reset is complete, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data.

4. The method as described in claim 3, characterized in that, The power-on reset signal also includes a partial power-on reset signal corresponding to the 7816 interface, and the method further includes: Determine whether the target chip interface includes the 7816 interface; if not, determine that the local power-on reset signal is high; when the global power-on reset signal is detected, perform a cold reset on the chip to be simulated, and after the cold reset is completed, simulate the data communication between the chip to be simulated and the target chip interface based on the chip data. If so, when the local power-on reset signal is detected, the chip to be simulated is thermally reset, and after the thermal reset is completed, the data communication between the interface between the chip to be simulated and the target chip is simulated based on the chip data.

5. The method as described in claim 2, characterized in that, The power supply voltage includes a first power supply voltage and a second power supply voltage. The first power supply voltage is used to represent the power supply voltage corresponding to interfaces other than the 7816 interface, and the second power supply voltage is used to represent the power supply voltage corresponding to the 7816 interface. Receiving the logic level signal sent by the target chip interface based on the power supply voltage includes: Determine whether the target chip interface includes the 7816 interface; if not, receive the logic level signal sent by the target chip interface based on the first power supply voltage. If so, receive the logic level signal sent by the target chip interface based on the second power supply voltage.

6. A simulator, characterized in that, include: The chip module is used to receive chip data from the chip to be simulated. The selection module is used to determine at least one target chip interface from multiple interface types of chip interfaces in response to the user's selection operation. The power-on module is used to receive the logic level signal sent by the target chip interface based on the power supply voltage, and determine the power-on reset signal corresponding to the logic level signal according to the input voltage of the target chip interface being within the level range corresponding to the power supply voltage. The reset module is used to reset the chip to be simulated based on the determined power-on reset signal, and after the reset is completed, to simulate the data communication between the interface between the chip to be simulated and the target chip based on the chip data. The step of determining the power-on reset signal corresponding to the logic level signal based on the input voltage of the target chip interface being within the level range corresponding to the power supply voltage includes: If the input voltage of the target chip interface is within the high-level range corresponding to the power supply voltage, the logic level signal is determined to be high, and then the power-on reset signal corresponding to the high level is determined. If the input voltage of the target chip interface is within the low level range corresponding to the power supply voltage, the logic level signal is determined to be low, and then the power-on reset signal corresponding to the low level is determined.

7. The simulator according to claim 6, characterized in that, The various interface types include: 7816 interface, SWP interface, SPI interface, and I2C interface.

8. The simulator according to claim 7, characterized in that, The power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface; The reset module is configured to perform a hard reset on the chip to be simulated if the global power-on reset signal changes from high to low, and terminate the data communication between the interface between the chip to be simulated and the target chip before the hard reset is completed; if the global power-on reset signal changes from low to high, determine that the hard reset of the chip to be simulated is complete, and after the hard reset is complete, simulate the data communication between the interface between the chip to be simulated and the target chip based on the chip data.

9. The simulator according to claim 8, characterized in that, The power-on reset signal also includes a partial power-on reset signal corresponding to the 7816 interface, and the emulator also includes: An interface control module is used to determine whether the target chip interface includes the 7816 interface; if not, it detects the global power-on reset signal and the local power-on reset signal is high, performs a cold reset on the chip to be simulated, and after the cold reset is completed, simulates the data communication between the chip to be simulated and the target chip interface based on the chip data; if yes, it detects the local power-on reset signal, performs a hot reset on the chip to be simulated, and after the hot reset is completed, simulates the data communication between the chip to be simulated and the target chip interface based on the chip data.

10. An electronic device, characterized in that, It includes a communication interface, a processor, a memory, and a bus, wherein the communication interface, the processor, and the memory are interconnected via the bus; The memory stores machine-readable instructions, and the processor executes the method according to any one of claims 1 to 5 by invoking the machine-readable instructions.

11. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores machine-readable instructions, which, when invoked and executed by a processor, implement the method described in any one of claims 1 to 5.

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