Clock self-calibration circuit, clock signal generation circuit, and display device

Abstract

This disclosure provides a clock self-calibration circuit, a clock signal generation circuit, and a display device, belonging to the field of display technology. The self-calibration circuit of this disclosure includes a first acquisition sub-circuit, a second acquisition sub-circuit, a compensation sub-circuit, a first control sub-circuit, and a second control sub-circuit. The first acquisition sub-circuit receives an acquired clock signal and outputs a first voltage signal under the control of the first control sub-circuit. The second acquisition sub-circuit receives a reference clock signal and outputs a second voltage signal. The compensation sub-circuit obtains a compensated clock signal based on the first and second voltage signals, and under the control of the second control sub-circuit, sends the compensated clock signal to a second signal terminal.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a clock self-calibration circuit, a clock signal generation circuit, and a display device. Background Technology

[0002] The gate driving circuit includes multiple cascaded shift registers. Each shift register provides a drive signal to one gate line. The gate driving circuit, composed of multiple cascaded shift registers, scans each row of gate lines line by line. Each shift register consists of multiple transistors and capacitors. The clock signal shared by the cascaded shift registers suffers some loss due to the resistance of the transistors and the coupling of the capacitors, leading to instability in the drive signals output by each cascaded shift register. This affects the display effect of some row pixel units, and consequently, the display effect of the display device. Therefore, there is an urgent need for a clock self-calibration circuit that can detect and calibrate the signal generation circuit. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a clock self-calibration circuit, a clock signal generation circuit, and a display device.

[0004] In a first aspect, embodiments of this disclosure provide a clock self-calibration circuit, comprising: a first control sub-circuit configured to output a sampled clock signal from a first signal terminal under the control of a first control signal; a first acquisition sub-circuit configured to receive the sampled clock signal and output a first voltage signal under the control of the first control sub-circuit; a second acquisition sub-circuit configured to receive a reference clock signal and output a second voltage signal, wherein the reference clock signal is out of phase with the sampled clock signal; a compensation sub-circuit configured to obtain a compensation clock signal based on the first voltage signal and the second voltage signal; and a second control sub-circuit configured to control the compensation sub-circuit to receive the compensation clock signal and send the compensation clock signal to a second signal terminal under the control of the second control signal; wherein the first signal terminal is the signal output terminal of any one of the shift registers connected to the clock signal line; and the second signal terminal is the signal input terminal of any one of the shift registers connected to the clock signal line.

[0005] Preferably, the first control sub-circuit includes a first control transistor; the first electrode of the first control transistor is electrically connected to the first signal terminal, the second electrode of the first control transistor is electrically connected to the first acquisition sub-circuit, and the control electrode of the first control transistor is electrically connected to the first control signal terminal.

[0006] Preferably, the second control sub-circuit includes a second control transistor; the first electrode of the second control transistor is electrically connected to the output terminal of the compensation sub-circuit, the second electrode of the second control transistor is electrically connected to the second signal terminal, and the control electrode of the second control transistor is electrically connected to the second control signal terminal.

[0007] Preferably, the first acquisition sub-circuit includes a first operational amplifier; the non-inverting input of the first operational amplifier is electrically connected to the first control sub-circuit, and the inverting input of the first operational amplifier is electrically connected to the first end of the first resistor, the output of the first operational amplifier, and the compensation sub-circuit.

[0008] Preferably, the first acquisition sub-circuit further includes a second resistor; the first end of the second resistor is electrically connected to the output terminal of the first operational amplifier and the compensation sub-circuit, and the second end of the second resistor is electrically connected to the first resistor.

[0009] Preferably, the second acquisition sub-circuit includes a second operational amplifier and a first inverter; the input terminal of the first inverter receives the reference clock signal, and the output terminal of the first inverter is electrically connected to the non-inverting input terminal of the second operational amplifier; the inverting input terminal of the second operational amplifier is electrically connected to the second terminal of the first resistor, the output terminal of the second operational amplifier, and the compensation sub-circuit.

[0010] Preferably, the second acquisition sub-circuit further includes a third resistor; the first end of the third resistor is electrically connected to the first resistor, and the first end of the third resistor is electrically connected to the output terminal of the second operational amplifier and the compensation sub-circuit.

[0011] Preferably, the compensation sub-circuit includes a third operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a second inverter; the non-inverting input of the third operational amplifier is electrically connected to the second terminal of the fourth resistor and the first terminal of the fifth resistor, and the inverting input of the third operational amplifier is electrically connected to the second terminal of the sixth resistor and the first terminal of the seventh resistor; the output of the third operational amplifier is electrically connected to the second terminal of the seventh resistor and the input of the second inverter; the second terminal of the fifth resistor is connected to a reference voltage terminal; the first terminal of the fourth resistor is electrically connected to the first acquisition sub-circuit, and the first terminal of the sixth resistor is electrically connected to the second acquisition sub-circuit; the output of the second inverter is electrically connected to the second control sub-circuit, and the output of the second inverter serves as the output of the compensation sub-circuit.

[0012] Secondly, this disclosure provides a clock signal generation circuit configured to provide a clock signal to a clock signal line connected to a gate driving circuit; the gate driving circuit includes a plurality of cascaded shift registers; the clock signal generation circuit includes: the aforementioned clock self-calibration circuit, and: a clock signal generation sub-circuit having a first output terminal and a second output terminal, the clock signal generation sub-circuit being configured to provide a working clock signal to the gate driving circuit through the first output terminal, and to provide a reference clock signal to the clock self-calibration circuit through the second output terminal; wherein the reference clock signal is out of phase with the working clock signal.

[0013] Thirdly, embodiments of this disclosure provide a display device that includes the clock signal generation circuit described above. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a gate drive circuit provided in an embodiment of the present disclosure.

[0015] Figure 2 This is a schematic diagram of a clock self-calibration circuit provided in an embodiment of this disclosure.

[0016] Figure 3 This is a schematic diagram of a clock signal generation circuit provided in an embodiment of the present disclosure.

[0017] Figure 4 This is a block diagram of a clock signal generation circuit provided in an embodiment of the present disclosure.

[0018] Figure 5 This is a schematic diagram of a clock signal generation sub-circuit provided in an embodiment of this disclosure.

[0019] Figure 6 The working process of the clock signal generation circuit provided in the embodiments of this disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0022] The display device includes a display substrate, which is divided into a display area and a peripheral area. The display area includes multiple pixel units, and each pixel unit includes a pixel driving circuit and a light-emitting device. The pixel driving circuit requires gate lines to control its operating state, with one gate line corresponding to one row of pixel units. To provide a driving signal to each gate line, a gate driving circuit is fabricated in the peripheral area of ​​the display substrate. The gate driving circuit includes multiple cascaded shift registers, with one shift register providing a driving signal to one gate line. The gate driving circuit, composed of multiple cascaded shift registers, enables the gate lines to be scanned line by line.

[0023] Figure 1 This is a schematic diagram of a gate drive circuit provided in an embodiment of the present disclosure.

[0024] like Figure 1As shown, the gate drive circuit includes multiple cascaded shift registers. Each shift register includes at least an input signal terminal IN, an output signal terminal OUT, a cascade signal terminal CR, a reset signal terminal RST, and a clock signal terminal CLK. The cascade signal terminal CR of the current shift register is connected to the reset signal terminal RST of the previous shift register and the input signal terminal IN of the next shift register. During operation, the clock signal terminals CLK of multiple shift registers are connected to the same clock signal line 10. Each shift register requires a clock signal to drive its operation. The shift register consists of multiple transistors and capacitors. The clock signal shared by the cascaded shift registers undergoes some loss due to the resistance of the transistors and the coupling of the capacitors. This results in different drive signals output by the cascaded shift registers, or the output drive signals may not meet the requirements for good driving due to the loss, or the drive signals output by a single shift register may be unstable and inconsistent in magnitude, thus affecting the display effect of some row pixel units and consequently the display effect of the display device.

[0025] In view of this, the present disclosure provides a clock self-calibration circuit 100, which can calculate a compensation clock signal based on the working clock signal and the reference time signal, and transmit the compensation clock signal to the working clock signal terminal to compensate the working clock signal, so as to ensure that the voltage value of each shift register in the drive cascade is large enough, and avoid insufficient drive, which would affect the display effect.

[0026] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between their source and drain. In the embodiments of this disclosure and the following description, to distinguish between the source and drain of the transistor, one of them is referred to as the first electrode, the other as the second electrode, and the gate is referred to as the control electrode.

[0027] The clock self-calibration circuit 100 provided in this disclosure will be further described in detail below with reference to specific embodiments and accompanying drawings. In a first aspect, embodiments of this disclosure provide a clock self-calibration circuit 100. Figure 2 This is a schematic diagram of a clock self-calibration circuit 100 provided in an embodiment of this disclosure.

[0028] like Figure 2As shown, the clock self-calibration circuit 100 includes: a first acquisition sub-circuit 1, a second acquisition sub-circuit 2, a compensation sub-circuit 3, a first control sub-circuit 4, and a second control sub-circuit 5. The first control sub-circuit 4 is configured to output an acquisition clock signal from a first signal terminal A' under the control of a first control signal. The first acquisition sub-circuit 1 is configured to receive the acquisition clock signal and output a first voltage signal under the control of the first control sub-circuit 4. The second acquisition sub-circuit 2 is configured to receive a reference clock signal and output a second voltage signal. The compensation sub-circuit 3 is configured to obtain a compensation clock signal based on the first and second voltage signals. The second control sub-circuit 5 is configured to control the compensation sub-circuit 3 to receive the compensation clock signal and send the compensation clock signal to the second signal terminal A under the control of the second control signal. The working clock signal and the reference clock signal have opposite phases. The first signal terminal A' is the signal output terminal of any shift register GOA among the shift registers GOA connected to the clock signal line 10, and the second signal terminal A is the signal input terminal of any shift register GOA among the shift registers GOA connected to the clock signal line 10, and is also the signal port for the compensation clock signal to compensate the working clock signal.

[0029] In some examples, continue to refer to Figure 2 The first control sub-circuit 4 includes a first control transistor M1; the first electrode of the first control transistor M1 is electrically connected to the first signal terminal A', the second electrode of the first control transistor M1 is electrically connected to the first acquisition sub-circuit 1, and the control electrode of the first control transistor M1 is electrically connected to the first control signal terminal.

[0030] In some examples, continue to refer to Figure 2 The second control sub-circuit 5 includes a second control transistor M2; the first electrode of the second control transistor M2 is electrically connected to the output terminal of the compensation sub-circuit 3, the second electrode of the second control transistor M2 is electrically connected to the second signal terminal A, and the control electrode of the second control transistor M2 is electrically connected to the second control signal terminal.

[0031] It should be noted that the first control transistor M1 and the second control transistor M2 can be either P-type transistors or N-type transistors, without further restrictions.

[0032] In some examples, continue to refer to Figure 2 The first acquisition sub-circuit 1 includes a first operational amplifier OP1; the non-inverting input terminal of the first operational amplifier OP1 is electrically connected to the first control sub-circuit 4, and the inverting input terminal of the first operational amplifier OP1 is electrically connected to the first terminal of the first resistor R1, the output terminal of the first operational amplifier OP1, and the compensation sub-circuit 3.

[0033] Furthermore, the first acquisition sub-circuit 1 also includes a second resistor R2; the first end of the second resistor R2 is electrically connected to the output terminal of the first operational amplifier OP1 and the compensation sub-circuit 3, and the second end of the second resistor R2 is electrically connected to the first resistor R1.

[0034] In some examples, continue to refer to Figure 2 The second acquisition sub-circuit 2 includes a second operational amplifier OP2 and a first inverter INV1. The input terminal of the first inverter INV1 is electrically connected to the second output terminal Q of the clock signal generation sub-circuit and receives the reference clock signal. The output terminal of the first inverter INV1 is electrically connected to the inverting input terminal of the second operational amplifier OP2. The non-inverting input terminal of the second operational amplifier OP2 is electrically connected to the second terminal of the first resistor R1, the output terminal of the second operational amplifier OP2, and the compensation sub-circuit 3. Since the reference clock signal and the working clock signal are out of phase, the first inverter INV1 is configured to invert the reference clock signal.

[0035] Furthermore, the second acquisition sub-circuit 2 also includes a third resistor R3; the first end of the third resistor R3 is electrically connected to the first resistor R1, and the second end of the third resistor R3 is electrically connected to the output of the second operational amplifier OP2 and the compensation sub-circuit 3.

[0036] In this embodiment, the non-inverting input of the first operational amplifier OP1 is electrically connected to the first control sub-circuit 4 and receives the acquisition clock signal. At this time, the voltage value of the inverting input of the first operational amplifier OP1 is the same as the voltage value of the non-inverting input. The voltage value of the non-inverting input of the first operational amplifier OP1 is V1, and the voltage value of the inverting input is V1'. The inverting input of the second operational amplifier OP2 is electrically connected to the second output terminal Q of the clock signal generation sub-circuit and receives the reference clock signal. At this time, the voltage value of the inverting input of the second operational amplifier OP2 is the same as the voltage value of the non-inverting input. The voltage value of the inverting input of the second operational amplifier OP2 is V2, and the voltage value of the non-inverting input is V2'. The inverting input of the first operational amplifier OP1 is electrically connected to the first end of the first resistor R1, and the non-inverting input of the second operational amplifier OP2 is electrically connected to the second end of the first resistor R1. At this time, the current I flowing through the first resistor R1 is (V2'-V1') / R1. Taking the output terminal of the first operational amplifier OP1 and the first terminal of the second resistor R2 as the first node N1, and the output terminal of the second operational amplifier OP2 and the second terminal of the third resistor R3 as the second node N2, the voltage of the first node N1 is the voltage value Vo1 of the first voltage signal, and the voltage of the second node N2 is the voltage value Vo2 of the second voltage signal. When the first acquisition sub-circuit 1 includes the second resistor R2 and the second acquisition sub-circuit 2 includes the third resistor R3, the voltage difference between the voltage Vo1 of the first node N1 and the voltage Vo2 of the second node N2 is Vo1-Vo2, where Vo1-Vo2=I×(R1+R2+R3)=(V2'-V1')(R1+R2+R3) / R1.

[0037] In some examples, continue to refer to Figure 2 The compensation sub-circuit 3 includes a third operational amplifier OP3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a second inverter INV2. The non-inverting input of the third operational amplifier OP3 is electrically connected to the second terminal of the fourth resistor R4 and the first terminal of the fifth resistor; the inverting input of the third operational amplifier OP3 is electrically connected to the second terminal of the sixth resistor R6 and the first terminal of the seventh resistor R7; the output of the third operational amplifier OP3 is electrically connected to the second terminal of the seventh resistor R7 and the input of the second inverter INV2; the second terminal of the fifth resistor R5 is connected to reference ground GND; the first terminal of the fourth resistor R4 is electrically connected to the first acquisition sub-circuit 1, and the first terminal of the sixth resistor R6 is electrically connected to the second acquisition sub-circuit 2. The output of the second inverter INV2 is electrically connected to the second control sub-circuit 5, and the output of the second inverter INV2 is multiplexed as the output of the compensation sub-circuit 3.

[0038] For example, let's set the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 to be the same, and the resistance values ​​of the sixth resistor R6 and the seventh resistor R7 to be the same. Since the resistance values ​​of the fourth and fifth voltages are the same, the voltage division is the same, and the voltage at the non-inverting input of the third operational amplifier OP3 is Vo1 / 2. The output of the third operational amplifier OP3 outputs a third voltage signal. The connection node between the output of the third operational amplifier OP3 and the second terminal of the seventh resistor R7 is the third node N3, and the voltage value at the third node N3 is Vf. Since the resistance values ​​of the sixth and seventh voltages are the same, the voltage division is the same, and the voltage at the inverting input of the third operational amplifier OP3 is (Vo2 + Vf) / 2. Based on the voltage characteristics of the operational amplifier, the voltages at the non-inverting and inverting inputs of the third operational amplifier OP3 are the same. Therefore, Vo1 / 2 = (Vo2 + Vf) / 2, and thus Vf = Vo2 - Vo1 = (V2' - V1')(R1 + R2 + R3) / R1 = (V2 - V1)(R1 + R2 + R3) / R1. V1 is the voltage value of the acquisition clock signal, and V2 is the voltage value of the reference clock signal. The clock self-calibration circuit 100 obtains a compensation clock signal calculation formula related to the reference clock signal and the acquisition clock signal, with the resistance ratio as the compensation ratio. Since the output compensation clock signal and the working clock signal are out of phase, a second inverter INV2 is set to invert the compensation clock signal. Then, the compensation clock signal is transmitted to the second signal terminal A to compensate the working clock signal, ensuring that the driving voltage of each shift register is sufficiently stable, thereby improving the overall display effect of the pixel unit.

[0039] In this embodiment of the disclosure, when the second resistor R2 and the third resistor R3 are not included, the voltage difference between the voltage Vo1 of the first node N1 and the voltage Vo2 of the second node N2 is Vo2-Vo1, and Vf is also Vo2-Vo1. At this time, only the signal loss of the working clock signal in the shift register GOA is compensated. In the actual manufacturing of the display device, the gate driving circuit 9 is fabricated in the peripheral area of ​​the display substrate, and the clock self-calibration circuit 100 is fabricated on a circuit board electrically connected to the display substrate. There are also signal lines, jumpers, or other structures between the circuit board and the gate driving circuit 9. Losses will still occur during transmission. Therefore, a second resistor R2 and a third resistor R3 are set. According to the formula Vf=Vo1-Vo2, the resistance values ​​of the second resistor R2 and the third resistor R3 are related to the magnitude of the compensation clock signal. That is, (R1+R2+R3) / R1 is the compensation ratio of the clock self-calibration circuit 100. When the signal loss is large during the transmission of the working clock signal from the circuit board to the gate driving circuit 9 in the peripheral area of ​​the display substrate, the resistance values ​​of the second resistor R2 and the third resistor R3 can be increased to improve the compensation ratio of the clock self-calibration circuit 100 and thus improve the compensation effect.

[0040] Secondly, this disclosure provides a clock signal generation circuit, which includes the clock self-calibration circuit 100 and the clock signal generation sub-circuit 200 in any of the above embodiments. The clock self-calibration circuit 100 has been described in detail above and will not be repeated here.

[0041] Figure 3 This is a schematic diagram of a clock signal generation circuit provided in an embodiment of the present disclosure. Figure 4 This is a block diagram of a clock signal generation circuit sub-circuit provided in an embodiment of the present disclosure. Figure 5 This is a schematic diagram of a clock signal generation sub-circuit provided in an embodiment of this disclosure. The clock signal generation circuit is configured to provide a clock signal to the clock signal line 10 connected to the gate drive circuit 9.

[0042] like Figure 3 As shown, the gate drive circuit 9 includes multiple cascaded shift registers GOA; the clock signal generation circuit includes a clock signal generation sub-circuit 200 and a clock self-calibration circuit 100; the clock signal generation sub-circuit 200 has a first output terminal Q' and a second output terminal Q, wherein the clock signal generation sub-circuit 200 is configured to provide a working clock signal to the signal input terminal of the gate drive circuit through its first output terminal Q', and to provide a reference clock signal to the second acquisition sub-circuit through its second output terminal Q, the reference clock signal being out of phase with the working clock signal.

[0043] It should be noted that the clock signal generation circuit may also include multiple clock signal lines, including a first clock signal line, a second clock signal line, and a third clock signal line, for providing different clock signals or providing clock signals to different shift registers (GOAs) cascaded in a gate drive circuit.

[0044] For example, in a cascaded array of shift registers GOA, all odd-numbered shift registers GOA are electrically connected to the first clock signal line, and all even-numbered shift registers GOA are electrically connected to the second clock signal line. This improves circuit neatness and facilitates subsequent inspection and maintenance. Each clock signal line 10 on the display substrate can be equipped with a corresponding clock self-calibration circuit 100, with the input signal end of each clock signal line 10 serving as the second signal terminal A.

[0045] In this embodiment, the clock signal generation circuit generates two clock signals. The first output terminal Q' outputs a working clock signal to the second signal terminal A, and the second output terminal Q outputs a reference clock signal with the opposite phase and the same period amplitude as the working clock signal. The reference clock signal is then transmitted to the second acquisition sub-circuit 2 of the clock self-calibration circuit 100, and the working clock signal is transmitted to the second signal terminal A, i.e., the signal input terminal of each shift register GOA. After passing through the shift register GOA, it is output as the acquisition clock signal at the first signal terminal A' and transmitted to the first acquisition circuit 1. At this time, when the working clock signal is lost, the clock self-calibration circuit 100 compares the working clock signal and the reference clock signal to obtain a compensation clock signal related to both. The compensation clock signal is used to compensate for losses in the gate drive circuit 9 and losses during transmission on the clock signal line 10. After compensation by the compensation clock signal, the voltage driving the shift registers can be sufficiently large, preventing insufficient drive and increasing circuit stability. The working clock signal can be the output signal of the last stage or a cascaded signal in each shift register GOA connected to the same clock signal line 10. Of course, depending on the layout design of the display substrate, the output signal or cascaded signal of other shift registers GOA can also be used as the working clock signal during manufacturing.

[0046] Clock signal generation sub-circuit 200 Second signal terminal A First signal terminal A' Second signal terminal A Second signal terminal A First signal terminal A' In some examples, refer to Figure 5 The clock signal generation sub-circuit 200 includes: an SR flip-flop 6, a first arithmetic module 7, and a second arithmetic module 8.

[0047] like Figure 5As shown, the SR flip-flop 6 includes a first output terminal Q', a second output terminal Q, a set terminal S, and a reset terminal R. The first arithmetic module 7 is configured to respond to a first clock signal from the first output terminal Q', select either a first power supply voltage or a second power supply voltage as the first voltage, compare the first voltage with a first reference voltage to obtain a second voltage, and output the second voltage to the set terminal S of the SR flip-flop 6. The second arithmetic module 8 is configured to respond to a second clock signal from the second output terminal Q, select either a first power supply voltage or a second power supply voltage as the third voltage, compare the third voltage with the first reference voltage to obtain a fourth voltage, and output the fourth voltage to the reset terminal R of the SR flip-flop 6. The first output terminal Q' of the SR flip-flop 6 sends a working clock signal to the second signal terminal A based on the second voltage received at the set terminal S and the fourth voltage at the reset terminal R; the second output terminal Q outputs a reference clock signal to the second acquisition sub-circuit 2 based on the second voltage received at the set terminal S and the fourth voltage at the reset terminal R. In this circuit, the working clock signal is multiplexed as the first clock signal, and the reference clock signal is multiplexed as the second clock signal. That is, the working clock signal is not only used to drive the shift register GOA, but is also multiplexed as the first clock signal to drive the first arithmetic module 7. Similarly, the reference clock signal is not only used to drive the second acquisition circuit 2, but is also multiplexed as the second clock signal to drive the second arithmetic module 8. At the same time, the first output terminal Q' of the SR flip-flop 6 is used as the first output terminal Q' of the clock signal generation sub-circuit, and the second output terminal Q of the SR flip-flop 6 is used as the second output terminal Q of the clock signal generation sub-circuit.

[0048] In some examples, when the signal received by the set terminal S of the SR flip-flop 6 is high and the signal received by the reset terminal R is low, the signal output by the first output terminal Q' is low and the signal output by the second output terminal Q is high; when the signal received by the set terminal S of the SR flip-flop 6 is low and the signal received by the reset terminal R is high, the signal output by the first output terminal Q' is high and the signal output by the second output terminal Q is low.

[0049] In some examples, continue to refer to Figure 5The first operational module 7 includes a first comparator CP1, a first switching transistor T1, a second switching transistor T2, a first capacitor C1, and a first current source Iosc1. The non-inverting input of the first comparator CP1 is electrically connected to the first reference voltage terminal Vref. The inverting input of the first comparator CP1 is electrically connected to the second terminal of the first switching transistor T1, the first terminal of the second switching transistor T2, and the first terminal of the first capacitor C1. The output of the first comparator CP1 is electrically connected to the set terminal S of the SR flip-flop 6. The first terminal of the first switching transistor T1 is electrically connected to the first power supply voltage terminal VDD. The control terminal of the first switching transistor T1 is electrically connected to the control terminal of the second switching transistor T2 and the first output terminal Q' of the SR flip-flop 6. The second terminal of the second switching transistor T2 is electrically connected to the first terminal of the first current source Iosc1; the second terminals of the first capacitor C1 and the first current source Iosc1 are electrically connected to reference ground GND. The switching characteristics of the first switching transistor T1 and the second switching transistor T2 are opposite. The first power supply voltage is a high-level signal provided by the first power supply voltage terminal VDD, and the second power supply voltage is a low-level signal identical to the first reference voltage terminal Vref.

[0050] In some examples, continue to refer to Figure 5 The second operational module 8 includes a second comparator CP2, a third switching transistor T3, a fourth switching transistor T4, a second capacitor C2, and a second current source Iosc2. The non-inverting input of the second comparator CP2 is electrically connected to the first reference voltage terminal Vref. The inverting input of the second comparator CP2 is electrically connected to the second terminal of the third switching transistor T3, the first terminal of the fourth switching transistor T4, and the first terminal of the second capacitor C2. The output of the second comparator CP2 is electrically connected to the reset terminal R of the SR flip-flop 6. The first terminal of the third switching transistor T3 is electrically connected to the first power supply voltage terminal VDD. The control terminal of the third switching transistor T3 is electrically connected to the control terminal of the fourth switching transistor T4 and the second output terminal Q of the SR flip-flop 6. The second terminal of the fourth switching transistor T4 is electrically connected to the first terminal of the second current source Iosc2; the second terminal of the second capacitor C2 and the second terminal of the second current source Iosc2 are electrically connected to reference ground GND. The switching characteristics of the third switching transistor T3 and the fourth switching transistor T4 are opposite. The first power supply voltage is a high-level signal provided by the first power supply voltage terminal VDD, and the second power supply voltage is a low-level signal identical to the first reference voltage terminal Vref.

[0051] In this embodiment, the first switching transistor T1 and the third switching transistor T3 are P-type transistors, which conduct when the control electrode receives a low-level signal, and the second switching transistor T2 and the fourth switching transistor T4 are N-type transistors, which conduct when the control electrode receives a high-level signal.

[0052] In the first stage, the set terminal S and the reset terminal R remain at a low level, and the first output terminal Q' and the second output terminal Q remain in the previous state. The following explanation will be based on the example where the first output terminal Q' was low in the previous state and the second output terminal Q was high in the previous state. When the second signal terminal A outputs a low-level signal, the first transistor T1 is turned on, and the first voltage is the first power supply voltage. The first power supply voltage charges the first capacitor C1. At this time, the inverting input terminal of the first comparator CP1 is high, and the non-inverting input terminal is low. The second voltage output by the first comparator CP1 is a low-level signal, and the set terminal S of the SR flip-flop 6 is low. When the first signal terminal A' outputs a high-level signal, the fourth transistor T4 turns on, and the second capacitor C2 begins to discharge under the drive of the second current source Iosc2 until it drops from the third voltage to the second power supply voltage. The voltage at the inverting input terminal of the second comparator CP2 gradually decreases from a high level to a low level until it is the same as the first reference voltage at the non-inverting output terminal of the second comparator CP2. At this time, the fourth voltage output by the output terminal of the second comparator CP2 is high, and the reset terminal R of the SR flip-flop 6 is high. When the set terminal S of the SR flip-flop 6 is low and the reset terminal R is high, the previous operating state is changed, the first output terminal Q' outputs a high-level signal, and the second output terminal Q outputs a low-level signal.

[0053] In the second stage, the first output terminal Q' was high in the previous state, and the second output terminal Q was low in the previous state. When the second signal terminal A outputs a high-level signal, the second transistor T2 turns on, and the first capacitor C1 begins to discharge under the drive of the first current source Iosc1 until it drops from the first voltage to the second power supply voltage. The voltage at the inverting input terminal of the first comparator CP1 gradually decreases from high to low until it is the same as the first reference voltage at the non-inverting output terminal of the first comparator CP1. At this time, the second voltage output by the first comparator CP1 is high, and the reset terminal R of the SR flip-flop 6 is high. When the first signal terminal A' outputs a low-level signal, the third transistor T3 turns on, and the third voltage is the first power supply voltage. The first power supply voltage charges the second capacitor C2. At this time, the inverting input terminal of the second comparator CP2 is high, the non-inverting input terminal is low, and the fourth voltage output by the second comparator CP2 is low. At this time, the set terminal S of the SR flip-flop 6 is low. When the set input S of the SR flip-flop 6 is at a high level and the reset input R is at a low level, the previous operating state is changed, the first output Q' outputs a low-level signal, and the second output Q outputs a high-level signal.

[0054] The first and second stages work alternately to output two clock signals with opposite phases from the first output terminal Q' and the second output terminal Q. The voltages used to charge the first capacitor C1 and the second capacitor C2 are set to be the same, and the current values ​​provided by the first current source Iosc1 and the second current source Iosc2 are the same. Therefore, the first capacitor C1 and the second capacitor C2 discharge at the same rate, and the first arithmetic module 7 and the second arithmetic module 8 operate in the same time domain and with opposite phases.

[0055] In this embodiment of the disclosure, Figure 6 The working process of the clock signal generation circuit provided in the embodiments of this disclosure is as follows: Figure 6 As shown, the clock signal generation circuit operates as follows:

[0056] S1: The clock signal generation circuit starts working and generates a working clock signal and a reference clock signal.

[0057] S2: The working clock signal is output to the gate drive circuit 9, and the gate drive circuit 9 starts to work.

[0058] S3: The first control sub-circuit 4 receives the first control signal and starts working.

[0059] Specifically, the external control circuit or chip sends a first control signal to the first control sub-circuit 4. Under the control of the first control signal, the first control sub-circuit 4 transmits the working clock signal output by the gate drive circuit 9 to the first acquisition sub-circuit 1. The acquisition clock signal can be the output signal of the last stage or a cascaded signal in each shift register GOA connected to the same clock signal line 10.

[0060] S4: The compensation clock signal is calculated by the clock self-calibration circuit 100.

[0061] S5: The external circuit or chip judges the compensation clock signal obtained by the clock self-calibration circuit 100 and transmits the compensation clock signal to the gate drive circuit 9.

[0062] Specifically, the S5 steps include:

[0063] S501: When the external circuit or chip detects that the compensation clock signal is 0, it does not send the second control signal to the second control sub-circuit 5.

[0064] S502: When the external circuit or chip detects that the compensation clock signal is not 0, it sends a second control signal to the second control sub-circuit 5. Under the control of the second control signal, the second control sub-circuit 5 transmits the compensation clock signal to the gate drive circuit 9.

[0065] Thirdly, embodiments of this disclosure also provide a display device, which includes the clock signal generating circuit of any of the above embodiments. This display device may include any product with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are readily understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0066] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A clock self-calibration circuit, comprising: The first control sub-circuit is configured to output a sampling clock signal from the first signal terminal under the control of the first control signal. The first acquisition sub-circuit is configured to receive the acquisition clock signal and output a first voltage signal under the control of the first control sub-circuit. The second acquisition sub-circuit is configured to receive a reference clock signal and output a second voltage signal, wherein the reference clock signal is out of phase with the working clock signal; the working clock signal comes from the second signal terminal. A compensation sub-circuit is configured to obtain the compensation clock signal based on the first voltage signal and the second voltage signal; the compensation sub-circuit includes a third operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; the non-inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the fourth resistor and the first terminal of the fifth resistor, and the inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the sixth resistor and the first terminal of the seventh resistor; the output terminal of the third operational amplifier is electrically connected to the second terminal of the seventh resistor; the second terminal of the fifth resistor is connected to a reference voltage terminal; the first terminal of the fourth resistor is electrically connected to the first acquisition sub-circuit, and the first terminal of the sixth resistor is electrically connected to the second acquisition sub-circuit; The second control sub-circuit is configured to, under the control of the second control signal, control the compensation sub-circuit to receive the compensation clock signal and send the compensation clock signal to the second signal terminal; Wherein, the first signal terminal is the signal output terminal of any one of the shift registers connected to the clock signal line; the second signal terminal is the signal input terminal of any one of the shift registers connected to the clock signal line.

2. The clock self-calibration circuit according to claim 1, wherein, The first control sub-circuit includes a first control transistor; The first electrode of the first control transistor is electrically connected to the first signal terminal, the second electrode of the first control transistor is electrically connected to the first acquisition sub-circuit, and the control electrode of the first control transistor is electrically connected to the first control signal terminal.

3. The clock self-calibration circuit according to claim 1, wherein, The second control sub-circuit includes a second control transistor; The first electrode of the second control transistor is electrically connected to the output terminal of the compensation sub-circuit, the second electrode of the second control transistor is electrically connected to the second signal terminal, and the control electrode of the second control transistor is electrically connected to the second control signal terminal.

4. The clock self-calibration circuit according to claim 1, wherein, The first acquisition sub-circuit includes a first operational amplifier; The non-inverting input of the first operational amplifier is electrically connected to the first control sub-circuit, and the inverting input of the first operational amplifier is electrically connected to the first end of the first resistor, the output of the first operational amplifier, and the compensation sub-circuit.

5. The clock self-calibration circuit according to claim 4, wherein, The first acquisition sub-circuit also includes a second resistor; The first end of the second resistor is electrically connected to the output of the first operational amplifier and the compensation sub-circuit, and the second end of the second resistor is electrically connected to the first resistor.

6. The clock self-calibration circuit according to claim 1, wherein, The second acquisition sub-circuit includes a second operational amplifier and a first inverter; The input terminal of the first inverter is configured to receive the reference clock signal, and the output terminal of the first inverter is electrically connected to the non-inverting input terminal of the second operational amplifier; The inverting input terminal of the second operational amplifier is electrically connected to the second terminal of the first resistor, the output terminal of the second operational amplifier, and the compensation sub-circuit.

7. The clock self-calibration circuit according to claim 6, wherein, The second acquisition sub-circuit also includes a third resistor; The first end of the third resistor is electrically connected to the first resistor, and the second end of the third resistor is electrically connected to the output of the second operational amplifier and the compensation sub-circuit.

8. The clock self-calibration circuit according to claim 1, wherein, The compensation sub-circuit also includes a second inverter; The output terminal of the third operational amplifier is also electrically connected to the input terminal of the second inverter; The output terminal of the second inverter is electrically connected to the second control sub-circuit, and the output terminal of the second inverter is used as the output terminal of the compensation sub-circuit.

9. A clock signal generating circuit configured to provide a clock signal to a clock signal line connected to a gate drive circuit; The gate drive circuit includes multiple cascaded shift registers; The clock signal generation circuit includes: The clock self-calibration circuit according to any one of claims 1-8, and; A clock signal generation sub-circuit has a first output terminal and a second output terminal. The clock signal generation sub-circuit is configured to provide a working clock signal to the gate drive circuit through the second output terminal and to provide a reference clock signal to the clock self-calibration circuit through the first output terminal. The reference clock signal is out of phase with the working clock signal.

10. A display device comprising the clock signal generating circuit of claim 9.

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