A memory cell, related apparatus and control method

Abstract

The application discloses a memory particle, a related device and a control method. The application provides a memory particle, which can comprise a first input power supply group, a second input power supply group, X first bare chips and Y second bare chips; X and Y are integers greater than 0; wherein the first input power supply group is connected with each of the X first bare chips, and the first input power supply group is used for supplying power to each of the first bare chips by connecting a first power supply; the second input power supply group is connected with each of the Y second bare chips, and the second input power supply group is used for supplying power to each of the second bare chips by connecting a second power supply. The memory particle provided by the application can effectively reduce standby power consumption of an electronic device, improve system integration, reduce system design complexity, reduce occupation of PCB layout space and reduce product cost.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a memory chip, related devices, and control methods. Background Technology

[0002] With the development of mobile internet, electronic devices such as smartphones, tablets, and smartwatches have become widely used, and interaction with these devices has become an important form of work and entertainment. To meet increasingly complex needs, electronic devices can run a wider variety of applications, leading to a greater demand for memory capacity. However, increased memory capacity also increases standby power consumption. Since electronic devices have limited battery capacity, increased standby power consumption reduces battery life, requiring frequent charging and resulting in a poor user experience. To improve user experience, various solutions for reducing standby power consumption have been developed, but these solutions still have some issues and require further optimization.

[0003] Currently, common methods for reducing standby power consumption in electronic devices typically involve configuring a large-capacity memory chip (such as Dynamic Random Access Memory, DRAM) to meet user performance requirements, and then configuring a smaller-capacity memory chip (such as Pseudo Static Random Access Memory, PSRAM). When in standby mode, the electronic device uses only the PSRAM for memory storage, thus reducing standby power consumption. However, this method suffers from low system integration, high system design complexity, large printed circuit board (PCB) layout space, and high product cost. This contradicts the trend towards miniaturization and lightweighting of electronic devices, hindering their long-term evolution and development. Therefore, given the limited battery capacity and ever-increasing demand for memory capacity in current electronic devices, it is crucial to address how to simultaneously reduce standby power consumption and improve standby endurance while simultaneously increasing system integration, reducing system design complexity, minimizing PCB space usage, and lowering product costs. Summary of the Invention

[0004] This application provides a memory chip, related devices, and a control method that can effectively reduce the standby power consumption of electronic devices while improving system integration, reducing system design complexity, reducing PCB layout space occupation, and lowering product costs.

[0005] In a first aspect, embodiments of this application provide a memory chip, which may include a first input power supply group, a second input power supply group, X first bare dies, and Y second bare dies; each of the X first bare dies and each of the Y second bare dies is used to store data, where X and Y are both integers greater than 0; wherein, the first input power supply group is connected to each of the X first bare dies, and the first input power supply group is used to supply power to each of the first bare dies by connecting to a first power supply; the second input power supply group is connected to each of the Y second bare dies, and the second input power supply group is used to supply power to each of the second bare dies by connecting to a second power supply.

[0006] In this embodiment, a memory chip is provided that can be applied to electronic devices. Different sets of bare dies within the memory chip can be powered independently, allowing each set of bare dies to be powered on or off individually. When the electronic device enters standby mode, only a portion of the bare dies can be powered on for storage, eliminating the need to add additional memory chips for standby mode. This effectively reduces the standby power consumption of the electronic device, while also improving system integration, reducing system design complexity, minimizing PCB layout space usage, and lowering product costs. Specifically, a memory chip may include multiple sets of bare dies (e.g., two sets of bare dies, namely a set of X first bare dies and a set of Y second bare dies). When packaging the memory chip, each set of bare dies can be packaged with an independent input power group (e.g., a first input power group and a second input power group). Different power modules (e.g., a first power supply and a second power supply) in the external power management unit of different input power groups provide separate power to the corresponding set of bare dies. When the electronic device enters standby mode, the power management unit can be controlled to adjust the voltage of the power modules to power down a portion of the set of bare dies (e.g., the set of X first bare dies is powered down), and data is stored only through the partially powered-on set of bare dies (e.g., the set of Y second bare dies is powered on). This ensures that the self-refresh scale of the electronic device in standby mode is only the portion of bare dies that are powered on, thereby reducing standby power consumption. Unlike existing technologies that typically reduce standby power consumption in electronic devices by adding a small-capacity memory chip (such as a PSRAM chip) and a corresponding MCU, where the PSRAM chip is used for storage when the device enters standby mode, this approach reduces system integration, increases design complexity, occupies more PCB space, and raises product costs. Therefore, this embodiment encapsulates multiple independent input power supplies, allowing different bare die sets within the memory chip to be powered on or off independently without requiring an additional memory chip. This effectively reduces standby power consumption while improving system integration, reducing design complexity, minimizing PCB space usage, and lowering product costs. Furthermore, users can choose to use some or all of the bare dies in the electronic device for storage based on their specific needs, enhancing the user experience.

[0007] In one possible implementation, the memory chip further includes a first reset pin and a second reset pin; wherein, the first reset pin is connected to each of the X first bare wafers, and the first reset pin is used to reset each of the first bare wafers by receiving a first reset signal; the second reset pin is connected to each of the Y second bare wafers, and the second reset pin is used to reset each of the second bare wafers by receiving a second reset signal; after power-on and reset, each of the first bare wafers and each of the second bare wafers enters a normal data storage state.

[0008] In this embodiment, the memory chip can encapsulate multiple independent input power groups and also encapsulate multiple independent reset pins for multiple bare die sets. Each reset pin can receive a reset signal sent by the main processor, allowing different bare die sets in the memory chip of the electronic device to be reset separately, making the working state of different bare dies independent. When the electronic device enters standby mode, only the reset signal pins of a portion of the bare dies that have been powered down can be set to a low level to prevent leakage. When the electronic device exits standby mode and the portion of bare dies that have been powered down is powered on again, a reset signal can be sent to that portion of bare dies to enable them to enter normal working state, while the other bare dies that were originally powered on are not affected.

[0009] In one possible implementation, the memory chip is coupled to a main processor, which includes a first control module and a second control module; wherein, the first reset pin of the memory chip is connected to the first control module, and the second reset pin of the memory chip is connected to the second control module; the first control module is used to send a first reset signal to the first reset pin, and the second control module is used to send a second reset signal to the second reset pin.

[0010] In this embodiment, the main processor coupled to the memory chip may include multiple control modules, which correspond to multiple independent reset pins in the memory chip. Different control modules can send reset signals to their respective reset pins individually.

[0011] In one possible implementation, the memory chip is coupled to a power management unit (PMU), the PMU including a first power supply and a second power supply; wherein the first input power supply group of the memory chip is connected to the first power supply, and the second input power supply group of the memory chip is connected to the second power supply.

[0012] In this embodiment, the power management unit coupled to the memory chip may include multiple power modules, corresponding to multiple independent input power groups in the memory chip, and different power modules can provide voltage to their respective input power groups individually.

[0013] In one possible implementation, the first input power supply group and the second input power supply group each include N output power supplies, and each of the first bare wafers and each of the second bare wafers each includes N input power supplies, where N is an integer greater than 0; wherein, the i-th output power supply of the first input power supply group is connected to the i-th input power supply in each of the first bare wafers, and the i-th output power supply of the second input power supply group is connected to the i-th input power supply in each of the second bare wafers, where i takes the values ​​1, 2, ..., N.

[0014] In this embodiment, the memory chip can encapsulate multiple independent input power supply groups. Each input power supply group can include one or more output power supplies (such as the operating voltage VDD1 / VDD2 and input / output (IO) voltage VDDQ in Double Data Rate (DDR) memory). By adjusting the voltage of the multiple output power supplies, different bare die sets in the memory chip can have multiple different combinations of operating states, thereby enabling the electronic device to support multiple operating modes and further reduce power consumption.

[0015] In one possible implementation, the memory chip includes a dynamic random access memory (DRAM) chip, a synchronous dynamic random access memory (SDRAM) chip, a pseudo static random access memory (PSRAM) chip, or a static random access memory (SRAM) chip.

[0016] In this embodiment, the memory chip can be a DRAM chip, an SDRAM chip, a PSRAM chip, or an SRAM chip. Since the above chips have a fast read and write speed, when the electronic device uses the above chips as memory, it can meet the higher performance requirements.

[0017] Secondly, embodiments of this application provide a power management unit (PMU), which may include a first power supply and a second power supply. The PMU is coupled to a memory chip, which includes a first input power supply group, a second input power supply group, X first bare dies, and Y second bare dies. Each of the X first bare dies and each of the Y second bare dies is used to store data, where X and Y are both integers greater than 0. The first input power supply group is connected to the first power supply and is also connected to each of the X first bare dies. The first input power supply group is used to supply power to each of the first bare dies by connecting to the first power supply. The second input power supply group is connected to the second power supply and is also connected to each of the Y second bare dies. The second input power supply group is used to supply power to each of the second bare dies by connecting to the second power supply.

[0018] In this embodiment of the application, the power management unit in the electronic device for coupling with the memory chip may include multiple power modules, each power module corresponding to multiple independent input power groups in the memory chip, and different power modules can provide voltage to their respective input power groups individually.

[0019] Thirdly, embodiments of this application provide a main processor, which may include a first control module and a second control module; the main processor is coupled to memory chips, the memory chips including X first bare wafers, Y second bare wafers, a first reset pin, and a second reset pin, each of the X first bare wafers and each of the Y second bare wafers being used to store data, where X and Y are both integers greater than 0; wherein, the first reset pin is connected to each of the X first bare wafers and is also connected to the first control module; the first reset pin is used to reset each of the first bare wafers by receiving a first reset signal sent by the first control module; the second reset pin is connected to each of the Y second bare wafers and is also connected to the second control module; the second reset pin is used to receive a second reset signal sent by the second control module to reset each of the second bare wafers.

[0020] In this embodiment of the application, the main processor coupled to the memory chip in the electronic device may include multiple control modules. Each control module corresponds to multiple independent reset pins in the memory chip, and different control modules can send reset signals to their respective reset pins individually.

[0021] Fourthly, embodiments of this application provide a memory chip that may include an input power supply group, a power switch, X first bare dies and Y second bare dies, wherein each of the X first bare dies and each of the Y second bare dies is used to store data, and X and Y are both integers greater than 0; wherein the input power supply group is connected to each of the X first bare dies; the input terminal of the power switch is connected to the input power supply group, and the output terminal of the power switch is connected to each of the Y second bare dies; the input power supply group is used to supply power to each of the first bare dies and each of the second bare dies by means of an access power supply; the power switch is used to control the connection circuit between each second bare die and the input power supply group to be turned on or off.

[0022] In this embodiment, a memory chip is provided that can be used in electronic devices. Different bare die sets within the memory chip can share the same power supply. Power switches can be encapsulated on the power supply circuits of different bare die sets. By controlling the power switches, different bare die sets can be individually powered on or off. When the electronic device enters standby mode, the power switches of some bare die sets can be turned off, and only the other part of the bare die sets can be powered on for storage. This can effectively reduce the standby power consumption of the electronic device, while improving system integration, reducing system design complexity, reducing PCB layout space occupation, and reducing product costs. Specifically, a memory chip may include multiple sets of bare dies (e.g., two sets of bare dies, i.e., a set of X first bare dies and a set of Y second bare dies). When packaging the memory chip, an input power supply group and a power switch can be packaged. The input power supply group is connected to the power module in the external power management unit to supply power to the multiple sets of bare dies in the memory chip. The power switch can be set between the input power supply group and each second bare die. When the electronic device enters standby mode, the power switch can be controlled to turn off a portion of the bare die sets (e.g., the set of Y second bare dies is powered off). Data is stored only through the partially powered-on bare die sets (e.g., the set of X first bare dies is powered on), so that the self-refresh scale of the electronic device in standby mode is only the portion of bare dies that are powered on, thereby reducing standby power consumption. In existing technologies, because different bare dies in the same memory chip (such as a DRAM chip) share the same input power supply group and the same reset signal pin, multiple bare dies in the memory chip can only be in a self-refresh state at the same time when the electronic device enters standby mode. That is to say, when the electronic device enters standby mode, the self-refresh scale of the electronic device covers all bare dies in the entire memory chip. Therefore, in order to reduce standby power consumption, existing technologies generally add an extra small-capacity memory chip (such as a PSRAM chip) and a corresponding MCU. When the electronic device enters standby mode, it only uses the PSRAM chip for storage. Although this achieves the goal of reducing standby power consumption, it also reduces system integration, increases system design complexity, occupies more PCB layout space, and increases product cost. In this embodiment, by adding a power switch, different sets of bare chips in the memory chip can be powered on and off independently without the need for an additional memory chip. This can effectively reduce the standby power consumption of electronic devices, while improving system integration, reducing system design complexity, reducing the space occupied by PCB layout, and reducing product costs. In addition, users can also determine whether to use some or all of the bare chips in the electronic device for storage according to actual needs, thereby improving the user experience.

[0023] In one possible implementation, the memory chip further includes a first reset pin and a second reset pin; wherein, the first reset pin is connected to each of the X first bare wafers, and the first reset pin is used to reset each of the first bare wafers by receiving a first reset signal; the second reset pin is connected to each of the Y second bare wafers, and the second reset pin is used to reset each of the second bare wafers by receiving a second reset signal; after power-on and reset, each of the first bare wafers and each of the second bare wafers enters a normal data storage state.

[0024] In one possible implementation, the memory chip is coupled to a main processor, which includes a first control module and a second control module; wherein, the first reset pin of the memory chip is connected to the first control module, and the second reset pin of the memory chip is connected to the second control module; the first control module is used to send a first reset signal to the first reset pin, and the second control module is used to send a second reset signal to the second reset pin.

[0025] In one possible implementation, the memory chip is coupled to a power supply unit (PMU), the PMU including a power supply module; wherein the input power supply group of the memory chip is connected to the power supply module.

[0026] In one possible implementation, the input power supply group includes N output power supplies, each first bare die and each second bare die each include N input power supplies, and the number of power switches is N, where N is an integer greater than 0; wherein, the i-th output power supply of the first input power supply group is connected to the i-th input power supply in each first bare die, the input terminal of the i-th power switch among the N power switches is connected to the i-th output power supply of the input power supply group, and the output terminal of the i-th power switch is connected to the i-th input power supply in each second bare die, where i takes the values ​​1, 2, ..., N.

[0027] In one possible implementation, the memory chip includes a dynamic random access memory (DRAM) chip, a synchronous dynamic random access memory (SDRAM) chip, a pseudo static random access memory (PSRAM) chip, or a static random access memory (SRAM) chip.

[0028] Fifthly, embodiments of this application provide an electronic device comprising a memory chip provided in any of the first aspects described above; the electronic device further comprises a main processor and a power management unit, the main processor and the power management unit being coupled to the memory chip respectively; wherein, the main processor is configured to receive control instructions and, based on the control instructions, control the PMU to adjust the voltage provided to X first bare wafers and / or Y second bare wafers of the memory chip; the electronic device further comprises internal memory and external memory, the internal memory and the external memory being configured to store program instructions and data necessary for the operation of the main processor and the PMU; the electronic device may further comprise a communication interface for communication between the electronic device and other devices or communication networks.

[0029] Sixthly, embodiments of this application provide a control method applicable to any of the electronic devices provided in the fifth aspect above. The method includes: when X first bare wafers and Y second bare wafers in the memory chip are in a normal data storage state, receiving control instructions through the main processor; and controlling the PMU to adjust the voltage supplied to the X first bare wafers and / or the Y second bare wafers based on the control instructions.

[0030] In this embodiment, different sets of bare dies within the memory chip of an electronic device can be powered independently, allowing each set to be powered on or off individually. When the electronic device enters standby mode, only a portion of the bare dies can be powered on for storage, effectively reducing standby power consumption, improving system integration, reducing system design complexity, minimizing PCB layout space usage, and lowering product costs. Specifically, the memory chip may include multiple sets of bare dies (e.g., two sets, consisting of X sets of first bare dies and Y sets of second bare dies). These sets are in normal data storage mode. When the main processor receives a control command (indicating entry into standby mode), it determines the required operating state of each set of bare dies in standby mode and controls the PMU to adjust the voltage of the power module corresponding to each set, thus entering standby mode. When the electronic device provided in this embodiment uses the control method provided to control the memory chip, the control logic is simplified, the requirements for the power supply circuit are reduced, and the applicability of the memory chip is improved.

[0031] In a seventh aspect, embodiments of this application provide an electronic device comprising a memory chip provided in any of the fourth aspects described above; the electronic device further comprises a main processor and a power management unit, the main processor and the power management unit being coupled to the memory chip respectively; wherein, the main processor is used to receive control instructions and control the power switch to be turned on or off based on the control instructions, and to control whether the PMU can provide voltage to Y second bare wafers of the memory chip; the electronic device further comprises an internal memory and an external memory, the internal memory and the external memory being used to store program instructions and data necessary for the operation of the main processor and the PMU; the electronic device may also include a communication interface for the electronic device to communicate with other devices or communication networks.

[0032] Eighthly, embodiments of this application provide a control method applicable to any of the electronic devices provided in the seventh aspect above. The method includes: when X first bare wafers and Y second bare wafers in the memory chip are in a normal data storage state, receiving control instructions through the main processor; controlling the on / off state of a power switch based on the control instructions, and controlling whether the PMU can provide voltage to the Y second bare wafers of the memory chip.

[0033] In this embodiment, different sets of bare dies within the memory chip of an electronic device can be individually powered on or off via a power switch. When the electronic device enters standby mode, only a portion of the bare dies can be powered on for storage, thereby effectively reducing the standby power consumption of the electronic device. Simultaneously, it can improve system integration, reduce system design complexity, decrease PCB layout space usage, and lower product costs. Specifically, the memory chip may include multiple sets of bare dies (e.g., two sets of bare dies, i.e., a set including X first bare dies and a set including Y second bare dies). The power switch is located between the input power supply group and each second bare die, where the X first bare dies and Y second bare dies share the input power supply group. When multiple sets of bare dies are in normal data storage state, when the main processor receives a control command (indicating entry into standby mode), the main processor can determine the required operating state of each set of bare dies in standby mode based on the control command, thereby controlling the on / off state of the power switch, so that some sets of bare dies are powered on while others are powered off. When the electronic device provided in this application uses the control method provided in this application to control the memory chip, the control logic can be simplified, the requirements of the memory chip on the voltage supply circuit can be reduced, and the applicability of the memory chip can be improved.

[0034] Ninthly, embodiments of this application provide a semiconductor chip, which includes memory chips provided in any of the first and fourth aspects described above, as well as possible implementations combining the first and fourth aspects.

[0035] In a tenth aspect, this application provides a computer storage medium storing a computer program that, when executed by an electronic device provided in any of the fifth or seventh aspects and in combination with any possible implementation of the fifth or seventh aspects, enables the electronic device to execute the control method flow described in any of the sixth or eighth aspects.

[0036] In the eleventh aspect, embodiments of this application provide a computer program including instructions that, when executed by an electronic device provided in any of the fifth or seventh aspects and in combination with possible implementations of the fifth or seventh aspects, cause the electronic device to execute the control method flow described in any of the sixth or eighth aspects.

[0037] In a twelfth aspect, this application provides a chip system comprising memory chips provided in any of the first and fourth aspects described above, as well as possible implementations combining the first and fourth aspects. In one possible design, the chip system further includes a processor, internal memory, and external memory, the internal and external memory being used to store necessary or related program instructions and data of the memory chips and the processor. This chip system may be composed of chips or may include chips and other discrete devices.

[0038] In a thirteenth aspect, this application provides a System-on-a-Chip (SOC) chip, which includes a memory chip provided in any of the first and fourth aspects described above, as well as possible implementations combining the first and fourth aspects, a processor coupled to the memory chip, internal memory, and external memory. The internal and external memory are used to store program instructions and data necessary or related to the operation of the memory chip and the processor. This SOC chip can be composed of a single chip or may include chips and other discrete devices. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments or background art of this application, the accompanying drawings used in the embodiments or background art of this application will be described below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the memory structure of an electronic device in the prior art.

[0041] Figure 2 This is a schematic diagram of a power supply structure for memory chips in the existing technology.

[0042] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0043] Figure 4a This is a schematic diagram of the structural topology of a single-channel DRAM chip provided in an embodiment of this application.

[0044] Figure 4b This is a schematic diagram of a single-channel DRAM chip stack provided in an embodiment of this application.

[0045] Figure 5a This is a schematic diagram of the structural topology of a multi-channel DRAM chip provided in an embodiment of this application.

[0046] Figure 5b This is a schematic diagram of a multi-channel DRAM chip stack provided in an embodiment of this application.

[0047] Figure 6 This is a stacking diagram of another single-channel DRAM chip provided in an embodiment of this application.

[0048] Figure 7 This is a stacking diagram of another multi-channel DRAM chip provided in an embodiment of this application.

[0049] Figure 8 This is a flowchart illustrating a DRAM chip control method provided in an embodiment of this application.

[0050] Figure 9 This is a flowchart illustrating another DRAM chip control method provided in an embodiment of this application. Detailed Implementation

[0051] The embodiments of this application will now be described with reference to the accompanying drawings.

[0052] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0053] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in one or more embodiments of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0054] First, some of the terms used in this application will be explained to facilitate understanding by those skilled in the art.

[0055] (1) Memory chips, channels, ranks, dies, and banks. A memory chip typically includes one or more dies, and a die typically includes one or more banks and one or more control circuits. Memory chips interact with processors (such as central processing units (CPUs), graphics processing units (GPUs), systems-on-a-chip, or microcontrollers) via a data bus. The data bus has interface bit width limitations, typically 16-bit, 32-bit, or 64-bit. Logically, memory chips can support single-channel, 2-channel, or 4-channel configurations. Each channel can include one or more ranks, and each rank consists of one or more dies. A rank refers to dies connected to the same chip select (CS). Each rank has its own data bus. When a single channel includes multiple ranks, only one rank can interact with the processor within one clock cycle. In this embodiment, by individually powering different bare chips in the memory chips of the electronic device, when the electronic device enters standby mode, only a portion of the bare chips can be powered on, while the other portion of bare chips are powered off. This allows the bare chips that are powered on in standby mode to self-refresh, thereby reducing the standby power consumption of the electronic device and improving its standby battery life.

[0056] (2) Self-Refresh (SR) is a refresh mode of dynamic memory, typically used to retain data in standby mode. In self-refresh mode, dynamic memory generally disables all external clocks and input buffers (except for the clock enable signal (ClockEnable, CKE)). For example, DDR will disable the external clock channel. Typically, after giving the command to exit self-refresh mode, a certain number of idle input cycles are maintained to ensure the device completes the exit from self-refresh mode. Generally, the shorter the self-refresh cycle, the more frequent the self-refresh operation, and the greater the power consumption. To save power, the self-refresh cycle is usually lengthened as much as possible. However, an excessively long cycle also has drawbacks; if it is insufficient to retain the contents of the dynamic memory, data loss will occur. Besides the self-refresh cycle affecting standby power consumption, the scale of the self-refresh also affects standby power consumption; the larger the scale of the self-refresh, the greater the standby power consumption. In this embodiment, by individually powering different bare chips in the memory chips of the electronic device, when the electronic device enters standby mode, only a portion of the bare chips can be powered on, while the other portion of bare chips is powered off. This allows the bare chips that are powered on to perform self-refresh in standby mode, while the other portion of bare chips that are completely powered off do not perform self-refresh, thus reducing the scale of self-refresh and thereby reducing the standby power consumption of the electronic device and improving its standby battery life.

[0057] (3) The reset signal, generated by the reset circuit, is used to enable the dynamic memory to start working from its initial state within a short period after receiving power. If the dynamic memory starts working without being reset after receiving power, it may malfunction due to interference. The reset circuit can be composed of a dedicated integrated circuit or discrete components. Generally, a low-level reset can be used (i.e., a low-level signal is applied to the reset terminal of the dynamic memory at the moment of power-on, and then switched to a high level when the dynamic memory is working normally). Of course, a high-level reset can also be used (i.e., a high-level signal is applied to the reset terminal of the dynamic memory at the moment of power-on, and then switched to a low level when the dynamic memory is working normally). In the embodiments of this application, by resetting different bare chips in the memory chips of the electronic device separately, the working states of different bare chips are independent. After the electronic device enters standby mode, only the reset signal pin of a portion of the bare chips that have been powered down can be set to a low level to prevent leakage. When the electronic device exits standby mode and the portion of bare chips that have been powered down is powered on again, a reset signal can be sent to that portion of bare chips to enable it to enter the normal working state, while the other bare chips that were originally powered on are not affected.

[0058] First, the technical problem to be solved in this application is analyzed and proposed. In the prior art, a common method to reduce the standby power consumption of electronic devices is to configure a small-capacity memory chip (such as a PSRAM chip) on the basis of configuring a large-capacity memory chip (such as a DRAM chip). In standby mode, the electronic device only uses the PSRAM chip for storage, so as to reduce the standby power consumption.

[0059] The above-mentioned solutions for reducing standby power consumption of electronic devices have the following drawbacks:

[0060] The system suffers from low integration, high design complexity, large PCB layout space, and high product cost. (See also...) Figure 1 , Figure 1This is a schematic diagram of the memory structure of an existing electronic device, which can include two storage methods: one is a System-on-Chip (SOC) and DRAM chips, and the other is a Microcontroller Unit (MCU) and PSRAM chips, all powered by a Power Management Unit (PMU). Typically, PSRAM chips have a capacity of 64MB, and DRAM chips have a capacity of 1-2GB. Regardless of whether it's PSRAM or DRAM, the standby power consumption of the electronic device is closely related to their capacity; the larger the capacity, the higher the standby power consumption. Based on this structure, when the electronic device needs to use a large memory capacity (such as running a large operating system like Android, or opening many programs), it uses the SOC and DRAM storage method, while shutting down the MCU and PSRAM. When the electronic device enters standby mode, because the requirements for capacity and performance are lower (such as when Android operating system support is not needed or fewer programs are running), it can use only the MCU and PSRAM storage method, while shutting down the SOC and DRAM, thereby reducing standby power consumption. However, the above structure requires the addition of PSRAM on top of the DRAM chips for storage, which leads to the need for an additional MCU and PSRAM interface in the system (e.g., SOC needs to add a protocol interface related to the MCU, and PMU needs to add power supply interfaces for PSRAM and MCU). Among them, the MCU generally has about 50 signals and 4 to 5 power supply channels, and the PSRAM generally has about 20 signals and 1 power supply channel. This increases the design complexity of the system and reduces the system integration. Furthermore, the need to add MCU and PSRAM devices and external resistors and capacitors on the PCB will undoubtedly increase the cost of the product, and it also contradicts the trend of miniaturization and lightweight development of electronic devices. If the MCU and PSRAM can be removed, the product cost can be reduced, and the PCB space can be saved for increasing battery capacity or placing devices that realize other functions, or further integration to reduce the product size.

[0061] To address the problems of low system integration, high system design complexity, large PCB layout space, and high product cost associated with existing solutions that involve adding an additional MCU and PSRAM to reduce standby power consumption, this application comprehensively considers the shortcomings of existing technologies and aims to solve the following technical problems:

[0062] In this application, a memory chip architecture is proposed where different bare dies can be powered and controlled independently. Specifically, the memory chip can support a single channel (Channel), where each channel includes multiple ranks, or it can support multiple channels (e.g., 2-channel, 4-channel, etc.), where each channel includes multiple ranks. Each rank can include one or more bare dies. When the memory chip supports a single channel with multiple ranks, the bare dies in different ranks of the memory chip can be powered and controlled independently, i.e., the ranks of the memory chip are used as the unit of power supply and control. When the memory chip supports multiple channels with one or more ranks, the bare dies in different ranks of the memory chip can be powered and controlled independently, i.e., the ranks of the memory chip are used as the unit of power supply and control. Alternatively, the bare dies in different channels of the memory chip can be powered and controlled independently, i.e., the channels of the memory chip are used as the unit of power supply and control. Based on the aforementioned architecture of separate power supply and control, when an electronic device enters standby mode, some bare chips in the memory chips can be powered down, while only the powered-on bare chips perform storage. This ensures that the self-refresh scale of the electronic device in standby mode is limited to the powered-on bare chips, thereby reducing standby power consumption. This differs from existing technologies, as can be seen in [reference needed]. Figure 2 , Figure 2This is a schematic diagram of a power supply structure for a memory chip in the prior art. Different bare dies within the same memory chip (such as a DRAM chip) share a common power supply and a common reset signal line. For example, when the memory chip supports a single channel, that channel can include multiple columns (such as Rank0 and Rank1), and each column can include one or more bare dies; or the memory chip supports multiple channels (such as channel A and channel B), and each channel can include one or more columns (such as Rank0 and Rank1 included in channel A and Rank0 and Rank1 included in channel B). Regardless of whether the memory chip supports single-channel or multi-channel operation, different channels or... In electronic devices, bare dies in different columns share power and reset signal lines. This means that multiple bare dies in the memory chip can only simultaneously store data, self-refresh, or power down. Therefore, when the electronic device enters standby mode, the self-refresh process covers all bare dies in the entire memory chip. To reduce standby power consumption, existing technologies add a small-capacity memory chip (such as a PSRAM chip) and a corresponding MCU, which reduces system integration, increases system design complexity, requires more PCB layout space, and raises product costs. A better approach would be to use only the PSRAM chip for storage when the electronic device enters standby mode. Since the capacity of a PSRAM chip is smaller than that of a DRAM chip, using only the PSRAM chip for storage reduces standby power consumption.

[0063] In summary, existing solutions that involve adding an MCU and PSRAM to reduce standby power consumption result in low system integration, high system design complexity, large PCB layout space, and high product costs, making it difficult to meet the demand for miniaturized and lightweight electronic devices. Therefore, the DRAM chip provided in this application can be used to solve the above-mentioned technical problems.

[0064] To better understand the memory chips provided in the embodiments of this application, the structure and application scenarios of the memory chips provided in the embodiments of this application will be described by way of example below. It is understood that the structure and application scenarios of the memory chips described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application.

[0065] See also Figure 3 , Figure 3This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 01 provided in this application may include one or more main processors 11, one or more DRAM chips 12, and one or more power management units 13, and may also include internal memory and external memory (not shown in the figure). The electronic device 01 may be a subscriber unit, a cellular phone, a smartphone, a personal digital assistant (PDA) computer, a tablet computer, a handset, a laptop computer, a machine type communication (MTC) terminal, a smart wearable device, a smart speaker, or other mobile smart terminals.

[0066] The main processor 11 is connected to the memory chip 12, the power management unit 13, and internal and external memory (not shown in the figure). The main processor 11 can be a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller (MCU), or a chip with other functions. The main processor 11 can be used to receive control commands, send reset signals, send control signals, and perform other necessary calculations. In this embodiment, the main processor 11 can receive control commands, which can be triggered by the user or when certain conditions are met (such as when the power management unit 13's remaining power reaches a certain threshold). The main processor 11 can send reset signals and control signals to the memory chip 12, enabling the memory chip 12 to start working from its initial state or enter a sleep state within a short period after receiving power. The main processor 11 can also send control signals to the power management unit 13, enabling the power management unit to adjust the voltage provided to different bare wafers in the memory chip 12.

[0067] Memory chips 12 are connected to the main processor 11, the power management unit 13, and internal and external memory (not shown in the figure), respectively. Memory chips 12 can be DRAM chips, PSRAM chips, or Static Random Access Memory (SRAM) chips, or other chips used for storage. The memory chip 12 can be a single-channel chip, where each channel includes multiple rows, each row including one or more bare dies, each bare die being used to store data; or it can be a multi-channel chip, where each channel includes one or more rows, each row including one or more bare dies, each bare die being used to store data. In this embodiment, when the memory chip 12 is packaged, different bare dies (which can be in units of channels or rows) can receive power from different power pins, and different bare dies can also receive control signals (including reset signals, clock signals, etc.) from different control pins (including reset pins, clock pins, etc.), meaning that different bare dies can be powered and controlled independently. The bare die in memory chip 12 can enter or exit the hibernation state after receiving a reset signal from the main processor 11, in order to match the normal operation mode or standby mode of electronic device 01.

[0068] The power management unit 13 is connected to the main processor 11, the memory chip 12, and the internal and external memory (not shown in the figure). The power management unit 13 can supply power to the main processor 11, the memory chip 12, and the internal and external memory (not shown in the figure). The power management unit 13 can also receive control signals from the main processor 11 and adjust the voltage provided to different bare wafers in the memory chip 12 based on the control signals.

[0069] Internal and external memory (not shown in the figure) are used to store programs and instructions necessary for the operation of the main processor 11, memory chips 12, and power management unit 13. Internal and external memory may include one or more local memories, one or more registers, one or more L1 caches, one or more L2 caches, and various types of buffers.

[0070] The following description will use DRAM chips as an example of the memory chip 12 described above. It is understood that the structure and application scenarios of DRAM chips are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application.

[0071] To facilitate understanding of the DRAM chip structure provided in the embodiments of this application, the following description will first take an example where the DRAM chip supports a single channel, which includes multiple ranks, each rank including one or more dies, and each rank can be independently powered on and off. See also... Figure 4a , Figure 4a This is a schematic diagram of the structural topology of a single-channel DRAM chip provided in an embodiment of this application. The DRAM chip supports a single channel (i.e., channel A). For ease of understanding, this is taken as an example where the single channel includes two columns (Rank0 and Rank1). Rank0 includes one or more bare dies (i.e., X first bare dies), and Rank1 includes one or more bare dies (i.e., Y second bare dies). The one or more bare dies in Rank0 share one power module (i.e., the first power supply) of the power management unit 13, and the one or more bare dies in Rank1 share another power module (i.e., the second power supply) of the power management unit 13, allowing the DRAM chip to be powered on or off in units of columns (Rank). For details on the internal connections of the DRAM chip, please refer to [link to relevant documentation]. Figure 4b , Figure 4bThis is a stacking diagram of a single-channel DRAM chip provided in an embodiment of this application. The DRAM chip includes Rank0 and Rank1, which belong to the same channel (i.e., channel A). During packaging, the DRAM chip can include two independent input power supply groups (i.e., a first input power supply group and a second input power supply group). The first input power supply group supplies power to the bare dies in Rank0 alone, and the second input power supply group supplies power to the bare dies in Rank1 alone. Optionally, the first input power supply group may include two output power supplies (e.g., VDD1-1, VDD2-1), and the second input power supply group may include two output power supplies (e.g., VDD1-2, VDD2-2). Correspondingly, each bare die in Rank0 may include two input power supplies (for connecting VDD1-1, VDD2-1), and each bare die in Rank1 may include two input power supplies (for connecting VDD1-2, VDD2-2). Understandably, each power supply (including output power and input power) may include one or more power pins. It should be noted that, in addition to the power supply pins of the first and second input power supply groups, DRAM chips may also include other power supply pins (such as ground pins, VDDQ), as well as other pins used for data transmission (DQ, such as DQ[15:0]) and signal control, such as data strobe (DQS, such as DQS[1:0]_T / C_A), chip select (CS, such as CS0_A, CS1_A), calibration (ZQ, such as ZQ0_A, ZQ1_A), clock enable (CKE, such as CKE0_A, CKE1_A), clock (CK, such as CK_t / c_A), address (CA, such as CA[5:0]_A), data mask (DM, such as DM[1:0]_A) and reset, etc. It should be noted that the first and second input power supply groups mentioned above may each include more or fewer output power supplies, such as only including VDD1 (i.e., VDD1-1 and VDD1-2) or VDD2 (i.e., VDD2-1 and VDD2-2), or a combination of VDD1, VDD2, and VDDQ, without specific limitations here. It should also be noted that the memory capacity of Rank 0 including one or more bare dies (i.e., X first bare dies) and the memory capacity of Rank 1 including one or more bare dies (i.e., Y second bare dies) may be the same or different, without specific limitations here.

[0072] Optionally, the two columns (Rank0 and Rank1) in a single channel of the aforementioned DRAM chip can be reset independently without interference. For example, during packaging, the aforementioned DRAM chip can also include two sets of independent reset pins (i.e., a first reset pin and a second reset pin). The first reset pin resets each die in Rank0 individually by receiving a reset signal (i.e., a first reset signal), and the second reset pin resets each die in Rank1 individually by receiving a reset signal (i.e., a second reset signal). Specifically, one or more dies in Rank0 share one control module of the main processor 11 (i.e., a first control module, not shown in the figure), and one or more dies in Rank1 share another control module of the main processor 11 (i.e., a second control module, not shown in the figure), so that the DRAM chip can be reset individually by column (Rank). That is to say, when one or more dies in Rank0 are reset, one or more dies in Rank1 can continue to work without being affected by the Rank0 reset signal (i.e., the first reset signal). Understandably, the main processor described above controls two bare die sets (i.e., Rank0 and Rank1) by setting up two different control modules to send reset signals to two reset pins respectively; of course, the main processor can also set up only one control module to send reset signals to two reset pins respectively to control two bare die sets (i.e., Rank0 and Rank1), and no specific limitation is made here.

[0073] Next, taking a DRAM chip supporting multiple channels, where each channel includes multiple ranks, each rank includes one or more dies, and each channel can be independently powered on and off as an example, further illustrative examples will be provided. See also... Figure 5a , Figure 5a This is a schematic diagram of the structural topology of a multi-channel DRAM chip provided in an embodiment of this application. For ease of understanding, it is assumed that the DRAM chip supports 2 channels, and each channel includes two columns (such as Rank0 and Rank1 in channel A, and Rank0 and Rank1 in channel B). Rank0 and Rank1 include one or more bare dies (i.e., X first bare dies), and Rank0 and Rank1 also include one or more bare dies (i.e., Y second bare dies). In channel A, one or more bare dies in Rank0 and Rank1 (i.e., X first bare dies) share one power module (i.e., the first power supply) of the power management unit 13, and in channel B, one or more bare dies in Rank0 and Rank1 (i.e., Y second bare dies) share another power module (i.e., the second power supply) of the power management unit 13, allowing the DRAM chip to be powered on or off on a channel-by-channel basis. For details on the internal connections of the DRAM chip, please refer to [link to relevant documentation]. Figure 5b , Figure 5b This is a stacking diagram of a multi-channel DRAM chip provided in an embodiment of this application. The DRAM chip supports two channels. Channel A includes Rank0 and Rank1, and channel B includes Rank0 and Rank1. During packaging, the DRAM chip can include two independent input power supply groups (i.e., a first input power supply group and a second input power supply group). The first input power supply group supplies power to the bare die in channel A, and the second input power supply group supplies power to the bare die in channel B. Understandably, the first and second input power supply groups can each include one or more output power supplies. Correspondingly, each bare die in channel A and channel B can each include one or more input power supplies, as described above for a single-channel DRAM chip, and will not be repeated here. It should be noted that, in addition to the power supply pins of the first and second input power supply groups, the multi-channel DRAM chip can also include other power supply pins (such as ground pins, VDDQ), and other pins for data transmission and signal control. It should also be noted that... Figure 5b The example provided uses a combination of VDD1 and VDD2 as the first and second input power groups. The first and second input power groups may also include more or fewer output power sources, such as only including VDD1 (i.e., VDD1-1 and VDD1-2) or VDD2 (i.e., VDD2-1 and VDD2-2), or including a combination of VDD1, VDD2 and VDDQ. No specific limitation is made here.

[0074] Optionally, each channel in the multi-channel DRAM chip described above can be reset independently without interference. For example, during packaging, the DRAM chip may also include two sets of independent reset pins (i.e., a first reset pin and a second reset pin). The first reset pin resets each die in channel A individually by receiving a reset signal (i.e., a first reset signal), and the second reset pin resets each die in channel B individually by receiving a reset signal (i.e., a second reset signal). (Refer to the above.) Figure 4b The description will not be repeated here.

[0075] Next, we will take the example of a DRAM chip supporting multiple channels, each channel including multiple ranks, each rank including one or more dies, and different ranks in different channels being able to be powered on and off independently, to further illustrate the point. For ease of understanding, let's take the DRAM chip that supports 2 channels as an example. Each channel in the 2 channels includes two columns (such as Rank0 and Rank1 in channel A, and Rank0 and Rank1 in channel B). Rank0 in channel A includes one or more bare dies, and Rank1 in channel A includes one or more bare dies (i.e., X first bare dies). Rank0 in channel B includes one or more bare dies, and Rank1 in channel B includes one or more bare dies (i.e., Y second bare dies). The one or more bare dies in Rank1 of channel A (i.e., X first bare dies) share one power module (i.e., the first power supply) of the power management unit 13. The one or more bare dies in Rank1 of channel B (i.e., Y second bare dies) share another power module (i.e., the second power supply) of the power management unit 13. Rank0 in channel A and Rank0 in channel B each include one or more bare dies that can share other power modules of the power management unit 13 (such as the third power supply and the fourth power supply), so that different columns (ranks) in different channels of the DRAM chip can be powered on or off independently. Regarding the specific internal connections of a DRAM chip, taking a 2-channel DRAM chip as an example, channel A includes Rank 0 and Rank 1, and channel B also includes Rank 0 and Rank 1. During packaging, the DRAM chip can include two independent input power groups (i.e., a first input power group and a second input power group). The first input power group supplies power to each die in Rank 1 of channel A, and the second input power group supplies power to each die in Rank 1 of channel B. Furthermore, other independent input power groups (such as a third and fourth input power group) can be packaged within the DRAM chip to supply power to other columns (Ranks). Understandably, the first and second input power groups can each include one or more output power supplies. Correspondingly, each die in channel A and channel B can each include one or more input power supplies. Refer to the description of a single-channel DRAM chip above; it will not be repeated here. It should be noted that multi-channel DRAM chips may include other pins besides the power pins of the first and second input power groups; these will not be elaborated upon here.It should also be noted that the above example uses the combination of VDD1 and VDD2 in the first and second input power groups as an example. The first and second input power groups can also include more or fewer output power sources, such as only including VDD1 (i.e., VDD1-1 and VDD1-2) or VDD2 (i.e., VDD2-1 and VDD2-2), or including a combination of VDD1, VDD2 and VDDQ. No specific limitation is made here.

[0076] Optionally, different ranks within different channels of the aforementioned DRAM chip can be reset independently without interference. For example, during packaging, the aforementioned DRAM chip can also include two sets of independent reset pins (i.e., a first reset pin and a second reset pin). The first reset pin, by receiving a reset signal (i.e., a first reset signal), resets each die in Rank 1 of channel A (i.e., each of the X first dies) individually. The second reset pin, by receiving a reset signal (i.e., a second reset signal), resets each die in Rank 1 of channel B (i.e., each of the Y second dies) individually. (Refer to the above.) Figure 4b The relevant descriptions will not be repeated here. Understandably, when packaging DRAM chips, separate reset pins (such as the third reset pin and the fourth reset pin) can be packaged for Rank0 in channel A and Rank0 in channel B. This allows each column in each channel to be reset independently without interference. That is to say, when one or more bare dies in Rank1 in channel A are reset, one or more bare dies in Rank0 in channel A, Rank0 in channel B, and Rank1 in channel B can continue to work without being affected by the Rank1 reset signal (i.e., the first reset signal) of channel A.

[0077] As described above, DRAM chips can achieve independent power supply to bare dies in different ranks or channels by including at least two independent input power groups in the package. This allows the electronic device to power only the bare dies in a portion of the ranks or channels when entering standby mode, while powering down the bare dies in other ranks or channels, thereby reducing standby power consumption and improving standby battery life. It should be noted that the independent power-on or power-off of a rank or channel is related to the independent input power groups. When there are more than two ranks or channels in the memory chip 12 that require independent power-on or power-off, the number of independent input power groups can be increased accordingly, without specific limitations here.

[0078] In addition, this application also provides a memory chip 12 that allows power to be supplied to bare dies in a portion of a row or channel while the other portion of the row or channel is powered off by setting a power switch to control the conduction or disconnection of power supply circuits in different rows or channels. For ease of understanding, the following description still uses a DRAM chip as an example.

[0079] First, let's take a DRAM chip supporting a single channel, where the channel includes multiple ranks, each rank includes one or more dies, and each rank can be independently powered on and off, as an example for further illustration. See also... Figure 6 , Figure 6This is a stacking diagram of another single-channel DRAM chip provided in this application embodiment. The DRAM chip supports a single channel (i.e., channel A). For ease of understanding, this is taken as an example where the single channel (channel A) includes two columns (Rank0 and Rank1). Rank0 includes one or more bare dies (i.e., X first bare dies), and Rank1 includes one or more bare dies (i.e., Y second bare dies). When the DRAM chip is packaged, an input power supply group and a power switch can be packaged. The input power supply group is used to access power from a power module of the power management unit 13 to power the bare dies of Rank0 and Rank1. That is, one or more bare dies in Rank0 and one or more bare dies in Rank1 share a power module of the power management unit 13. The power switch can be set between the input power supply group and each bare die in Rank1 (i.e., each second bare die), so that Rank1 in the DRAM chip can be powered down independently. Optionally, the input power supply group may include two output power supplies (such as VDD1 and VDD2). Correspondingly, each bare die in Rank 0 and each bare die in Rank 1 may each include two input power supplies (for connecting VDD1 and VDD2). Each power supply (including output power and input power) may include one or more power pins. The specific number of power switches can be the product of the number of power supply paths and the number of power pins per power supply. For ease of understanding, taking one power pin per power supply as an example, the number of power switches is equal to the number of power supply paths (i.e., two power switches, used to control the conduction or disconnection of the VDD1 and VDD2 circuits). It should be noted that in addition to the power pins of the input power supply group, the DRAM chip may also include other power pins (such as ground pins, IO voltage VDDQ), and may also include other pins used for data transmission and signal control, which will not be elaborated here. It should also be noted that the above-mentioned input power supply group may also include more or fewer output power supplies, such as only including VDD1 or VDD2, or including a combination of VDD1, VDD2, and VDDQ, which is not specifically limited here. It should also be noted that the power supply of the above power switch can share the power supply of Rank0. The control logic for the power switch can be based on the control instruction set of Rank0 with a small number of control commands (such as power switch commands). In order to ensure that the above power switch is always in a controllable state when the electronic device is running, Rank0 will always be powered on.Optionally, if it is necessary to enable the electronic device to power down any column, the number of power switches in the DRAM chip can be increased according to the number of columns. Taking Rank0 and Rank1 as examples, the power switches can be set between the input power group and each bare die in Rank0 (i.e., each first bare die) and each bare die in Rank1 (i.e., each second bare die), so that different columns (Rank) in the DRAM chip can be powered on or off independently. In this case, the power switch does not share the power supply with any column (Rank).

[0080] Optionally, the two columns (Rank0 and Rank1) in a single channel of the aforementioned DRAM chip can be reset independently without interference. For example, during packaging, the aforementioned DRAM chip can also include two sets of independent reset pins (i.e., a first reset pin and a second reset pin). The first reset pin resets each die in Rank0 individually by receiving a reset signal (i.e., a first reset signal), and the second reset pin resets each die in Rank1 individually by receiving a reset signal (i.e., a second reset signal). (Refer to the above.) Figure 4b The description will not be repeated here.

[0081] Next, taking a DRAM chip supporting multiple channels, where each channel includes multiple ranks, each rank includes one or more dies, and each channel can be independently powered on and off as an example, further illustrative examples will be provided. See also... Figure 7 , Figure 7This is a stacking diagram of a multi-channel DRAM chip provided in an embodiment of this application. For ease of understanding, it is assumed that the DRAM chip supports 2 channels, and each channel in the 2 channels includes two columns (such as Rank0 and Rank1 in channel A, and Rank0 and Rank1 in channel B). Rank0 and Rank1 in channel A include one or more bare dies (i.e., X first bare dies), and Rank0 and Rank1 in channel B include one or more bare dies (i.e., Y second bare dies). When the DRAM chip is packaged, an input power supply group and a power switch can be packaged. The input power supply group is used to connect to a power module of the power management unit 13 to supply power to the bare dies of channel A and channel B. That is, one or more bare dies in channel A and one or more bare dies in channel B share a power module of the power management unit 13. The power switch can be set between the input power supply group and each bare die (i.e., each second bare die) in channel B, so that channel B in the DRAM chip can be powered down independently. Understandably, the input power supply group can include one or more output power supplies (the diagram uses two outputs, VDD1 and VDD2, as an example). Each power supply can include one or more power pins. In this case, the specific number of power switches can be the product of the number of power supply paths and the number of power pins per power supply. It should be noted that the DRAM chip can also include other power pins, data pins, and control pins; the input power supply group can also include more or fewer output power supplies; the power supply for the power switches can share the power supply of channel A; optionally, the number of power switches can be configured according to the number of channels that need to be independently powered down. For information on other pins of the DRAM chip, the number of output power supply paths in the input power supply group, and the number of power switches, please refer to the above. Figure 6 The relevant descriptions will not be repeated here.

[0082] Optionally, each channel in the multi-channel DRAM chip described above can be reset independently without interference. For example, during packaging, the DRAM chip may also include two sets of independent reset pins (i.e., a first reset pin and a second reset pin). The first reset pin resets each die in channel A individually by receiving a reset signal (i.e., a first reset signal), and the second reset pin resets each die in channel B individually by receiving a reset signal (i.e., a second reset signal). (Refer to the above.) Figure 4b The description will not be repeated here.

[0083] Next, we will take the example of a DRAM chip supporting multiple channels, each channel including multiple ranks, each rank including one or more dies, and different ranks in different channels being able to be powered on and off independently, to further illustrate the point. For ease of understanding, let's take the example of a DRAM chip supporting 2 channels, where each channel includes two columns (e.g., Rank0 and Rank1 in channel A, and Rank0 and Rank1 in channel B). Rank0 in channel A includes one or more bare dies, and Rank1 in channel A includes one or more bare dies (i.e., X first bare dies). Rank0 in channel B includes one or more bare dies, and Rank1 in channel B includes one or more bare dies (i.e., Y second bare dies). During packaging, the DRAM chip can include an input power supply group and a power switch. This input power supply group is used to draw power from a power module of the power management unit 13 to power the bare dies in channels A and B. That is, one or more bare dies in channel A (including Rank0 and Rank1) and one or more bare dies in channel B (including Rank0 and Rank1) share a power module of the power management unit 13. The power switch can be positioned between the input power supply group and each bare die (i.e., each second bare die) in Rank1 of channel B, allowing Rank1 dies in channel B of the DRAM chip to be powered down independently. Understandably, the input power supply group can include one or more output power supplies (taking two outputs, VDD1 and VDD2, as an example). Each power supply can include one or more power pins. In this case, the specific number of power switches can be the product of the number of power supply channels and the number of power pins per power supply. It should be noted that the DRAM chip can also include other power pins, data pins, and control pins; the input power supply group can also include more or fewer output power supplies; the power supply for the power switches can share the power supply of channel A; optionally, the number of power switches can be configured according to the number of columns (ranks) that need to be independently powered down. For information on other pins of the DRAM chip, the number of output power supply channels in the input power supply group, and the number of power switches, please refer to the above. Figure 6 The relevant descriptions will not be repeated here.

[0084] Optionally, different columns (ranks) within different channels of the aforementioned DRAM chip can be reset independently without interference. For example, during packaging, the aforementioned DRAM chip can also include two sets of independent reset pins (i.e., a first reset pin and a second reset pin). The first reset pin resets each die in Rank 1 of channel A (i.e., each of the X first dies) individually by receiving a reset signal (i.e., a first reset signal). The second reset pin resets each die in Rank 1 of channel B (i.e., each of the Y second dies) individually by receiving a reset signal (i.e., a second reset signal). (Refer to the above.) Figure 4b The relevant descriptions will not be repeated here. Understandably, when packaging DRAM chips, separate reset pins (such as the third reset pin and the fourth reset pin) can be packaged separately for Rank0 in channel A and Rank0 in channel B, so that each column in each channel can be reset independently without interference.

[0085] The above is a description of the DRAM chip structure. The following will use the scenario of the aforementioned electronic device 01 entering and exiting standby mode as an example to illustrate the control method of the aforementioned DRAM chip.

[0086] See also Figure 8 , Figure 8 This is a flowchart illustrating a DRAM chip control method provided in an embodiment of this application, wherein electronic device 01 includes the above-described... Figure 4a Taking a DRAM chip as an example, the DRAM chip supports a single channel, which includes two columns (Rank). When electronic device 01 enters standby mode, some columns (such as Rank0 or Rank1) in the DRAM chip can be powered down, thereby reducing the standby power consumption of electronic device 01. This control method includes the following steps S100 to S101:

[0087] Step S100: The main processor receives control instructions.

[0088] Specifically, the control command can be triggered actively by the user or when certain conditions are met (such as when the battery is low, a pop-up window can prompt the user for confirmation, thereby triggering the command). This control command is used to instruct the main processor 11 to perform corresponding configurations (such as configuring the CKE clock enable signal, reset signal, etc.), so that the electronic device 01 can enter standby mode. For example, in the memory chip 12 (such as DRAM chip) of the electronic device, Rank0 (including X first bare dies) and Rank1 (including Y second bare dies) normally store data. When the electronic device 01 needs to enter standby mode, Rank0 (or Rank1) in the above-mentioned DRAM chip can be powered down, leaving only Rank1 (or Rank0) in the self-refresh state.

[0089] Step S101: The main processor controls the PMU to adjust the voltage provided to the X first bare wafers and / or the Y second bare wafers based on the control instructions.

[0090] Specifically, when the main processor 11 receives a control command, it determines the operating state of Rank0 and Rank1 in standby mode, and then controls the PMU to adjust the power supply voltage corresponding to Rank0 and Rank1 according to their operating states. For example, when the main processor 11 receives a control command, it can determine that in the standby mode of the electronic device, Rank0 needs to be powered down and Rank1 needs to be put into a sleep state. At this time, a Self-Refresh Power Down (SRPD) command can be sent to Rank0 first, and the data that needs to be saved in Rank0 can be backed up to Rank1. Then, the CKE1 signal level and the Reset1 signal level can be fixed by configuration, so that Rank1 enters a sleep state. Then, the input power supply group (such as VDD1-1, VDD2-1) and other power supply pins (such as VDDQ) corresponding to Rank0 are completely powered down, so that Rank0 is completely powered down. In addition, the input power supply group (such as VDD1-2, VDD2-2) corresponding to Rank1 can be adjusted to a low-power state (for example, the switching frequency corresponding to VDD1-2, VDD2-2 is reduced). It should be noted that the address allocation for Rank0 and Rank1 is generally different. Taking a DRAM chip with a capacity of 2GB as an example, if the memory controller is configured with an interleaving granularity of 1GB, then Rank0 can be configured with a low address space of 0-1GB, and Rank1 can be configured with a high address space of 1GB-2GB. Since the starting address recognized by the main processor 11 may start from the low address, when the main processor 11 is configured to power down Rank0 and only use Rank1 to work, the low address 0-1GB can be decoded and mapped to the high address 1GB-2GB through remap decoding, thereby ensuring that the main processor 11 can store and access data normally when only Rank1 is working. Understandably, the main processor 11 can adjust the voltage of Rank0 (i.e., including X first bare dies) and / or Rank1 (i.e., including Y second bare dies) by controlling the PMU, so that Rank0 and Rank1 can change their operating states independently. This allows the electronic device to have a variety of different combinations of operating states between Rank0 and Rank1 under different operating modes. For details, please refer to Table 1 below. Table 1 is an example table of electronic device operating modes, memory chip operating states, and power supply states.The electronic device can include six operating modes (i.e., mode 1, mode 2, ..., mode 6), and the Rank0 and Rank1 of the memory chips (such as DRAM chips) of the electronic device can each include three operating states (i.e., working, sleeping, and power-off). Correspondingly, the power supplies that provide separate power to Rank0 and Rank1 also include three power supply states (i.e., normal power-on, low power consumption, and power-off). Taking the electronic device in mode 2 as an example, Rank0 of the memory chips can be in the working state and Rank1 can be in the sleeping state. Correspondingly, VDD1-1, VDD2-1, and VDDQ-1 are in the normal power-on state, while VDD1-2, VDD2-2, and VDDQ-2 are in the sleeping state.

[0091] Table 1. Examples of Electronic Device Operating Modes, Memory Chip Operating States, and Power Supply States

[0092]

[0093] Understandably, when an electronic device requires strong performance, both Rank0 and Rank1 can be put into operating mode (i.e., the first mode, generally referred to as high-performance mode), and their power supplies are normally powered on. When the electronic device has lower performance requirements, Rank0 and Rank1 can be put into operating mode and sleep mode respectively (i.e., the second or third mode, generally referred to as running mode), and their power supplies are normally powered on and low-power mode respectively. The electronic device can also put both Rank0 and Rank1 into sleep mode (i.e., the fourth mode, generally referred to as sleep mode). Furthermore, the electronic device can also put Rank0 or Rank1 into power-off mode (i.e., the fifth or sixth mode, generally referred to as...). (For standby mode) When an electronic device needs to enter standby mode, such as the sixth mode, Rank0 needs to be powered down and Rank1 needs to be adjusted to sleep mode. At this time, the SRPD command can be sent to Rank0 first, and the data that needs to be saved in Rank0 can be backed up to Rank1. Then, the CKE1 signal level and the Reset1 signal level can be fixed by configuration, so that Rank1 enters sleep mode. Then, the input power supply group (such as VDD1-1, VDD2-1) and other power supply pins (such as VDDQ) corresponding to Rank0 are completely powered down, so that Rank0 is completely powered down. In addition, the input power supply group (such as VDD1-2, VDD2-2) corresponding to Rank1 can be adjusted to a low power state (for example, the switching frequency corresponding to VDD1-2, VDD2-2 is reduced).

[0094] It should be noted that the above flowchart illustrates the application of control methods to, including, Figure 4a The example of a single-channel, multi-rank electronic device illustrates that this control method can also be applied to, among other things. Figure 5a In multi-channel multi-row (Rnk) electronic devices, the specific process can be referred to the above description. As for the specific effect of using the memory chip 12 provided in the embodiments of this application, please refer to Table 2 below, which is a comparison table of standby time of a certain smartwatch platform. The electronic device has a 350mAh battery and supports multiple channels (channel A and channel B) with 12 memory chips, each with a capacity of 1GB. When the device is in standby mode with both channels A and B powered on, the total standby power consumption is 1.67mA, the memory chip's standby power consumption is 1.0mA, and the total standby time is 210 hours. When the device is in standby mode with either channel A or channel B powered off, the total standby power consumption is 1.17mA, the memory chip's standby power consumption is 0.5mA, and the total standby time is 299 hours. The standby power consumption of other parts of the smartwatch is almost unchanged compared to the scenario where both channels A and B are powered on, resulting in an 89-hour increase in total standby time, representing a 42% improvement.

[0095] Table 2: Comparison of Standby Time on a Certain Smartwatch Platform

[0096]

[0097] The following is an example illustrating a scenario where electronic device 01 exits standby mode. (See also...) Figure 9 , Figure 9 This is a flowchart illustrating another DRAM chip control method provided in an embodiment of this application, still using electronic device 01 including the above-described method. Figure 4a Taking a DRAM chip as an example, the DRAM chip supports a single channel, which includes two columns (Rank). When electronic device 01 exits standby mode, it can control the power-on of some columns (such as Rank0 or Rank1) in the DRAM chip, so that electronic device 01 can meet the performance requirements of the application scenario. The control method includes the following steps S110 to S111:

[0098] Step S110: The main processor receives the wake-up command.

[0099] Specifically, the wake-up command can be triggered actively by the user or when certain conditions are met (such as when the battery is fully charged, a pop-up window can be used to prompt the user for confirmation, thereby triggering the wake-up command). This wake-up command is used to instruct the main processor 11 to perform corresponding configurations (such as configuring the CKE clock enable signal, reset signal, etc.), so that the electronic device 01 can exit the standby mode. Optionally, Rank0 (including X first bare dies) or Rank1 (including Y second bare dies) of the memory chip 12 (such as DRAM chips) of the electronic device is in a power-off state. When the electronic device 01 needs to exit the standby mode, Rank0 (or Rank1) of the aforementioned DRAM chips can be powered on, so that Rank0 and Rank1 can store data normally.

[0100] Step S111: The main processor controls the PMU to adjust the voltage provided to the X first bare wafers and / or the Y second bare wafers based on the wake-up command.

[0101] Specifically, when the main processor 11 receives the wake-up command, it determines the working state of Rank0 and Rank1 in standby mode, and then controls the PMU to adjust the power supply voltage corresponding to Rank0 and Rank1 according to their working states. For example, when the main processor 11 receives a wake-up command, it can determine that the electronic device needs to exit the standby mode based on the wake-up command. For example, it needs to power on Rank0 and adjust Rank1 to the working state. At this time, the input power supply group (such as VDD1-1, VDD2-1) and other power supply pins (such as VDDQ) corresponding to Rank0 can be fully powered on. Then, the CKE0 signal level and the Reset0 signal level can be pulled high by configuration, so that Rank0 enters the working state. Then, the CKE1 signal level and the Reset1 signal level can be pulled high by configuration. In addition, the input power supply group (such as VDD1-2, VDD2-2) corresponding to Rank1 can be adjusted to the working state (such as increasing the switching frequency corresponding to VDD1-2, VDD2-2), so that Rank1 changes from the sleep state to the working state, and the data backed up in Rank1 when the electronic device 01 enters the standby mode is restored to Rank0.

[0102] It should be noted that in the above example of an electronic device entering or exiting standby mode, the control method for the memory chip 12 (such as a DRAM chip) can also be used for the electronic device to enter or exit high-performance mode, running mode, or hibernation mode. This is achieved by adjusting the specific content of the control and wake-up instructions according to the combination of the working states of different columns in the memory chip 12 and the power supply working states corresponding to those columns in different modes. Understandably, the memory chip 12 described above is only an example of a DRAM chip that supports a single channel, with two columns (ranks) in that single channel. Of course, the memory chip 12 can also support multiple channels, with each channel including one or more columns (ranks). Each channel can be powered individually, or some or all columns (ranks) in each channel can be powered individually. When the memory chip 12 supports multiple channels, the main processor 11 of the electronic device only needs to determine, based on requirements, whether a specific channel or several channels are normally powered on, hibernating, or powered off, or whether a specific column or several columns in each channel are normally powered on, hibernating, or powered off, thereby controlling the PMU to adjust the corresponding voltage. It should also be noted that when different columns or channels in the memory chip 12 are powered on or off individually by controlling the power supply circuit through a power switch, the main processor 11 of the electronic device only needs to determine whether a specific channel or several channels are powered on or off normally, or determine whether a specific column or several columns in each channel are powered on or off normally, thereby controlling the corresponding power switch to be turned on or off.

[0103] Understandably, when an electronic device uses the aforementioned memory chip 12, since different columns or channels within the memory chip 12 can be powered down individually, when the electronic device enters standby mode, only the bare wafers in the powered-on columns or channels can be used for storage. This allows the self-refresh scale of the electronic device in standby mode to be limited to the powered-on bare wafers, thereby reducing standby power consumption. It should be noted that the memory chips provided in this application are not limited to the column-by-rank or channel-by-channel power-down methods described in the above embodiments. Any memory chip with a portion (e.g., a storage array (Bank) or storage cell (Cell)) capable of power-down should also be within the scope of protection of this application.

[0104] This application also provides a semiconductor chip, which includes the memory chip provided in all the above embodiments of this application. It is understood that the functions and roles of each part of the memory chip can be referred to the above descriptions. Figures 3 to 9 The specific implementation methods of each embodiment are not described here.

[0105] This application also provides an electronic device, which includes the memory chip provided in all the above embodiments of this application. It is understood that the functions and roles of each part of the memory chip can be referred to the above descriptions. Figures 3 to 9 The specific implementation methods of each embodiment are not described in detail here. Optionally, the electronic device may also include a communication interface for communication between the electronic device and other devices or communication networks.

[0106] This application also provides an electronic device that has the function of implementing any of the above-described control methods for memory chips. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions.

[0107] This application provides a computer storage medium storing a computer program, which, when executed by an electronic device, enables the electronic device to perform the aforementioned control method flow for memory chips.

[0108] This application provides a computer program that includes instructions that, when executed by an electronic device, enable the electronic device to perform the aforementioned control method flow for memory chips.

[0109] This application provides a chip system comprising any of the aforementioned memory chips. In one possible design, the chip system further includes a main processor, internal memory, and external memory, wherein the internal and external memory are used to store necessary or related program instructions and data of the memory chips and the processor. This chip system can be composed of chips or may include chips and other discrete devices.

[0110] This application provides a system-on-a-chip (SoC) chip, which includes a memory chip provided by any of the above implementations, a processor coupled to the memory chip, internal memory, and external memory. This SoC chip can be composed of a single chip or may include chips and other discrete components.

[0111] It should be noted that the connection relationships involved in this embodiment, such as series or parallel connections, refer to electrical connections, which can be not only directly connected through wires, but also coupled through other electrical actions.

[0112] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory chip, characterized in that, The memory chip includes a first input power group, a second input power group, X first bare dies, and Y second bare dies; the memory chip is a single-channel memory chip, and each of the X first bare dies and each of the Y second bare dies is used to store data, where X and Y are both integers greater than 0; Wherein, the first input power supply group is connected to each of the X first bare wafers, and the first input power supply group is used to supply power to each first bare wafer by connecting to a first power supply; The second input power group is connected to each of the Y second bare wafers, and the second input power group is used to supply power to each second bare wafer by connecting to a second power source; The memory chip also includes a first reset pin and a second reset pin; Wherein, the first reset pin is connected to each of the X first bare wafers, and the first reset pin is used to reset each of the first bare wafers by receiving a first reset signal; The second reset pin is connected to each of the Y second bare wafers, and the second reset pin is used to reset each second bare wafer by receiving a second reset signal; after power-on and reset, each first bare wafer and each second bare wafer enter the normal data storage state.

2. The memory chip as described in claim 1, characterized in that, The memory chip is coupled to the main processor, which includes a first control module and a second control module. The first reset pin of the memory chip is connected to the first control module, and the second reset pin of the memory chip is connected to the second control module. The first control module is used to send a first reset signal to the first reset pin, and the second control module is used to send a second reset signal to the second reset pin.

3. The memory chip as described in claim 1 or 2, characterized in that, The memory chip is coupled to a power management unit (PMU), which includes a first power supply and a second power supply; wherein the first input power supply group of the memory chip is connected to the first power supply, and the second input power supply group of the memory chip is connected to the second power supply.

4. The memory chip as described in any one of claims 1-3, characterized in that, The first input power group and the second input power group each include N output power supplies, and each of the first bare wafers and each of the second bare wafers each includes N input power supplies, where N is an integer greater than 0; wherein, the i-th output power supply of the first input power group is connected to the i-th input power supply in each of the first bare wafers, and the i-th output power supply of the second input power group is connected to the i-th input power supply in each of the second bare wafers, where i takes the values ​​1, 2, ..., N.

5. The memory chip as described in any one of claims 1-4, characterized in that, The memory chips include dynamic random access memory (DRAM) chips, synchronous dynamic random access memory (SDRAM) chips, pseudo static random access memory (PSRAM) chips, or static random access memory (SRAM) chips.

6. A power management unit (PMU), characterized in that, The PMU includes a first power supply and a second power supply; the PMU is coupled to a memory chip, the memory chip includes a first input power supply group, a second input power supply group, X first bare dies and Y second bare dies, the memory chip is a single-channel memory chip, each of the X first bare dies and each of the Y second bare dies is used to store data, and X and Y are both integers greater than 0; Wherein, the first input power group is connected to the first power source, and the first input power group is connected to each of the X first bare wafers; the first input power group is used to supply power to each first bare wafer by connecting to the first power source; The second input power group is connected to the second power supply, and the second input power group is connected to each of the Y second bare wafers; the second input power group is used to supply power to each second bare wafer by connecting to the second power supply; The memory chip also includes a first reset pin and a second reset pin; Wherein, the first reset pin is connected to each of the X first bare wafers, and the first reset pin is used to reset each of the first bare wafers by receiving a first reset signal; The second reset pin is connected to each of the Y second bare wafers, and the second reset pin is used to reset each second bare wafer by receiving a second reset signal; after power-on and reset, each first bare wafer and each second bare wafer enter the normal data storage state.

7. A main processor, characterized in that, The main processor includes a first control module and a second control module; the main processor is coupled to a memory chip, the memory chip including X first bare wafers, Y second bare wafers, a first reset pin and a second reset pin, the memory chip is a single-channel memory chip, each of the X first bare wafers and each of the Y second bare wafers is used to store data, and X and Y are both integers greater than 0; The first reset pin is connected to each of the X first bare wafers and is also connected to the first control module. The first reset pin is used to reset each of the first bare wafers by receiving a first reset signal sent by the first control module. The second reset pin is connected to each of the Y second bare wafers, and the second reset pin is also connected to the second control module; the second reset pin is used to receive a second reset signal sent by the second control module to reset each second bare wafer; The memory chip also includes a first reset pin and a second reset pin; Wherein, the first reset pin is connected to each of the X first bare wafers, and the first reset pin is used to reset each of the first bare wafers by receiving a first reset signal; The second reset pin is connected to each of the Y second bare wafers, and the second reset pin is used to reset each second bare wafer by receiving a second reset signal; after power-on and reset, each first bare wafer and each second bare wafer enter the normal data storage state.

8. A memory chip, characterized in that, The memory chip includes an input power supply group, a power switch, X first bare chips and Y second bare chips. The memory chip is a single-channel memory chip. Each of the X first bare chips and each of the Y second bare chips is used to store data. X and Y are both integers greater than 0. The input power supply group is connected to each of the X first bare wafers; The input terminal of the power switch is connected to the input power group, and the output terminal of the power switch is connected to each of the Y second bare wafers. The input power group is used to supply power to each first bare wafer and each second bare wafer by connecting to the power supply. The power switch is used to control the connection circuit between each second bare wafer and the input power group to be turned on or off. The memory chip also includes a first reset pin and a second reset pin; Wherein, the first reset pin is connected to each of the X first bare wafers, and the first reset pin is used to reset each of the first bare wafers by receiving a first reset signal; The second reset pin is connected to each of the Y second bare wafers, and the second reset pin is used to reset each second bare wafer by receiving a second reset signal; after power-on and reset, each first bare wafer and each second bare wafer enter the normal data storage state.

9. The memory chip as described in claim 8, characterized in that, The memory chip is coupled to the main processor, which includes a first control module and a second control module. The first reset pin of the memory chip is connected to the first control module, and the second reset pin of the memory chip is connected to the second control module. The first control module is used to send a first reset signal to the first reset pin, and the second control module is used to send a second reset signal to the second reset pin.

10. The memory chip as described in claim 8 or 9, characterized in that, The memory chip is coupled to a power supply unit (PMU), which includes a power supply module; wherein the input power supply group of the memory chip is connected to the power supply module.

11. The memory chip as described in any one of claims 8-10, characterized in that, The input power supply group includes N output power supplies, and each of the first bare wafers and each of the second bare wafers includes N input power supplies. The number of power switches is N, where N is an integer greater than 0. The i-th output power supply of the input power supply group is connected to the i-th input power supply in each of the first bare wafers. The input terminal of the i-th power switch among the N power switches is connected to the i-th output power supply of the input power supply group, and the output terminal of the i-th power switch is connected to the i-th input power supply in each of the second bare wafers. i takes the values ​​1, 2, ..., N.

12. The memory chip as described in any one of claims 8-11, characterized in that, The memory chips include dynamic random access memory (DRAM) chips, synchronous dynamic random access memory (SDRAM) chips, pseudo static random access memory (PSRAM) chips, or static random access memory (SRAM) chips.

13. An electronic device, characterized in that, The electronic device includes a memory chip as described in any one of claims 1-5, and further includes a main processor and a PMU, wherein the memory chip is coupled to the main processor and the PMU respectively; wherein the main processor is used to receive control instructions and control the PMU to adjust the voltage provided by X first bare wafers and / or Y second bare wafers of the memory chip based on the control instructions; the electronic device further includes internal memory and external memory, wherein the internal memory and external memory are used to store program instructions and data necessary for the operation of the main processor and the PMU.

14. A control method, characterized in that, The method is applicable to the electronic device as described in claim 13, the electronic device comprising memory chips, a main processor, and a PMU, the method comprising: When the X first bare wafers and Y second bare wafers in the memory chip are in a normal data storage state, control instructions are received through the main processor; Based on the control commands, the PMU is controlled to adjust the voltage supplied to the X first bare wafers and / or the Y second bare wafers.

15. An electronic device, characterized in that, The electronic device includes a memory chip as described in any one of claims 8-12, and further includes a main processor and a power supply unit (PMU), wherein the memory chip is coupled to the main processor and the PMU respectively; wherein the main processor is used to receive control instructions and control the power switch to be turned on or off based on the control instructions, and to control whether the PMU can provide voltage to Y second bare wafers of the memory chip; the electronic device further includes internal memory and external memory, which are used to store program instructions and data necessary for the operation of the main processor and the PMU.

16. A control method, characterized in that, The method is applicable to the electronic device as described in claim 15, the electronic device comprising memory chips, a main processor, and a PMU, the method comprising: When the X first bare wafers and Y second bare wafers in the memory chip are in a normal data storage state, control instructions are received through the main processor; Based on the control command, the power switch is turned on or off, and the PMU is controlled to provide voltage to the Y second bare wafers of the memory chip.

17. A system-on-a-chip (SoC) chip, the SoC chip comprising a memory chip as described in any one of claims 1-5 or as described in any one of claims 8-12, and a processor, internal memory, and external memory coupled to the memory chip, the internal memory and external memory being used to store necessary or related program instructions and data for the operation of the memory chip and the processor.

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