A method for manufacturing an anti-radiation trench MOSFET

Abstract

The application discloses a manufacturing method of an anti-radiation trench type MOSFET, and belongs to the field of semiconductor power devices. Main process features are as follows: before trench etching, the well region is pushed and bonded by using the heat process of the source trench sacrifice oxidation process, so that the high-temperature heat process after the gate oxide process is avoided, and the total dose performance of the product is improved; two times of trench etching are used, the source trench modulates the epitaxial layer, the on-resistance is reduced, and the gate trench realizes the control of the channel; local oxidation thickening is carried out on the bottom of the gate trench, and the ability of the device to resist single particle gate penetration is increased. Through optimization of process steps and process flow, the trench type MOSFET product with the anti-radiation characteristic can be processed under the condition that the process difficulty and manufacturing cost increase are limited, the anti-radiation performance is reinforced on the basis of the commercial trench type MOSFET device, and the use environment of the component in the aerospace field is met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and in particular to a method for manufacturing a radiation-resistant trench MOSFET. Background Technology

[0002] Trench MOSFETs are a new type of discrete power MOSFET device. Compared with bipolar power devices, they offer advantages such as lower conduction losses, higher operating frequencies, voltage-controlled operation, and simpler control circuitry, making them increasingly popular in industry. Compared to planar MOSFETs and conventional trench MOSFETs, trench MOSFETs can achieve smaller cell sizes and higher current densities, improving current capability and switching performance, especially in the low-to-medium voltage power MOSFET field.

[0003] As humanity explores space, electronic components not only need excellent electrical performance but also need to withstand the harsh environment of space, such as gamma rays and solar wind. In the ionizing radiation environment of space, the radiation effects on devices mainly include total dose radiation, single-event burn-out, and single-event gate breakdown. Therefore, radiation-hardened designs are required for these devices.

[0004] The radiation-hardened MOSFET proposed in this invention achieves excellent electrical performance and is further enhanced by radiation hardening design to better meet the usage environment in the space field. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a radiation-resistant trench MOSFET to solve the problems in the prior art.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a radiation-resistant trench MOSFET, comprising:

[0007] A first silicon oxide layer is grown on a silicon epitaxial wafer. P-well implantation is achieved through ion implantation, and a first silicon nitride layer is deposited to form a three-layer thin film structure of epitaxial silicon-silicon oxide-silicon nitride.

[0008] The first trench is created on the wafer using trench lithography and etching processes. A field oxide layer is grown and in-situ polycrystalline material is deposited using thermal oxidation. The polycrystalline material outside the trench is then etched away using a polycrystalline etch-back process.

[0009] A second trench is cut out on the wafer, and an oxide layer and a second silicon nitride layer are deposited.

[0010] The first silicon nitride layer, the second silicon nitride layer, and the thin sidewall oxide layer are removed using a phosphoric acid process, ensuring that the bottom oxide thickening portion is retained; gate oxide is grown, in-situ polycrystalline is deposited, and the polycrystalline silicon surface is etched away using a gate polycrystalline etch-back process;

[0011] Achieve source implantation and activation, and perform deposition and planarization of dielectric ILD; firstly, perform dielectric hole etching and silicon hole etching using hole lithography, then use hole implantation to dope P-type impurities into the deep bulk region, and finally form a bulk region through thermal activation.

[0012] Tungsten filling and grinding are used to bring out the metal in the contact holes, and metal interconnection is achieved through metal deposition, photolithography and etching.

[0013] In one embodiment, the thickness of the first silicon oxide layer is The process parameters for P-trap implantation are: implantation of boron element, energy 50–120 keV, and dose 1 E13–5 E13 cells / cm³. 2 The thickness of the first silicon nitride layer is

[0014] In one embodiment, the first trench has smooth sidewalls, an inclination angle of 88-90°, and a semi-circular bottom; the depth of the first trench is 2-6 μm, which needs to match the actual requirements of the product.

[0015] After completing the first trench process, the method further includes: growing a sacrificial oxide layer to repair the damage to the sidewalls and bottom silicon surface of the first trench during dry etching, pushing the well region together, and then removing the sacrificial oxide layer using wet etching.

[0016] In one embodiment, the temperature range of the sacrificial oxide layer is 1000–1150°C, and the oxide thickness is [missing information]. This high-temperature thermal process is used to push the P-well together to form the well region.

[0017] In one embodiment, the second trench has smooth sidewalls, an inclination angle of 88-90°, a semi-circular bottom shape, and a depth range of 1-2 μm.

[0018] After completing the second trenching process, the method further includes: repairing sidewall and bottom damage through sacrificial oxidation and pull-out processes, wherein the sacrificial oxidation temperature ranges from 1000 to 1150°C, and the oxidation thickness is [missing information].

[0019] In one embodiment, after depositing an oxide layer and a second silicon nitride layer, the method further includes:

[0020] Using dry etching anisotropic anomalies, the second silicon nitride layer at the bottom of the first and second trenches of the gate is etched away, while the sidewalls and bottom silicon surface still retain silicon nitride;

[0021] Then, through a thermal oxidation process, an oxide layer is grown at the bottom of the first and second trenches of the gate to achieve localized oxidation thickening at the bottom.

[0022] In one embodiment, the method for achieving source implantation and activation is as follows: N+ lithography and ion implantation are used, with the implanted element being As / P, the implantation energy being 60–100 keV, and the implantation dose being 5E15–1E16 ions / cm². 2 .

[0023] This invention provides a method for manufacturing a radiation-hardened trench MOSFET. Well region implantation needs to be performed before trench etching, utilizing a sacrificial oxidation thermal process to achieve junction push-in. The source trench and gate trench need to be processed separately due to differences in etching depth requirements. Considering the requirement for single-event gate penetration resistance, the oxide layer at the bottom of the gate trench needs to be thickened. Furthermore, to meet the total dose resistance requirements of the gate oxide itself, a low-temperature wet oxygen process is required. This invention, by optimizing process steps and flow, enables the fabrication of radiation-hardened trench MOSFET products with limited increases in process difficulty and manufacturing cost. It enhances the radiation resistance of commercial trench MOSFET devices, meeting the usage environment requirements in the aerospace field. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the completed well injection and source first trench structure;

[0025] Figure 2 This is a schematic diagram of the field oxygen growth and polycrystalline etch-back structure of the first trench of the source electrode;

[0026] Figure 3 This is a schematic diagram of the structure forming the second trench of the gate;

[0027] Figure 4 This is a schematic diagram of the oxide structure at the bottom of the gate;

[0028] Figure 5 This is a schematic diagram of gate oxide growth and gate polysilicon etch-back;

[0029] Figure 6 This is a diagram illustrating N+ injection and activation;

[0030] Figure 7 This is a schematic diagram of dielectric deposition and surface planarization;

[0031] Figure 8 This is a schematic diagram of the pit corrosion and pit injection activation structure;

[0032] Figure 9 This is a schematic diagram of device interconnection completed by metal photolithography / etching. Detailed Implementation

[0033] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the manufacturing method of a radiation-resistant trench MOSFET proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0034] Radiation-resistant trench MOSFET devices are three-terminal discrete devices. The front side of the wafer is divided into two parts: the source region and the gate region. These two regions are isolated from the outside world by a source trench. The drain region of the device is on the back side of the wafer. The process of this invention mainly focuses on the wafer source. The gate is led out to the edge of the die through a polysilicon in the trench, and then interconnected with metal by drilling contact holes on it. The drain only needs to be led out by thinning the back side and plating metal, which is understood by those skilled in the art, and therefore will not be described in detail in this invention. This invention mainly proposes a process technology for the cell region, using a source trench isolation ring to terminate the junction around the entire die region.

[0035] This invention provides a method for manufacturing a radiation-resistant trench MOSFET. While achieving reduced on-resistance, it also enhances radiation resistance. By improving certain processes, it effectively improves the high reliability of the trench MOSFET.

[0036] Specifically, the radiation-resistant trench-type MOSFET is fabricated using the following method:

[0037] Taking an N-type device as an example, a P-type device can be obtained using the corresponding method. A first silicon oxide layer 2 is grown on a silicon epitaxial wafer 1, wherein the thickness of the first silicon oxide layer 2 is... P-trap (PW) implantation was achieved using ion implantation technology, with boron (B) implanted at energies of 50–120 keV and doses of 1–5 E13 cells / cm². 2 Then, a three-layer epitaxial silicon-silicon oxide-silicon nitride thin film structure is formed by chemical vapor deposition of the first silicon nitride layer 3, the thickness of which is... Trench grooves with smooth sidewalls, tilt angles of 88–90°, semi-circular bottoms, and a certain depth are created on a wafer using photolithography and etching processes. Figure 1As shown. The depth of the first trench is 2-6µm, which needs to match the actual requirements of the product. For example, the depth of the first trench in the N40V product is about 2.5µm. Figure 1 As shown.

[0038] After completing the first trench process at the source, a sacrificial oxide layer needs to be grown to repair the damage to the sidewalls and bottom silicon surface of the first trench during dry etching and to push the well region together. This sacrificial oxide layer is then removed using wet etching. Generally, the temperature range for sacrificial oxide is 1000–1150℃, and the oxide thickness is [missing information]. This high-temperature thermal process is used to push the P-well together to form a well region;

[0039] After completing the first trench process of the source electrode, a field oxide layer 4 and in-situ polycrystalline material 5 are grown using a thermal oxidation process; the polycrystalline material outside the trench area is etched away using a polycrystalline etch-back process, such as... Figure 2 As shown.

[0040] Next, photolithography and etching processes are performed on the second gate trench. A second trench with smooth sidewalls, an inclination angle of 88–90°, a semi-circular bottom, and a certain depth (1–2 μm) is then created on the wafer. Figure 3 As shown. Sidewall and bottom damage are repaired using a sacrificial oxidation and pull-out process, where the sacrificial oxidation temperature ranges from 1000 to 1150°C, and the oxidation thickness is [missing information].

[0041] After etching and repairing the second gate trench, an oxide layer 6 and a second silicon nitride layer 7 are deposited. Using dry etching anisotropy, the second silicon nitride layer at the bottom of the first and second gate trenches is etched away, while silicon nitride remains on the sidewalls and bottom silicon surface. Then, an oxide layer is grown at the bottom of the first and second gate trenches using a thermal oxidation process, achieving localized oxide thickening at the bottom. (See...) Figure 4 .

[0042] The first silicon nitride layer 3, the second silicon nitride layer 7, and the thin sidewall oxide layer are removed using a phosphoric acid process. The wet etching time of the oxide layer is controlled to ensure that the thickened oxide layer at the bottom is preserved. A low-temperature wet oxide process is used to grow the gate oxide and deposit in-situ polycrystalline material. The polycrystalline material on the silicon surface is then etched away using a gate polycrystalline etch-back process. Figure 5 As shown.

[0043] Source implantation and activation were achieved using N+ lithography and ion implantation. The implanted element was As / P, the implantation energy was 60–100 keV, and the implantation dose was 5E15–1E16 ions / cm³. 2 ,See Figure 6 .

[0044] This completes the front-end device fabrication process. Then, chemical vapor deposition (CVD) is used to deposit and planarize the dielectric ILD, such as... Figure 7 As shown. Using hole lithography, the first step involves etching the dielectric vias and the silicon vias. P-type impurities are then doped into the deep bulk region using via implantation, and subsequently extracted through thermal activation to form the bulk region, as shown. Figure 8 As shown.

[0045] Tungsten filling and polishing are used to bring out the metal contacts in the holes. Metal interconnects are then achieved through metal deposition, photolithography, and etching, completing the overall device. Figure 9 .

[0046] Based on the trench MOSFET process, this invention optimizes the process to increase the radiation resistance of the device, making it suitable for the ionizing radiation environment in space and improving the high reliability of the device.

[0047] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a radiation-resistant trench MOSFET, characterized in that, include: A first silicon oxide layer is grown on a silicon epitaxial wafer. P-well implantation is achieved through ion implantation, and a first silicon nitride layer is deposited to form a three-layer thin film structure of epitaxial silicon-silicon oxide-silicon nitride. The first trench is created on the wafer using trench lithography and etching processes. A field oxide layer is grown and in-situ polycrystalline material is deposited using thermal oxidation. The polycrystalline material outside the trench is then etched away using a polycrystalline etch-back process. A second trench is cut out on the wafer, and an oxide layer and a second silicon nitride layer are deposited. The first silicon nitride layer, the second silicon nitride layer, and the thin sidewall oxide layer are removed using a phosphoric acid process, ensuring that the bottom oxide thickening portion is retained; gate oxide is grown, in-situ polycrystalline is deposited, and the polycrystalline silicon surface is etched away using a gate polycrystalline etch-back process; Achieve source injection and activation, and perform deposition and planarization of the dielectric ILD; The first step of dielectric hole etching and silicon hole etching is performed using hole lithography. P-type impurities are then doped into the deep bulk region using hole injection, and then extracted by thermal activation to form a bulk region. Tungsten filling and grinding are used to bring out the metal in the contact holes, and metal interconnection is achieved through metal deposition, photolithography and etching.

2. The method for manufacturing a radiation-resistant trench MOSFET as described in claim 1, characterized in that, The thickness of the first silicon oxide layer is The process parameters for P-trap implantation are: implantation of boron element, energy 50–120 keV, and dose 1 E13–5 E13 cells / cm³. 2 The thickness of the first silicon nitride layer is 3. The method for manufacturing a radiation-resistant trench MOSFET as described in claim 1, characterized in that, The first trench has smooth sidewalls, an inclination angle of 88-90°, and a semi-circular bottom; the depth of the first trench is 2-6 μm, which needs to match the actual requirements of the product. After completing the first trench process, the method further includes: growing a sacrificial oxide layer to repair the damage to the sidewalls and bottom silicon surface of the first trench during dry etching, pushing the well region together, and then removing the sacrificial oxide layer using wet etching.

4. The method for manufacturing a radiation-resistant trench MOSFET as described in claim 3, characterized in that, The temperature range of the sacrificial oxide layer is 1000–1150℃, and the oxide thickness is [missing information]. This high-temperature thermal process is used to push the P-well together to form the well region.

5. The method for manufacturing a radiation-resistant trench MOSFET as described in claim 1, characterized in that, The second trench has smooth sidewalls, an inclination angle of 88-90°, a semi-circular bottom shape, and a depth range of 1-2 μm. After completing the second trenching process, the method further includes: repairing sidewall and bottom damage through sacrificial oxidation and pull-out processes, wherein the sacrificial oxidation temperature ranges from 1000 to 1150°C, and the oxidation thickness is [missing information].

6. The method for manufacturing a radiation-resistant trench MOSFET as described in claim 1, characterized in that, After depositing an oxide layer and a second silicon nitride layer, the method further includes: Using dry etching anisotropic anomalies, the second silicon nitride layer at the bottom of the first and second trenches of the gate is etched away, while the sidewalls and bottom silicon surface still retain silicon nitride; Then, through a thermal oxidation process, an oxide layer is grown at the bottom of the first and second trenches of the gate to achieve localized oxidation thickening at the bottom.

7. The method for manufacturing a radiation-resistant trench MOSFET as described in claim 1, characterized in that, The method for achieving source implantation and activation is as follows: N+ lithography and ion implantation, with As / P implanted elements, an implantation energy of 60–100 keV, and an implantation dose of 5E15–1E16 ions / cm². 2 .

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