A method for manufacturing CMOS devices based on multilayer stress memory technology
By employing multilayer stress memory technology in CMOS device manufacturing, depositing and processing dense high-tensile stress layers and low-tensile stress layers, combined with rapid thermal annealing, the problem of insufficient density in plasma nitriding treatment is solved, improving NMOS performance and preventing PMOS performance degradation, thus achieving low-cost, high-performance manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2023-10-17
- Publication Date
- 2026-07-17
AI Technical Summary
In existing CMOS device manufacturing technologies, ultraviolet curing processes increase costs, while plasma nitriding treatments result in insufficient etch barrier layer density, leading to hydrogen atom diffusion and affecting the performance and reliability of PMOS devices, particularly the NBTI effect.
By employing multilayer stress memory technology, a dense stress layer structure is formed by depositing an etch barrier layer on the wafer, followed by plasma nitriding, and then depositing high-tensile stress layers and low-tensile stress layers multiple times, combined with rapid thermal annealing, to block the diffusion of hydrogen atoms.
It effectively reduces the NBTI effect in CMOS devices, improves the performance of NMOS devices, prevents the degradation of PMOS device performance, and reduces manufacturing costs.
Smart Images
Figure CN117410235B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit manufacturing technology, and in particular relates to a method for manufacturing CMOS devices based on multilayer stress memory technology. Background Technology
[0002] With advancements in semiconductor manufacturing technology, stress memory technology (SMT) can effectively improve the performance of complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs). By introducing localized unidirectional stress into the conductive channel of a CMOS, the carrier mobility within the conductive channel is increased, thereby significantly increasing the drive current even when the gate dielectric layer thickness is thinned or remains constant, ultimately improving the performance of CMOS devices.
[0003] Simultaneously, with the shrinking size of MOS devices and the thinning of the oxide layer, the electric field strength acting on the gate oxide layer increases significantly, making the reliability control of MOS devices increasingly important. In particular, the negative bias temperature instability (NBTI) effect is becoming increasingly pronounced. NBTI is mainly caused by the changes in trapped charge at the silicon / oxide (Si / SiO2) interface and the oxide layer charge. Some Si dangling bonds exist at the silicon / oxide interface of the gate. During the manufacturing process, once hydrogen diffuses into the silicon / oxide interface, it combines with the silicon dangling bonds to form Si-H bonds. However, during device operation, a high electric field is generated on the gate, at which point the Si-H bonds are easily broken, and the Si dangling bonds reappear, attracting charge and thus becoming positively charged interface traps. These interface traps increase with increasing gate bias voltage and temperature, further affecting device performance and reliability.
[0004] The performance of PMOS devices is affected by two factors: tensile stress reduces hole mobility, and hydrogen (H) influences device doping and interface states, further impacting performance and reliability. Generally, for cost-constrained manufacturing processes, [the following is a more detailed description of the process:] ... <100> The crystal orientation of wafers used in CMOS device fabrication can protect PMOS devices from tensile stress, which will not be elaborated on in this article. However, the impact of H on device performance and reliability still exists.
[0005] In stress memory technology, chemical vapor deposition (CVD) thin films use a mixture of SiH4 and NH3 as the source gas. The deposited film contains a large amount of hydrogen (H), which diffuses into the device after annealing. This H not only combines with Si dangling bonds at the silicon / oxygen interface to form Si-H bonds but also diffuses into the source / drain regions of the device. This causes boron doping in the PMOS source / drain regions to diffuse into the channel region, increasing the short-channel effect and leading to a decrease in integrated circuit performance. Typically, UV curing can avoid these problems by treating the etch barrier layer; however, the introduction of UV curing and other processes increases manufacturing and equipment costs. For cost reduction, plasma nitriding is used instead of UV curing. Experiments show that plasma nitriding results in a lower barrier layer density and poorer hydrogen blocking effect compared to UV curing. Summary of the Invention
[0006] In view of this, the present invention provides a CMOS device manufacturing method based on multilayer stress memory technology, thereby effectively improving the electrical performance of semiconductor devices.
[0007] To achieve the above objectives, the technical solution of the present invention is implemented as follows:
[0008] A method for manufacturing CMOS devices based on multilayer stress memory technology, comprising:
[0009] Deposit an etching barrier layer on the wafer;
[0010] The etching barrier layer is subjected to plasma nitriding treatment;
[0011] A high tensile stress layer is deposited n times on the treated etch barrier layer, and the high tensile stress layer is subjected to plasma nitriding treatment; n≥1;
[0012] A low tensile stress layer is deposited in the high tensile stress layer after plasma nitriding treatment; wherein the tensile stress and hydrogen content of the low tensile stress layer are both lower than those of the high tensile stress layer.
[0013] Rapid thermal annealing is performed on wafers with deposited etch barrier layers, high tensile stress layers, and low tensile stress layers;
[0014] The wafer is etched after rapid thermal annealing to remove the high tensile stress layer and the low tensile stress layer.
[0015] Preferably, the wafer is <100> Crystal orientation.
[0016] Preferably, before depositing the etch barrier layer on the wafer, the wafer is further processed as follows: a gate structure and sidewalls are formed on the semiconductor substrate of the wafer; source / drain ion implantation is completed in the NMOS device region and the PMOS device region by resist coating and development, respectively.
[0017] Preferably, an etch barrier layer is deposited in the NMOS device region and PMOS device region where source / drain ions are implanted.
[0018] Preferably, the etching barrier layer is made of silicon nitride, silicon oxynitride, or silicon nitride.
[0019] Preferably, the plasma nitriding treatment method involves introducing a nitrogen-containing gas into the surface of the etched barrier layer under reaction conditions of 200-650°C. The nitrogen-containing gas is one or any combination of nitrogen, nitric oxide, and nitrous oxide. The flow rate of the nitrogen-containing gas is in the range of 50-5000 standard conditions per cubic centimeter, the high-frequency power of the nitrogen-containing gas is in the range of 10-2000 watts, and the pressure of the nitrogen-containing gas is in the range of 1-100 Torr.
[0020] Preferably, the deposition process for the high-tensile-stress layer and the low-tensile-stress layer is chemical vapor deposition (CVD). The deposition process conditions are as follows: For the high-tensile-stress layer, the reactants are silicon-containing gas and nitrogen-containing gas, with the flow rate of the silicon-containing gas ranging from 1 to 200 sccm and the flow rate of the nitrogen-containing gas ranging from 1 to 200 sccm; the deposition process pressure range is 1 to 100 Torr; the deposition process temperature range is 200 to 650°C; and the deposition process RF power is 50 to 200 W. For the low-tensile-stress layer, the deposition process conditions are as follows: The reactants are silicon-containing gas and nitrogen-containing gas, with the flow rate of the silicon-containing gas ranging from 1 to 200 sccm and the flow rate of the nitrogen-containing gas ranging from 1 to 200 sccm; the deposition process pressure range is 1 to 100 Torr; the deposition process temperature range is 200 to 650°C; and the deposition process RF power is 1 to 49 W.
[0021] Preferably, the deposition thickness of the high tensile stress layer is [missing information]. The tensile stress range is 800-1400 MPa; the deposition thickness of the low tensile stress layer is... The tensile stress range is 1-700 MPa.
[0022] Preferably, the tensile stresses of adjacent high tensile stress layers are different or the same.
[0023] As a preferred option, n = 1 to 5.
[0024] This invention involves depositing an etch barrier layer and a high tensile stress layer on a wafer device before depositing a low tensile stress layer. The etch barrier layer and the high tensile stress layer simultaneously cover at least both the N-well and the P-well. The etch barrier layer undergoes surface plasma nitriding, followed by the deposition of the high tensile stress layer, and then another surface plasma nitriding treatment. This process is repeated multiple times, with the number of cycles depending on the reliability testing requirements of the PMOS device manufactured using this method. Finally, a low tensile stress layer is deposited, and the wafer is annealed to enhance the stress application effect. This invention reduces the NBTI effect in NMOS and PMOS devices by strengthening the barrier layer and the high tensile stress layer through multiple cycles of deposition and treatment, thus avoiding performance degradation of PMOS devices caused by boron diffusion from hydrogen atoms in the stress material layer formed by the above process.
[0025] The beneficial effects of this invention are:
[0026] This invention reduces the NBTI effect in CMOS devices and mitigates the performance degradation of PMOS devices by depositing multiple dense, high-tensile-stress layers to resist hydrogen atom diffusion.
[0027] This invention increases the nitrogen content on the surface of the high tensile stress layer by performing plasma nitriding treatment, making the surface of the high tensile stress layer more compact and forming a dense interface. This further increases the ability to block hydrogen atom diffusion and reduces the hydrogen atom content within the high tensile stress layer itself, thereby promoting the degradation of PMOS device performance.
[0028] By using the semiconductor device and manufacturing method provided by this invention, the electrical performance of semiconductor devices can be improved at an ultra-low manufacturing cost, ensuring further optimization of NMOS device performance while preventing degradation of PMOS device performance. Attached Figure Description
[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is a flowchart of the method of the present invention;
[0031] Figures 2A-2J This is a schematic cross-sectional view of the process of steps 101-110 of the present invention. Detailed Implementation
[0032] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.
[0033] To fully understand this invention, detailed steps will be set forth in the following description to illustrate the method for implementing stress memory proposed by this invention. Obviously, the implementation of this invention is not limited to the specific details familiar to those skilled in the art of semiconductors. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.
[0034] It should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the said feature, integral, step, operation, element and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or combinations thereof.
[0035] Below, refer to Figure 1 and Figures 2A-2J The following describes the detailed steps of the method for implementing stress memory proposed in this invention.
[0036] Reference Figure 1 The flowchart of the method for implementing stress memory proposed in this invention is shown, which briefly illustrates the entire manufacturing process.
[0037] Step 101, in <100> Gate structures and sidewalls are formed on a crystal-oriented semiconductor substrate.
[0038] like Figure 2AAs shown, a semiconductor substrate 202 is provided. The semiconductor substrate 202 can be made of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), etc. As an example, in this embodiment, the semiconductor substrate 202 is made of single-crystal silicon. The crystal orientation of the substrate can also be selected. As an example, in this embodiment, the substrate is selected as... <100> Crystal orientation. An isolation structure 201 is formed in the semiconductor substrate 202. The isolation structure 201 is a shallow trench isolation (STI) structure, dividing the semiconductor substrate 202 into an NMOS region and a PMOS region. Various well structures are also formed in the semiconductor substrate 202. PMOS is fabricated on the N-well, and NMOS is fabricated on the P-well. For simplicity, these are omitted in the figure. A gate structure is formed on the semiconductor substrate 202. As an example, the gate structure may include a gate dielectric layer 203 and a gate material layer 204 stacked sequentially from bottom to top. The gate dielectric layer 203 may include an oxide, such as a silicon dioxide (SiO2) layer. The gate material layer 204 may include a polysilicon layer. In addition, as an example, spacer structures 205 and sidewall structures 206 are also formed on the semiconductor substrate 202, located on both sides of the gate structure and close to the gate structure. The spacer structure 205 may include at least one oxide layer and / or at least one nitride layer. The sidewall structure 206 includes at least one nitride layer.
[0039] Step 102: Source / drain ion implantation is performed on the NMOS and PMOS device regions by ion implantation.
[0040] like Figure 2B As shown, doped source / drain regions are formed in the semiconductor substrate 202 located on both sides of the gate structure, and the channel region between the source / drain regions is omitted in the figure for simplicity. The source / drain region 211 located in the PMOS region is doped with p-type impurities, and the source / drain region 212 located in the NMOS region is doped with n-type impurities.
[0041] Step 103: Deposit an etch barrier layer in the NMOS and PMOS regions.
[0042] like Figure 2C As shown, an etch barrier layer 221 is formed on the semiconductor substrate 202 using a chemical vapor deposition process to cover the gate structure. The etch barrier layer 221 simultaneously covers the P-well, N-well, and STI region; the etch barrier layer 221 can be silicon nitride, silicon oxynitride, or silicon nitride material, and the deposition method for the etch barrier layer 221 can be CVD, LPCVD, or PECVD. The thickness of the etch barrier layer is...
[0043] Step 104: Perform plasma nitriding treatment on the etch barrier layer to form a denser etch barrier layer 231.
[0044] like Figure 2D As shown, the etching barrier layer is subjected to plasma nitriding treatment to obtain a denser etching barrier layer 231. The purpose of surface nitriding treatment of the barrier layer is to increase the nitrogen content on the surface of the barrier layer, making the surface of the barrier layer more dense, and increasing the ability to block hydrogen atom diffusion at the interface formed between the tensile stress layer deposited in subsequent steps and the barrier layer. The nitriding treatment method involves introducing a nitrogen-containing gas into the surface of the barrier layer under reaction conditions in the temperature range of 200 to 650 degrees Celsius. As an example, in this embodiment, the nitrogen-containing gas is selected from nitrogen, nitric oxide, and nitrous oxide, or any combination thereof. The flow rate of the nitrogen-containing gas is in the range of 50 to 5000 sccm, for example, 50 sccm, 2000 sccm, or 5000 sccm; the high-frequency power range of the nitrogen-containing gas is in the range of 10 to 2000 watts (W), for example, 10 watts, 1000 watts, or 2000 watts; and the pressure range of the nitrogen-containing gas is in the range of 1 to 100 Torr, for example, 1 Torr, 50 Torr, or 100 Torr.
[0045] Because the diffusion of hydrogen atoms at the Si / SiO2 interface between the etch barrier layer and the stacked gate on the surface of the underlying silicon substrate determines the generation of interface traps in the NBTI effect, reducing the hydrogen atom content at the Si / SiO2 interface on the one hand further increases the ability of the etch barrier layer to resist the diffusion of hydrogen atoms. Both of these factors simultaneously reduce the NBTI effect and improve the performance of NMOS devices. On the other hand, they prevent hydrogen from diffusing into PMOS devices, thus preventing boron loss caused by hydrogen diffusion and improving the performance of PMOS devices.
[0046] Step 105: A high tensile stress layer A is deposited on the densified etch barrier layer using chemical vapor deposition.
[0047] like Figure 2EAs shown, a high tensile stress layer A241 is formed on the semiconductor substrate 202 using a chemical vapor deposition (CVD) process. This high tensile stress layer preferably contains a high tensile stress nitride to cover the densification etch barrier layer 231. The CVD method can be CVD, LPCVD, or PECVD, with PECVD being preferred. Furthermore, the reactants in the deposition process are silicon-containing gases. As an example, in this embodiment, the silicon-containing gas is selected from silane and nitrogen-containing gases, such as ammonia and nitrogen. The flow rate range of the silicon-containing gas in the deposition process is 1 to 200 sccm, for example, 20 sccm or 50 sccm; the flow rate range of the nitrogen-containing gas in the deposition process is 1-200 sccm, for example, 25 sccm, etc. The pressure range of the deposition process is 1-100 Torr, for example, 1 Torr, 50 Torr, or 100 Torr. The temperature range of the deposition process is 200 to 650 degrees Celsius. The deposition process has a radio frequency (RF) power of 50 to 200 watts (W), for example, 10 watts, 100 watts, or 200 watts. The deposition process yields a high tensile stress layer with a thickness of... The achieved high tensile stress ranges from 800 to 1400 MPa.
[0048] Step 106: Perform plasma nitriding treatment on the high tensile stress layer to form a dense high tensile stress layer A251.
[0049] like Figure 2F As shown, the specific process steps of plasma nitriding are the same as those in step 104 above, and will not be repeated here. The purpose of plasma nitriding the surface of the high tensile stress layer A241 is to increase the nitrogen content on the surface of the high tensile stress layer, making the surface of the high tensile stress layer more compact, forming a dense interface, further increasing the ability to block hydrogen atom diffusion, and also reducing the hydrogen atom content within the high tensile stress layer A241 itself, thereby promoting the degradation of PMOS device performance.
[0050] Step 107: Repeat the deposition of the high tensile stress layer and plasma nitriding treatment.
[0051] like Figure 2G and Figure 2H As shown, a high tensile stress layer B261 is deposited, and a denser high tensile stress layer B271 is obtained after plasma nitriding. The specific details of the deposition and plasma nitriding processes are as described above and will not be repeated here. The high tensile stress layer serves both as a stress-applying layer and as a hydrogen barrier. The purpose of repeating the process is to create multiple dense interfaces within the multiple high tensile stress layers, further hindering hydrogen diffusion. The process is repeated 1 to 5 times; the example shown represents a process step repeated once. The actual number of repetitions depends on whether the reliability testing of the PMOS device manufactured using this method meets the standards.
[0052] Step 108: Deposit a low tensile stress layer.
[0053] like Figure 2I As shown, a low tensile stress layer 281 is formed on the densified high tensile stress layer B271 using a chemical vapor deposition (CVD) process. The low tensile stress layer preferably contains a low tensile stress nitride to cover the high tensile stress layer 251. The CVD method can be CVD, LPCVD, or PECVD, with PECVD being preferred. Furthermore, the reactants in the deposition process are silicon-containing gases, such as silanes, and nitrogen-containing gases, such as ammonia and nitrogen. The flow rate of the silicon-containing gas in the deposition process ranges from 1 to 200 sccm, for example, 20 sccm or 50 sccm; the flow rate of the nitrogen-containing gas in the deposition process ranges from 1 to 200 sccm, for example, 25 sccm, etc. The pressure range of the deposition process is 1 to 100 Torr, for example, 1 Torr, 50 Torr, or 100 Torr. The temperature range of the deposition process is 200 to 650 degrees Celsius. The radio frequency (RF) power of the deposition process is 1 to 49 watts (W), for example, 10 watts, 100 watts, or 200 watts. The deposition process yields a low-tensile-stress layer with a thickness of [missing information]. The achieved low tensile stress ranges from 1 to 700 MPa. The low-stress layer contains more hydrogen, resulting in more hydrogen evolution after annealing compared to the high-stress layer, leading to greater deformation applied to the gate 204. Therefore, the purpose of depositing the low-stress layer is to intensify the deformation applied to the gate 204 after the next rapid thermal annealing process, increase the stress applied to the NMOS channel region 292, improve the carrier mobility in the NMOS device channel region 292, and further enhance NMOS performance.
[0054] Step 109: Perform rapid thermal annealing.
[0055] In this step, the annealing method can be either peak annealing or laser annealing. During annealing, the atoms of the low tensile stress layer 281 and the denser high tensile stress layers B271 and A251 rearrange themselves more densely, thus applying greater compressive stress to the NMOS gate 204. Specifically, the compressive stress applied to the NMOS gate by the multilayer tensile stress layers (low tensile stress layer 281, denser high tensile stress layer B271, and denser high tensile stress layer A251) increases the electron mobility within the NMOS conductive channel, improving the NMOS's conductivity. The low tensile stress layer is sparser than the high tensile stress layer, contains more hydrogen, and undergoes greater deformation after rapid thermal annealing, allowing it to retain greater stress in the channel region 291. The high tensile stress layer is denser, contains less hydrogen, undergoes less deformation after rapid thermal annealing, and after plasma nitrogen treatment, has a stronger ability to block hydrogen.
[0056] Step 110: Remove all stress layers.
[0057] like Figure 2JAs shown, after the rapid thermal annealing process is completed, an etching process (e.g., dry etching or wet etching) will be used to remove the stress layer, and finally the etching will stop on the etching barrier layer.
[0058] After completion, standard CMOS processes are then performed, such as SAB (Salicide Block) process, Salicide process, contact hole process, and subsequent copper interconnect process, to complete the manufacturing of the CMOS device.
[0059] As can be seen from the specific embodiments of the present invention, the present invention provides a method for fabricating CMOS devices using stress memory technology. This method involves depositing an etch barrier layer on a wafer device before depositing a high tensile stress layer, the etch barrier layer covering at least simultaneously both the N-well and P-well; performing plasma nitriding on the etch barrier layer; and then repeatedly depositing and plasma nitriding the high tensile stress layer, the number of repetitions depending on the performance of the PMOS device; followed by depositing a low-stress layer; and finally annealing the wafer to promote stress application. The present invention reduces the NBTI effect of CMOS devices and mitigates the performance degradation of PMOS devices by strengthening the barrier layer and the ability of deposited and nitrided multilayer dense high tensile stress layers to resist hydrogen atom diffusion.
[0060] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.
Claims
1. A method for manufacturing CMOS devices based on multilayer stress memory technology, characterized in that... The method includes: An etch barrier layer is deposited on a wafer, and then subjected to plasma nitriding treatment; the wafer is... <100> Crystal orientation; A high tensile stress layer is deposited n times on the treated etch barrier layer, and the high tensile stress layer is subjected to plasma nitriding treatment; n≥1; A low tensile stress layer is deposited on the high tensile stress layer after plasma nitriding treatment; wherein the tensile stress of the low tensile stress layer is less than that of the high tensile stress layer, and the hydrogen content of the low tensile stress layer is greater than that of the high tensile stress layer. Rapid thermal annealing is performed on wafers with deposited etch barrier layers, high tensile stress layers, and low tensile stress layers; The wafer is etched after rapid thermal annealing to remove the high tensile stress layer and the low tensile stress layer.
2. The method according to claim 1, characterized in that, Before depositing the etch barrier layer on the wafer, the wafer is further processed as follows: a gate structure and sidewalls are formed on the semiconductor substrate of the wafer; source / drain ion implantation is completed in the NMOS device region and the PMOS device region by coating and developing, respectively.
3. The method according to claim 2, characterized in that, Etch barrier layers are deposited in the NMOS device region and PMOS device region where source / drain ions are implanted.
4. The method according to claim 1 or 3, characterized in that, The etching barrier layer is made of silicon nitride, silicon oxynitride, or silicon nitride.
5. The method according to claim 1, characterized in that, The plasma nitriding treatment conditions are as follows: nitrogen-containing gas is introduced into the surface of the etching barrier layer at a temperature of 200-650℃; the flow rate of the nitrogen-containing gas is 50-5000 sccm; the high-frequency power range of the nitrogen-containing gas is 10-2000W; and the pressure range of the nitrogen-containing gas is 1-100 Torr.
6. The method according to claim 1, characterized in that, The deposition process for the high tensile stress layer and the low tensile stress layer is chemical vapor deposition. The deposition process conditions for the high tensile stress layer are as follows: the reactants are silicon-containing gas and nitrogen-containing gas, the flow rate of the silicon-containing gas is 1-200 sccm, and the flow rate of the nitrogen-containing gas is 1-200 sccm; the pressure range of the deposition process is 1-100 Torr; the temperature range of the deposition process is 200-650℃; and the radio frequency power of the deposition process is 50-200W. The deposition process conditions for the low tensile stress layer are as follows: the reactants are silicon-containing gas and nitrogen-containing gas, the flow rate of the silicon-containing gas is 1-200 sccm, and the flow rate of the nitrogen-containing gas is 1-200 sccm; the pressure range of the deposition process is 1-100 Torr; and the temperature range of the deposition process is 200-650℃. The radio frequency power of the deposition process is 1-49W.
7. The method according to claim 1 or 6, characterized in that, The deposition thickness of the high tensile stress layer is 1-100 Å, and the tensile stress ranges from 800-1400 MPa; the deposition thickness of the low tensile stress layer is 1-300 Å, and the tensile stress ranges from 1-700 MPa.
8. The method according to claim 1, characterized in that, The tensile stresses of adjacent high tensile stress layers may be different or the same.
9. The method according to claim 1, characterized in that, An etch barrier layer and a high tensile stress layer are simultaneously applied over both the N-well and the P-well.