Charge collector, digital-analog converter, analog-digital conversion circuit and OLED touch device

Abstract

The application provides a charge collector, a digital-analog converter, an analog-digital conversion circuit and an OLED touch device. The charge collector comprises a K-bit switch capacitor array, a buffer module, a Na-time current mirror and a Nb-time current mirror. The charge collector can output a charge amount of Nb*Qin / Na by controlling the Na-time current mirror and the Nb-time current mirror, and the values of Na and Nb are variable. Therefore, the adjustable range of the charge amount can be increased under a small layout area and a small voltage, and the problems of increased circuit layout area, increased circuit cost and increased complexity caused by the method of multiplying voltage by capacitance to increase the charge amount in the prior art can be avoided. When applied to the DAC and the analog-digital conversion circuit, high-range high-signal-to-noise ratio detection of the DAC and the analog-digital conversion circuit can be realized. When applied to the OLED touch device, the touch sensitivity and accuracy of the OLED touch device can be improved.

Description

Technical Field

[0001] This invention relates to the field of OLED touch technology, and in particular to a charge harvester, a digital-to-analog converter, an analog-to-digital conversion circuit, and an OLED touch device. Background Technology

[0002] Generally, the feedback charge of a DAC (Digital-to-Analog Converter) is achieved by multiplying the voltage by the capacitance (i.e., Qdac = Vcom * Cin). Obviously, if a large feedback charge is required, a large voltage or a large capacitor is needed. A large voltage is generally achieved using a charge pump, but it is difficult to easily increase the voltage further using a charge pump. A large capacitor requires increasing the capacitance, which leads to a large layout area, and the increase in layout area is proportional to the increase in capacitance.

[0003] Therefore, how to obtain a large amount of feedback charge and improve the range of the DAC with a very small layout area and a very small voltage has become one of the technical problems that urgently need to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a charge harvester, a digital-to-analog converter, an analog-to-digital converter circuit, and an OLED touch device, which can output a high range and high precision charge quantity with a very small layout area and a very small voltage. Furthermore, when applied to an OLED touch device, it can improve the touch sensitivity and accuracy of the OLED touch device.

[0005] To achieve the above objectives, the present invention provides a charge harvester, comprising:

[0006] A K-bit switched capacitor array is used to provide K bits of input capacitance and provide a corresponding initial charge Qin based on the input capacitance, where K ≥ 2;

[0007] A buffer module, coupled to the output terminal of the K-bit switched capacitor array, is used to output a corresponding bias voltage according to the initial charge provided by the K-bit switched capacitor array.

[0008] A Na-fold current mirror, coupled to the output of the K-bit switched capacitor array and the output of the buffer module, is used to reduce the initial charge Qin to Qin / Na under the control of the bias voltage, where the value of Na is variable and Na≥1; and

[0009] The Nb current multiplier mirror is coupled to the output terminal of the Na current multiplier mirror and the buffer module. It is used to amplify the charge Qin / Na to Qdac=Nb*Qin / Na and output it under the control of the bias voltage. The value of Nb is variable and Nb≥1.

[0010] Optionally, the K-bit switched capacitor array includes K capacitors, one end of each of the K capacitors is connected to form the output terminal of the K-bit switched capacitor array, the other end of each capacitor is connected to one end of two corresponding switches, the other end of the switch to which each capacitor is connected is connected to a first voltage line to access the first voltage, the other end of the switch to which each capacitor is connected is connected to a second voltage line, the second voltage line can be selectively connected to a second voltage or ground, and the control terminals of the two switches are connected to inverted control signals.

[0011] Optionally, the Na-multiplier current mirror has n1 current mirror branches with binary weighting, and the value of Na ranges from [1, 2]. n1-1 ]; and / or, the Nb current-multiplying mirror has n² current mirror branches with binary weighting, and the value of Nb ranges from [1, 2]. n2 -1 ].

[0012] Optionally, each current mirror branch of the Na-fold current mirror and / or the Nb-fold current mirror includes an upper current mirror, an upper control switch, a lower control switch, and a lower current mirror that are coupled in sequence; the buffer module provides the corresponding bias voltage for the upper current mirror and the lower current mirror respectively.

[0013] Optionally, the upper current mirror includes cascaded PMOS transistors, and the lower current mirror includes cascaded NMOS transistors; the size or number of PMOS transistors in the n1 or n2 current mirror branches is binary weighted, and the size or number of NMOS transistors in the n1 or n2 current mirror branches is binary weighted.

[0014] Optionally, the number of n1 upper control switches and n1 lower control switches connected in the Na-multiplier current mirror can be controlled according to the value of Na, and / or the number of n2 upper control switches and n2 lower control switches connected in the Nb-multiplier current mirror can be controlled according to the value of Nb.

[0015] Based on the same inventive concept, the present invention also provides a digital-to-analog converter, which includes the charge acquisition device described in the present invention, for receiving corresponding digital signals and outputting the charge amount Nb*Qin / Na under the control of the digital signals.

[0016] Based on the same inventive concept, the present invention also provides an analog-to-digital converter circuit, which includes an integrator, a programmable gain amplifier, an analog-to-digital converter, and a digital-to-analog converter as described in the present invention; wherein, the output terminal of the integrator is coupled to the input terminal of the programmable gain amplifier, the output terminal of the programmable gain amplifier is coupled to the input terminal of the analog-to-digital converter, the input terminal of the digital-to-analog converter is coupled to the output terminal of the analog-to-digital converter, and the output terminal of the digital-to-analog converter is coupled to the input terminal of the integrator.

[0017] Optionally, the integrator includes an operational amplifier, an integrating capacitor, and an integrating switch. One end of the integrating capacitor and one end of the integrating switch are both coupled to the negative input terminal of the operational amplifier and the output terminal of the digital-to-analog converter. The other end of the integrating capacitor and the other end of the integrating switch are both coupled to the output terminal of the operational amplifier.

[0018] Optionally, the analog-to-digital converter outputs the digital signal to control the switches in the K-bit switched capacitor array of the digital-to-analog converter.

[0019] Based on the same inventive concept, the present invention also provides an OLED touch device, which includes an input electrode and an analog-to-digital conversion circuit coupled thereto as described in the present invention, the analog-to-digital conversion circuit being used to convert induced charge signals on the input electrode into digital signals.

[0020] Optionally, the OLED touch device further includes a current source coupled to the input electrode. The current source is used to extract or inject a corresponding amount of charge into the induced charge of the input electrode to obtain the charge amount of the input electrode after subtracting a reference. The digital-to-analog converter of the analog-to-digital conversion circuit is used to convert the digital signal into a feedback charge amount. The integrator of the analog-to-digital conversion circuit is used to integrate and output the difference between the charge amount after subtracting the reference and the charge amount fed back by the digital-to-analog converter.

[0021] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0022] 1. By adding a buffer module, a Na-time multiplier current mirror, and an Nb-time multiplier current mirror, Qdac can be flexibly magnified to Nb times its original value or reduced to 1 / Na times its original value. Na and Nb are variable, thereby increasing the adjustable range of the charge Qdac with a very small layout area and a very small voltage. This avoids the problems of increased circuit layout area, circuit cost, and complexity caused by using voltage multiplied by capacitance to increase the charge Qdac in the existing technology.

[0023] 2. The Na-multiplier current mirror has a binary-weighted n1-channel current mirror branch, and the Nb-multiplier current mirror has a binary-weighted n2-channel current mirror branch. This simplifies circuit design and makes it easier to dynamically adjust Na and Nb, which in turn makes it easier to dynamically control the charge Qdac.

[0024] 3. When applied to DACs, it can achieve high-range, high-signal-to-noise ratio detection for DACs.

[0025] 4. When applied to analog-to-digital converter circuits, it can increase the range of the input signal of the analog-to-digital converter circuit.

[0026] 5. When applied to OLED touch devices, it can improve the touch sensitivity and accuracy of the OLED touch devices. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an existing analog-to-digital converter (ADC).

[0028] Figure 2 This is a schematic diagram of the DAC structure in an existing analog-to-digital converter (ADC).

[0029] Figure 3 This is a schematic diagram of the structure of a DAC according to an embodiment of the present invention.

[0030] Figure 4 for Figure 3 The diagram shows the structure and circuit connection of the K-bit switched capacitor array and buffer module in the DAC.

[0031] Figure 5 for Figure 3 The diagram shows the structure and circuit connection of the Na-multiplier current mirror and the Nb-multiplier current mirror in the DAC.

[0032] Figure 6 This is a schematic diagram of the structure of an analog-to-digital converter (ADC) and an OLED touch device according to an embodiment of the present invention.

[0033] Figure 7 for Figure 6 The diagram shows a specific example of the structure of the analog-to-digital converter (ADC) and the OLED touch device. Detailed Implementation

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0035] In organic light-emitting diode (OLED) touch panel applications, the capacitance C of a finger or other object approaching or touching the OLED touch panel is collected. finger The change (of which is a variable, ranging from tens of fF to several pF) is used to detect the corresponding touch information, where the collected capacitance C finger The conversion is usually performed using an analog-to-digital converter (ADC) circuit. The accuracy of this ADC circuit determines the capacitance C of the sampled data. finger To ensure accuracy, a SAR ADC typically incorporates a digital-to-analog converter (DAC) and a successive approximation register analog-to-digital converter (SAR ADC). The DAC converts the SAR ADC output into a feedback charge quantity, which is then integrated and amplified before being input to the SAR ADC input. The range of the feedback charge quantity output by the DAC determines the range of the SAR ADC input signal, and this range further affects the SAR ADC's noise filtering capability.

[0036] Please refer to Figure 1 A typical existing analog-to-digital converter (ADC) circuit is a Σ-Δ (sigma-delta) ADC, which includes an integrator INT, a programmable gain amplifier PGA, a successive approximation ADC (SAR ADC), and a feedback DAC. The integrator INT, PGA, and SAR ADC are sequentially coupled. The input of the feedback DAC is coupled to the output of the SAR ADC, and the output of the feedback DAC is coupled to the negative input of the integrator INT. The positive input of the integrator INT is connected to a voltage Vcom. The feedback DAC converts the digital signal output from the SAR ADC into an analog signal (i.e., charge Qdac), which is provided to the negative input of the integrator INT. The integrator INT integrates the difference between the received input charge and the feedback charge Qdac. In some embodiments, a charge pump (charge_pump) providing the power supply voltage and a subtraction reference (superimposed on capacitor C) are also included. finger OLED screen capacitance C pannel The amount of charge minus the current source Idc.

[0037] Please refer to Figure 2 Traditional feedback DACs typically employ an array of n+1 switched capacitors. By using this feedback DAC to provide feedback on the digital signal output from the analog-to-digital converter in the OLED touch device, the sensitivity and accuracy of touch detection results can be improved.

[0038] Taking n=6 as an example, the feedback DAC is configured with: capacitors C0 to C6 (forming a capacitor array), switches SB0 to SB6, SA0 to SA6, and S0 to S1. One end of capacitors C0 to C6 and one end of switch S0 are interconnected and connected to the inverting input of integrator A0 to provide feedback charge Qdac to integrator INT. The other end of capacitor C0 is coupled to one end of switches SA0 and SB0, the other end of capacitor C1 is coupled to one end of switches SA1 and SB1, the other end of capacitor C2 is coupled to one end of switches SA2 and SB2, and the other end of capacitor C3 is coupled to one end of switches SA3 and SB3. The other end of capacitor C4 is coupled to one end of switches SA4 and SB4; the other end of capacitor C5 is coupled to one end of switches SA5 and SB5; the other end of capacitor C6 is coupled to one end of switches SA6 and SB6; the other ends of switches SA0 to SA6 and switch S0 are all coupled to the first voltage line Vcom; the other ends of switches SB0 to SB6 are all coupled to the second voltage line, and one end of the second voltage line is coupled to the fixed end of switch S1. The movable end of switch S1 can be selectively connected to the second voltage 2*Vcom or grounded AVSS; the control ends of switches SB0 to SB6 are connected to the switch signal V_S one by one. <0> ~V_S <6> The control terminals of switches SA0 to SA6 are connected to the switch signal V_L one by one. <0> ~V_L <6> The control terminal of switch S0 is connected to the clock signal CLK.

[0039] The capacitance values ​​of capacitors C0 through C6 are binary weighted. For example, the capacitance value of capacitor C0 is 1*150fF, the capacitance value of capacitor C1 is 2*150fF, the capacitance value of capacitor C2 is 4*150fF, the capacitance value of capacitor C3 is 8*150fF, the capacitance value of capacitor C4 is 16*150fF, the capacitance value of capacitor C5 is 32*150fF, and the capacitance value of capacitor C6 is 64*150fF. That is to say, the capacitance value of C1 is twice that of C0, the capacitance value of C2 is twice that of C1, the capacitance value of C3 is twice that of C2, the capacitance value of C4 is twice that of C3, the capacitance value of C5 is twice that of C4, and the capacitance value of C6 is twice that of C5.

[0040] In the circuit described above, the digital signal value Data<6:0> output by the SAR ADC corresponds to the 7-bit switching signals V_S<6:0> and V_L<6:0> of the feedback DAC, controlling the specific value of Cin connected to the feedback DAC. Since the capacitance values ​​of capacitors C0 to C6 are binary weighted, respectively [64,32,16,8,4,2,1]*150fF, when the switching signals V_S<6:0> and V_L<6:0> vary within the range of 1111111 to 0000000, the total capacitance value Cin connected to the feedback DAC can be N*150fF, where N is any natural number from 0 to 127.

[0041] In the above scheme, if a large feedback charge Qdac is to be achieved in the feedback DAC, it is necessary to increase Vcom, which requires increasing the output of the charge pump, but this will make the charge pump more complex and costly. On the other hand, increasing Cin will greatly increase the layout area of ​​the capacitor array.

[0042] In addition, since the range of the DAC determines the range of the entire analog-to-digital converter circuit, a small range of the analog-to-digital converter circuit means that even a small amount of noise will cause the analog-to-digital converter circuit to be fully biased, and the effective signal will not be captured. Therefore, increasing the range of the analog-to-digital converter circuit can improve the signal-to-noise ratio. Consequently, in the application of OLED touch devices, increasing the range of the analog-to-digital converter circuit can improve the touch sensitivity and accuracy of the OLED touch device.

[0043] Based on this, the present invention provides a new technical solution that can increase the range of a feedback DAC by tens of times with a very small area and a very small voltage. It is worth noting that the aforementioned... Figure 1 and Figure 2 This description is merely a source of information for the technical problems addressed in this invention and does not limit the application scope of the charge collector described below. When the charge collector described in this invention is applied to a DAC, the range of the DAC can be increased by tens of times. When a DAC containing this charge collector is applied to an ADC, the range of the ADC's input signal can be increased by a corresponding factor, while avoiding the problem of increasing the circuit layout area due to the use of large capacitors. This allows the analog-to-digital conversion circuit to have low power consumption characteristics while also achieving small circuit layout area, large range, high speed, and high precision. When a DAC containing this charge collector is applied to an OLED touch device, the touch sensitivity and accuracy of the OLED touch device can be improved.

[0044] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0045] Please refer to Figure 3 One embodiment of the present invention provides a charge harvester, which includes a K-bit switched capacitor array 10, a buffer module 11, a Na-fold current mirror 12 and an Nb-fold current mirror 13.

[0046] The K-bit switched capacitor array 10 is used to provide a K-bit input capacitor Cin and to provide a corresponding initial charge Qin = Vcom * Cin based on the input capacitor Cin, where K ≥ 2.

[0047] Optional, please refer to Figure 4 The K-bit switched capacitor array 10 includes K capacitors. One end of each of the K capacitors is connected to the other to form the output terminal of the K-bit switched capacitor array 10. The other end of each capacitor is connected to one end of two corresponding switches. The other end of the switch to which each capacitor is connected is connected to a first voltage line to access the first voltage. The other end of the switch to which each capacitor is connected is connected to a second voltage line. The second voltage line can be selectively connected to a second voltage or ground. The control terminals of the two switches are connected to inverted control signals.

[0048] Please continue to refer to this. Figure 4Taking K=7 as an example, the K-bit switched capacitor array 10 includes 7 capacitors C0 to C6 (forming a capacitor array) and switches SB0 to SB6, SA0 to SA6, and S0 to S1. One end of capacitors C0 to C6 is connected to one end of switch S0 to form the output terminal of the K-bit switched capacitor array 10, which provides an initial charge Qin to the buffer module 11. The other end of capacitor C0 is coupled to one end of switches SA0 and SB0, the other end of capacitor C1 is coupled to one end of switches SA1 and SB1, the other end of capacitor C2 is coupled to one end of switches SA2 and SB2, and the other end of capacitor C3 is coupled to one end of switches SA3 and S1. One end of B3 and the other end of capacitor C4 are coupled to one end of switches SA4 and SB4. The other end of capacitor C5 is coupled to one end of switches SA5 and SB5. The other end of capacitor C6 is coupled to one end of switches SA6 and SB6. The other ends of switches SA0 to SA6 and switch S0 are all coupled to the first voltage line Vcom. The other ends of switches SB0 to SB6 are all coupled to the second voltage line, and one end of the second voltage line is coupled to the fixed end of switch S1. The movable end of switch S1 can be selectively connected to the second voltage 2*Vcom or grounded AVSS. The control ends of switches SB0 to SB6 are connected to the switch signal V_S one by one. <0> ~V_S <6> The control terminals of switches SA0 to SA6 are connected to the switch signal V_L one by one. <0> ~V_L <6> The control terminal of switch S0 is connected to the clock signal CLK.

[0049] The capacitance values ​​of capacitors C0 through C6 are binary weighted. For example, the capacitance value of capacitor C0 is 1*150fF, the capacitance value of capacitor C1 is 2*150fF, the capacitance value of capacitor C2 is 4*150fF, the capacitance value of capacitor C3 is 8*150fF, the capacitance value of capacitor C4 is 16*150fF, the capacitance value of capacitor C5 is 32*150fF, and the capacitance value of capacitor C6 is 64*150fF. That is to say, the capacitance value of C1 is twice that of C0, the capacitance value of C2 is twice that of C1, the capacitance value of C3 is twice that of C2, the capacitance value of C4 is twice that of C3, the capacitance value of C5 is twice that of C4, and the capacitance value of C6 is twice that of C5.

[0050] In this 7-bit switched capacitor array, the 7-bit switching signals V_S<6:0> and V_L<6:0> control the on / off state of switches SB0-SB6 and SA0-SA6, thereby controlling the value of the input capacitor Cin provided by the 7-bit switched capacitor array. Since the capacitance values ​​of capacitors C0-C6 are binary weighted, respectively [64,32,16,8,4,2,1]*150fF, when the values ​​of the switching signals V_S<6:0> and V_L<6:0> vary within the range of 1111111 to 0000000, the input capacitor Cin provided by the 7-bit switched capacitor array can be N*150fF, where N is any natural number from 0 to 127. Therefore, by using the 7-bit switching signals V_S<6:0> and V_L<6:0>, the 7-bit switched capacitor array can provide the corresponding initial charge Qin = Vcom*Cin.

[0051] Please refer to Figure 3 and Figure 4 The input terminal of the buffer module 11 is coupled to the output terminal of the K-bit switched capacitor array 10, and the output terminal of the buffer module 11 is coupled to the control terminals of the Na-multiplier current mirror 12 and the Nb-multiplier current mirror 13. The buffer module 11 is used to output corresponding bias voltages Vbias1 to Vbias4 (the four bias voltages Vbias1 to Vbias4 can be the same or different) according to the initial charge Qin = Vcom * Cin provided by the K-bit switched capacitor array 10, so as to adaptively provide them to the control terminals of the Na-multiplier current mirror 12 and the Nb-multiplier current mirror 13.

[0052] Please continue to refer to this. Figure 4 As an example, the buffer module 11 can be a voltage buffer. In one embodiment, it includes an operational amplifier OP1. The positive input terminal of the operational amplifier OP1 is connected to an initial charge Qin = Vcom * Cin, and the negative input terminal of the operational amplifier OP1 is connected to a reference signal Vcom. The operational amplifier OP1 has four output terminals. The operational amplifier OP1 generates bias voltages Vbias1 to Vbias4 based on the initial charge Qin = Vcom * Cin and the reference signal Vcom, and outputs them to the four output terminals.

[0053] Please refer to Figures 3 to 5 The Na-multiplier current mirror 12 is coupled to the output terminal of the K-bit switched capacitor array 10 and the output terminal of the buffer module 11. It is used to multiply the initial charge Qin to Qin / Na under the control of bias voltages Vbias1 to Vbias4. The value of Na is variable and Na≥1.

[0054] Optionally, the Na-multiplier current mirror 12 has n1 current mirror branches with binary weighting, and the value of Na ranges from [1, 2].n1 -1], in one embodiment, Na is an n1-bit binary number with a minimum value of 1 and a maximum value of 2. n1 -1 (i.e., 2) n1-1 +2 n1-2 +... +2 0 Among them, the n1 current mirror branch can be controlled by the switching signal SBW. <n1:1>and switch signal SAW <n1:1>Switch signal SBW <n1:1>and switch signal SAW <n1:1>They can be the same or different.

[0055] Optionally, each current mirror branch in the Na-fold current mirror includes an upper current mirror, an upper control switch, a lower control switch, and a lower current mirror that are coupled in sequence. The buffer module 11 provides corresponding bias voltages for the upper current mirror and the lower current mirror, and the connection nodes of the upper control switch and the lower control switch of each current mirror branch are coupled to each other, serving as the input terminal of the Na-fold current mirror 12 and coupled to the output terminal of the K-bit switched capacitor array 10 to receive the initial charge Qin = Vcom * Cin.

[0056] In order to reduce the circuit layout area, the Na-fold current mirror 12 is a capacitor-free circuit module, which is mainly constructed using transistors such as MOS transistors. The upper current mirror includes at least two cascaded PMOS transistors, and the lower current mirror includes at least two cascaded NMOS transistors.

[0057] Please refer to Figures 3 to 5 Taking n1=6 as an example, the Na-fold current mirror 12 has 6 current mirror branches. Each current source branch includes an upper current mirror, an upper control switch SBW, a lower control switch SAW, and a lower current mirror that are coupled in sequence. The upper current mirror includes a first PMOS transistor and a second PMOS transistor, and the lower current mirror includes a first NMOS transistor and a second NMOS transistor.

[0058] Specifically, the first current mirror branch includes a first PMOS transistor PM11b, a second PMOS transistor PM11a, and a switch signal SBW. <1> The upper control switch SBW is controlled by the switch signal SAW. <1> The first control switch SAW, the first NMOS transistor NM11a, and the second NMOS transistor NM11b; the second current mirror branch includes the first PMOS transistor PM12b, the second PMOS transistor PM12a, and the switch controlled by the switching signal SBW. <2> The upper control switch SBW is controlled by the switch signal SAW. <2> The lower control switch SAW, the first NMOS transistor NM12a, and the second NMOS transistor NM12b; the third current mirror branch includes the first PMOS transistor PM13b, the second PMOS transistor PM13a, and the switch controlled by the switching signal SBW. <3> The upper control switch SBW is controlled by the switch signal SAW. <3> The lower control switch SAW, the first NMOS transistor NM13a, and the second NMOS transistor NM13b; the fourth current mirror branch includes the first PMOS transistor PM14b, the second PMOS transistor PM14a, and the switch controlled by the switching signal SBW. <4> The upper control switch SBW is controlled by the switch signal SAW. <4> The lower control switch SAW, the first NMOS transistor NM14a, and the second NMOS transistor NM14b; the fifth current mirror branch includes the first PMOS transistor PM15b, the second PMOS transistor PM15a, and the switch controlled by the switching signal SBW. <5> The upper control switch SBW is controlled by the switch signal SAW. <5> The lower control switch SAW, the first NMOS transistor NM15a, and the second NMOS transistor NM15b; the sixth current mirror branch includes the first PMOS transistor PM16b, the second PMOS transistor PM16a, and the switch controlled by the switching signal SBW. <6> The upper control switch SBW is controlled by the switch signal SAW. <6> The lower control switch SAW, the first NMOS transistor NM16a, and the second NMOS transistor NM16b.

[0059] In the first current mirror branch, the drain of the first PMOS transistor PM11b is coupled to the source of the second PMOS transistor PM11a, the drain of the second PMOS transistor PM11a is coupled to one end of the upper control switch in this branch, the drain of the first NMOS transistor NM11a is coupled to one end of the lower control switch in this branch, the drain and source of the first NMOS transistor NM11a are coupled to the drain of the second NMOS transistor NM11b, and the source of the second NMOS transistor NM11b is grounded to AVSS.

[0060] The connections of the transistors and control switches in the current mirror branches 2 to 6 are the same as those in the current mirror branch 1, and will not be described in detail here.

[0061] Furthermore, the gates of the first PMOS transistors PM11b to PM16b can be coupled to each other and to the first output terminal of the buffer module 11 to receive a bias voltage Vbias1; the gates of the second PMOS transistors PM11a to PM16a can be coupled to each other and to the second output terminal of the buffer module 11 to receive a bias voltage Vbias2; the gates of the first NMOS transistors NM11a to NM16a can be coupled to each other and to the third output terminal of the buffer module 11 to receive a bias voltage Vbias3; and the gates of the second NMOS transistors NM11b to NM16b can be coupled to each other and to the fourth output terminal of the buffer module 11 to receive a bias voltage Vbias4.

[0062] It should be noted that the dimensions of the first PMOS transistors PM11b to PM16b are binary weighted, that is, the dimension M of the first PMOS transistor PM11b is 1, the dimension M of the first PMOS transistor PM12b is 2 (twice the dimension of the first PMOS transistor PM11b), the dimension M of the first PMOS transistor PM13b is 4 (twice the dimension of the first PMOS transistor PM12b), the dimension M of the first PMOS transistor PM14b is 8 (twice the dimension of the first PMOS transistor PM13b), the dimension M of the first PMOS transistor PM15b is 16 (twice the dimension of the first PMOS transistor PM14b), and the dimension M of the first PMOS transistor PM16b is 32 (twice the dimension of the first PMOS transistor PM15b). In another embodiment, the number of first PMOS transistors PM11b to PM16b is binary weighted: the first PMOS transistor PM12b of branch M=2 can be implemented by two transistors identical to the first PMOS transistor PM11b of branch M=1 connected in parallel; the first PMOS transistor PM13b of branch M=4 can be implemented by four transistors identical to the first PMOS transistor PM11b of branch M=1 connected in parallel; ... the first PMOS transistor PM16b of branch M=32 can be implemented by 32 transistors identical to the first PMOS transistor PM11b of branch M=1 connected in parallel.

[0063] The dimensions of the second NMOS transistors NM11b to NM16b are also binary weighted. That is, the dimension M of the second NMOS transistor NM11b is 1, the dimension M of the second NMOS transistor NM12b is 2 (twice the dimension of the second NMOS transistor NM11b), the dimension M of the second NMOS transistor NM13b is 4 (twice the dimension of the second NMOS transistor NM12b), the dimension M of the second NMOS transistor NM14b is 8 (twice the dimension of the second NMOS transistor NM13b), the dimension M of the second NMOS transistor NM15b is 16 (twice the dimension of the second NMOS transistor NM14b), and the dimension M of the second NMOS transistor NM16b is 32 (twice the dimension of the second NMOS transistor NM15b). In another embodiment, the number of the first NMOS transistors NM11b to NM16b is binary weighted: the first NMOS transistor NM12b of the M=2 branch can be implemented by two transistors identical to the first NMOS transistor NM11b of the M=1 branch connected in parallel; the first NMOS transistor NM13b of the M=4 branch can be implemented by four transistors identical to the first NMOS transistor NM11b of the M=1 branch connected in parallel; and so on, the first NMOS transistor NM16b of the M=32 branch can be implemented by 32 transistors identical to the first NMOS transistor NM11b of the M=1 branch connected in parallel.

[0064] The switching signals SBW<6:1> and SAW<6:1> can be the same or different.

[0065] Please refer to Figures 3 to 5 The Nb current multiplier mirror 13 is coupled to the output terminal of the Na current multiplier mirror 13 and the buffer module 11. Under the control of the bias voltage Vbias1~Vbias4, it amplifies the charge Qin / Na provided by the Na current multiplier mirror 13 to Nb*Qin / Na and outputs it. The value of Nb is variable and Nb≥1.

[0066] Optionally, the Nb current doubler mirror 13 has n² current mirror branches with binary weighting, and the value of Nb ranges from [1, 2]. n2 -1], in one embodiment, Nb is an n2-bit binary number with a minimum value of 1 and a maximum value of 2. n2 -1 (i.e., 2) n2-1 +2 n2-2 +... +2 0 Furthermore, n2 can be equal to or different from n1 of the aforementioned Na-fold current mirror 12. Additionally, the n2 current mirror branch can be controlled by the switching signal SDW. <n2:1>and switch signal SCW <n2:1>Switch signal SDW <n2:1>and switch signal SCW <n2:1>They can be the same or different.

[0067] Optionally, each current mirror branch in the Nb current multiplier 13 includes an upper current mirror, an upper control switch, a lower control switch, and a lower current mirror that are coupled in sequence. The buffer module 11 provides corresponding bias voltages for each upper and lower current mirror of the Nb current multiplier 13. The connection nodes of the upper and lower control switches of each current mirror branch of the Nb current multiplier 13 are coupled to each other, serving as the output terminal of the Nb current multiplier 13, with an output charge Qdac = Nb * Qin / Na.

[0068] In order to save circuit layout area, the Nb current doubler mirror 13 is a capacitor-free circuit module, which is mainly constructed using transistors such as MOS transistors. The upper current mirror includes at least two cascaded PMOS transistors, and the lower current mirror includes at least two cascaded NMOS transistors.

[0069] Please refer to Figures 3 to 5 Taking n2=6 as an example, the Nb current multiplier mirror 13 has 6 current mirror branches. Each current source branch includes an upper current mirror, an upper control switch SBW, a lower control switch SAW, and a lower current mirror that are coupled in sequence. The upper current mirror includes a first PMOS transistor and a second PMOS transistor, and the lower current mirror includes a first NMOS transistor and a second NMOS transistor.

[0070] Specifically, in the Nb current multiplier mirror 13, the first current mirror branch includes a first PMOS transistor PM21b, a second PMOS transistor PM21a, and a switch signal SDW. <1> The upper control switch SDW is controlled by the switch signal SCW. <1> The first control switch SCW, the first NMOS transistor NM21a, and the second NMOS transistor NM21b; the second current mirror branch includes the first PMOS transistor PM22b, the second PMOS transistor PM22a, and the switch controlled by the switching signal SDW. <2> The upper control switch SDW is controlled by the switch signal SCW. <2> The lower control switch SCW, the first NMOS transistor NM22a, and the second NMOS transistor NM22b; the third current mirror branch includes the first PMOS transistor PM23b, the second PMOS transistor PM23a, and the switch controlled by the switching signal SDW. <3> The upper control switch SDW is controlled by the switch signal SCW. <3> The lower control switch SCW, the first NMOS transistor NM23a, and the second NMOS transistor NM23b; the fourth current mirror branch includes the first PMOS transistor PM24b, the second PMOS transistor PM24a, and the switch controlled by the switching signal SDW. <4> The upper control switch SBW is controlled by the switch signal SCW. <4> The lower control switch SAW, the first NMOS transistor NM24a, and the second NMOS transistor NM24b; the fifth current mirror branch includes the first PMOS transistor PM25b, the second PMOS transistor PM25a, and the switch controlled by the switching signal SDW. <5> The upper control switch SDW is controlled by the switch signal SCW. <5> The lower control switch SCW, the first NMOS transistor NM25a, and the second NMOS transistor NM25b; the sixth current mirror branch includes the first PMOS transistor PM26b, the second PMOS transistor PM26a, and the switch controlled by the switching signal SDW. <6> The upper control switch SDW is controlled by the switch signal SCW. <6> The lower control switch SCW, the first NMOS transistor NM26a, and the second NMOS transistor NM26b.

[0071] In the first current mirror branch, the drain of the first PMOS transistor PM21b is coupled to the source of the second PMOS transistor PM21a, the drain of the second PMOS transistor PM21a is coupled to one end of the upper control switch in this branch, the drain of the first NMOS transistor NM21a is coupled to one end of the lower control switch in this branch, the drain and source of the first NMOS transistor NM21a are coupled to the drain of the second NMOS transistor NM21b, and the source of the second NMOS transistor NM21b is grounded to AVSS.

[0072] The connections of the transistors and control switches in the current mirror branches 2 to 6 are the same as those in the current mirror branch 1, and will not be described in detail here.

[0073] Furthermore, the gates of the first PMOS transistors PM21b to PM26b can be coupled to each other and to the first output terminal of the buffer module 11 and the gates of the first PMOS transistors PM11b to PM16b to access the bias voltage Vbias1. The gates of the second PMOS transistors PM21a to PM26a can be coupled to each other and to the second output terminal of the buffer module 11 and the gates of the second PMOS transistors PM11a to PM16a to access the bias voltage Vbias2. The gates of the first NMOS transistors NM21a to NM26a can be coupled to each other and to the third output terminal of the buffer module 11 and the gates of the first NMOS transistors NM11a to NM16a to access the bias voltage Vbias3. The gates of the second NMOS transistors NM21b to NM26b can be coupled to each other and to the fourth output terminal of the buffer module 11 and the gates of the second NMOS transistors NM11b to NM16b to access the bias voltage Vbias4.

[0074] It should be noted that the dimensions of the first PMOS transistors PM21b to PM26b are binary weighted, that is, the dimension M of the first PMOS transistor PM21b is 1, the dimension M of the first PMOS transistor PM22b is 2 (twice the dimension of the first PMOS transistor PM21b), the dimension M of the first PMOS transistor PM23b is 4 (twice the dimension of the first PMOS transistor PM22b), the dimension M of the first PMOS transistor PM24b is 8 (twice the dimension of the first PMOS transistor PM23b), the dimension M of the first PMOS transistor PM25b is 16 (twice the dimension of the first PMOS transistor PM24b), and the dimension M of the first PMOS transistor PM26b is 32 (twice the dimension of the first PMOS transistor PM25b). In another embodiment, the number of first PMOS transistors PM21b to PM26b is binary weighted: the first PMOS transistor PM22b of branch M=2 can be implemented by two transistors identical to the first PMOS transistor PM21b of branch M=1 connected in parallel; the first PMOS transistor PM23b of branch M=4 can be implemented by four transistors identical to the first PMOS transistor PM21b of branch M=1 connected in parallel; ... the first PMOS transistor PM26b of branch M=32 can be implemented by 32 transistors identical to the first PMOS transistor PM21b of branch M=1 connected in parallel.

[0075] The dimensions of the second NMOS transistors NM21b to NM26b are also binary weighted. That is, the dimension M of the second NMOS transistor NM21b is 1, the dimension M of the second NMOS transistor NM22b is 2 (twice the dimension of the second NMOS transistor NM21b), the dimension M of the second NMOS transistor NM23b is 4 (twice the dimension of the second NMOS transistor NM22b), the dimension M of the second NMOS transistor NM24b is 8 (twice the dimension of the second NMOS transistor NM23b), the dimension M of the second NMOS transistor NM25b is 16 (twice the dimension of the second NMOS transistor NM24b), and the dimension M of the second NMOS transistor NM26b is 32 (twice the dimension of the second NMOS transistor NM25b). In another embodiment, the number of the first NMOS transistors NM21b to NM26b is binary weighted: the first NMOS transistor NM22b of the M=2 branch can be implemented by two transistors identical to the first NMOS transistor NM11b of the M=1 branch connected in parallel; the first NMOS transistor NM23b of the M=4 branch can be implemented by four transistors identical to the first NMOS transistor NM21b of the M=1 branch connected in parallel; and so on, the first NMOS transistor NM26b of the M=32 branch can be implemented by 32 transistors identical to the first NMOS transistor NM21b of the M=1 branch connected in parallel.

[0076] Furthermore, the switching signals SDW<6:1> and SCW<6:1> can be the same or different.

[0077] Of course, in other embodiments of the present invention, the aforementioned MOS transistors can be replaced by suitable switching elements such as bipolar transistors or triodes.

[0078] In addition, in each current mirror branch, the second PMOS transistor is the follower transistor of the first PMOS transistor cascaded thereto, and the first NMOS transistor is the follower transistor of the second NMOS transistor cascaded thereto. The purpose of setting these follower transistors is to improve the load-carrying capacity and output current capacity of the current mirror branch in which it is located, reduce the output impedance, and not affect the current or voltage gain, so as to avoid the output distortion of the current mirror branch in which it is located.

[0079] In each current mirror branch of the Na-multiplier current mirror 12 and the Nb-multiplier current mirror 13, the cascaded first PMOS transistor and the second PMOS transistor constitute an upper current mirror (or more than two PMOS transistors can be cascaded to form an upper current mirror). The first PMOS transistor determines the current magnitude of the upper current mirror. The cascaded first NMOS transistor and the second NMOS transistor constitute a lower current mirror (or more than two NMOS transistors can be cascaded to form a lower current mirror, with the first NMOS transistor determining the current magnitude of the lower current mirror).

[0080] The operation of the charge harvester in this embodiment consists of two stages:

[0081] In the initial stage, the K-bit switched capacitor array 10 remains unchanged, and the voltage at the positive input terminal of the buffer module 11 is stable and equal to the voltage Vcom at the negative input terminal.

[0082] During the change phase, when the switching on and off of switches SB0~SB6 and SA0~SA6 of the K-bit switched capacitor array 10 changes, the input capacitance Cin provided by them changes, which in turn changes the initial charge output Qin = Vcom * Cin. Therefore, if this causes the voltage at the positive input terminal of the buffer module 11 to increase, the bias voltages Vbias1~Vbias4 output by the buffer module 11 also increase. Consequently, the gate voltage of the PMOS transistor in the upper current mirror increases, thus increasing the leakage current I. D As the current decreases, the gate voltage of the NMOS transistor in the lower current mirror increases, thus increasing the leakage current I. D The leakage current I of the upper and lower current mirrors increases. D The difference is the node current of the NMOS transistor in the lower current mirror flowing from the initial charge Qin. This causes excess charge in the initial charge Qin to flow to ground AVSS through the NMOS transistor in the lower current mirror, thus consuming this excess charge until the voltage at the positive input terminal of the buffer module 11 drops to the voltage at the negative input terminal Vcom, returning to the initial state. During this process, the switching signal SAW in the Na-fold current mirror is adjusted. <n1:1>and switch signal SBW <n1:1>The number of actual current mirrors, Na, is adjusted to divide the initial charge Qin into Na parts. The charge in each Na-fold current mirror is Q1 = Qin / Na. The switching signal SDW in the Nb-fold current mirror is further adjusted. <n2:1>and switch signal SCW <n2:1>This is to adjust the actual number of current mirrors Nb, thereby adjusting the charge output of the Nb-fold current mirror to Qdac = Q1 * Nb = Nb * Qin / Na. Here, Na is an n1-bit binary value, ranging from [1, 2]. n1 -1], Nb is an n2-bit binary value, whose value range is [1, 2]. n2 -1]. Specifically, when n1 = 6, the size or number of PMOS transistors PM11b to PM16b in the upper current mirror is determined by binary weighting. When switch SBW<6:1> is 111111, the maximum Na value is 32 + 16 + 8 + 4 + 2 + 1 = 64 - 1 = 63. When switch SBW<6:1> is 000001, the minimum Na value is 1. This allows Na to take any value from 1 to 63. When N2 = 6, the size or number of PMOS transistors PM21b to PM26b in the upper current mirror is determined by binary weighting. When switch SDW<6:1> is 111111, the maximum Nb value is 32 + 16 + 8 + 4 + 2 + 1 = 26 - 1 = 63. When switch SDW<6:1> is 000001, the minimum Nb value is 1. This allows Nb to take any value from 1 to 63.

[0083] Obviously, by changing the values ​​of Nb and Na, Qdac can be flexibly increased to 64 times its original value or decreased to 1 / 64 of its original value. In summary, in this embodiment, the number of 6 (n1) upper control switches SBW<6:1> and 6 (n1) lower control switches SAW<6:1> connected in the Na-multiplier current mirror can be controlled according to the value of Na, and / or the number of 6 (n2) upper control switches SDW<6:1> and 6 (n2) lower control switches SCW<6:1> connected in the Nb-multiplier current mirror can be controlled according to the value of Nb. That is, in any embodiment of the present invention, the n1 upper control switches SBW<6:1> in the Na-multiplier current mirror can be controlled according to the value of Na. <n1:1>and n1 lower control switches SAW <n1:1>The number of connected devices, and / or, based on the value of Nb, control the n2 upper control switches SDW in the Nb-multiplier current mirror. <n2:1>and n2 lower control switches SCW <n2:1>Number of connections.

[0084] It should be understood that in the above examples, both the Na-multiplied current mirror and the Nb-multiplied current mirror have an upper current mirror and a lower current mirror, but the technical solution of the present invention is not limited to this. In other examples of the present invention, the following can be omitted. Figure 5 The upper circuitry of each current mirror branch of the Na-multiplier current mirror and / or Nb-multiplier current mirror (including the first PMOS transistor, the second PMOS transistor, and the upper control switch), or, omitted. Figure 5 The lower circuits of each current mirror branch of the Na-multiplier current mirror and / or Nb-multiplier current mirror (including the first NMOS transistor, the second NMOS transistor, and the lower control switch) can be adaptively adjusted to the circuits of modules such as the buffer module 11 and the subsequent circuits of the charge acquisition unit, so as to eliminate redundant circuit parts of unwanted signals provided by these modules to or received from the Na-multiplier current mirror and / or Nb-multiplier current mirror.

[0085] It should be further understood that, in the above examples, components such as follower transistors are provided, but the technical solution of the present invention is not limited to this, and follower transistors may be omitted in other embodiments of the present invention.

[0086] In summary, the charge harvester of this embodiment can obtain a large charge output without increasing the voltage (Vcom) or increasing the capacitance (Cin) by expanding the layout area. At the same time, it can obtain an increased or decreased charge output without changing the original capacitor array design.

[0087] Based on the same inventive concept, please refer to Figures 3 to 5 An embodiment of the present invention also provides a digital-to-analog converter (DAC), which includes the charge collector described in any embodiment of the present invention. The charge collector is used to receive a corresponding digital signal and output a corresponding charge quantity Qdac=Cin*Vcom*Nb / Na under the control of the digital signal.

[0088] Since the digital-to-analog converter (DAC) of this embodiment uses the charge harvester of the present invention, the range of the DAC can be increased without increasing the voltage (Vcom) or by increasing the circuit layout area to increase the capacitance (Cin).

[0089] Based on the same inventive concept, please refer to Figures 3 to 7 An embodiment of the present invention also provides an analog-to-digital converter circuit, which includes an integrator INT, a programmable gain amplifier PGA, an analog-to-digital converter (SAR ADC), and a digital-to-analog converter (DAC) as described in the present invention. The output terminal of the integrator INT is coupled to the input terminal of the programmable gain amplifier PGA, the output terminal of the programmable gain amplifier PGA is coupled to the input terminal of the SAR ADC, the input terminal of the DAC is coupled to the output terminal of the SAR ADC, and the output terminal of the DAC is coupled to the negative input terminal of the integrator INT.

[0090] Optionally, the integrator INT includes operational amplifier OP2 and integrating capacitor C. INT Integrating switch SW_INT, integrating capacitor C INT One end of the integrating capacitor and one end of the integrating switch SW_INT are both coupled to the negative input terminal of the operational amplifier OP2 and the output terminal of the digital-to-analog converter DAC. INT The other end of the circuit and the other end of the integral switch SW_INT are both coupled to the output of the operational amplifier OP2.

[0091] Optionally, the digital signal Data output by the analog-to-digital converter (SAR ADC) controls the digital-to-analog converter (DAC) in functions such as... Figure 4 The switching signal V_S in the K-bit switched capacitor array shown <k-1:0>and V_L <k-1:0>.

[0092] Based on the same inventive concept, please refer to Figures 3 to 7 An embodiment of the present invention also provides an OLED touch device, which includes an input electrode TRX pad and a current source I for implementing a subtraction reference. dc And the analog-to-digital converter circuit as described in this invention. The input electrode TRX pad is coupled to the input terminal of the integrator INT and the output terminal of the digital-to-analog converter DAC in the analog-to-digital converter circuit. The current source I... dc The system is used to extract or inject a corresponding amount of charge into the induced charge of the input electrode TRX pad to obtain the subtracted reference charge of the input electrode TRX pad. The digital-to-analog converter (DAC) is used to convert the output (i.e., digital signal Data) of the analog-to-digital converter (SAR ADC) into a feedback charge Qdac. The integrator (INT) is used to integrate the difference between the subtracted reference charge and the charge Qdac fed back by the DAC and output the result. The programmable gain amplifier (PGA) is used to amplify the output of the integrator (INT), and the SAR ADC is used to convert the analog signal output by the PGA into a digital signal Data.

[0093] It should be understood that the digital signal Data output by the analog-to-digital converter (SAR ADC) may include: the switching signal V_S required by the K-bit switched capacitor array 10. <k-1:0>and V_L <k-1:0>It is worth noting that the switching signal SAW required for the Na-multiplier current mirror... <n1:1>and SBW <n1:1>And, the switching signal SDW required for the Nb current-doubling mirror. <n2:1>and SCW <n2:1>The range required by the digital-to-analog converter (DAC) is used to debug, determine, and temporarily store the data.

[0094] In summary, the charge harvester, digital-to-analog converter, analog-to-digital converter circuit, and OLED touch device of the present invention can avoid the use of voltage divider technology, driver operational amplifiers, and a large number of capacitors, thus simplifying the circuit, reducing costs, and saving circuit layout area. More importantly, by changing the number of current mirrors Na connected to the Na-multiplier current mirror and the number of current mirrors Nb connected to the Nb-multiplier current mirror, the output charge Qdac can be increased or decreased with a very small area and a very small voltage. This can improve the range of the DAC, enabling high-range, high-signal-to-noise ratio signal detection in the analog-to-digital converter circuit, thereby improving the touch sensitivity and accuracy of the OLED touch device.

[0095] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. A charge harvester, characterized in that, include: A K-bit switched capacitor array is used to provide K bits of input capacitance and provide a corresponding initial charge Qin based on the input capacitance, where K ≥ 2; A buffer module, coupled to the output terminal of the K-bit switched capacitor array, is used to output a corresponding bias voltage according to the initial charge provided by the K-bit switched capacitor array. A Na-fold current mirror is coupled to the output of the K-bit switched capacitor array and the output of the buffer module. It is used to reduce the initial charge Qin to Qin / Na under the control of the bias voltage. The value of Na is variable and Na≥1. and The Nb current multiplier mirror is coupled to the output terminal of the Na current multiplier mirror and the buffer module. It is used to amplify the charge Qin / Na to Nb * Qin / Na and output it under the control of the bias voltage. The value of Nb is variable and Nb≥1.

2. The charge harvester as described in claim 1, characterized in that, The K-bit switched capacitor array includes K capacitors. One end of each of the K capacitors is connected to the other to form the output terminal of the K-bit switched capacitor array. The other end of each capacitor is connected to one end of two corresponding switches. The other end of the switch to which each capacitor is connected is connected to a first voltage line to receive a first voltage. The other end of the switch to which each capacitor is connected is connected to a second voltage line, which is connected to a second voltage or ground. The control terminals of the two switches are connected to inverted control signals.

3. The charge harvester as described in claim 1, characterized in that, The Na-multiplier current mirror has n1 current mirror branches with binary weighting, and the value of Na ranges from [1, 2]. n1 -1]; and / or, the Nb current doubler mirror has n2 current mirror branches with binary weighting, and the value range of Nb is [1, 2]. n2 -1].

4. The charge harvester as described in claim 3, characterized in that, Each current mirror branch of the Na-fold current mirror and / or the Nb-fold current mirror includes an upper current mirror, an upper control switch, a lower control switch, and a lower current mirror that are coupled in sequence; the buffer module provides the corresponding bias voltage for the upper current mirror and the lower current mirror respectively.

5. The charge harvester as described in claim 4, characterized in that, The upper current mirror includes cascaded PMOS transistors, and the lower current mirror includes cascaded NMOS transistors; the size or number of PMOS transistors in the n1 current mirror branch or the n2 current mirror branch is binary weighted, and the size or number of NMOS transistors in the n1 current mirror branch or the n2 current mirror branch is binary weighted.

6. The charge harvester as described in claim 4, characterized in that, The number of n1 upper control switches and n1 lower control switches connected in the Na-multiplier current mirror is controlled according to the value of Na, and / or the number of n2 upper control switches and n2 lower control switches connected in the Nb-multiplier current mirror is controlled according to the value of Nb.

7. A digital-to-analog converter, characterized in that, The charge harvester includes any one of claims 1-6, for receiving a corresponding digital signal and outputting the charge amount Nb * Qin / Na under the control of the digital signal.

8. An analog-to-digital converter circuit, characterized in that, The system includes an integrator, a programmable gain amplifier, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC) as described in claim 7; wherein the output of the integrator is coupled to the input of the programmable gain amplifier, the output of the programmable gain amplifier is coupled to the input of the ADC, the input of the DAC is coupled to the output of the ADC, and the output of the DAC is coupled to the input of the integrator.

9. The analog-to-digital converter circuit as described in claim 8, characterized in that, The integrator includes an operational amplifier, an integrating capacitor, and an integrating switch. One end of the integrating capacitor and one end of the integrating switch are both coupled to the negative input terminal of the operational amplifier and the output terminal of the digital-to-analog converter. The other end of the integrating capacitor and the other end of the integrating switch are both coupled to the output terminal of the operational amplifier.

10. The analog-to-digital converter circuit as described in claim 8, characterized in that, The analog-to-digital converter outputs the digital signal to control the switches in the K-bit switched capacitor array of the digital-to-analog converter.

11. An OLED touch device, characterized in that, The analog-to-digital converter circuit as described in any one of claims 8-10 includes an input electrode and a circuit coupled thereto thereto, the analog-to-digital converter circuit being used to convert an induced charge signal on the input electrode into a digital signal.

12. The OLED touch device as claimed in claim 11, characterized in that, It also includes a current source coupled to the input electrode, the current source being used to extract or inject a corresponding amount of charge into the induced charge of the input electrode to obtain the charge amount of the input electrode after subtracting the reference. The digital-to-analog converter of the analog-to-digital conversion circuit is used to convert the digital signal into a feedback charge amount. The integrator of the analog-to-digital conversion circuit is used to integrate and output the difference between the charge amount after subtracting the reference and the charge amount fed back by the digital-to-analog converter.

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