Time synchronization method and apparatus

Abstract

The application provides a time synchronization method and device, the method comprising: receiving a first PTP protocol message sent by a master device, the first PTP protocol message comprising a first timestamp with a first sub-timestamp and a second sub-timestamp; transmitting the first sub-timestamp and the second sub-timestamp to a clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp in a first time register; periodically acquiring the first sub-timestamp from the first time register and transmitting the first sub-timestamp to a switching chip by a software task, the switching chip stores the first sub-timestamp in a second time register; and the clock chip generates a hardware task, the hardware task is used to periodically acquire the second sub-timestamp from the first time register and transmit the second sub-timestamp to the switching chip and a PHY chip, the switching chip stores the second sub-timestamp in the second time register, and the PHY chip stores the second sub-timestamp in a third time register.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a time synchronization method and apparatus. Background Technology

[0002] Precision Time Protocol (PTP) is a time synchronization protocol used for high-precision time and frequency synchronization between devices. PTP's time synchronization accuracy is at the sub-microsecond level.

[0003] Currently, networks using the PTP protocol are called PTP domains. A PTP domain has one and only one clock source, and all devices within the domain are synchronized with this clock. This clock source refers to the time configured within the master device. Devices other than the master device within the domain are called slave devices, and slave devices need to synchronize their time with the master device via PTP.

[0004] The master / slave device obtains the current timestamp from its local PHY chip and sends it to the peer in a PTP protocol message. Upon receiving the PTP protocol message from the master device, the slave device obtains the current timestamp and modifies the time register in its local PHY chip accordingly to ensure time synchronization with the master device.

[0005] However, the existing time synchronization methods also reveal the following problems: 1) The slave device includes not only the PHY chip, but also clock chips, switching chips, etc. When synchronizing with the master device, the slave device only modifies the time register in the PHY chip, while leaving the time registers in other chips unchanged. This results in phase differences among the multiple chips within the slave device; 2) The existence of phase differences also leads to inaccurate timestamps obtained by the slave device. This is because within the slave device, the clock chip provides a reference clock and a 1PPS signal to the PHY chip. After the time register in the PHY chip is modified, the clock chip can then modify the time register in the PHY chip again using the reference clock and the 1PPS signal. Summary of the Invention

[0006] In view of this, this application provides a time synchronization method and apparatus to solve the problems of phase difference between multiple chips inside the device and inaccurate current timestamp obtained from the device in existing time synchronization methods.

[0007] In a first aspect, this application provides a time synchronization method applied to a slave device located in a PTP domain, the PTP domain further including a master device, the slave device including a clock chip, a PHY chip, and a switching chip, the method comprising:

[0008] Receive a first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp.

[0009] The first sub-timestamp and the second sub-timestamp are transmitted to the clock chip so that the clock chip stores the first sub-timestamp and the second sub-timestamp in the first time register in the clock chip;

[0010] Through a software task, the first sub-timestamp is periodically retrieved from the first time register and transmitted to the switching chip. The switching chip stores the first sub-timestamp in its second time register. This also causes the clock chip to generate a hardware task, which enables the clock chip to periodically retrieve from the first time register and transmit the second sub-timestamp to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in its second time register, and the PHY chip stores the second sub-timestamp in its third time register.

[0011] Secondly, this application provides a time synchronization device applied to a slave device located in a PTP domain. The PTP domain also includes a master device. The slave device includes a clock chip, a PHY chip, and a switching chip. The device comprises:

[0012] The receiving unit is configured to receive a first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp.

[0013] A transmission unit is used to transmit the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp in the first time register of the clock chip;

[0014] The transmission unit is further configured to periodically acquire and transmit the first sub-timestamp from the first time register to the switching chip via a software task. The switching chip stores the first sub-timestamp in a second time register within the switching chip. The clock chip also generates a hardware task to cause the clock chip to periodically acquire and transmit the second sub-timestamp from the first time register to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in the second time register, and the PHY chip stores the second sub-timestamp in a third time register within the PHY chip.

[0015] Thirdly, this application provides a network device, which is a slave device in a PTP domain. The PTP domain also includes a master device. The slave device includes a processor, a communication interface, a memory, a communication bus, a clock chip, a PHY chip, and a switching chip. The processor, the communication interface, the memory, the clock chip, the PHY chip, and the switching chip communicate with each other through the communication bus.

[0016] The communication interface is used to receive a first PTP protocol message sent by the master device and transmit the first PTP protocol message to the processor. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp.

[0017] The memory is used to store computer programs;

[0018] When the processor executes the program stored in the memory, it transmits the first sub-timestamp and the second sub-timestamp to the clock chip.

[0019] The clock chip is used to store the first sub-timestamp and the second sub-timestamp into the first time register in the clock chip;

[0020] The processor is also configured to, when executing a program stored in the memory, periodically retrieve from the first time register and transmit the first sub-timestamp to the switching chip via a software task;

[0021] The clock chip is also used to generate hardware tasks based on the software tasks, wherein the hardware tasks are to periodically obtain from the first time register and transmit the second sub-timestamp to the switching chip and the PHY chip;

[0022] The switching chip is used to store the first sub-timestamp into the second time register in the switching chip, and to store the second sub-timestamp into the second time register;

[0023] The PHY chip is used to store the second sub-timestamp into the third time register in the PHY chip.

[0024] Therefore, by applying the time synchronization method and apparatus provided in this application, the slave device receives a first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, which includes a first sub-timestamp and a second sub-timestamp. The slave device transmits the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp in a first time register in the clock chip. Through a software task, the slave device periodically retrieves the first sub-timestamp from the first time register and transmits it to the switching chip. The switching chip stores the first sub-timestamp in a second time register in the switching chip. This also causes the clock chip to generate a hardware task, which is used to make the clock chip periodically retrieve the second sub-timestamp from the first time register and transmit it to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in a second time register, and the PHY chip stores the second sub-timestamp in a third time register in the PHY chip.

[0025] Thus, time synchronization between the slave and master devices is achieved through PTP; simultaneously, time synchronization is also achieved among the clock chip, PHY chip, and other chips within the slave device. This solves the problems of phase differences among multiple chips within the slave device and inaccurate timestamps obtained by the slave device in existing time synchronization methods. Attached Figure Description

[0026] Figure 1 A flowchart illustrating the time synchronization method provided in the embodiments of this application;

[0027] Figure 2 The connection relationship and task transfer diagram between multiple chips within the device provided in this application embodiment;

[0028] Figure 3 A structural diagram of a time synchronization device provided in an embodiment of this application;

[0029] Figure 4 The network device hardware structure provided in the embodiments of this application. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0031] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the corresponding listed items.

[0032] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0033] The time synchronization method provided in the embodiments of this application will be described in detail below. See also Figure 1 , Figure 1 A flowchart illustrating a time synchronization method provided in an embodiment of this application. This method is applied to a slave device and may include the following steps.

[0034] Step 110: Receive the first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp.

[0035] Specifically, the slave device resides in a PTP domain, which also includes the master device. There is one and only one clock source within the PTP domain, and all devices within the domain synchronize with this clock. This clock source refers to the time configured within the master device. All other devices within the domain besides the master device are called slave devices, and slave devices must synchronize their time with the master device via PTP.

[0036] The master device obtains the first timestamp from its local PHY chip and sends it to the slave device along with the first PTP protocol message. After receiving the first PTP protocol message sent by the master device, the slave device obtains the first timestamp from it. The first timestamp includes a first sub-timestamp and a second sub-timestamp.

[0037] The first sub-timestamp refers to the time value included in the first timestamp, measured in units of year, month, day, hour, minute, and second. The second sub-timestamp refers to the time value included in the first timestamp, measured in units of milliseconds, microseconds, and nanoseconds. The first sub-timestamp is measured in seconds, and the second sub-timestamp is measured in nanoseconds.

[0038] Step 120: Transmit the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp in the first time register of the clock chip;

[0039] Specifically, according to the description of step 110, after obtaining the first timestamp from the device, the time values ​​of different units of measurement are converted into seconds or nanoseconds, and the first sub-timestamp and the second sub-timestamp are obtained.

[0040] The device transmits the first and second sub-timestamps to the clock chip, respectively. After receiving the first and second sub-timestamps, the clock chip stores them in the corresponding positions of the first time register.

[0041] It should be noted that the first time register can be divided into multiple regions, with different regions used to store different sub-timestamps.

[0042] Step 130: Through a software task, the first sub-timestamp is periodically obtained from the first time register and transmitted to the switching chip. The switching chip stores the first sub-timestamp in the second time register of the switching chip. This also causes the clock chip to generate a hardware task. The hardware task is used to make the clock chip periodically obtain from the first time register and transmit the second sub-timestamp to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in the second time register, and the PHY chip stores the second sub-timestamp in the third time register of the PHY chip.

[0043] Specifically, a periodic software task (i.e., a task generated by the processor within the device) is initiated from within the device. Through this task, the device periodically retrieves a first sub-timestamp from a first time register and transmits it to the switching chip. The switching chip then stores the first sub-timestamp in a second time register within the switching chip.

[0044] Simultaneously, this task can also trigger the clock chip to generate a hardware task (i.e., a task generated through logic circuitry between components). This hardware task is used to enable the clock chip to periodically retrieve the second sub-timestamp from the first time register and transmit the second sub-timestamp to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in the second time register, and the PHY chip stores the second sub-timestamp in the third time register within the PHY chip.

[0045] Thus, the PHY chip stores the first sub-timestamp, and the switching chip stores both the first and second sub-timestamps. It is understandable that the second actual register can also be divided into multiple regions, with different regions used to store different sub-timestamps.

[0046] Furthermore, the hardware task specifically involves the clock chip periodically sending a 1PPS signal, which includes a second sub-timestamp.

[0047] Furthermore, in this embodiment, when the second sub-timestamp stored in the first time register of the clock chip accumulates to a whole second, the clock chip generates a hardware task again, that is, generates and outputs a 1PPS signal to the switching chip and the PHY chip. After receiving the 1PPS signal, the switching chip and the PHY chip clear the second sub-timestamp stored in their local time registers.

[0048] In this embodiment, the clock chip also provides a reference clock for the PHY chip and the switching chip respectively; the PHY chip and the switching chip start up and begin working according to the reference clock.

[0049] like Figure 2 As shown, Figure 2 This application provides a diagram illustrating the connection relationships and task transfer between multiple chips within a device, as shown in the embodiments of this application. Figure 2 Each chip contains a time register. The S part represents the first sub-timestamp, and the NS part represents the second sub-timestamp. The S part is synchronized or acquired by the clock chip through software tasks or software read methods, while the NS part is synchronized or acquired by the clock chip through a 1PPS signal.

[0050] Therefore, by applying the time synchronization method provided in this application, the slave device receives a first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, which includes a first sub-timestamp and a second sub-timestamp. The slave device transmits the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp in a first time register in the clock chip. Through a software task, the slave device periodically retrieves the first sub-timestamp from the first time register and transmits it to the switching chip. The switching chip stores the first sub-timestamp in a second time register in the switching chip. This also causes the clock chip to generate a hardware task, which is used to make the clock chip periodically retrieve the second sub-timestamp from the first time register and transmit it to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in a second time register, and the PHY chip stores the second sub-timestamp in a third time register in the PHY chip.

[0051] Thus, time synchronization between the slave and master devices is achieved through PTP; simultaneously, time synchronization is also achieved among the clock chip, PHY chip, and other chips within the slave device. This solves the problems of phase differences among multiple chips within the slave device and inaccurate timestamps obtained by the slave device in existing time synchronization methods.

[0052] Optionally, in this embodiment of the application, the process of obtaining the device's local current timestamp and sending a second PTP protocol message to the master device is also included.

[0053] Specifically, after receiving the second PTP protocol message, the slave device obtains the master device's local first timestamp from it. According to existing PTP regulations, the slave device needs to obtain its own local current timestamp and send the second PTP protocol message to the master device.

[0054] The slave device retrieves the currently stored third sub-timestamp from the first time register and the currently stored fourth sub-timestamp from the third time register via software reading. The slave device then concatenates and combines the third and fourth sub-timestamps to obtain the second timestamp. The slave device generates and sends a second PTP protocol message to the master device, which includes the second timestamp.

[0055] The third sub-timestamp is measured in seconds, and the fourth sub-timestamp is measured in nanoseconds. The slave device can convert the third sub-timestamp into a time value measured in years, months, days, hours, minutes, and seconds; and convert the fourth sub-timestamp into a time value measured in milliseconds, microseconds, and nanoseconds. The slave device then concatenates and combines the converted time values ​​to obtain the second timestamp.

[0056] Optionally, in embodiments of this application, a process for configuring the clock protocol locally by the device is also included.

[0057] Specifically, the user inputs configuration commands via command line, which include the clock protocol. The slave device configures the clock protocol locally so that after receiving the timestamp synchronized by the master device, it stores the timestamp in the first time register, the second time register, and the third time register through the clock chip, the PHY chip, and the interaction chip.

[0058] Based on the same inventive concept, embodiments of this application also provide a time synchronization device corresponding to the time synchronization method. See also Figure 3 , Figure 3 The time synchronization device provided in this application embodiment is applied to a slave device located in a PTP domain. The PTP domain also includes a master device. The slave device includes a clock chip, a PHY chip, and a switching chip. The device includes:

[0059] The receiving unit 310 is configured to receive a first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp.

[0060] The transmission unit 320 is used to transmit the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp in the first time register in the clock chip;

[0061] The transmission unit 320 is further configured to periodically obtain and transmit the first sub-timestamp from the first time register to the switching chip via a software task. The switching chip stores the first sub-timestamp in a second time register in the switching chip. The clock chip also generates a hardware task to cause the clock chip to periodically obtain and transmit the second sub-timestamp from the first time register to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in the second time register, and the PHY chip stores the second sub-timestamp in a third time register in the PHY chip.

[0062] Optionally, the device further includes: an acquisition unit (not shown in the figure), configured to acquire the currently stored third sub-timestamp from the first time register and acquire the currently stored fourth sub-timestamp from the third time register by means of software reading;

[0063] A splicing unit (not shown in the figure) is used to splice and combine the third sub-timestamp and the fourth sub-timestamp to obtain the second timestamp;

[0064] A sending unit (not shown in the figure) is used to send a second PTP protocol message to the master device, the second PTP protocol message including the second timestamp.

[0065] Optionally, the receiving unit 310 is further configured to receive a configuration instruction input by a user, the configuration instruction including a clock protocol, the clock protocol being configured to enable the slave device to store the timestamp synchronized by the master device into the first time register, the second time register, and the third time register through the clock chip, the PHY chip, and the switching chip after receiving the timestamp.

[0066] Therefore, by applying the time synchronization device provided in this application, the slave device receives a first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, which includes a first sub-timestamp and a second sub-timestamp. The slave device transmits the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp in a first time register in the clock chip. Through a software task, the slave device periodically retrieves the first sub-timestamp from the first time register and transmits it to the switching chip. The switching chip stores the first sub-timestamp in a second time register in the switching chip. This also causes the clock chip to generate a hardware task, which is used to make the clock chip periodically retrieve the second sub-timestamp from the first time register and transmit it to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in a second time register, and the PHY chip stores the second sub-timestamp in a third time register in the PHY chip.

[0067] Thus, time synchronization between the slave and master devices is achieved through PTP; simultaneously, time synchronization is also achieved among the clock chip, PHY chip, and other chips within the slave device. This solves the problems of phase differences among multiple chips within the slave device and inaccurate timestamps obtained by the slave device in existing time synchronization methods.

[0068] Based on the same inventive concept, embodiments of this application also provide a network device, which is a slave device located in a PTP domain, and the PTP domain further includes a master device. Figure 4 As shown, the slave device includes a processor 410, a communication interface 420, a memory 430, a communication bus 440, a clock chip 450, a PHY chip 460, and a switching chip 470. The processor 410, the communication interface 420, the memory 430, the clock chip 450, the PHY chip 460, and the switching chip 470 communicate with each other via the communication bus 440.

[0069] The communication interface 420 is used to receive a first PTP protocol message sent by the master device and transmit the first PTP protocol message to the processor 410. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp.

[0070] The memory 430 is used to store computer programs;

[0071] When the processor 410 executes the program stored in the memory 430, it transmits the first sub-timestamp and the second sub-timestamp to the clock chip 450.

[0072] The clock chip 450 is used to store the first sub-timestamp and the second sub-timestamp into the first time register in the clock chip 450;

[0073] The processor 410 is also configured to, when executing the program stored in the memory 430, periodically retrieve from the first time register and transmit the first sub-timestamp to the switching chip 470 through a software task.

[0074] The clock chip 450 is also used to generate a hardware task based on the software task, wherein the hardware task is to periodically obtain the second sub-timestamp from the first time register and transmit it to the switching chip 470 and the PHY chip 460.

[0075] The switching chip 470 is used to store the first sub-timestamp into the second time register in the switching chip 470, and to store the second sub-timestamp into the second time register;

[0076] The PHY chip 460 is used to store the second sub-timestamp into the third time register in the PHY chip 460.

[0077] Optionally, the processor 410 is further configured to, when executing the program stored in the memory 430, obtain the currently stored third sub-timestamp from the first time register and obtain the currently stored fourth sub-timestamp from the third time register by means of software reading.

[0078] The third sub-timestamp and the fourth sub-timestamp are spliced ​​together to obtain the second timestamp, and the second timestamp is transmitted to the communication interface 420.

[0079] The communication interface 420 is further configured to send a second PTP protocol message to the master device, the second PTP protocol message including the second timestamp.

[0080] Optionally, the communication interface 420 is further configured to receive configuration instructions input by the user and transmit the configuration instructions to the processor 410, the configuration instructions including a clock protocol;

[0081] The processor 410 is further configured to, when executing the program stored in the memory 430, locally configure the clock protocol. The clock protocol is configured to enable the processor 410 to obtain the timestamp synchronized by the master device and then store the timestamp in the first time register, the second time register, and the third time register through the clock chip 450, the PHY chip 460, and the switching chip 470.

[0082] Optionally, the clock chip 450 is specifically used to periodically obtain the second sub-timestamp from the first time register, generate and send 1PPS signals to the switching chip 470 and the PHY chip 460 respectively, and each 1PPS signal includes the second sub-timestamp.

[0083] Optionally, the clock chip 450 is further configured to send 1PPS information to the PHY chip 460 and the switching chip 470 respectively when the first time register reaches a whole second.

[0084] The PHY chip 460 is used to clear the second sub-timestamp stored in the third time register;

[0085] The switching chip 470 is used to clear the second sub-timestamp stored in the second time register.

[0086] Optionally, the clock chip 450 is further configured to provide a reference clock for the PHY chip 460 and the switching chip 470 respectively;

[0087] The PHY chip 460 is also used to start according to the reference clock;

[0088] The switching chip 470 is also used to start according to the reference clock.

[0089] The foregoing Figure 3 The time synchronization device shown can be used as follows: Figure 4 The network device hardware structure shown is implemented. The aforementioned memory 430 may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, memory 430 may also be at least one storage device located remotely from the aforementioned processor 410.

[0090] The processor 410 mentioned above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0091] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0092] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0093] For the time synchronization device and machine-readable storage medium embodiments, since the methods involved are basically similar to those described in the foregoing method embodiments, the description is relatively simple, and relevant details can be found in the descriptions of the method embodiments.

[0094] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A time synchronization method, characterized in that, The method is applied to a slave device located in a PTP domain, which also includes a master device. The slave device includes a clock chip, a PHY chip, and a switching chip. The method includes: Receive a first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp. The first sub-timestamp and the second sub-timestamp are transmitted to the clock chip so that the clock chip stores the first sub-timestamp and the second sub-timestamp in the first time register in the clock chip; Through a software task, the first sub-timestamp is periodically retrieved from the first time register and transmitted to the switching chip. The switching chip stores the first sub-timestamp in its second time register. This also causes the clock chip to generate a hardware task, which enables the clock chip to periodically retrieve from the first time register and transmit the second sub-timestamp to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in its second time register, and the PHY chip stores the second sub-timestamp in its third time register.

2. The method according to claim 1, characterized in that, The method further includes: The third sub-timestamp currently stored is obtained from the first time register by software reading, and the fourth sub-timestamp currently stored is obtained from the third time register. The third sub-timestamp and the fourth sub-timestamp are spliced ​​together to obtain the second timestamp; Send a second PTP protocol message to the master device, the second PTP protocol message including the second timestamp.

3. The method according to claim 1, characterized in that, Before receiving the first PTP protocol message sent by the master device, the method further includes: The system receives configuration instructions input by the user. The configuration instructions include a clock protocol. The clock protocol is used to enable the slave device to receive a timestamp synchronized by the master device and then store the timestamp in the first time register, the second time register, and the third time register through the clock chip, the PHY chip, and the switching chip.

4. A time synchronization device, characterized in that, The device is applied to a slave device located in a PTP domain. The PTP domain also includes a master device. The slave device includes a clock chip, a PHY chip, and a switching chip. The device comprises: The receiving unit is configured to receive a first PTP protocol message sent by the master device. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp. A transmission unit is used to transmit the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp in the first time register of the clock chip; The transmission unit is further configured to periodically acquire and transmit the first sub-timestamp from the first time register to the switching chip via a software task. The switching chip stores the first sub-timestamp in a second time register within the switching chip. The clock chip also generates a hardware task to cause the clock chip to periodically acquire and transmit the second sub-timestamp from the first time register to the switching chip and the PHY chip. The switching chip stores the second sub-timestamp in the second time register, and the PHY chip stores the second sub-timestamp in a third time register within the PHY chip.

5. The apparatus according to claim 4, characterized in that, The device further includes: The acquisition unit is used to acquire the currently stored third sub-timestamp from the first time register and the currently stored fourth sub-timestamp from the third time register by means of software reading. The splicing unit is used to splice and combine the third sub-timestamp and the fourth sub-timestamp to obtain the second timestamp. The sending unit is configured to send a second PTP protocol message to the master device, the second PTP protocol message including the second timestamp.

6. The apparatus according to claim 4, characterized in that, The receiving unit is further configured to receive configuration instructions input by the user. The configuration instructions include a clock protocol. The clock protocol is configured to enable the slave device to receive a timestamp synchronized by the master device and then store the timestamp in the first time register, the second time register, and the third time register through the clock chip, the PHY chip, and the switching chip.

7. A network device, characterized in that, The network device is a slave device in a PTP domain, which also includes a master device. The slave device includes a processor, a communication interface, a memory, a communication bus, a clock chip, a PHY chip, and a switching chip. The processor, the communication interface, the memory, the clock chip, the PHY chip, and the switching chip communicate with each other through the communication bus. The communication interface is used to receive a first PTP protocol message sent by the master device and transmit the first PTP protocol message to the processor. The first PTP protocol message includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp. The memory is used to store computer programs; When the processor executes the program stored in the memory, it transmits the first sub-timestamp and the second sub-timestamp to the clock chip. The clock chip is used to store the first sub-timestamp and the second sub-timestamp into the first time register in the clock chip; The processor is also configured to, when executing a program stored in the memory, periodically retrieve from the first time register and transmit the first sub-timestamp to the switching chip via a software task; The clock chip is also used to generate hardware tasks based on the software tasks, wherein the hardware tasks are to periodically obtain from the first time register and transmit the second sub-timestamp to the switching chip and the PHY chip; The switching chip is used to store the first sub-timestamp into the second time register in the switching chip, and to store the second sub-timestamp into the second time register; The PHY chip is used to store the second sub-timestamp into the third time register in the PHY chip.

8. The network device according to claim 7, characterized in that, The processor is further configured to, when executing a program stored in the memory, obtain the currently stored third sub-timestamp from the first time register and obtain the currently stored fourth sub-timestamp from the third time register by means of software reading. The third sub-timestamp and the fourth sub-timestamp are concatenated and combined to obtain the second timestamp, and the second timestamp is transmitted to the communication interface. The communication interface is also used to send a second PTP protocol message to the master device, the second PTP protocol message including the second timestamp.

9. The network device according to claim 7, characterized in that, The communication interface is also used to receive configuration instructions input by the user and transmit the configuration instructions to the processor, the configuration instructions including a clock protocol; The processor is further configured to, when executing a program stored in the memory, locally configure the clock protocol, wherein the clock protocol enables the processor to obtain a timestamp synchronized by the master device and then store the timestamp in the first time register, the second time register, and the third time register through the clock chip, the PHY chip, and the switching chip.

10. The network device according to claim 7, characterized in that, The clock chip is specifically used to periodically obtain the second sub-timestamp from the first time register, generate and send 1PPS signals to the switching chip and the PHY chip respectively, and each 1PPS signal includes the second sub-timestamp.

11. The network device according to claim 7, characterized in that, The clock chip is also used to send 1PPS information to the PHY chip and the switching chip respectively when the first time register reaches a whole second. The PHY chip is used to clear the second sub-timestamp stored in the third time register; The switching chip is used to clear the second sub-timestamp stored in the second time register.

12. The network device according to claim 7, characterized in that, The clock chip is also used to provide a reference clock for the PHY chip and the switching chip respectively; The PHY chip is also used to start according to the reference clock; The switching chip is also used to start according to the reference clock.

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