Memory elements and their manufacturing methods

Abstract

This invention provides a memory element and a method for forming the memory element. The memory element includes a semiconductor substrate, an isolation structure, and an antifuse structure. The isolation structure is located in the semiconductor substrate. The antifuse structure is located in the isolation structure and includes a first electrode and a second electrode. The second electrode is adjacent to the first electrode, wherein the top surface of both the first electrode and the top surface of the second electrode are below the top surface of the semiconductor substrate. This reduces the size of the memory element and simplifies its manufacturing process.

Description

Technical Field

[0001] This invention relates to a memory element and a method for forming a memory element. Background Technology

[0002] Semiconductor memory devices can be divided into two categories: volatile memory devices and non-volatile memory devices. Compared to volatile memory devices, information in non-volatile memory devices is retained even when power is off. For non-volatile memory devices, some designs allow for multiple programming, while others allow for one-time programming. Typically, the manufacturing techniques used to form non-volatile memory devices differ from standard logic processes, which significantly increases complexity and chip size. Summary of the Invention

[0003] The technical form of the present invention is a memory element.

[0004] According to some embodiments of the present invention, a memory element includes a semiconductor substrate, an isolation structure, and an antifuse structure. The isolation structure is located in the semiconductor substrate. The antifuse structure is located in the isolation structure and includes a first electrode and a second electrode. The second electrode is adjacent to the first electrode, wherein the top surface of both the first electrode and the top surface of the second electrode are below the top surface of the semiconductor substrate.

[0005] In some embodiments of the present invention, the memory element further includes a first contact and a second contact. The first contact is located on a first electrode. The second contact is located on a second electrode.

[0006] In some embodiments of the present invention, the bottom surfaces of both the first contact and the second contact are below the top surface of the semiconductor substrate.

[0007] In some embodiments of the present invention, the memory element further includes a dielectric layer located on the semiconductor substrate and the isolation structure.

[0008] In some embodiments of the present invention, the first contact includes a bottom portion located in the isolation structure and a top portion located in the dielectric layer.

[0009] In some embodiments of the invention, a first contact is configured to apply a first voltage to a first electrode, and a second contact is configured to apply a second voltage, different from the first voltage, to a second electrode, to convert a portion of the isolation structure between the first and second electrodes into a permanent conductive path.

[0010] In some embodiments of the present invention, the top surface of the first electrode and the top surface of the second electrode are both below the top surface of the isolation structure.

[0011] In some embodiments of the present invention, the top surface of the first electrode and the top surface of the second electrode are substantially coplanar.

[0012] In some embodiments of the present invention, the bottom surface of the first electrode and the bottom surface of the second electrode are substantially coplanar.

[0013] In some embodiments of the present invention, in a top view, the first electrode extends along a first direction, and the first electrode and the second electrode are arranged parallel to each other along a second direction perpendicular to the first direction.

[0014] In some embodiments of the present invention, the first electrode has a strip-shaped profile in a top view.

[0015] In some embodiments of the present invention, the first electrode and the second electrode comprise the same material.

[0016] Another technical aspect of the present invention is a method for forming memory elements.

[0017] According to some embodiments of the present invention, a method of forming a memory element includes forming an isolation structure in a semiconductor substrate. The isolation structure is etched to form a first opening and a second opening. A first electrode and a second electrode, respectively, of antifuse structures are formed in the first and second openings, such that the top surfaces of the first electrode and the second electrode are both below the top surface of the isolation structure. A dielectric layer is formed on the isolation structure. A first voltage is applied to the first electrode and a second voltage, different from the first voltage, is applied to the second electrode to convert a portion of the isolation structure between the first and second electrodes into a permanent conductive path.

[0018] In some embodiments of the present invention, the method of forming a memory element further includes forming a first contact and a second contact in a dielectric layer, such that a first voltage is applied to a first electrode through the first contact and a second voltage is applied to a second electrode through the second contact.

[0019] In some embodiments of the present invention, a first contact and a second contact are formed such that a portion of the first contact and a portion of the second contact are formed within an isolation structure.

[0020] In some embodiments of the present invention, a first contact and a second contact are formed such that the top surface of the first electrode and the top surface of the second electrode respectively contact the first contact and the second contact.

[0021] In some embodiments of the present invention, the first electrode and the second electrode are formed such that the top surface of the first electrode and the top surface of the second electrode are both below the top surface of the semiconductor substrate.

[0022] In some embodiments of the present invention, a first electrode and a second electrode are formed such that the first electrode and the second electrode have a contact isolation structure.

[0023] In some embodiments of the present invention, a first electrode and a second electrode are formed such that the bottom surface of the first electrode and the bottom surface of the second electrode are substantially coplanar.

[0024] In some embodiments of the present invention, forming an isolation structure in a semiconductor substrate includes forming a trench in the semiconductor substrate and filling the trench with antifuse dielectric material to form an isolation structure.

[0025] In the above embodiments, since the top surfaces of both the first electrode and the second electrode are below the top surface of the semiconductor substrate, the size of the memory element can be reduced. Furthermore, the manufacturing process of the memory element can be simplified. Attached Figure Description

[0026] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:

[0027] Figure 1 This is a top view of the layout of memory elements according to some embodiments of the present invention.

[0028] Figure 2 For along Figure 1 A cross-sectional view of the memory element in line 2-2.

[0029] Figures 3 to 6 This is a cross-sectional view of a method for forming memory elements at different stages according to some embodiments of the present invention. Detailed Implementation

[0030] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential and therefore should not be used to limit the invention. Furthermore, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simplified schematic manner. In addition, for the reader's convenience, the dimensions of the elements in the drawings are not drawn to scale.

[0031] As used in this invention, "about," "approximately," or "substantially" generally refers to within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent. The values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the meaning of the terms "about," "approximately," or "substantially" can be inferred.

[0032] Furthermore, for ease of description, spatially relative terms such as "below," "under," "below," "above," "above," and the like may be used in some embodiments of the invention to describe the relationship between one element or feature as depicted in the figures and other elements or features(s). These spatially relative terms are intended to cover different orientations of elements in use or operation, in addition to those described in the figures. Elements may be additionally positioned (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used in some embodiments of the invention are interpreted accordingly.

[0033] Figure 1 This is a top view of the layout of a memory element 10 according to some embodiments of the present invention. Figure 2 For along Figure 1 A cross-sectional view of memory element 10 along line 2-2. See also... Figure 1 and Figure 2 The memory element 10 includes a semiconductor substrate 110, an isolation structure 120, and an antifuse structure AF. The isolation structure 120 is disposed within the semiconductor substrate 110. The antifuse structure AF is disposed within the isolation structure 120. The antifuse structure AF includes a first electrode 130 and a second electrode 140. The second electrode 140 of the antifuse structure AF is positioned adjacent to but separated from the first electrode 130 of the antifuse structure AF. The top surface 131 of both the first electrode 130 and the second electrode 140 of the antifuse structure AF is below the top surface 111 of the semiconductor substrate 110. Because the entire antifuse structure AF is disposed within the isolation structure 120 (or the semiconductor substrate 110), the size of the memory element 10 can be reduced. Furthermore, the manufacturing process of the memory element 10 can be simplified.

[0034] The memory element 10 further includes a first contact 150 and a second contact 160, with the second contact 160 adjacent to the first contact 150. The first contact 150 is disposed on the first electrode 130 of the antifuse structure AF, and the second contact 160 is disposed on the second electrode 140 of the antifuse structure AF. Specifically, the first contact 150 contacts and is electrically connected to the first electrode 130, and the second contact 160 contacts and is electrically connected to the second electrode 140.

[0035] The programming mechanism for storing digital information using an antifuse structure AF involves applying a first voltage V1 to the first electrode 130 via the first contact 150 and a second voltage V2 to the second electrode 140 via the second contact 160. This converts a portion 122 of the isolation structure 120 between the first electrode 130 and the second electrode 140 into a permanent conductive path 122a, thereby conducting electricity between the first electrode 130 and the second electrode 140 of the antifuse structure AF, thus putting the antifuse structure AF in an "on" state. Conversely, an unprogrammed antifuse structure AF is in a "off" state. Notably, the voltage difference (also known as the bias voltage) between the first voltage V1 and the second voltage V2 can exceed a specific level (e.g., exceeding a predetermined bias voltage) to program the antifuse structure AF. In some embodiments, the first voltage V1 connected to the first electrode 130 via the first contact 150 is greater than the second voltage V2 connected to the second electrode 140 via the second contact 160. For example, the first voltage V1 is a high voltage, and the second voltage V2 is a low voltage or zero (ground) voltage. It is worth noting that the antifuse structure AF also includes a portion 122 of the isolation structure 120 between the first electrode 130 and the second electrode 140, and the portion 122 of the isolation structure 120 is considered as the antifuse dielectric material of the antifuse structure AF. Programming the antifuse structure AF involves applying a bias voltage to the first electrode 130 and the second electrode 140 to break down the portion 122 of the isolation structure 120 (i.e., the antifuse dielectric material) and form a permanent conductive path 122a between the first electrode 130 and the second electrode 140. In other words, when the antifuse structure AF is programmed, the portion 122 of the isolation structure 120 changes from non-conductive (i.e., dielectric material) to conductive (i.e., conductor).

[0036] In some embodiments, the top surface 131 of the first electrode 130 of the antifuse structure AF and the top surface 141 of the second electrode 140 of the antifuse structure AF are both below the top surface 121 of the isolation structure 120. In other words, the entire antifuse structure AF (including the first electrode 130, the second electrode 140, and the portion 122 of the isolation structure 120 between the first electrode 130 and the second electrode 140) is located within the isolation structure 120 (or the semiconductor substrate 110).

[0037] In some embodiments, the height H1 of the first electrode 130 of the antifuse structure AF is substantially the same as the height H2 of the second electrode 140 of the antifuse structure AF. Specifically, the top surface 131 of the first electrode 130 of the antifuse structure AF and the top surface 141 of the second electrode 140 of the antifuse structure AF are substantially coplanar, and the bottom surface 133 of the first electrode 130 of the antifuse structure AF and the bottom surface 143 of the second electrode 140 of the antifuse structure AF are substantially coplanar. In some embodiments, the height H1 of the first electrode 130 of the antifuse structure AF is in the range of about 130 nanometers (nm) to about 150 nanometers (e.g., 140 nm), and the height H2 of the second electrode 140 of the antifuse structure AF is in the range of about 130 nm to about 150 nm (e.g., 140 nm). This allows the first electrode 130 and the second electrode 140 of the antifuse structure AF to have better uniformity.

[0038] In some embodiments, the thickness T1 of the first electrode 130 of the antifuse structure AF is substantially the same as the thickness T2 of the second electrode 140 of the antifuse structure AF. The thickness T1 of the first electrode 130 of the antifuse structure AF is in the range of about 70 nanometers to about 90 nanometers (e.g., 80 nanometers), and the thickness T2 of the second electrode 140 of the antifuse structure AF is in the range of about 70 nanometers to about 90 nanometers (e.g., 80 nanometers). In this way, a permanent conductive path 122a between the first electrode 130 and the second electrode 140 of the antifuse structure AF can be readily formed during programming.

[0039] In some embodiments, the distance dl between the first electrode 130 and the second electrode 140 of the antifuse structure AF (i.e., the length of the portion 122 of the isolation structure 120 from the first electrode 130 to the second electrode 140) is in the range of about 20 nanometers to about 35 nanometers (e.g., 27 nanometers). In this way, a permanent conductive path 122a can be formed between the first electrode 130 and the second electrode 140. Furthermore, the size of the antifuse structure AF can be reduced. If the distance d1 between the first electrode 130 and the second electrode 140 is less than about 20 nanometers, interference will occur, which will adversely affect the performance of the memory element 10; if the distance d1 between the first electrode 130 and the second electrode 140 is greater than about 35 nanometers, the size of the antifuse structure AF (or the memory element 10) will be too large. In some embodiments, the area of ​​the antifuse structure AF is about 240 to 250 nanometers (e.g., 248 nanometers) multiplied by about 240 to 250 nanometers (e.g., 248 nanometers). By configuring the antifuse structure AF as described above, the area (or size) of the antifuse structure AF can be reduced. For example, the area (or size) of the antifuse structure AF can be reduced by approximately 12%.

[0040] In some embodiments, the first electrode 130 of the antifuse structure AF and the second electrode 140 of the antifuse structure AF have the same profile, such as a tapered profile. For example, the first electrode 130 of the antifuse structure AF includes a first bottom and a first top that is wider than the first bottom, and the second electrode 140 of the antifuse structure AF includes a second bottom and a second top that is wider than the second bottom.

[0041] The memory element 10 further includes a dielectric layer 170 located on the semiconductor substrate 110 and the isolation structure 120. The dielectric layer 170 surrounds the first contact 150 and the second contact 160, and the isolation structure 120 surrounds the first electrode 130 and the second electrode 140 of the antifuse structure AF. In some embodiments, the first contact 150 includes a bottom portion 152 in the isolation structure 120 and a top portion 154 in the dielectric layer 170. The second contact 160 includes a bottom portion 162 in the isolation structure 120 and a top portion 164 in the dielectric layer 170. In some embodiments, the bottom surface 153 of the first contact 150 and the bottom surface 163 of the second contact 160 are both below the top surface 111 of the semiconductor substrate 110. The bottom surface 153 of the first contact 150 is separated from the dielectric layer 170, and the bottom surface 163 of the second contact 160 is also separated from the dielectric layer 170.

[0042] In some embodiments, the bottom portion 152 of the first contact 150 has a different profile than the top portion 154 of the first contact 150. For example, the bottom portion 152 of the first contact 150 has a tapered profile, while the top portion 154 of the first contact 150 has a rectangular profile. The minimum width of the bottom portion 152 of the first contact 150 is smaller than the minimum width of the top portion 154 of the first contact 150. Similarly, the bottom portion 162 of the second contact 160 has a different profile than the top portion 164 of the second contact 160. For example, the bottom portion 162 of the second contact 160 has a tapered profile, while the top portion 164 of the second contact 160 has a rectangular profile. The minimum width of the bottom portion 162 of the second contact 160 is smaller than the minimum width of the top portion 164 of the second contact 160.

[0043] In some implementations, such as Figure 1As shown in the top view, the first electrode 130 of the antifuse structure AF extends along a first direction D1, and the second electrode 140 of the antifuse structure AF also extends along the first direction D1. The first electrode 130 and the second electrode 140 of the antifuse structure AF are arranged parallel to each other along a second direction D2 perpendicular to the first direction D1. In some embodiments, the first electrode 130 and the second electrode 140 of the antifuse structure AF have the same outline in the top view. For example, the first electrode 130 and the second electrode 140 of the antifuse structure AF have a strip-shaped outline (or a straight-line outline).

[0044] In some implementations, such as Figure 1 As shown, the first contact 150 is disposed above the end of the first electrode 130, and the second contact 160 is disposed above the end of the second electrode 140, wherein the ends of the first electrode 130 and the second electrode 140 are not aligned. Therefore, the first contact 150 and the second contact 160 are not aligned with each other. If the first contact 150 and the second contact 160 were aligned (for example, the first contact 150 and the second contact 160 are arranged along the second direction D2), the first contact 150 would be too close to the second contact 160, thereby causing interference.

[0045] In some embodiments, the first electrode 130 and the second electrode 140 of the antifuse structure AF contain the same material. For example, the first electrode 130 and the second electrode 140 of the antifuse structure AF contain a metal (e.g., titanium), a metal nitride (e.g., titanium nitride), or other suitable conductive material. The first contact 150 and the second contact 160 may contain the same material, such as tungsten, or other suitable metallic material.

[0046] Figures 3 to 6 This is a cross-sectional view of a method for forming memory elements at different stages according to some embodiments of the present invention.

[0047] See Figure 3 A semiconductor substrate 110 is provided. In some embodiments, the semiconductor substrate 110 comprises silicon. In some other embodiments, the semiconductor substrate 110 comprises other elemental semiconductors, such as germanium; compound semiconductors comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0048] An isolation structure 120 is formed in a semiconductor substrate 110. In some embodiments, the isolation structure 120 is a shallow isolation trench (STI). The formation of the isolation structure 120 may involve etching the semiconductor substrate 110 to form a trench 124 in the semiconductor substrate 110, and then filling the trench 124 with an antifuse dielectric material. The antifuse dielectric material may comprise an insulating material, such as silicon dioxide. In some embodiments, the isolation structure 120 is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or similar methods.

[0049] See Figure 4 After the isolation structure 120 is formed, an etching process is performed to form a first opening O1 and a second opening O2 in the isolation structure 120, thereby partially removing the isolation structure 120. The openings O1 and O2 expose the underlying isolation structure 120.

[0050] See Figure 4 and Figure 5 The first electrode 130 and the second electrode 140 of the antifuse structure AF are respectively formed in the first opening O1 and the second opening O2, such that the top surface 131 of the first electrode 130 and the top surface 141 of the second electrode 140 of the antifuse structure AF are below the top surface 121 of the isolation structure 120. Furthermore, the top surface 131 of the first electrode 130 and the top surface 141 of the second electrode 140 of the antifuse structure AF are both below the top surface 111 of the semiconductor substrate 110.

[0051] In some embodiments, the first electrode 130 and the second electrode 140 forming the antifuse structure AF include a first opening O1 and a second opening O2 filled with conductive material to form a first electrode layer and a second electrode layer in the isolation structure 120, respectively. Then, the first electrode layer and the second electrode layer are etched back to form the first electrode 130 and the second electrode 140, respectively.

[0052] In some embodiments, each of the first electrode 130 and the second electrode 140 is a single layer and comprises, for example, titanium (Ti) or titanium nitride (TiN). In some embodiments, both the first electrode 130 and the second electrode 140 are multilayer structures and comprise, for example, a titanium nitride layer and a tungsten layer above the titanium nitride layer. The first electrode 130 and the second electrode 140 can be formed, exemplarily, using CVD processes, PVD processes, atomic layer deposition (ALD) processes, similar fabrication methods, and / or combinations thereof.

[0053] In some embodiments, the first electrode 130 and the second electrode 140 forming the antifuse structure AF are positioned such that a portion 122 of the isolation structure 120 is located directly between the first electrode 130 and the second electrode 140, and the portion 122 of the isolation structure is considered as the antifuse dielectric material of the antifuse structure AF. In some embodiments, the first electrode 130 and the second electrode 140 of the antifuse structure AF are surrounded by the isolation structure 120 and are in contact with the isolation structure 120.

[0054] After the first electrode 130 and the second electrode 140 of the antifuse structure AF are formed, a dielectric layer 170 is formed on the isolation structure 120 and the semiconductor substrate 110. The dielectric layer 170 may include a first portion 172 and a second portion 174 located within the isolation structure 120, wherein the first portion 172 contacts the first electrode 130 and the second portion 174 contacts the second electrode 140. The dielectric layer 170 has a lowest bottom surface below the top surface 121 of the isolation structure 120 (or the top surface 111 of the semiconductor substrate 110). The dielectric layer 170 can be formed by CVD, high-density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the dielectric layer 170 is formed of a different dielectric material than the isolation structure 120. For example, the dielectric layer 170 contains a nitride (e.g., silicon nitride), while the isolation structure 120 contains an oxide (e.g., silicon dioxide).

[0055] See Figure 5 and Figure 6 After the dielectric layer 170 is formed, an etching process is performed to form a third opening O3 and a fourth opening O4 in the dielectric layer 170, thereby partially removing the dielectric layer 170. The etching process removes the first portion 172 and the second portion 174 of the dielectric layer 170, thereby exposing the first electrode 130 and the second electrode 140 of the antifuse structure AF.

[0056] Back Figure 2 In the formation of the third opening O3 and the fourth opening O4 (see...) Figure 6 After that, the first contact 150 and the second contact 160 are formed at the third opening O3 and the fourth opening O4, respectively (see...). Figure 6 In the process, a first voltage V1 is applied to the first electrode 130 of the antifuse structure AF through the first contact 150, and a second voltage V2, different from the first voltage V1, is applied to the second electrode 140 of the antifuse structure AF through the second contact 160, so as to convert a portion 122 of the isolation structure 120 between the first electrode 130 and the second electrode 140 of the antifuse structure AF into a permanent conductive path 122a. Therefore, as shown in the figure, a permanent conductive path 122a can be obtained. Figure 2 The memory element 10 shown.

[0057] While the present invention has been disclosed in detail above, other embodiments are possible and are not intended to limit the invention. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments of the present invention.

[0058] Those skilled in the art can make various changes or substitutions without departing from the spirit and scope of the present invention, and all such changes or substitutions should be covered within the protection scope of the appended claims.

[0059] [Symbol Explanation]

[0060] 10: Memory elements

[0061] 110: Semiconductor substrate

[0062] 111: Top surface

[0063] 120: Isolation Structure

[0064] 121: Top surface

[0065] 122: Part

[0066] 122a: Permanent conductive path

[0067] 124: Trench

[0068] 130: First electrode

[0069] 131: Top surface

[0070] 133: Bottom surface

[0071] 140: Second electrode

[0072] 141: Top surface

[0073] 143: Bottom surface

[0074] 150: First Contact

[0075] 152: Bottom part

[0076] 153: Bottom

[0077] 154: Top section

[0078] 160: Second Contact

[0079] 162: Bottom part

[0080] 163: Bottom

[0081] 164: Top section

[0082] 170: Dielectric layer

[0083] 172: Part One

[0084] 174: Part Two

[0085] AF: Anti-fuse structure

[0086] d1: Distance

[0087] D1: First Direction

[0088] D2: Second Direction

[0089] H1: Height

[0090] H2: Height

[0091] O1: Opening

[0092] O2: Opening

[0093] O3: Opening

[0094] O4: Opening

[0095] T1: Thickness

[0096] T2: Thickness

[0097] V1: First voltage

[0098] V2: Second voltage

[0099] 2-2: Line.

Claims

1. A memory element, characterized in that, Include: Semiconductor substrate; An isolation structure is located within the semiconductor substrate; and An antifuse structure, located within the isolation structure, comprises: First electrode; as well as The second electrode is adjacent to the first electrode and separate from it, wherein the top surface of both the first electrode and the top surface of the second electrode are below the top surface of the semiconductor substrate.

2. The memory element according to claim 1, wherein, Also includes: The first contact is located on the first electrode; and The second contact is located on the second electrode.

3. The memory element according to claim 2, wherein the bottom surface of the first contact and the bottom surface of the second contact are both below the top surface of the semiconductor substrate.

4. The memory element according to claim 2, wherein, Also includes: A dielectric layer is located on the semiconductor substrate and the isolation structure.

5. The memory element of claim 4, wherein the first contact comprises a bottom portion in the isolation structure and a top portion in the dielectric layer.

6. The memory element of claim 2, wherein the first contact is configured to apply a first voltage to the first electrode, and the second contact is configured to apply a second voltage different from the first voltage to the second electrode to convert a portion of the isolation structure between the first electrode and the second electrode into a permanent conductive path.

7. The memory element of claim 1, wherein the top surface of the first electrode and the top surface of the second electrode are both below the top surface of the isolation structure.

8. The memory element of claim 1, wherein the top surface of the first electrode and the top surface of the second electrode are substantially coplanar.

9. The memory element of claim 1, wherein a bottom surface of the first electrode and a bottom surface of the second electrode are substantially coplanar.

10. The memory element of claim 1, wherein, in a top view, the first electrode extends along a first direction, and the first electrode and the second electrode are arranged parallel to each other along a second direction perpendicular to the first direction.

11. The memory element of claim 1, wherein, in a top view, the first electrode has a strip-shaped profile.

12. The memory element of claim 1, wherein the first electrode and the second electrode comprise the same material.

13. A method for forming a memory element, characterized in that, Include: An isolation structure is formed in the semiconductor substrate; The isolation structure is etched to form the first opening and the second opening; A first electrode and a second electrode, respectively forming an anti-fuse structure, are respectively placed in the first opening and the second opening, such that the top surface of the first electrode and the top surface of the second electrode are both below the top surface of the isolation structure; A dielectric layer is formed on the isolation structure; as well as A first voltage is applied to the first electrode and a second voltage, different from the first voltage, is applied to the second electrode to convert a portion of the isolation structure between the first electrode and the second electrode into a permanent conductive path.

14. The method according to claim 13, wherein, Also includes: A first contact and a second contact are formed in the dielectric layer such that a first voltage is applied to the first electrode through the first contact, and a second voltage is applied to the second electrode through the second contact.

15. The method of claim 14, wherein the first contact and the second contact are formed such that a portion of the first contact and a portion of the second contact are formed within the isolation structure.

16. The method of claim 14, wherein the first contact and the second contact are formed such that the top surface of the first electrode and the top surface of the second electrode respectively contact the first contact and the second contact.

17. The method of claim 13, wherein forming the first electrode and the second electrode further comprises such that the top surface of the first electrode and the top surface of the second electrode are both below the top surface of the semiconductor substrate.

18. The method of claim 13, wherein the first electrode and the second electrode are formed such that the first electrode and the second electrode contact the isolation structure.

19. The method of claim 13, wherein the first electrode and the second electrode are formed such that the bottom surface of the first electrode and the bottom surface of the second electrode are substantially coplanar.

20. The method of claim 13, wherein forming the isolation structure on the semiconductor substrate comprises: Trenches are formed in the semiconductor substrate; and The antifuse dielectric material is filled into the trench to form an isolation structure.

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