Load balancing architecture for ganged voltage regulators

Abstract

Certain aspects of the present disclosure provide a power supply system. The power supply system generally includes a first voltage regulator and a second voltage regulator, outputs of the first voltage regulator and the second voltage regulator being coupled to an output of the power supply system. The power supply system can also include a current balancer circuit configured to adjust an output current of the first voltage regulator based on a determined margin of the first voltage regulator and a margin of the second voltage regulator.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 350,535, filed June 17, 2021, which has been assigned to the assignee of this patent application and whose entire contents are incorporated herein by reference. Technical Field

[0003] Certain aspects of this disclosure relate generally to electronic circuits, and more specifically to power supply circuits and regulation. Background Technology

[0004] Ideally, a voltage regulator should provide a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators can be categorized as linear regulators or switching regulators. While linear regulators are small and compact, many applications can benefit from the increased efficiency of switching regulators. For example, a linear regulator can be implemented using a low dropout (LDO) regulator. Switching regulators can be implemented using switch-mode power supplies (SMPS), such as buck converters, boost converters, or buck-boost converters.

[0005] Power management integrated circuits (PMICs) are used to manage the power requirements of a host system and may include and / or control one or more voltage regulators (e.g., boost converters). PMICs can be used in battery-powered devices, such as mobile phones, tablets, laptops, wearable devices, etc., to control the flow and direction of power within the device. PMICs can perform various functions for the device, such as DC-DC conversion (e.g., using voltage regulators as described above), battery charging, power selection, voltage scaling, power sequencing, etc. For example, a PMIC may have the functionality of a boost converter to increase the voltage level of the DC input voltage. Summary of the Invention

[0006] Some aspects of this disclosure relate to a power supply system. The power supply system typically includes a first voltage regulator; a second voltage regulator, the outputs of which are coupled to an output of the power supply system; and a current balancer circuit configured to adjust the output current of the first voltage regulator based on determined margins of the first and second voltage regulators.

[0007] Some aspects of this disclosure relate to a method of power supply. The method typically includes generating a first output current via a first voltage regulator; generating a second output current via a second voltage regulator, the first and second output currents being provided to a common output node; and adjusting the first output current via a current balancer circuit based on determined margins of the first and second voltage regulators.

[0008] Some aspects of this disclosure relate to an apparatus for supplying power. The apparatus typically includes components for generating a first output current; components for generating a second output current, the first and second output currents being provided to a common output node; and components for adjusting the first output current based on a determined margin associated with the components for generating the first and second output currents.

[0009] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate certain exemplary features of these one or more aspects in detail. However, these features indicate only a few of the various ways in which the principles of these aspects can be employed. Attached Figure Description

[0010] To gain a more detailed understanding of the foregoing features of this disclosure, a more specific description, some of which is illustrated in the accompanying drawings, may be obtained by referring to the aspects in which the brief summary is presented. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and are therefore not intended to limit its scope, as the specification may acknowledge other equally valid aspects.

[0011] Figure 1 This is a block diagram of an exemplary device including a voltage regulator according to certain aspects of this disclosure.

[0012] Figure 2 A power supply system using a linked low-dropout (LDO) regulator is shown according to certain aspects of this disclosure.

[0013] Figure 3 This is a diagram of various operating regions of an LDO regulator according to certain aspects of this disclosure.

[0014] Figure 4 This is a table illustrating exemplary techniques for headroom (HR) adjustment and current balancing according to certain aspects of this disclosure.

[0015] Figure 5 This is a flowchart illustrating exemplary operation for voltage regulation according to certain aspects of this disclosure.

[0016] To facilitate understanding, the same reference numerals have been used wherever possible to designate the same elements that are common to the accompanying drawings. It is conceivable that elements disclosed in one aspect may be usefully applied to other aspects without specific description. Detailed Implementation

[0017] Certain aspects of this disclosure relate to apparatus and techniques for the linkage of voltage regulators, such as low-dropout (LDO) regulators. For example, multiple LDO regulators can be used to supply current to a common load. Some aspects of this disclosure use determined LDO regulator margins to perform current balancing and margin adjustment of the LDO regulators. For example, if the margin of any one of the LDO regulators is too low, the margin of (all) LDO regulators can be increased. If the margin of all LDO regulators is too high, the margin of these LDO regulators can be decreased. If the margin of any one of the LDO regulators is too high, while the margin of one or more other LDO regulators is acceptable, current balancing can be used to balance the output current of the LDO regulators, as described in more detail herein.

[0018] The various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of protection of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the disclosure herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or method of practice. Furthermore, the scope of this disclosure is intended to cover such apparatus or methods implemented using structures, functions, or structures and functions other than or different from the aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more components of these claims.

[0019] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” herein is not necessarily to be construed as preferred or superior to other aspects.

[0020] The techniques described herein can be used in combination with various wireless technologies such as Code Division Multiple Access (CDMA), Orthogonal Frequency Division Multiplexing (OFDM), Time Division Multiple Access (TDMA), Space Division Multiple Access (SDMA), Single Carrier Frequency Division Multiple Access (SC-FDMA), and Time Division Synchronous Code Division Multiple Access (TD-SCDMA). Multiple user terminals can concurrently transmit / receive data via: (1) an orthogonal code channel for CDMA, (2) a time slot for TDMA, or (3) a subband for OFDM. CDMA systems can implement IS-2000, IS-95, IS-856, Wideband CDMA (W-CDMA), or some other standard. OFDM systems can implement IEEE 802.11, IEEE 802.16, Long Term Evolution (LTE) (e.g., in TDD and / or FDD modes), or some other standard. TDMA systems can implement Global System for Mobile Communications (GSM), or some other standard. These various standards are known in the art.

[0021] Exemplary device

[0022] Figure 1 Device 100 is shown. Device 100 can be a battery-powered device, such as a cellular phone, personal digital assistant (PDA), handheld device, wireless modem, laptop computer, tablet computer, personal computer, etc. Device 100 is an example of a device that can be configured to implement the various systems and methods described herein.

[0023] Device 100 may include processor 104, which controls the operation of device 100. Processor 104 may also be referred to as a central processing unit (CPU). Memory 106, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to processor 104. A portion of memory 106 may also include non-volatile random access memory (NVRAM). Processor 104 typically performs logical and arithmetic operations based on program instructions stored in memory 106. Instructions in memory 106 can be executed to implement the methods described herein.

[0024] Device 100 may also include a housing 108, which may include a transmitter 110 and a receiver 112 to allow data transmission and reception between device 100 and a remote location. The transmitter 110 and receiver 112 may be combined into a transceiver 114. Multiple antennas 116 may be attached to housing 108 and electrically coupled to transceiver 114. Device 100 may also include (not shown) multiple transmitters, multiple receivers, and multiple transceivers.

[0025] Device 100 may also include a signal detector 118, which can be used to detect and quantize the signal level received by transceiver 114. Signal detector 118 can detect signals such as total energy, energy per subcarrier per symbol, power spectral density, and other signals. Device 100 may also include a digital signal processor (DSP) 120 for processing the signals.

[0026] Device 100 may also include a battery 122 for powering various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to the various components of device 100. PMIC 124 can perform various functions for the device, such as DC-DC conversion, battery charging, power selection, voltage scaling, power sequencing, etc. In some aspects, PMIC 124 may include a voltage regulator system implemented by linkage with a low-dropout (LDO) regulator.

[0027] The various components of device 100 can be coupled together through bus system 126, which includes not only data bus, but also power bus, control signal bus and status signal bus.

[0028] Exemplary voltage regulation system

[0029] Certain aspects of this disclosure generally relate to techniques for linkage regulators (e.g., low dropout (LDO) regulators). Regulator linkage allows power management integrated circuits (PMICs) (e.g., PMIC 124) to meet higher current demands. Regulator linkage also makes it more flexible to reuse existing PMICs in different chipsets. Configuring regulators to operate within an acceptable margin range (e.g., a desired margin range for improving performance and reducing power consumption) can save system power and address thermal challenges. Some aspects of this disclosure use current balancing to increase the power efficiency associated with regulator linkage. As used herein, the term "current balancing" can refer to adjusting the output current of the regulator to improve performance or increase the power efficiency associated with regulator linkage (even if the output current may not be equal after such adjustment). Current balancing can be used when amplifier margins are too low, causing amplifier performance to begin to degrade. In some aspects, the margin of each amplifier can be detected, and the detected margins can be used to adjust the current balance of the regulator to increase the power efficiency of the power system.

[0030] Figure 2A power supply system 200 using linked LDO regulators according to certain aspects of this disclosure is illustrated. As shown, the power supply system 200 may include multiple LDO regulators (e.g., LDO regulator 202 and LDO regulator 222) having outputs coupled to a load (e.g., represented by current source 252). For example, LDO regulator 202 may include a transistor 204 (referred to as a "transfer transistor") having a drain coupled to an input voltage (Vin) node 206 and a source coupled to an output voltage (Vout1) node 208. LDO regulator 202 also includes an amplifier 210 (e.g., an error amplifier) ​​having a first input (e.g., a positive input) coupled to an input reference voltage (Vref_in) node 212 and a second output (e.g., a negative output) coupled to the Vout1 node 208. Vref_in at node 212 can be used to control the output current (Iout1) 214 of the LDO regulator 202 (e.g., the drain-to-source current of transistor 204), thereby effectively regulating the voltage at node 208 (e.g., labeled "Vout1"). In other words, increasing Vref_in causes Iout1 214 to increase (e.g., through resistor R1).

[0031] As shown, the LDO regulator 222 may include a transistor 224 having a drain coupled to the Vin node 206 and a source coupled to the output voltage node 228 (labeled "Vout2"). The LDO regulator 222 also includes an amplifier 230 having a first input (e.g., a positive input) coupled to the common reference voltage (Vref) node 232 and a second input (e.g., a negative input) coupled to the Vout2 node 228. Vref at the Vref node 232 can be used to control the output current (Iout2) 225 of the LDO regulator 222 (e.g., the drain-to-source current of the transistor 224). In other words, increasing Vref causes Iout2 225 to increase (e.g., through the resistor element R2). As shown in the figure, Vout2 node 228 and Vout1 node 208 are coupled to a common output node 250 (denoted as "Vout") via corresponding resistors R1 and R2 (e.g., in some aspects, the resistances of resistors R1 and R2 may differ due to resistor tolerances and / or routing variations). The common output node 250 may be coupled to a load circuit (denoted as "Iload") represented by current source 252. The difference between Vin (e.g., at Vin node 206) and Vout1 or Vout2 represents the headroom (HR) of LDO regulator 202 or LDO regulator 222, respectively. Regarding... Figure 3 The HR associated with LDO is described in more detail.

[0032] Figure 3 Figure 300 illustrates various operating regions of an LDO regulator according to certain aspects of this disclosure. Regarding Figure 3 The described operating regions can be associated with different HR and output current ranges for different LDO regulators, depending on the characteristics of the LDO regulator (e.g., the characteristics of the transistor used to implement the LDO regulator). As shown, the LDO regulator can operate within one of three operating regions: transistor region 302, saturation region 304, and HR-acceptable region 306 (also referred to as the "HR-suitable" region). As used herein, operating at an acceptable HR (e.g., operating in HR-acceptable region 306) generally refers to setting the HR of the LDO regulator to provide better performance compared to operating in the transistor region and better power efficiency compared to operating in the saturation region. HR-acceptable region 306 can be the region following curve 316, represented by the following equation:

[0033]

[0034] Where Irated is the rated current (e.g., 100mV) of the LDO transistor (e.g., transistor 204 or transistor 224), Iout is the output current of the LDO regulator (e.g., Iout1 214 or Iout2 225), and HR is the margin of the LDO. As shown, different acceptable HRs exist depending on the Iout of the LDO regulator (e.g., in the HR acceptable region 306). For a specific output current of the LDO regulator, the HR acceptable region 306 may have a range (e.g., HR range 380), which may be set based on the implementation and using the configuration tolerance from curve 316. Curves 308, 310, 312, and 314 correspond to different gate-source voltages (Vgs) of the LDO regulator transistors (e.g., transistor 204 or transistor 224).

[0035] In some aspects of this disclosure, the LDO regulator can detect the HR of the LDO regulator. If the HR is too low (e.g., HR corresponds to operation in transistor region 302), the LDO regulator may not be able to supply sufficient current and may require an increase in the HR of the LDO regulator. For example, referencing Figure 2When the HR of LDO regulator 202 is too low (e.g., the LDO regulator is operating in transistor region 302), LDO performance begins to degrade. Power system 200 may include a power supply 260 (e.g., a switch-mode power supply, such as a buck converter) capable of generating and regulating Vin. When the HR of LDO regulator 202 is too low, power supply 260 may increase Vin, thereby effectively increasing the HR of LDO regulator 202 (e.g., and LDO regulator 222, since Vin node 206 is common to both LDO regulator 202 and LDO regulator 222).

[0036] If the HR of the LDO regulator is appropriate (e.g., the LDO regulator operates in the HR-acceptable region 306), the LDO may not request any change to the HR. If the HR of the LDO regulator is too high (e.g., the LDO regulator operates in the saturation region 304), the LDO regulator may be configured to provide more current (e.g., reduce the output current that would be supplied by other LDO regulators) until all LDOs report the same condition, and then request a reduction in HR to save power, as per [reference to...]. Figure 4 A more detailed description.

[0037] Figure 4 Table 400 illustrates exemplary techniques for HR adjustment and current balancing according to certain aspects of this disclosure. As shown, if the HR of any of the LDO regulators is too low (e.g., operating in transistor region 302), Vin can be increased to increase the HR of all LDO regulators. For example, as shown in Table 400, if the HR of LDO regulator 202 (also referred to as "LDO1") or LDO regulator 222 (also referred to as "LDO2") is too low, the HR of both LDOs can be increased.

[0038] If the HR of all LDO regulators is too high (e.g., operating in saturation region 304), Vin can be reduced to reduce the HR of all LDO regulators. For example, as shown in Table 400, if the HR of both LDO regulator 202 and LDO regulator 222 is too high, the HR of these two LDOs can be reduced.

[0039] In other situations, such as when the HR of one LDO regulator is too high while the HR of another LDO regulator is appropriate, current balancing can be used. (Refer to previous text) Figure 2The power supply system 200 may include a current balancer 270. The current balancer 270 may include an adjustable voltage source 272, which can be controlled to set the voltage difference (ΔVref) between Vref and Vref_in. By increasing ΔVref (e.g., increasing the voltage offset associated with the adjustable voltage source 272), Iout1 214 may increase, resulting in a decrease in Iout2 225. Conversely, by decreasing ΔVref (e.g., decreasing the voltage associated with the adjustable voltage source 272), Iout1 214 may decrease, resulting in an increase in Iout2 225. The current balancer 270 can be used to control the gate voltage of transistor 224 of LDO regulator 202 by applying a voltage offset to Vref, which is used to control the gate voltage of transistor 204 of LDO regulator 222. Therefore, LDO regulator 202 may be referred to as a "slave LDO regulator," and LDO regulator 222 may be referred to as a "master LDO regulator."

[0040] If a subset of the LDO regulators are in the HR-acceptable region 306, and at least one of the LDO regulators is in the saturation region 304, current balancing (e.g., via current balancer 270) can be used to balance the current supplied by the LDO regulators. For example, as shown in Table 400, if the HR of LDO regulator 202 (LDO 1) is too high (e.g., LDO regulator 202 operates in the saturation region 304), but the HR of LDO regulator 222 (LDO 2) is acceptable (e.g., LDO regulator 222 operates in the HR-acceptable region 306), the current balancer can increase ΔVref. As an example, if LDO regulator 202 (LDO 1) is in the HR-acceptable region 306, the current balancer can increase ΔVref. Figure 3 Operating at the operating point 390 shown, ΔVref can be increased, thereby increasing Iout1 of LDO regulator 202, causing LDO regulator 202 to operate at operating point 392 (e.g., in the HR acceptable region 306). On the other hand, if the HR of LDO regulator 222 (LDO 2) is too high (e.g., LDO regulator 222 operates in the saturation region), but the HR of LDO regulator 202 (LDO 1) is acceptable (e.g., LDO regulator 202 operates in the acceptable HR region), the current balancer can reduce ΔVref.

[0041] In some respects, Figure 2The power supply system 200 may include an automatic headroom control (AHC) circuit 280. LDO regulators 202 and 222 may provide AHC request signals (AHC_REQ_1 and AHC_REQ_2, respectively) to the AHC circuit 280. These AHC request signals may indicate whether the HR of each corresponding LDO regulator is too high, too low, or acceptable. For example, each of LDO regulators 202 and 222 may include circuitry for detecting the HR of the LDO regulator (e.g., the difference between Vin and Vout1 or Vin and Vout2) and the output current of the LDO (e.g., Iout1 214 or Iout2 225). Based on the detected HR and Iout, each LDO regulator may determine and indicate whether its HR is too high, too low, or acceptable, as shown in Figure 300. In some cases, each LDO regulator may provide more detailed information, such as the detected HR and Iout of the LDO, via the AHC request signal.

[0042] Based on this AHC request signal, the AHC circuit 280 can, according to the relevant information... Figure 4 The described techniques are used to control power supply 260 (e.g., for controlling HR by adjusting Vin) and current balancer 270 (e.g., for current balancing). For example, the AHC circuit can provide the power supply with an AHC direction signal indicating whether HR is increasing or decreasing, and an AHC step signal indicating the step size associated with that increase or decrease.

[0043] Although only two LDO regulators are described for ease of understanding, various aspects of this disclosure can be implemented for any number of LDO regulators. For example, if the linkage of more than two LDO regulators is implemented, a current balancer can be implemented for all LDO regulators except for one of them. For example, for three LDO regulators, if the HR of any one of the three LDO regulators is too low, the HR of all LDO regulators can be increased. If the HR of all three LDO regulators is too high, the HR of that LDO regulator can be decreased. If the HR of any one of the LDO regulators is too high, while the HR of one or more other LDO regulators is acceptable, current balancing can be used to balance the output current of the LDO regulators, as described herein.

[0044] Compared to conventional implementations, certain aspects described herein achieve higher power efficiency. The techniques described herein are scalable to multiple LDOs across a PMIC and can be implemented for linkage of different types of LDO regulators.

[0045] Exemplary technologies for power supply

[0046] Figure 5This is a flowchart illustrating an exemplary operation 500 for power supply according to certain aspects of this disclosure. Operation 500 may be performed, for example, by a power supply system 200.

[0047] Operation 500 begins at block 505, where the power system generates a first output current (e.g., Iout1 214) via a first voltage regulator (e.g., LDO regulator 202). At block 510, the power system generates a second output current (e.g., Iout2 214) via a second voltage regulator (e.g., LDO regulator 222), and the first and second output currents are provided to a common output node (e.g., common output node 250). At block 515, the power system adjusts the first output current via a current balancer circuit (e.g., current balancer 270) based on determined margins in the first and second voltage regulators.

[0048] In some aspects, the first voltage regulator may include a first transistor (e.g., transistor 204), the margin of which is determined as the difference between the drain voltage (e.g., Vin) and the source voltage (e.g., Vout1) of the first transistor. The second voltage regulator may include a second transistor (e.g., transistor 224), the margin of which is determined as the difference between the drain voltage (e.g., Vin) and the source voltage (e.g., Vout2) of the second transistor.

[0049] In some aspects, the power supply system can adjust the first output current via a current balancer circuit based on whether the determined margin of the first voltage regulator is within a first margin range (e.g., the HR range corresponding to the HR acceptable region 306 of LDO regulator 222) and whether the determined margin of the second voltage regulator is within a second margin range (e.g., the HR range corresponding to the HR acceptable region 306 of LDO regulator 202). The upper limit of the first or second margin range may be less than the lower limit of a third margin range (e.g., the HR range in saturation region 304) associated with the first or second voltage regulator operating in saturation state. The lower limit of the first or second margin range may be greater than the upper limit of a fourth margin range (e.g., the HR range in transistor region 302) associated with the first or second voltage regulator operating in transistor state. In some aspects, adjusting the first output current may include decreasing the first output current based on the determined margin of the second voltage regulator (e.g., LDO regulator 222) being higher than the upper limit of the second margin range (e.g., the HR range in the HR acceptable region 306 of LDO regulator 202) and the determined margin of the first voltage regulator (e.g., LDO regulator 222) being lower than the lower limit of the first margin range (e.g., the HR range in the HR acceptable region 306 of LDO regulator 202). In some aspects, adjusting the first output current may include increasing the first output current based on the determined margin of the first voltage regulator (e.g., LDO regulator 202) being higher than the upper limit of the first margin range (e.g., the HR range in the HR acceptable region 306 of LDO regulator 222) and the determined margin of the second voltage regulator being lower than the lower limit of the second margin range (e.g., the HR range in the HR acceptable region 306 of LDO regulator 202).

[0050] In some aspects, the power system may adjust the margins of the first voltage regulator and the second voltage regulator via a margin adjustment circuit (e.g., AHC circuit 280) based on at least one of the determined margins of the first voltage regulator and the second voltage regulator. In some aspects, adjusting the margins may include increasing the margins of the first voltage regulator and the second voltage regulator based on the determined margin of at least one of the first or second voltage regulator being below a margin range (e.g., the HR range in HR acceptable region 306). In some aspects, adjusting the margins may include decreasing the margins of the first voltage regulator and the second voltage regulator based on the determined margins of the first voltage regulator and the second voltage regulator being above a margin range (e.g., the HR range in HR acceptable region 306).

[0051] In some aspects, the power supply system may adjust the margins of the first voltage regulator and the second voltage regulator via a margin adjustment circuit (e.g., power supply 260). The power supply system may also receive indications (e.g., AHC request signals) of the determined margins of the first and second voltage regulators via an automatic margin control circuit (e.g., AHC circuit 280), and control the margin adjustment circuit and the current balancer circuit via the automatic margin control circuit based on the determined margin indications. In some aspects, the margin adjustment circuit may include a power supply (e.g., power supply 260) configured to generate input voltages (e.g., at Vin node 206) for the first and second voltage regulators. In some aspects, adjusting the first output current may include adjusting the offset (e.g., corresponding to ΔVref) between a first reference voltage (e.g., Vref_in) for the first voltage regulator and a second reference voltage (e.g., Vref) for the second voltage regulator.

[0052] The various operations described above can be performed by any suitable component capable of performing the corresponding function. The device may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Typically, where the operations shown in the accompanying drawings are present, those operations may have corresponding devices plus functional components with similar reference numerals.

[0053] For example, components used to generate the output current may include an LDO regulator, such as LDO regulator 202 or LDO regulator 222. Alternatively or otherwise, components used to generate the output current may include a power source, such as a battery (e.g., battery 122) and one or more power supply circuits (e.g., power supply 260). Components used for adjustment may include a current balancer circuit, such as current balancer 212.

[0054] As used herein, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculation, operation, processing, deduction, investigation, lookup (e.g., searching in a table, database, or other data structure), assertion, and so on. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and so on. Additionally, "determine" can include parsing, selecting, choosing, building, and so on.

[0055] As used herein, the phrase “at least one of the items” refers to any combination of these items (including a single member). For example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, cc, and ccc, or any other ordering of a, b, and c).

[0056] The various illustrative logic blocks, modules, and circuits described in this disclosure can be implemented or executed using a general-purpose processor, digital signal processor (DSP), ASIC, field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors and a DSP core, or any other such configuration.

[0057] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchanged without departing from the scope of the claims. That is, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0058] The functionality described herein can be implemented using hardware, software, firmware, or any combination thereof. If implemented in hardware, an exemplary hardware configuration may include a processing system in a wireless node. This processing system can be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnect buses and bridges. The bus can link various circuits together, including processors, machine-readable media, and bus interfaces. The bus interface can be used to connect network adapters, etc., to the processing system via the bus. Network adapters can be used to implement signal processing functions at the physical (PHY) layer. In the case of a user terminal, a user interface (e.g., a keypad, display, mouse, joystick, etc.) can also be connected to the bus. The bus can also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0059] The processing system can be configured as a general-purpose processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of machine-readable medium, all of which are linked together with other supporting circuitry via an external bus architecture. Alternatively, the processing system can be implemented using an ASIC with a processor, a bus interface, a user interface (in the case of an access terminal), supporting circuitry, and at least a portion of machine-readable medium integrated into a single chip, or using one or more FPGAs, PLDs, controllers, state machines, gating logic devices, discrete hardware components, or any other suitable circuitry or any combination of circuitry capable of performing the various functions described throughout this disclosure. Those skilled in the art will recognize how best to implement the functions of the processing system depends on the specific application and the overall design constraints imposed on the system as a whole.

[0060] Exemplary aspects

[0061] In addition to the aspects mentioned above, specific combinations of these aspects are also within the scope of this disclosure, and some details of these specific combinations are as follows:

[0062] Aspect 1: A power supply system comprising: a first voltage regulator; a second voltage regulator, the outputs of the first voltage regulator and the second voltage regulator being coupled to an output of the power supply system; and a current balancer circuit configured to adjust the output current of the first voltage regulator based on determined margins of the first voltage regulator and the second voltage regulator.

[0063] Aspect 2: The power supply system according to Aspect 1, wherein: the first voltage regulator includes a first transistor, and the determined margin of the first voltage regulator is the difference between the drain voltage and the source voltage of the first transistor; and the second voltage regulator includes a second transistor, and the determined margin of the second voltage regulator is the difference between the drain voltage and the source voltage of the second transistor.

[0064] Aspect 3: The power supply system according to aspect 1 or 2, wherein the current balancer circuit is configured to adjust the output current of the first voltage regulator based on whether the determined margin of the first voltage regulator is within a first margin range and whether the determined margin of the second voltage regulator is within a second margin range.

[0065] Aspect 4: The power supply system according to aspect 3, wherein: the first margin range includes an acceptable margin of the first voltage regulator given the output current of the first voltage regulator; and the second margin range includes an acceptable margin of the second voltage regulator given the output current of the second voltage regulator.

[0066] Aspect 5: The power supply system according to aspect 3 or 4, wherein: the upper limit of the first margin range or the second margin range is less than the lower limit of the third margin range associated with the first voltage regulator or the second voltage regulator operating in saturation state; and the lower limit of the first margin range or the second margin range is greater than the upper limit of the fourth margin range associated with the first voltage regulator or the second voltage regulator operating in transistor state.

[0067] Aspect 6: The power supply system according to any one of aspects 3 to 5, wherein the current balancer circuit is configured to reduce the output current of the first voltage regulator based on the fact that the determined margin of the second voltage regulator is higher than the upper limit of the second margin range and the determined margin of the first voltage regulator is lower than the lower limit of the first margin range.

[0068] Aspect 7: A power supply system according to any one of aspects 3 to 6, wherein the current balancer circuit is configured to increase the output current of the first voltage regulator based on the determined margin of the first voltage regulator being higher than the upper limit of the first margin range and the determined margin of the second voltage regulator being lower than the lower limit of the second margin range.

[0069] Aspect 8: The power system according to any of the foregoing aspects further includes a margin adjustment circuit configured to adjust the margin of the first voltage regulator and the margin of the second voltage regulator based on at least one of the determined margins of the first voltage regulator and the second voltage regulator.

[0070] Aspect 9: The power supply system according to aspect 8, wherein the margin adjustment circuit is configured to increase the margin of the first voltage regulator and the margin of the second voltage regulator based on the determined margin of at least one of the first voltage regulator or the second voltage regulator being below the margin range.

[0071] Aspect 10: The power supply system according to aspect 8 or 9, wherein the margin adjustment circuit is configured to reduce the margin of the first voltage regulator and the margin of the second voltage regulator based on the determined margin of the first voltage regulator and the margin of the second voltage regulator being above the margin range.

[0072] Aspect 11: The power supply system according to any one of aspects 1 to 7 further includes: a margin adjustment circuit configured to adjust the margin of the first voltage regulator and the margin of the second voltage regulator; and an automatic margin control circuit configured to: receive an indication of the determined margin of the first voltage regulator and the margin of the second voltage regulator; and control the margin adjustment circuit and the current balancer circuit based on the indication of the determined margin.

[0073] Aspect 12: The power supply system according to aspect 11, wherein the margin adjustment circuit includes a power supply configured to generate input voltages for the first voltage regulator and the second voltage regulator.

[0074] Aspect 13: A power supply system according to any of the foregoing aspects, wherein the current balancer circuit is configured to adjust the offset between a first reference voltage for the first voltage regulator and a second reference voltage for the second voltage regulator.

[0075] Aspect 14: The power supply system according to aspect 13, wherein: the first voltage regulator includes a first amplifier having a first input configured to receive the first reference voltage and a second input coupled to the output of the first voltage regulator; and the second voltage regulator includes a second amplifier having a first input configured to receive the second reference voltage and a second input coupled to the output of the second voltage regulator.

[0076] Aspect 15: The power supply system according to aspect 14, wherein the current balancer circuit includes an adjustable voltage source coupled between a reference voltage node and the first input of the first amplifier, and the current balancer circuit is configured to adjust the offset by controlling the adjustable voltage source.

[0077] Aspect 16: The power supply system according to any of the foregoing aspects further includes: a first resistive element coupled between the output of the first voltage regulator and the output of the power supply system and having a first resistance; and a second resistive element coupled between the output of the second voltage regulator and the output of the power supply system and having a second resistance different from the first resistance of the first resistive element.

[0078] Aspect 17: The power supply system according to any of the foregoing aspects, wherein the first voltage regulator and the second voltage regulator include low dropout (LDO) regulators.

[0079] Aspect 18: A method of power supply, the method comprising: generating a first output current via a first voltage regulator; generating a second output current via a second voltage regulator, the first output current and the second output current being provided to a common output node; and adjusting the first output current via a current balancer circuit based on determined margins of the first voltage regulator and the second voltage regulator.

[0080] Aspect 19: The method according to aspect 18, wherein: the first voltage regulator includes a first transistor; the method further includes determining the margin of the first voltage regulator by determining the difference between the drain voltage and the source voltage of the first transistor; the second voltage regulator includes a second transistor; and the method further includes determining the margin of the second voltage regulator by determining the difference between the drain voltage and the source voltage of the second transistor.

[0081] Aspect 20: The method according to aspect 18 or 19, wherein the adjustment of the first output current is based on whether the determined margin of the first voltage regulator is within a first margin range and whether the determined margin of the second voltage regulator is within a second margin range.

[0082] Aspect 21: The method according to aspect 20, wherein: the upper limit of the first margin range or the second margin range is less than the lower limit of a third margin range associated with the first voltage regulator or the second voltage regulator operating in saturation state; and the lower limit of the first margin range or the second margin range is greater than the upper limit of a fourth margin range associated with the first voltage regulator or the second voltage regulator operating in transistor state.

[0083] Aspect 22: According to the method of aspect 20, adjusting the first output current includes reducing the first output current based on the determined margin of the second voltage regulator being higher than the upper limit of the second margin range and the determined margin of the first voltage regulator being lower than the lower limit of the first margin range.

[0084] Aspect 23: According to the method of aspect 20, adjusting the first output current includes increasing the first output current based on the determined margin of the first voltage regulator being higher than the upper limit of the first margin range and the determined margin of the second voltage regulator being lower than the lower limit of the second margin range.

[0085] Aspect 24: The method according to any one of aspects 18 to 23 further includes adjusting the margin of the first voltage regulator and the margin of the second voltage regulator via a margin adjustment circuit based on at least one of the determined margin of the first voltage regulator and the margin of the second voltage regulator.

[0086] Aspect 25: The method according to aspect 24, wherein adjusting the margin includes increasing the margin of the first voltage regulator and the margin of the second voltage regulator based on the fact that the margin of at least one of the first voltage regulator or the second voltage regulator is below the margin range.

[0087] Aspect 26: According to the method of aspect 24, adjusting the margin includes reducing the margin of the first voltage regulator and the margin of the second voltage regulator based on the determined margin of the first voltage regulator and the margin of the second voltage regulator being higher than the margin range.

[0088] Aspect 27: The method according to any one of aspects 18 to 23, further comprising: adjusting the margin of the first voltage regulator and the margin of the second voltage regulator via a margin adjustment circuit; receiving an indication of the determined margin of the first voltage regulator and the margin of the second voltage regulator via an automatic margin control circuit; and controlling the margin adjustment circuit and the current balancer circuit via the automatic margin control circuit based on the indication of the determined margin.

[0089] Aspect 28: The method according to aspect 24 or 27, wherein the margin adjustment circuit includes a power supply configured to generate input voltages for the first voltage regulator and the second voltage regulator.

[0090] Aspect 29: The method according to any one of aspects 18 to 28, wherein adjusting the first output current includes adjusting the offset between a first reference voltage for the first voltage regulator and a second reference voltage for the second voltage regulator.

[0091] Aspect 30: An apparatus for supplying power, the apparatus comprising: a component for generating a first output current; a component for generating a second output current, the first output current and the second output current being provided to a common output node; and a component for adjusting the first output current based on a determined margin associated with the component for generating the first output current and the component for generating the second output current.

[0092] It should be understood that the claims are not limited to the precise configurations and components described above. Various modifications, substitutions, and variations can be made to the layout, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A power supply system, the power supply system comprising: First voltage regulator; A second voltage regulator, the outputs of the first voltage regulator and the second voltage regulator are coupled to the output of the power supply system; and A current balancer circuit is configured to adjust the output current of the first voltage regulator based on the determined margins of the first voltage regulator and the second voltage regulator, wherein: The current balancer circuit is configured to adjust the output current of the first voltage regulator based on whether the determined margin of the first voltage regulator is within a first margin range and whether the determined margin of the second voltage regulator is within a second margin range. The upper limit of the first margin range or the second margin range is less than the lower limit of the third margin range associated with the first voltage regulator or the second voltage regulator operating in saturation.

2. The power supply system according to claim 1, wherein: The first voltage regulator includes a first transistor, and the determined margin of the first voltage regulator is the difference between the drain voltage and the source voltage of the first transistor. and The second voltage regulator includes a second transistor, and the determined margin of the second voltage regulator is the difference between the drain voltage and the source voltage of the second transistor.

3. The power supply system according to claim 1, wherein: The first margin range includes the acceptable margin of the first voltage regulator given the output current of the first voltage regulator; and The second margin range includes the acceptable margin of the second voltage regulator given the output current of the second voltage regulator.

4. The power supply system according to claim 1, wherein: The lower limit of the first margin range or the second margin range is greater than the upper limit of the fourth margin range associated with the first voltage regulator or the second voltage regulator operating in transistor mode.

5. The power supply system according to claim 1, wherein, The current balancer circuit is configured to reduce the output current of the first voltage regulator based on the determined margin of the second voltage regulator being higher than the upper limit of the second margin range and the determined margin of the first voltage regulator being lower than the lower limit of the first margin range.

6. The power supply system according to claim 1, wherein, The current balancer circuit is configured to increase the output current of the first voltage regulator based on the determined margin of the first voltage regulator being higher than the upper limit of the first margin range and the determined margin of the second voltage regulator being lower than the lower limit of the second margin range.

7. The power supply system of claim 1, further comprising a margin adjustment circuit configured to adjust the margin of the first voltage regulator and the margin of the second voltage regulator based on at least one of a determined margin of the first voltage regulator and a margin of the second voltage regulator.

8. The power supply system according to claim 7, wherein, The margin adjustment circuit is configured to increase the margin of the first voltage regulator and the margin of the second voltage regulator based on the fact that the margin of at least one of the first voltage regulator or the second voltage regulator is below the margin range.

9. The power supply system according to claim 7, wherein, The margin adjustment circuit is configured to reduce the margin of the first voltage regulator and the margin of the second voltage regulator based on the determined margin of the first voltage regulator and the margin of the second voltage regulator being above the margin range.

10. The power supply system according to claim 1, further comprising: A margin adjustment circuit is configured to adjust the margin of the first voltage regulator and the margin of the second voltage regulator; and Automatic margin control circuit, the automatic margin control circuit being configured to: Receive indications of the determined margins of the first voltage regulator and the second voltage regulator; and The margin adjustment circuit and the current balancer circuit are controlled based on the indication of the determined margin.

11. The power supply system according to claim 10, wherein, The margin adjustment circuit includes a power supply configured to generate input voltages for the first voltage regulator and the second voltage regulator.

12. The power supply system according to claim 1, wherein, The current balancer circuit is configured to adjust the offset between a first reference voltage for the first voltage regulator and a second reference voltage for the second voltage regulator.

13. The power supply system according to claim 12, wherein: The first voltage regulator includes a first amplifier having a first input configured to receive the first reference voltage and a second input coupled to the output of the first voltage regulator; and The second voltage regulator includes a second amplifier having a first input configured to receive the second reference voltage and a second input coupled to the output of the second voltage regulator.

14. The power supply system according to claim 13, wherein, The current balancer circuit includes an adjustable voltage source coupled between a reference voltage node and the first input of the first amplifier, and the current balancer circuit is configured to adjust the offset by controlling the adjustable voltage source.

15. The power supply system according to claim 1, further comprising: A first resistive element is coupled between the output of the first voltage regulator and the output of the power supply system, and has a first resistance. and A second resistive element is coupled between the output of the second voltage regulator and the output of the power supply system, and has a second resistance different from the first resistance of the first resistive element.

16. The power supply system according to claim 1, wherein, The first voltage regulator and the second voltage regulator include low dropout (LDO) regulators.

17. A method of supplying power, the method comprising: A first output current is generated via a first voltage regulator; A second output current is generated via a second voltage regulator, and the first and second output currents are provided to a common output node. as well as Based on the determined margins of the first voltage regulator and the second voltage regulator, the first output current is adjusted via a current balancer circuit, wherein: The adjustment of the first output current is based on whether the determined margin of the first voltage regulator is within a first margin range and whether the determined margin of the second voltage regulator is within a second margin range. The upper limit of the first margin range or the second margin range is less than the lower limit of the third margin range associated with the first voltage regulator or the second voltage regulator operating in saturation.

18. The method of claim 17, wherein: The first voltage regulator includes a first transistor; The method further includes determining the margin of the first voltage regulator by determining the difference between the drain voltage and the source voltage of the first transistor; The second voltage regulator includes a second transistor; and The method further includes determining the margin of the second voltage regulator by determining the difference between the drain voltage and the source voltage of the second transistor.

19. The method of claim 17, wherein: The lower limit of the first margin range or the second margin range is greater than the upper limit of the fourth margin range associated with the first voltage regulator or the second voltage regulator operating in transistor mode.

20. The method of claim 17, wherein, Adjusting the first output current includes reducing the first output current based on the determined margin of the second voltage regulator being higher than the upper limit of the second margin range and the determined margin of the first voltage regulator being lower than the lower limit of the first margin range.

21. The method according to claim 17, wherein, Adjusting the first output current includes increasing the first output current based on the determined margin of the first voltage regulator being higher than the upper limit of the first margin range and the determined margin of the second voltage regulator being lower than the lower limit of the second margin range.

22. The method of claim 17, further comprising adjusting the margin of the first voltage regulator and the margin of the second voltage regulator via a margin adjustment circuit based on at least one of the determined margins of the first voltage regulator and the second voltage regulator.

23. The method according to claim 22, wherein, Adjusting the margin includes increasing the margin of the first voltage regulator and the margin of the second voltage regulator based on the fact that the margin of at least one of the first voltage regulator or the second voltage regulator is below the margin range.

24. The method according to claim 22, wherein, Adjusting the margin includes reducing the margins of the first voltage regulator and the second voltage regulator based on the determined margins of the first voltage regulator and the second voltage regulator being above the margin range.

25. The method according to claim 17, further comprising: The margins of the first voltage regulator and the second voltage regulator are adjusted via a margin adjustment circuit. The system receives indications of the determined margins of the first voltage regulator and the second voltage regulator via an automatic margin control circuit; and Based on the indicated margin, the margin adjustment circuit and the current balancer circuit are controlled via the automatic margin control circuit.

26. The method of claim 25, wherein, The margin adjustment circuit includes a power supply configured to generate input voltages for the first voltage regulator and the second voltage regulator.

27. The method according to claim 17, wherein, Adjusting the first output current includes adjusting the offset between a first reference voltage for the first voltage regulator and a second reference voltage for the second voltage regulator.

28. An apparatus for supplying power, the apparatus comprising: Components used to generate the first output current; A component for generating a second output current, wherein the first output current and the second output current are provided to a common output node; and A component for adjusting the first output current based on a determined margin associated with the component for generating the first output current and the component for generating the second output current, wherein: The component for adjusting the first output current is configured to adjust the first output current based on whether a determined margin associated with the component for generating the first output current is within a first margin range and whether a determined margin associated with the component for generating the second output current is within a second margin range. The upper limit of the first margin range or the second margin range is less than the lower limit of the third margin range associated with the component for generating the first output current or the component for generating the second output current operating in saturation state.

29. The apparatus of claim 28, further comprising: A component for performing the method according to any one of claims 18 to 27.

30. A power supply system, the power supply system comprising: First voltage regulator; A second voltage regulator, the outputs of the first voltage regulator and the second voltage regulator are coupled to the output of the power supply system; and A current balancer circuit is configured to adjust the output current of the first voltage regulator based on the determined margins of the first voltage regulator and the second voltage regulator, wherein: The current balancer circuit is configured to adjust the output current of the first voltage regulator based on whether the determined margin of the first voltage regulator is within a first margin range and whether the determined margin of the second voltage regulator is within a second margin range. The lower limit of the first margin range or the second margin range is greater than the upper limit of the third margin range associated with the first voltage regulator or the second voltage regulator operating in transistor mode.

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