Display panel and display device

Abstract

The application provides a display panel and a display device, the display panel comprising: an array substrate and a color film substrate; the array substrate comprising a substrate and a plurality of pixel units, a plurality of data lines and a plurality of gate lines; each pixel unit comprising a plurality of sub-pixels and a plurality of transistors, the sub-pixel comprising a light emitting unit, a pixel electrode and a common electrode, the first electrode of each transistor being connected to the pixel electrode of each sub-pixel in a one-to-one correspondence; the second electrode of the plurality of transistors in each pixel unit being connected to the same data line, and the gate electrode of the plurality of transistors in each pixel unit being connected to the plurality of gate lines in a one-to-one correspondence; the color film substrate comprising a black matrix and a plurality of color film units, the plurality of color film units being arranged in the pixel openings of the black matrix in a one-to-one correspondence; the pixel electrode comprising a connecting portion and a plurality of strip-shaped electrodes arranged in a row direction at intervals, the plurality of strip-shaped electrodes being connected together through the connecting portion, and the orthographic projection of the connecting portion on the substrate being located in the orthographic projection of the black matrix on the substrate.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With the development of driving methods and manufacturing processes, liquid crystal display (LCD) devices have seen significant improvements in production costs and image quality. Currently, triplet driving (TRD) technology has been proposed for pixel arrangement within the LCD device, reducing the number of source driver ICs to one-third, thereby lowering production costs.

[0003] In terms of font display in LCD devices, conventional pixel arrangement methods have systematic optimization algorithms. However, because the pixel arrangement method of conventional TRD technology differs from that of conventional pixel arrangement methods, the readability of clear characters is reduced by at least 30%. Therefore, while pursuing the ultimate aperture ratio in the pixels of the new three-speed drive technology, improving liquid crystal efficiency is particularly important.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a display panel and a display device.

[0006] According to a first aspect of the present invention, a display panel is provided, the display panel comprising:

[0007] An array substrate includes a substrate and a plurality of pixel units disposed on the substrate, a plurality of data lines extending in the column direction and spaced apart in the row direction, and a plurality of gate lines extending in the row direction and spaced apart in the column direction; each pixel unit includes a plurality of sub-pixels and a plurality of transistors, each sub-pixel includes a light-emitting unit and pixel electrodes and a common electrode located on both sides of the light-emitting unit, the first electrode of each transistor is connected to the pixel electrode of each sub-pixel in a one-to-one correspondence; the second electrodes of the plurality of transistors in each pixel unit are connected to the same data line, and the gates of the plurality of transistors in each pixel unit are connected to the plurality of gate lines in a one-to-one correspondence;

[0008] A color filter substrate includes a black matrix and multiple color filter units, wherein the black matrix has multiple pixel openings, and the multiple color filter units are disposed in the pixel openings one by one;

[0009] The pixel electrode includes a connecting portion and multiple strip electrodes spaced apart along the row direction. The multiple strip electrodes are connected together through the connecting portion, and the orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the black matrix on the substrate.

[0010] In an exemplary embodiment of this disclosure, the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a first transistor, a second transistor, and a third transistor. The pixel electrode of the first sub-pixel is connected to the first transistor, the pixel electrode of the second sub-pixel is connected to the second transistor, and the pixel electrode of the third sub-pixel is connected to the third transistor.

[0011] The plurality of gate lines include a first gate line, a second gate line, and a third gate line, wherein the first gate line is connected to the gate of the first transistor, the second gate line is connected to the gate of the second transistor, and the third gate line is connected to the gate of the third transistor;

[0012] Along the column direction, the first gate line and the second gate line are located at the two ends of the first sub-pixel, the second sub-pixel and the third sub-pixel, and the third gate line is located in the middle of the first sub-pixel, the second sub-pixel and the third sub-pixel.

[0013] In an exemplary embodiment of this disclosure, the first sub-pixel, the second sub-pixel, and the third sub-pixel in the pixel unit are arranged sequentially in the row direction. Two transistors connected to two sub-pixels of the first sub-pixel, the second sub-pixel, and the third sub-pixel are located at opposite ends of the corresponding sub-pixels in the column direction, and the other transistor is located in the middle of the corresponding sub-pixel in the column direction.

[0014] In one exemplary embodiment of this disclosure, the connection portions of the pixel electrodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all located at the ends of the first sub-pixel, the second sub-pixel, and the third sub-pixel in the column direction.

[0015] In one exemplary embodiment of this disclosure, one end of the plurality of strip electrodes in the column direction is connected together by the connecting portion.

[0016] In an exemplary embodiment of this disclosure, the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a first transistor, a second transistor, and a third transistor. The pixel electrode of the first sub-pixel is connected to the first transistor, the pixel electrode of the second sub-pixel is connected to the second transistor, and the pixel electrode of the third sub-pixel is connected to the third transistor.

[0017] The plurality of gate lines include a first gate line, a second gate line, and a third gate line, wherein the first gate line is connected to the gate of the first transistor, the second gate line is connected to the gate of the second transistor, and the third gate line is connected to the gate of the third transistor;

[0018] Wherein, along the column direction, the third gate line is located at one end of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the first gate line and the second gate line are located in the middle of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0019] In an exemplary embodiment of this disclosure, the first sub-pixel, the second sub-pixel, and the third sub-pixel in the pixel unit are arranged sequentially in the row direction. Two transistors connected to two of the first, second, and third sub-pixels are located in the middle part of the corresponding sub-pixel in the column direction, and the other transistor is located at the end of the corresponding sub-pixel in the column direction.

[0020] In one exemplary embodiment of this disclosure, the connection portions of the pixel electrodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all located in the middle of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0021] In one exemplary embodiment of this disclosure, the plurality of strip electrodes are connected together at the middle of the column direction via the connecting portion.

[0022] According to a second aspect of the present invention, a display device is provided, the display device including the display panel described above.

[0023] The display panel disclosed herein connects a single data line to the second electrode of multiple transistors in a pixel unit simultaneously. This means that multiple sub-pixels in a pixel unit along the row direction can be connected simultaneously via a single data line. Therefore, one source driver IC can perform the work of multiple source driver ICs, doubling the driving speed and reducing production costs. Simultaneously, the orthographic projection of the multiple strip electrode connection portions in the pixel electrode onto the substrate lies within the orthographic projection of the black matrix onto the substrate. This means that the black matrix completely blocks the horizontally connected multiple strip electrode connection portions, improving the liquid crystal efficiency under the same aperture ratio and thus enhancing the display effect of the display panel.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0026] Figure 1 This is a partial structural layout of a display panel provided in this disclosure;

[0027] Figure 2 For the purposes of this disclosure Figure 1 Structural layout of the middle pixel electrode;

[0028] Figure 3 For the purposes of this disclosure Figure 1 Structural layout of the mid-pixel electrode and the black matrix;

[0029] Figure 4 This is a partial structural layout of another display panel provided in this disclosure;

[0030] Figure 5 For the purposes of this disclosure Figure 4 Structural layout of the middle pixel electrode;

[0031] Figure 6 For the purposes of this disclosure Figure 4 Structural layout of the mid-pixel electrode and the black matrix;

[0032] Figure 7 A partial cross-sectional view of a display panel provided in one embodiment of this disclosure;

[0033] Figure 8 A partial structural layout of a display panel provided in one embodiment of this disclosure;

[0034] Figure 9 One embodiment of this disclosure provides Figure 8 Structural layout of the middle grid lines;

[0035] Figure 10 One disclosed embodiment provides Figure 8 The structural layout of the data cable;

[0036] Figure 11 One embodiment of this disclosure provides Figure 8 Layout of the grid lines and data lines;

[0037] Figure 12 One disclosed embodiment provides Figure 8 Structural layout of the middle pixel electrode;

[0038] Figure 13 One disclosed embodiment provides Figure 8 Structural layout of the black matrix;

[0039] Figure 14 One disclosed embodiment provides Figure 8 Structural layout of the mid-pixel electrode and the black matrix;

[0040] Figure 15 A partial structural layout of a display panel provided for another embodiment of this disclosure;

[0041] Figure 16 Provided as an embodiment of this disclosure Figure 15 Structural layout of the middle grid lines;

[0042] Figure 17 Provided as an embodiment of this disclosure Figure 15 The structural layout of the data cable;

[0043] Figure 18 Provided as an embodiment of this disclosure Figure 15 Layout of the grid lines and data lines;

[0044] Figure 19 Provided as an embodiment of this disclosure Figure 15 Structural layout of the middle pixel electrode;

[0045] Figure 20 Provided as an embodiment of this disclosure Figure 15 Structural layout of the black matrix;

[0046] Figure 21 Provided for one embodiment of this disclosure Figure 15 The structural layout of the middle pixel electrode and the black matrix. Detailed Implementation

[0047] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0048] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring aspects of this disclosure. The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0049] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0050] The terms “a,” “one,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” “third,” etc. are used only as markers and are not a limitation on the number of objects.

[0051] like Figures 1-6 As shown, in the pixels of a liquid crystal display panel, the pixel electrode (ITO) 500' is usually connected near the conductive block (Pad) 501'. However, in the pixels of the new TRD technology, in order to pursue the ultimate aperture ratio of the display panel, when the ITO is connected near the Pad, the black-black matrix (BM) 700' cannot completely block the horizontally connected ITO, which leads to a decrease in liquid crystal efficiency under the same aperture ratio.

[0052] This disclosure provides a liquid crystal display panel, such as Figure 8 and Figure 15As shown, the pixel arrangement uses triple-rate driving (TRD) technology, which reduces the number of source driver ICs to one-third, thereby reducing production costs.

[0053] Specifically, such as Figures 8-11 , Figures 15-18 As shown, the pixel unit includes three sub-pixels, which are arranged sequentially in the row direction. Each sub-pixel is equipped with a corresponding transistor. Three gate lines 220 are connected to the gates of the three transistors respectively, and a data line 210 is connected to the sources of the three transistors simultaneously. The data voltage provided by the three sub-pixels in a time-division manner through the data line is provided by the data line. That is, the three sub-pixels in the row direction are connected simultaneously through the data line 210. In other words, one source driver IC can perform the work of three source driver ICs, which can increase the driving speed by up to three times and reduce the production cost.

[0054] In one embodiment, the display panel includes an array substrate and a color filter substrate. The array substrate includes a substrate and a plurality of pixel units disposed on the substrate, a plurality of data lines 210 extending in the column direction and spaced apart in the row direction, and a plurality of gate lines 220 extending in the row direction and spaced apart in the column direction. Each pixel unit includes a plurality of sub-pixels and a plurality of transistors. Each sub-pixel includes a light-emitting unit and pixel electrodes and a common electrode located on both sides of the light-emitting unit. The first electrode of each transistor is connected to the pixel electrode of each sub-pixel in a one-to-one correspondence. The second electrodes of the plurality of transistors in each pixel unit are connected to the same data line 210, and the gates of the plurality of transistors in the pixel unit are connected to the plurality of gate lines 220 in a one-to-one correspondence. The color filter substrate includes a black matrix 700 and a plurality of color filter units. The black matrix 700 forms a plurality of pixel openings, and the plurality of color filter units are disposed in the pixel openings in a one-to-one correspondence. Pixel electrodes 500 include a connecting portion and a plurality of strip electrodes spaced apart in the row direction. The plurality of strip electrodes are connected together through the connecting portion, and the orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the black matrix 700 on the substrate.

[0055] The display panel disclosed herein connects a single data line 210 to the second electrode of three transistors in a pixel unit. That is, it connects three sub-pixels in a pixel unit in the row direction through a single data line 210. Therefore, one source driver IC can perform the work of three source driver ICs, thereby increasing the driving speed by up to three times and reducing production costs. At the same time, the orthographic projection of the multiple strip electrode connection portions in the pixel electrode 500 onto the substrate is located within the orthographic projection of the black matrix 700 onto the substrate. That is, the black matrix 700 completely blocks the multiple horizontally connected strip electrode connection portions, improving the liquid crystal efficiency under the same aperture ratio, thereby improving the display effect of the display panel.

[0056] In one embodiment, such as Figure 7As shown, the liquid crystal display panel provided in this disclosure can be an in-plane switching type (IPS), where the first electrode 310 of the transistor can be the drain and the second electrode 330 can be the source. The pixel electrode 500 and the common electrode 600 are located on the same side of the liquid crystal and on one side of the TFT substrate. When there is no voltage, light passes through the lower polarizer and forms linearly polarized light parallel to the short axis of the liquid crystal molecules. The polarization direction cannot be rotated, so it is absorbed by the upper polarizer and cannot be emitted. When a voltage is applied, a transverse electric field is formed on the left and right sides of the liquid crystal. The liquid crystal molecules align along the direction of the electric field, and the light passes through the lower polarizer and the liquid crystal layer in a polarized state, allowing it to pass through the upper polarizer and be emitted. Of course, the liquid crystal display panel can also be a multi-quadrant vertical alignment type (VA) or a twisted nematic type (TN), and this disclosure does not limit this.

[0057] Specifically, such as Figure 7 As shown, a planar conversion type (IPS) liquid crystal display panel may include a substrate (Glass) 110, a shield layer (shield) 120, a buffer layer (Buffer) 130, a data line (Date) 210, a first electrode (10), an active layer (320), a second electrode (330), a gate (340), a gate insulating layer (GI) 350, a first passivation layer (PVX1) 410, a resin layer (Resin) 420, a second passivation layer (PVX2) 430, a pixel electrode (Pixel-ITO) 500, and a common electrode (Com-ITO) 600. A shielding layer 120 is disposed on one side of a substrate 110, a data line 210 is formed on one side of a substrate 110, a buffer layer 130 covers the data line 210 and the shielding layer 120 on the substrate 110, an active layer 320 is located on the side of the buffer layer 130 away from the substrate 110, a gate insulating layer 350 is formed on the active layer 320, a first electrode 310 on the gate insulating layer 350 is connected to the data line 210 through a via, a gate electrode 340 is located on the gate insulating layer 350 and is correspondingly disposed with respect to the active layer 320; a first passivation layer 410 covers the gate electrode 340, the first electrode 310 and the gate insulating layer 350, a resin layer 420 is located on the side of the first passivation layer 410 away from the substrate 110, a common electrode 600 is located on the side of the resin layer 420 away from the first passivation layer 410, a second passivation layer 430 covers the common electrode 600 and the resin layer 420, and a pixel electrode 500 is connected to the second electrode 330 in the via.

[0058] In one embodiment, such as Figures 8-12As shown, a pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a first transistor 241, a second transistor 242, and a third transistor 243. The first pixel electrode 510 of the first sub-pixel is connected to the first transistor 241, the second pixel electrode 520 of the second sub-pixel is connected to the second transistor 242, and the third pixel electrode 530 of the third sub-pixel is connected to the third transistor 243. That is, in one pixel unit, the drains of the first transistor 241, the second transistor 242, and the third transistor 243 are connected to the pixel electrodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, in a one-to-one correspondence. The sources of the first transistor 241, the second transistor 242, and the third transistor 243 are connected to the same data line 210. The first sub-pixel, the second sub-pixel, and the third sub-pixel can be one of a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively.

[0059] like Figure 8 , Figure 9 and Figure 11 As shown, the multiple gate lines 220 include a first gate line 221, a second gate line 222, and a third gate line 223. The first gate line 221 is connected to the gate 340 of the first transistor 241, the second gate line 222 is connected to the gate 340 of the second transistor 242, and the third gate line 223 is connected to the gate 340 of the third transistor 243. That is, the gate 340 of the transistor connected to each sub-pixel is connected to a corresponding gate line 220.

[0060] like Figure 8 and Figure 11 As shown, along the column direction, the first gate line 221 and the second gate line 222 are located at the two ends of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the third gate line 223 is located in the middle of the first sub-pixel, the second sub-pixel, and the third sub-pixel; the first gate line 221 is connected to the gate 340 of the first transistor 241, the second gate line 222 is connected to the gate 340 of the second transistor 242, and the third gate line 223 is connected to the gate 340 of the third transistor 243; when there are multiple pixel units in the row direction, the gates 340 of the first transistor 241 corresponding to the first sub-pixel on the same row are all connected to the same first gate line 221, the gates 340 of the second transistor 242 corresponding to the second sub-pixel on the same row are all connected to the same second gate line 222, and the gates 340 of the third transistor 243 corresponding to the third sub-pixel on the same row are all connected to the same third gate line 223.

[0061] In this pixel unit, the first, second, and third sub-pixels are arranged sequentially in the row direction. Two transistors connected to two of the first, second, and third sub-pixels are located at opposite ends of the corresponding sub-pixel in the column direction, while the transistor connected to the other sub-pixel is located in the middle of the corresponding sub-pixel in the column direction. For example... Figure 8 , Figure 11 and Figure 12 As shown, the first sub-pixel, the second sub-pixel, and the third sub-pixel in the pixel unit are arranged sequentially in the row direction. The first transistor 241 and the third transistor 243, which are connected to the first sub-pixel and the third sub-pixel respectively, are located at opposite ends of the corresponding sub-pixel in the column direction. The second transistor 242 is located in the middle part of the corresponding second sub-pixel in the column direction, so that the gate 340 of the first transistor 241 is connected to the first gate line 221, the gate 340 of the second transistor 242 is connected to the second gate line 222, and the gate 340 of the third transistor 243 is connected to the third gate line 223.

[0062] like Figures 12-14 As shown, the connection portions of the pixel electrodes 500 of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all located at the ends of the first sub-pixel, the second sub-pixel, and the third sub-pixel in the column direction. By locating the connection portions of the pixel electrodes 500 of the first sub-pixel, the second sub-pixel, and the third sub-pixel at their ends in the column direction, the black matrix 700, at these ends, needs to simultaneously block the first gate line 221 and the second gate line 222. Therefore, the width of the black matrix 700 in the column direction at these locations is larger, allowing the connection portions of the pixel electrodes 500 of the first sub-pixel, the second sub-pixel, and the third sub-pixel to be completely located below the black matrix 700. This completely blocks the connection portions of the pixel electrodes 500 of the first sub-pixel, the second sub-pixel, and the third sub-pixel, thereby improving liquid crystal efficiency.

[0063] In this configuration, multiple strip electrodes are connected together at one end along the column direction via a connecting portion. For example... Figure 12As shown, the ends of multiple first strip electrodes 511 of the first pixel electrode 510 are connected together by a first connecting portion 512, making the lengths of the multiple first strip electrodes 511 consistent; the ends of multiple second strip electrodes 521 of the second pixel electrode 520 are connected together by a second connecting portion 522, making the lengths of the multiple second strip electrodes 521 consistent; the ends of multiple third strip electrodes 531 of the third pixel electrode 530 are connected together by a third connecting portion 532, making the lengths of the multiple third strip electrodes 531 consistent; the first connecting portion 512, the second connecting portion 522, and the third connecting portion 532 are located on the same side, so that the first connecting portion 512, the second connecting portion 522, and the third connecting portion 532 are located below the wider portion of the black matrix 700, so as to improve the masking effect of the black matrix 700 on the first connecting portion 512, the second connecting portion 522, and the third connecting portion 532. Of course, the first connecting part 512, the second connecting part 522 and the third connecting part 532 may also be located on different sides, and this disclosure does not limit this.

[0064] In another embodiment, such as Figures 15-21 As shown, a pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a first transistor 241, a second transistor 242, and a third transistor 243. The pixel electrode 500 of the first sub-pixel is connected to the first transistor 241, the pixel electrode 500 of the second sub-pixel is connected to the second transistor 242, and the pixel electrode 500 of the third sub-pixel is connected to the third transistor 243. That is, in one pixel unit, the drains of the first transistor 241, the second transistor 242, and the third transistor 243 are connected to the pixel electrodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, in a one-to-one correspondence. The sources of the first transistor 241, the second transistor 242, and the third transistor 243 are connected to the same data line 210. The first sub-pixel, the second sub-pixel, and the third sub-pixel can be one of a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively.

[0065] like Figure 15 , Figure 16 and Figure 18 As shown, the multiple gate lines 220 include a first gate line 221, a second gate line 222, and a third gate line 223. The first gate line 221 is connected to the gate 340 of the first transistor 241, the second gate line 222 is connected to the gate 340 of the second transistor 242, and the third gate line 223 is connected to the gate 340 of the third transistor 243. That is, the gate 340 of the transistor connected to each sub-pixel is connected to a corresponding gate line 220.

[0066] like Figure 15 and Figure 18As shown, along the column direction, the first gate line 221 and the second gate line 222 are located in the middle of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the third gate line 223 is located at the ends of the first sub-pixel, the second sub-pixel, and the third sub-pixel. The first gate line 221 is connected to the gate 340 of the first transistor 241, the second gate line 222 is connected to the gate 340 of the second transistor 242, and the third gate line 223 is connected to the gate 340 of the third transistor 243. When there are multiple pixel units in the row direction, the gates 340 of the first transistors 241 corresponding to the first sub-pixels in the same row are all connected to the same first gate line 221, the gates 340 of the second transistors 242 corresponding to the second sub-pixels in the same row are all connected to the same second gate line 222, and the gates 340 of the third transistors 243 corresponding to the third sub-pixels in the same row are all connected to the same third gate line 223.

[0067] In this pixel unit, the first, second, and third sub-pixels are arranged sequentially in the row direction. The transistor connected to one of the first, second, and third sub-pixels is located at the end of the corresponding sub-pixel in the column direction, while the transistors connected to the other two sub-pixels are located in the middle of the corresponding sub-pixels in the column direction. For example... Figure 15 , Figure 18 and Figure 19 As shown, the first sub-pixel, the second sub-pixel, and the third sub-pixel in the pixel unit are arranged sequentially in the row direction. The first transistor 241 and the second transistor 242, which are connected to the first sub-pixel and the second sub-pixel respectively, are located in the middle part of the corresponding sub-pixel in the column direction. The third transistor 243 is located at the end of the corresponding third sub-pixel in the column direction, so that the gate 340 of the first transistor 241 is connected to the first gate line 221, the gate 340 of the second transistor 242 is connected to the second gate line 222, and the gate 340 of the third transistor 243 is connected to the third gate line 223.

[0068] like Figures 19-21As shown, the connection portions of the pixel electrodes 500 of the first, second, and third sub-pixels are all located in the middle of the first, second, and third sub-pixels in the column direction. By locating the connection portions of the pixel electrodes 500 of the first, second, and third sub-pixels in the middle of the first, second, and third sub-pixels in the column direction, the black matrix 700, located in the middle of the first, second, and third sub-pixels in the column direction, needs to simultaneously block the first gate line 221 and the second gate line 222. Therefore, the width of the black matrix 700 in the column direction at this location is relatively large, allowing the connection portions of the pixel electrodes 500 of the first, second, and third sub-pixels to be completely located below the black matrix 700. This completely blocks the connection portions of the pixel electrodes 500 of the first, second, and third sub-pixels, thereby improving liquid crystal efficiency.

[0069] In this configuration, multiple strip electrodes are connected together at their midpoints along the column direction via a connecting portion. For example... Figure 19 As shown, the middle portions of multiple first strip electrodes 511 of the first pixel electrode 510 are connected together by a first connecting portion 512, making the lengths of the multiple first strip electrodes 511 consistent; the middle portions of multiple second strip electrodes 521 of the second pixel electrode 520 are connected together by a second connecting portion 522, making the lengths of the multiple second strip electrodes 521 consistent; the middle portions of multiple third strip electrodes 531 of the third pixel electrode 530 are connected together by a third connecting portion 532, making the lengths of the multiple third strip electrodes 531 consistent; the first connecting portion 512, the second connecting portion 522, and the third connecting portion 532 are all located in the middle portion of the pixel electrode 500, so that the first connecting portion 512, the second connecting portion 522, and the third connecting portion 532 are located below the wider portion of the black matrix 700, thereby improving the masking effect of the black matrix 700 on the first connecting portion 512, the second connecting portion 522, and the third connecting portion 532. Of course, the first connecting part 512, the second connecting part 522 and the third connecting part 532 may also be located at the end, and this disclosure does not limit this.

[0070] In one embodiment, such as Figure 11 and Figure 18 As shown, the display panel also includes a touch line 230, which extends along the column direction, and a data line 210 is located between two adjacent touch lines 230.

[0071] Embodiments of this disclosure also provide a display device, which includes the aforementioned display panel. The display device may be, for example, a mobile phone, tablet computer, watch, television, electronic device, display panel, advertising screen, or other device with display function; these are not listed here. In the display device provided by this disclosure, one data line of the display panel is simultaneously connected to the second electrode of multiple transistors in a pixel unit. That is, multiple sub-pixels in a pixel unit in the row direction are simultaneously connected through one data line. Therefore, one source driver IC can perform the work of three source driver ICs, increasing the driving speed by up to three times and reducing production costs. Simultaneously, the orthogonal projection of the multiple strip-shaped electrode connection portions in the pixel electrode onto the substrate lies within the orthogonal projection of the black matrix onto the substrate. That is, the black matrix completely blocks the horizontally connected multiple strip-shaped electrode connection portions, improving the liquid crystal efficiency under the same aperture ratio, thereby improving the display effect of the display device. For more beneficial effects of the display device provided by this disclosure, please refer to the discussion in the display panel embodiments; they will not be repeated here.

[0072] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0073] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A display panel, characterized in that, include: An array substrate includes a substrate and a plurality of pixel units disposed on the substrate, a plurality of data lines extending in the column direction and spaced apart in the row direction, and a plurality of gate lines extending in the row direction and spaced apart in the column direction; each pixel unit includes a plurality of sub-pixels and a plurality of transistors, each sub-pixel includes a light-emitting unit and pixel electrodes and a common electrode located on both sides of the light-emitting unit, the first electrode of each transistor is connected to the pixel electrode of each sub-pixel in a one-to-one correspondence; the second electrodes of the plurality of transistors in each pixel unit are connected to the same data line, and the gates of the plurality of transistors in each pixel unit are connected to the plurality of gate lines in a one-to-one correspondence; A color filter substrate includes a black matrix and multiple color filter units, wherein the black matrix has multiple pixel openings, and the multiple color filter units are disposed in the pixel openings one by one; The pixel electrode includes a connecting portion and multiple strip electrodes spaced apart along the row direction. The multiple strip electrodes are connected together through the connecting portion, and the orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the black matrix on the substrate. The pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a first transistor, a second transistor, and a third transistor. The pixel electrode of the first sub-pixel is connected to the first transistor, the pixel electrode of the second sub-pixel is connected to the second transistor, and the pixel electrode of the third sub-pixel is connected to the third transistor. The plurality of gate lines include a first gate line, a second gate line, and a third gate line, wherein the first gate line is connected to the gate of the first transistor, the second gate line is connected to the gate of the second transistor, and the third gate line is connected to the gate of the third transistor; Along the column direction, the first gate line and the second gate line are located at the two ends of the first sub-pixel, the second sub-pixel and the third sub-pixel, and the third gate line is located in the middle of the first sub-pixel, the second sub-pixel and the third sub-pixel.

2. The display panel according to claim 1, characterized in that, The first sub-pixel, the second sub-pixel, and the third sub-pixel in the pixel unit are arranged sequentially in the row direction. Two transistors connected to two sub-pixels of the first sub-pixel, the second sub-pixel, and the third sub-pixel are located at opposite ends of the corresponding sub-pixels in the column direction, and the other transistor is located in the middle of the corresponding sub-pixel in the column direction.

3. The display panel according to claim 2, characterized in that, The connection portions of the pixel electrodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all located at the ends of the first sub-pixel, the second sub-pixel, and the third sub-pixel in the column direction.

4. The display panel according to claim 2, characterized in that, The multiple strip electrodes are connected together at one end in the column direction via the connecting part.

5. A display panel, characterized in that, include: An array substrate includes a substrate and a plurality of pixel units disposed on the substrate, a plurality of data lines extending in the column direction and spaced apart in the row direction, and a plurality of gate lines extending in the row direction and spaced apart in the column direction; each pixel unit includes a plurality of sub-pixels and a plurality of transistors, each sub-pixel includes a light-emitting unit and pixel electrodes and a common electrode located on both sides of the light-emitting unit, the first electrode of each transistor is connected to the pixel electrode of each sub-pixel in a one-to-one correspondence; the second electrodes of the plurality of transistors in each pixel unit are connected to the same data line, and the gates of the plurality of transistors in each pixel unit are connected to the plurality of gate lines in a one-to-one correspondence; A color filter substrate includes a black matrix and multiple color filter units, wherein the black matrix has multiple pixel openings, and the multiple color filter units are disposed in the pixel openings one by one; The pixel electrode includes a connecting portion and multiple strip electrodes spaced apart along the row direction. The multiple strip electrodes are connected together through the connecting portion, and the orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the black matrix on the substrate. The pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a first transistor, a second transistor, and a third transistor. The pixel electrode of the first sub-pixel is connected to the first transistor, the pixel electrode of the second sub-pixel is connected to the second transistor, and the pixel electrode of the third sub-pixel is connected to the third transistor. The plurality of gate lines include a first gate line, a second gate line, and a third gate line, wherein the first gate line is connected to the gate of the first transistor, the second gate line is connected to the gate of the second transistor, and the third gate line is connected to the gate of the third transistor; Wherein, along the column direction, the third gate line is located at one end of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the first gate line and the second gate line are located in the middle of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

6. The display panel according to claim 5, characterized in that, The first sub-pixel, the second sub-pixel, and the third sub-pixel in the pixel unit are arranged sequentially in the row direction. Two transistors connected to two sub-pixels of the first sub-pixel, the second sub-pixel, and the third sub-pixel are located in the middle part of the corresponding sub-pixel in the column direction, and the other transistor is located at the end of the corresponding sub-pixel in the column direction.

7. The display panel according to claim 6, characterized in that, The connection portions of the pixel electrodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all located in the middle of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

8. The display panel according to claim 5, characterized in that, The multiple strip electrodes are connected together at the middle of the column direction via the connecting portion.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 8.

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