一种面向DDR功耗优化的智能控制方法及装置
By pre-training a deep learning model to form an application configuration library, the storage array and mapping address of the DDR memory are adjusted in real time, which solves the problem of DDR power waste in high-performance computer chips and achieves low power optimization and energy efficiency improvement.
CN117421176BActive Publication Date: 2026-07-17NAT UNIV OF DEFENSE TECH
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAT UNIV OF DEFENSE TECH
- Filing Date
- 2023-10-31
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In the prior art, high-performance computer chips suffer from significant power waste in dynamic random access memory (DDR) under different application modes, and mismatched address mapping configurations lead to power waste and inefficiency.
Method used
By pre-training deep learning models to form an application configuration model library, the application status of computer chips is monitored in real time, and the storage array size and mapping address of DDR memory are dynamically adjusted to match the current application requirements and optimize power consumption.
Benefits of technology
Significantly reduces the overall power consumption of computer chips, improves energy efficiency, and optimizes low power consumption to meet the needs of different applications.
✦ Generated by Eureka AI based on patent content.
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Abstract
本发明公开了一种面向DDR功耗优化的智能控制方法及装置，该方法步骤包括：步骤S1：使用训练数据集基于深度学习模型进行预训练，得到不同应用与最优初始存储空间以及最优映射地址之间的应用配置模型库；步骤S2：在计算机芯片运行过程中，实时监测计算机芯片的应用的变化状态；步骤S3：当应用发生变化时，根据当前应用从应用配置模型库中搜索出最优初始存储空间、最优映射地址，如果未搜索到则分配初始存储空间后，搜索出最优映射地址；步骤S4：按照当前搜索出的初始存储空间、最优映射地址配置DDR存储器，返回执行步骤S2直至退出控制。本发明能够实现DDR配置的智能动态控制，优化DDR功耗，提高计算机芯片整体能效。
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