A method and device for designing and using FPGA-oriented soft scan chain

Abstract

The application provides a soft scan chain design and use method and device for FPGA, which comprises the following steps: inserting a flip-flop with the same data bit width as the on-chip memory of a DUT, and setting a control logic module at the read-write port of the flip-flop, and sequentially connecting the flip-flop to form a soft scan chain for the on-chip memory; when the DUT is normally running, the control logic module directly transmits the original address and enable signal to the on-chip memory; when the DUT is suspended, the last-stage on-chip memory RAM of the DUT closest to the output end of the on-chip soft scan chain is used as the current memory RAM; the control logic module of the current memory RAM sends a read command to the current memory RAM, so that the on-chip memory content is scanned through the soft scan chain of the current memory RAM, and the data in the current memory RAM is read out one by one; whether the current memory RAM is the last on-chip memory of the DUT is judged, if yes, the scanning of all the on-chip memories is completed, and all the read-out results are saved as the on-chip memory scanning results.

Description

Technical Field

[0001] This invention relates to the field of accelerated simulation and prototype verification of FPGA-based digital logic design. Background Technology

[0002] FPGAs have become one of the main devices for building digital logic design acceleration simulation and prototyping platforms. To observe and debug the logic behavior of running circuits, it is necessary to accurately read the operating state of the internal logic circuits of the FPGA. Currently, the main methods for reading the state of circuit designs deployed on FPGAs include signal tracing and readback methods. Generally, signal tracing is the fastest and can observe the circuit state in real time, but it has many limitations in practical applications. The number and duration of traceable signals are limited, and the tracing logic consumes a significant amount of FPGA logic resources. The readback method can achieve debugging capabilities where all signals are visible at any time. It introduces the least resource overhead, almost without increasing the FPGA logic usage. However, existing commercial FPGA manufacturers have not fully disclosed the readback data format, and there are differences in readback functionality and readback data format between different manufacturers or different FPGA models, resulting in poor usability and portability of this method.

[0003] Scanchain-based observation and debugging techniques are important methods used in Design for Testability (DFT) of digital logic chips. Essentially, the scanchain method involves replacing or enriching sequential circuit elements (typically D flip-flops, on-chip memory, etc.) in the chip's back-end design with a scanchain circuit based on scanable sequential circuit elements. Through the input / output ports of the scanchain circuit itself, the scanchain can be driven to read the states from each flip-flop and on-chip memory, thereby observing whether the chip is operating normally and determining if there are any problems in the chip's manufacturing process.

[0004] While researching hardware simulation acceleration technology, the inventors discovered that this deficiency stemmed from the inadequacy of current techniques for deriving and importing the states of sequential logic units within FPGAs. Further research revealed that this deficiency could be addressed by drawing upon the scan chain design concept from Design for Testability. By improving the scan chain circuit structure and control mechanism, a method was developed to insert a soft scan chain into the logic design under test (DUT), enabling the acquisition of complete circuit state information of the DUT during FPGA deployment and testing. Summary of the Invention

[0005] This invention employs a method of inserting a soft scan chain into the logic design to obtain all circuit state information of the logic design deployed and running on an FPGA, thereby enabling design debugging. It is important to note that the "soft scan chain" in this invention is not a software / hardware concept, but rather refers to a more flexible form of scan chain in an FPGA, built upon programmable resources, compared to the scan chain fixed in ASIC chip fabrication. Unlike the hard scan chain circuit inserted in design for test, the soft scan chain is built along with the design under test (DUT) based on the on-chip programmable logic resources of the FPGA, and its structure is adjusted according to changes in the DUT. With the increasing scale and complexity of digital circuits, the number of flip-flops and on-chip memory used in the design circuit has also increased significantly. How to adopt a suitable soft scan chain structure that ensures the acquisition of all timing circuit states of the DUT while minimizing the logic resource overhead introduced by inserting the soft scan chain has become a key technical problem.

[0006] Specifically, this invention proposes a method for designing and using a soft scan chain for FPGAs, including:

[0007] Step 1 is used to obtain the FPGA with the Design Under Test (DUT). For each on-chip memory of the DUT, a number of flip-flops with the same data bit width are inserted, and control logic modules are set at its read and write ports. These are then connected in series to form the first soft scan chain facing the on-chip memory.

[0008] Step 2: When the DUT is running normally, the control logic module directly connects the original address and enable signal to the on-chip memory; by turning off the clock of other circuits except for the scan chain itself and the on-chip memory RAM, the DUT is put into a pause state. When the DUT is paused, the first-level on-chip memory RAM in the DUT that is closest to the output of the first soft scan chain is used as the current memory RAM.

[0009] Step 3: The control logic module of the current memory RAM issues a read command to the current memory RAM to scan the on-chip memory contents through the first soft scan chain of the current memory RAM and read out the data in the current memory RAM one by one;

[0010] Step 4 is used to determine whether the current RAM is the last on-chip memory of the DUT. If so, the scanning of all on-chip memory is completed, and all read results are saved as the on-chip memory scan results. Otherwise, the next RAM is used as the current RAM and Step 3 is executed again.

[0011] The aforementioned method for designing and using a soft scan chain for FPGAs includes:

[0012] Step 5: Insert selectors into each on-chip memory of the DUT to control whether the data input to the on-chip memory is the raw input data when the DUT is running normally or the scan input signal when it is paused.

[0013] When the DUT is paused, data is input through the first soft scan chain. When the data of the first word of the last on-chip memory of the DUT reaches its corresponding trigger position, the recovery process is started and the data is written into the on-chip memory. When writing the last word, data is input into the previous on-chip memory of the current on-chip memory until the recovery of all on-chip memory of the DUT is completed.

[0014] The described method for designing and using a soft scan chain for FPGAs includes step 6:

[0015] Replace the clock port of the flip-flop in the DUT with a dedicated clock signal; add additional logic gates to the reset port RST and enable port E of the flip-flop in the DUT, controlled by the scan enable signal FF_SE. During the scan process, the enable signal is always valid, and the reset signal of the flip-flop is always invalid.

[0016] The flip-flops in the DUT are connected in series from beginning to end to form a second soft scan chain oriented towards the flip-flops. This includes inserting a two-way data selector into the D port of each flip-flop, one channel connected to the original input signal and the other channel used as the scan input. The Q terminal of each flip-flop is connected to the data selector input of the next flip-flop with the next number in sequence to construct the complete second soft scan chain. The scan input of the first flip-flop is used as the input of the second soft scan chain, and the Q terminal of the last flip-flop is used as the output of the second soft scan chain.

[0017] When saving the flip-flop state, the scan enable signal FF_SE is pulled high, and the clock signal is controlled to toggle. After each clock cycle, the internal data of the flip-flops on the second soft scan chain is transferred to the next flip-flop until the data of each flip-flop is exported from the output of the second soft scan chain, thus completing the saving of the flip-flop state.

[0018] The aforementioned soft scan chain design and usage method for FPGA includes, in step 2, the original address and enable signals as follows: address signal for reading data from memory, memory read enable signal, memory write enable signal, and address signal for writing data to memory.

[0019] This invention also proposes a design and usage apparatus for a soft scan chain for FPGAs, including:

[0020] Module 1 is used to acquire the FPGA with the Design Under Test (DUT). For each on-chip memory of the DUT, a number of flip-flops with the same data bit width are inserted, and control logic modules are set at its read and write ports. These modules are then connected in series to form the first soft scan chain facing the on-chip memory.

[0021] Module 2 is used to control the control logic module to pass the original address and enable signal directly to the on-chip memory when the DUT is running normally; by turning off the clock of other circuits except for the scan chain itself and the on-chip memory RAM, the DUT is put into a pause state. When the DUT is paused, the first-level on-chip memory RAM in the DUT that is closest to the output of the first soft scan chain is used as the current memory RAM.

[0022] Module 3 is used to control the control logic module of the current memory RAM to issue a read command to the current memory RAM, so as to scan the on-chip memory contents through the first soft scan chain of the current memory RAM and read out the data in the current memory RAM one by one;

[0023] Module 4 is used to determine whether the current RAM is the last on-chip memory of the DUT. If so, the scan of all on-chip memory is completed and all read results are saved as the on-chip memory scan results. Otherwise, the next RAM is used as the current RAM and module 3 is called again.

[0024] The aforementioned soft scan chain design and usage apparatus for FPGAs includes:

[0025] Module 5 is used to insert selectors into each on-chip memory of the DUT to control the data input to the on-chip memory as the raw input data when the DUT is running normally or the scan input signal when it is paused.

[0026] When the DUT is paused, data is input through the first soft scan chain. When the data of the first word of the last on-chip memory of the DUT reaches its corresponding trigger position, the recovery process is started and the data is written into the on-chip memory. When writing the last word, data is input into the previous on-chip memory of the current on-chip memory until the recovery of all on-chip memory of the DUT is completed.

[0027] The aforementioned soft scan chain design and usage device for FPGA includes module 6:

[0028] Used to replace the clock port of the flip-flop in the DUT with a dedicated clock signal; additional logic gates are added to the reset port RST and enable port E of the flip-flop in the DUT, controlled by the scan enable signal FF_SE. During the scan process, the enable signal is always valid, and the reset signal of the flip-flop is always invalid.

[0029] The flip-flops in the DUT are connected in series from beginning to end to form a second soft scan chain oriented towards the flip-flops. This includes inserting a two-way data selector into the D port of each flip-flop, one channel connected to the original input signal and the other channel used as the scan input. The Q terminal of each flip-flop is connected to the data selector input of the next flip-flop with the next number in sequence to construct the complete second soft scan chain. The scan input of the first flip-flop is used as the input of the second soft scan chain, and the Q terminal of the last flip-flop is used as the output of the second soft scan chain.

[0030] When saving the flip-flop state, the scan enable signal FF_SE is pulled high, and the clock signal is controlled to toggle. After each clock cycle, the internal data of the flip-flops on the second soft scan chain is transferred to the next flip-flop until the data of each flip-flop is exported from the output of the second soft scan chain, thus completing the saving of the flip-flop state.

[0031] The aforementioned soft scan chain design and usage device for FPGA includes, in module 2, the original address and enable signals as follows: an address signal for reading data from memory, a memory read enable signal, a memory write enable signal, and an address signal for writing data to memory.

[0032] The present invention also proposes a server, including the aforementioned soft scan chain design and usage device for FPGA.

[0033] The present invention also proposes a storage medium for storing the computer program of the FPGA-oriented soft scan chain design and usage method.

[0034] As can be seen from the above solutions, the advantages of the present invention are:

[0035] This invention proposes targeted scan chain design methods and devices for two typical sequential logic units in FPGAs (D flip-flops and on-chip memory). Compared with signal tracing and readback methods, this invention sets up a soft scan chain using resources other than the Design Under Test (DUT) within the FPGA. Therefore, the soft scan chain method of this invention is highly versatile, requiring no consideration of the specific implementation details of the FPGA device, and is a cross-platform debugging method with good portability and scalability. Attached Figure Description

[0036] Figure 1 A schematic diagram of the on-chip memory structure before the insertion of the soft scan chain;

[0037] Figure 2 This is a schematic diagram of the on-chip memory structure after the soft scan chain is inserted.

[0038] Figure 3 A schematic diagram illustrating the replacement of the on-chip memory clock structure using a gated clock method;

[0039] Figure 4 A diagram illustrating the data saving process;

[0040] Figure 5 This is a diagram of the data recovery process;

[0041] Figure 6 A schematic diagram of the trigger structure before the soft scan chain is inserted;

[0042] Figure 7 This is a schematic diagram of the trigger structure after the soft scan chain is inserted. Detailed Implementation

[0043] This invention proposes a soft scan chain design method and apparatus for FPGAs, specifically a soft scan chain mechanism for saving and restoring the states of on-chip memory and flip-flop circuits. Addressing the shortcomings of traditional soft scan chain structures in handling FPGA on-chip memory, this invention proposes a soft scan chain structure for on-chip memory and provides a runtime control method. Furthermore, an optimized soft scan chain structure is proposed for flip-flops, which uses an independent clock to prevent interference with on-chip memory scanning, and the soft scan chain circuitry is optimized to shield against accidental reset signal disturbances.

[0044] This invention first addresses the problem of existing soft scan chain methods being unable to efficiently export and import internal data states from multiple on-chip memories simultaneously. It improves the circuit structure of the on-chip memory soft scan chain by proposing a circuit structure that effectively reduces the overhead of the soft scan chain's input and output port control logic, thus lowering the control difficulty of acquiring or recovering the target design's on-chip memory data through the scan chain. Then, it proposes an optimized soft scan chain structure for flip-flops. By setting a clock gating signal independent of the on-chip memory scan chain, it ensures that the scan does not interfere with the on-chip memory scan. Finally, it optimizes the soft scan chain circuit to shield against accidental reset signal disturbances.

[0045] For scan chains oriented towards flip-flops, this invention adds some combinational logic components around the original ordinary flip-flops, "replacing" them with scan chain flip-flops, and cascading them together as a whole, such as... Figure 7 As shown in the diagram. In this scenario, no new triggers are added; instead, the existing triggers in the Design Under Test (DUT) are enriched. The DUT can be part of the FPGA. For scan chains targeting on-chip memory (on-chip storage), such as... Figure 2 , Figure 3 As shown, the technical concept of this invention is to add a new flip-flop to the periphery of the RAM and reconstruct a set of scan chain logic.

[0046] To achieve the above-mentioned technical effects, the present invention includes two key points: key point 1 is a soft scan chain structure and method for on-chip memory, and key point 2 is a soft scan chain structure and method for triggers.

[0047] Key point 1 is to read the data in the on-chip memory one by one to the scan trigger or write it to the scan trigger, and to connect the scan triggers in series to form a soft scan chain to realize the serial export and import of data;

[0048] Compared to the traditional approach of inserting an independent soft scan chain into each on-chip memory, the method and apparatus described in this invention allow on-chip memories with different data bit widths and sizes in the same clock domain to be connected in series into a soft scan chain. It does not require exposing an access interface for each on-chip memory separately, nor does it require external control of each on-chip memory separately, which can significantly reduce the input and output port overhead of the soft scan chain.

[0049] Key Point 2: The method and apparatus described in this invention provide a soft scan chain structure and insertion method for flip-flops. The soft scan chain for flip-flops described in this invention has three characteristics: First, the scan chain directly inserts a 2-to-1 data selector at the D terminal of each flip-flop in the original design and connects all flip-flops sequentially, eliminating the need to insert a shadow flip-flop for each flip-flop in the original design. This effectively saves register resources in the FPGA deployment of the logic circuit after the scan chain is inserted. Second, the soft scan chain for flip-flops and the on-chip memory scan chain are controlled by different clocks. This separates the scan process for flip-flops from the on-chip memory scan process described in Key Point 1, preventing mutual interference. Third, an AND gate connected to the enable signal is designed at the asynchronous reset terminal of the flip-flops. This simultaneously shields against interference signals that may be accidentally transmitted to the reset port when entering the scan state.

[0050] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.

[0051] On-chip memory is addressable on-chip memory with complete read and write ports. Each set of read or write ports includes address, enable, and data ports. Data interaction can occur once per clock cycle with the location specified by the address signal. Address and data ports often have multiple bits. The address width WA allows the on-chip memory to have up to 2^WA locations for storing data. Each location is called a word, and the word length is equal to the data port width WD. During the insertion of the soft scan chain, the method and apparatus described in this invention only consider one set of read and write ports for each on-chip memory. The enable ports of the remaining ports are inserted into the control logic to ensure they do not operate during the scan. The descriptions of the on-chip memory ports are shown in Table 1.

[0052] Table 1: Port List of On-Chip Memory

[0053]

[0054] On-chip memory can only read and write data to one location per cycle, unlike flip-flop circuits which can perform a scan operation directly within a single clock cycle using a traditional soft scan chain. The method and apparatus described in this invention read data from the on-chip memory one by one into or write data from the flip-flops, and then connect these flip-flops in series to form a soft scan chain for data export and import. This approach allows on-chip memory modules with different data widths and sizes but within the same clock domain to be connected in series into a single soft scan chain, eliminating the need to expose a separate access interface for each memory module and avoiding significant overhead.

[0055] Therefore, in this invention, each memory location does not correspond to just one trigger; rather, the number of triggers is determined based on the data width of each memory location. For example... Figure 2 As shown, when the data width of a RAM is [Wx-1:0], which is Wx bit width, its corresponding scan chain segment requires Wx cascaded flip-flops.

[0056] Structure of the device described in this invention:

[0057] The on-chip memory circuit structures before and after inserting the soft scan chain are as follows: Figure 1 and Figure 2 As shown. For each on-chip memory in the DUT circuit, a control logic module (such as...) needs to be inserted into the address and enable signal of the read / write port. Figure 2(CTRL section in the code). The internal control logic module mainly includes an address generation and memory access control submodule and a scan completion indication submodule. During normal DUT operation, the control logic module directly connects the original address and enable signal to the on-chip memory port. During save and restore processes, it masks DUT signals (original address and enable signals). The address generation and memory access control submodule issues read and write commands to scan the on-chip memory content. Simultaneously, the scan completion indication submodule outputs a LAST signal to instruct the next level control logic to start scanning. The control logic is serially connected via the LAST indication signal line. Saving refers to scanning and reading the state of each timing unit in the DUT using the scan chain. This process erases the original state information in the DUT. Therefore, in order for the DUT to continue operating after the scan is completed, a restore process is also required, that is, writing the original state back to the DUT.

[0058] Optional, such as Figure 3 The inserted clock gate shown is an optional method for switching RAM_CLK, switching to a unique clock during scan chain operation. The purpose of setting an independent clock is to allow the scan flip-flop and on-chip memory processes to use specific clock frequencies independently, without interference. The clock signal can be replaced with a separate RAM_CLK, and the inserted clock gate method can be used to process the original operating clock. During normal operation of the DUT, the clocks of both the flip-flop circuits and the on-chip memory circuits are enabled; when entering on-chip memory scan mode, only the corresponding clock RAM_CLK is enabled, while the clocks of the rest of the circuits are masked to ensure their state remains unchanged, allowing the on-chip memory circuits to be driven independently during the scan process.

[0059] Next, the on-chip memory read / write data ports will be modified. Similar to the classic flip-flop soft scan chain structure, a selector will be inserted into the on-chip memory write data port. The scan enable signal RAM_SE controls whether to select the raw input signal or the scan input signal. Since read / write data ports are often multi-bit, a soft scan chain is formed for each on-chip memory segment, with a number of flip-flops equal to its data bit width inserted. Each bit of the read data port is connected to the flip-flop scan input port, and the flip-flop outputs are aggregated and connected to the on-chip memory scan input port. Data from the on-chip memory is then transferred bit by bit along the soft scan chain.

[0060] The method described in this invention:

[0061] 1. The specific operation steps during on-chip memory data saving are as follows: Figure 4 As shown, and in combination Figure 2 , 3 The circuit structure of the scan chain shown is explained below:

[0062] 1.1 First, enable the RAM_CLK clock and disable the clocks of all circuits except the scan chain itself and the on-chip RAM, putting the DUT into a paused state. Its internal sequential logic units, such as flip-flops, will no longer change. The scan chain circuit then enters the working state.

[0063] 1.2 Startup Figure 2 , 3 The process of saving the rightmost on-chip memory RAM (RAM_SDO closest to the output terminal, i.e., number k=1) is shown. The address is incremented until all addresses of number k=1 RAM are traversed, and the data in it is read out one by one.

[0064] 1.3 such as Figure 2 , 3 As shown, each end of the soft scan chain has an input LAST signal terminal and an output LAST signal terminal. Each control logic CTRL in the middle section has an input LAST signal terminal and an output LAST signal terminal. When the last word is scanned (read), the control logic CTRL will issue a LAST signal to start the saving process of the previous on-chip memory. When the last word of the on-chip memory is scanned, it will issue a LAST signal to the previous one (i.e., k = k + 1). This process is repeated iteratively, scanning each RAM one by one, until k = N, completing the scanning of all on-chip memory.

[0065] 2. The specific steps for on-chip memory data recovery are as follows: Figure 5 As shown, and in combination Figure 2 , 3 The circuit structure of the scan chain shown is explained below:

[0066] 2.1 First, enable the RAM_CLK clock and disable the clocks of all circuits except the scan chain itself and the on-chip RAM, putting the DUT into a paused state. Its internal sequential logic units, such as flip-flops, will no longer change. The scan chain circuit then enters the working state.

[0067] 2.2 Data is first input via a soft scan chain. When the data of the first word of the last on-chip memory reaches its corresponding trigger position, the recovery process is initiated, and the data is written to it. Similarly, when scanning the last word, CTRL issues a LAST signal to begin recovering the previous on-chip memory. This process is repeated until all on-chip memory is recovered. Data recovery can essentially be considered the reverse process of data saving.

[0068] It should be noted that the apparatus and method described in this invention are applicable to all types of on-chip memory, including but not limited to single-port / dual-port RAM, distributed / block RAM, and other on-chip memory with various technical features. For dual-port RAM, either of the two sets of memory access interfaces can be selected to perform a scanning operation using the apparatus and method described in this invention.

[0069] For flip-flops in logic circuits (such as Figure 6 The first step is to handle the clock, reset, and enable ports. The clock port is replaced with a dedicated signal FF_CLK to allow for separate scanning from on-chip memory. Additional logic gates are added to the reset port RST and enable port E, controlled by the scan enable signal FF_SE. During the scan, the enable signal remains active, while the reset signal of the flip-flop remains inactive. This shields the flip-flop from potential reset signal disturbances during the scan, ensuring a stable output value from the Q terminal of the flip-flop in each cycle and receiving a new value from the D terminal.

[0070] Each flip-flop in the circuit is numbered and added to the soft scan chain in numerical order. First, a two-way data selector is inserted into the D port of each flip-flop; one path connects to the existing input signal, and the other serves as the scan input. Then, the Q input of each flip-flop is connected to the data selector input of the next flip-flop with that number in numerical order, constructing a complete soft scan chain. The scan input of the first flip-flop serves as the input of the soft scan chain (FF_SDI), and the Q input of the last flip-flop serves as the output of the soft scan chain (FF_SDO). The structure is as follows: Figure 7 As shown. Saving the flip-flop state requires pulling the scan enable signal FF_SE high and toggling the clock signal FF_CLK. Each clock cycle, the internal data of the flip-flops in the soft scan chain is transferred to the next flip-flop. Over time, the data of each flip-flop is exported from FF_SDO, thus completing the state saving. It's important to note that this process can corrupt the internal state of the flip-flops. Therefore, the data output from FF_SDO each cycle must be simultaneously input into FF_SDI. After the scan process ends, each flip-flop will be filled back with its original data, ensuring that the flip-flop state remains unchanged before and after saving. The process of restoring the state is the same as saving; simply input the data to be restored from FF_SDI, ignoring the output of FF_SDO.

[0071] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0072] This invention also proposes a design and usage apparatus for a soft scan chain for FPGAs, including:

[0073] Module 1 is used to acquire the FPGA with the Design Under Test (DUT). For each on-chip memory of the DUT, a number of flip-flops with the same data bit width are inserted, and control logic modules are set at its read and write ports. These modules are then connected in series to form the first soft scan chain facing the on-chip memory.

[0074] Module 2 is used to control the control logic module to pass the original address and enable signal directly to the on-chip memory when the DUT is running normally; by turning off the clock of other circuits except for the scan chain itself and the on-chip memory RAM, the DUT is put into a pause state. When the DUT is paused, the first-level on-chip memory RAM in the DUT that is closest to the output of the first soft scan chain is used as the current memory RAM.

[0075] Module 3 is used to control the control logic module of the current memory RAM to issue a read command to the current memory RAM, so as to scan the on-chip memory contents through the first soft scan chain of the current memory RAM and read out the data in the current memory RAM one by one;

[0076] Module 4 is used to determine whether the current RAM is the last on-chip memory of the DUT. If so, the scan of all on-chip memory is completed and all read results are saved as the on-chip memory scan results. Otherwise, the next RAM is used as the current RAM and module 3 is called again.

[0077] The aforementioned soft scan chain design and usage apparatus for FPGAs includes:

[0078] Module 5 is used to insert selectors into each on-chip memory of the DUT to control whether the data input to the on-chip memory is the raw input data when the DUT is running normally or the scan input signal when it is paused.

[0079] When the DUT is paused, data is input through the first soft scan chain. When the data of the first word of the last on-chip memory of the DUT reaches its corresponding trigger position, the recovery process is started and the data is written into the on-chip memory. When writing the last word, data is input into the previous on-chip memory of the current on-chip memory until the recovery of all on-chip memory of the DUT is completed.

[0080] The aforementioned soft scan chain design and usage device for FPGA includes module 6:

[0081] Used to replace the clock port of the flip-flop in the DUT with a dedicated clock signal; additional logic gates are added to the reset port RST and enable port E of the flip-flop in the DUT, controlled by the scan enable signal FF_SE. During the scan process, the enable signal is always valid, and the reset signal of the flip-flop is always invalid.

[0082] The flip-flops in the DUT are connected in series from beginning to end to form a second soft scan chain oriented towards the flip-flops. This includes inserting a two-way data selector into the D port of each flip-flop, one channel connected to the original input signal and the other channel used as the scan input. The Q terminal of each flip-flop is connected to the data selector input of the next flip-flop with the next number in sequence to construct the complete second soft scan chain. The scan input of the first flip-flop is used as the input of the second soft scan chain, and the Q terminal of the last flip-flop is used as the output of the second soft scan chain.

[0083] When saving the flip-flop state, the scan enable signal FF_SE is pulled high, and the clock signal is controlled to toggle. After each clock cycle, the internal data of the flip-flops on the second soft scan chain is transferred to the next flip-flop until the data of each flip-flop is exported from the output of the second soft scan chain, thus completing the saving of the flip-flop state.

[0084] The aforementioned soft scan chain design and usage device for FPGA includes, in module 2, the original address and enable signals as follows: an address signal for reading data from memory, a memory read enable signal, a memory write enable signal, and an address signal for writing data to memory.

[0085] The present invention also proposes a server, including the aforementioned soft scan chain design and usage device for FPGA.

[0086] The present invention also proposes a storage medium for storing the computer program of the FPGA-oriented soft scan chain design and usage method.

[0087] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A method for designing and using a soft scan chain for FPGAs, characterized in that, include: Step 1 is used to obtain the FPGA with the Design Under Test (DUT). For each on-chip memory of the DUT, a number of flip-flops with the same data bit width are inserted, and control logic modules are set at its read and write ports. These are then connected in series to form the first soft scan chain facing the on-chip memory. Step 2: When the DUT is running normally, the control logic module directly connects the original address and enable signal to the on-chip memory; by turning off the clock of other circuits except for the scan chain itself and the on-chip memory RAM, the DUT is put into a pause state. When the DUT is paused, the first-level on-chip memory RAM in the DUT that is closest to the output of the first soft scan chain is used as the current memory RAM. Step 3: The control logic module of the current memory RAM issues a read command to the current memory RAM to scan the on-chip memory contents through the first soft scan chain of the current memory RAM and read out the data in the current memory RAM one by one; Step 4 is used to determine whether the current RAM is the last on-chip memory of the DUT. If so, the scanning of all on-chip memory is completed, and all read results are saved as the on-chip memory scan results. Otherwise, the next RAM is used as the current RAM and Step 3 is executed again.

2. The method for designing and using a soft scan chain for FPGAs as described in claim 1, characterized in that, include: Step 5: Insert selectors into each on-chip memory of the DUT to control whether the data input to the on-chip memory is the raw input data when the DUT is running normally or the scan input signal when it is paused. When the DUT is paused, data is input through the first soft scan chain. When the data of the first word of the last on-chip memory of the DUT reaches its corresponding trigger position, the recovery process is started and the data is written into the on-chip memory. When writing the last word, data is input into the previous on-chip memory of the current on-chip memory until the recovery of all on-chip memory of the DUT is completed.

3. The method for designing and using a soft scan chain for FPGAs as described in claim 1, characterized in that, Including step 6: Replace the clock port of the flip-flop in the DUT with a dedicated clock signal; add additional logic gates to the reset port RST and enable port E of the flip-flop in the DUT, controlled by the scan enable signal FF_SE. During the scan process, the enable signal is always valid, and the reset signal of the flip-flop is always invalid. The flip-flops in the DUT are connected in series from beginning to end to form a second soft scan chain oriented towards the flip-flops. This includes inserting a two-way data selector into the D port of each flip-flop, one channel connected to the original input signal and the other channel used as the scan input. The Q terminal of each flip-flop is connected to the data selector input of the next flip-flop with the next number in sequence to construct the complete second soft scan chain. The scan input of the first flip-flop is used as the input of the second soft scan chain, and the Q terminal of the last flip-flop is used as the output of the second soft scan chain. When saving the flip-flop state, the scan enable signal FF_SE is pulled high, and the clock signal is controlled to toggle. After each clock cycle, the internal data of the flip-flops on the second soft scan chain is transferred to the next flip-flop until the data of each flip-flop is exported from the output of the second soft scan chain, thus completing the saving of the flip-flop state.

4. The method for designing and using a soft scan chain for FPGAs as described in claim 1, characterized in that, In step 2, the original address and enable signals include: the address signal for reading data from memory, the memory read enable signal, the memory write enable signal, and the address signal for writing data to memory.

5. A design and application apparatus for a soft scan chain for FPGAs, characterized in that, include: Module 1 is used to acquire the FPGA with the Design Under Test (DUT). For each on-chip memory of the DUT, a number of flip-flops with the same data bit width are inserted, and control logic modules are set at its read and write ports. These modules are then connected in series to form the first soft scan chain facing the on-chip memory. Module 2 is used to control the control logic module to pass the original address and enable signal directly to the on-chip memory when the DUT is running normally; by turning off the clock of other circuits except for the scan chain itself and the on-chip memory RAM, the DUT is put into a pause state. When the DUT is paused, the first-level on-chip memory RAM in the DUT that is closest to the output of the first soft scan chain is used as the current memory RAM. Module 3 is used to control the control logic module of the current memory RAM to issue a read command to the current memory RAM, so as to scan the on-chip memory contents through the first soft scan chain of the current memory RAM and read out the data in the current memory RAM one by one; Module 4 is used to determine whether the current RAM is the last on-chip memory of the DUT. If so, the scan of all on-chip memory is completed and all read results are saved as the on-chip memory scan results. Otherwise, the next RAM is used as the current RAM and module 3 is called again.

6. The apparatus for designing and using a soft scan chain for FPGAs as described in claim 5, characterized in that, include: Module 5 is used to insert selectors into each on-chip memory of the DUT to control whether the data input to the on-chip memory is the raw input data when the DUT is running normally or the scan input signal when it is paused. When the DUT is paused, data is input through the first soft scan chain. When the data of the first word of the last on-chip memory of the DUT reaches its corresponding trigger position, the recovery process is started and the data is written into the on-chip memory. When writing the last word, data is input into the previous on-chip memory of the current on-chip memory until the recovery of all on-chip memory of the DUT is completed.

7. The apparatus for designing and using a soft scan chain for FPGAs as described in claim 5, characterized in that, Includes module 6: Used to replace the clock port of the flip-flop in the DUT with a dedicated clock signal; additional logic gates are added to the reset port RST and enable port E of the flip-flop in the DUT, controlled by the scan enable signal FF_SE. During the scan process, the enable signal is always valid, and the reset signal of the flip-flop is always invalid. The flip-flops in the DUT are connected in series from beginning to end to form a second soft scan chain oriented towards the flip-flops. This includes inserting a two-way data selector into the D port of each flip-flop, one channel connected to the original input signal and the other channel used as the scan input. The Q terminal of each flip-flop is connected to the data selector input of the next flip-flop with the next number in sequence to construct the complete second soft scan chain. The scan input of the first flip-flop is used as the input of the second soft scan chain, and the Q terminal of the last flip-flop is used as the output of the second soft scan chain. When saving the flip-flop state, the scan enable signal FF_SE is pulled high, and the clock signal is controlled to toggle. After each clock cycle, the internal data of the flip-flops on the second soft scan chain is transferred to the next flip-flop until the data of each flip-flop is exported from the output of the second soft scan chain, thus completing the saving of the flip-flop state.

8. The apparatus for designing and using a soft scan chain for FPGAs as described in claim 5, characterized in that, The original address and enable signals of module 2 include: an address signal for reading data from memory, a memory read enable signal, a memory write enable signal, and an address signal for writing data to memory.

9. A server, characterized in that, Includes the soft scan chain design and usage apparatus for FPGA as described in any one of claims 5-8.

10. A storage medium for storing a computer program that executes the method for designing and using a soft scan chain for an FPGA as described in any one of claims 1-4.

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