A data bundle-based asynchronous circuit control chain timing constraint analysis method

Abstract

The application discloses a kind of asynchronous circuit control chain timing constraint analysis methods based on data bundling, this method includes: two-phase data bundling asynchronous handshake structure is extended to LCM module and PLCM module processing, output the local clock signal after extension;The local clock signal after extension is analyzed by timing constraint analysis method, and the local clock signal after constraint is obtained;According to the local clock signal after constraint, comprehensive and generate timing report, and according to timing report, evaluation feedback is carried out, and the optimal asynchronous circuit control chain is built.The control chain of 2-phase data bundling asynchronous template built by the application is timed, and then the control chain capable of outputting accurate control delay is obtained.The application can be widely applied to integrated circuit design technical field as a kind of asynchronous circuit control chain timing constraint analysis methods based on data bundling.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a method for timing constraint analysis of asynchronous circuit control chains based on data bundling. Background Technology

[0002] With the continuous development of the integrated circuit field and the increasing scale of designs, the "power wall" and "memory" problems have become increasingly prominent. For example, fields such as IoT chips and neural network chip design have placed new demands on low-power design, making the design of processor chips with low-power characteristics a top priority for many emerging applications. Against this backdrop, asynchronous circuits have gained favor among designers due to their low power consumption, absence of clock skew, and event-driven characteristics. Both industry and academia are exploring asynchronous circuits as a method for achieving low-power design. From an industry perspective, some fields have already experimented with asynchronous circuits and produced commercial products based on asynchronous circuit technology.

[0003] Two-phase bundled-data (BD) asynchronous circuits have gained widespread attention due to their area being similar to synchronous circuits and their ability to achieve rapid transitions from synchronous to asynchronous operation via asynchronous handshake templates. This type of asynchronous circuit features simple handshake template structures and flexible construction methods. These handshake templates function by forming an asynchronous control chain through handshake signals. Each handshake structure generates a local clock to drive the operation of various asynchronous modules. Therefore, the asynchronous control chain and its generated control signals (i.e., local clocks at each stage) are crucial in the design. However, current design methods do not constrain or analyze the control chain. This results in poor matching between the control chain, local clocks, and various asynchronous modules, potentially leading to poor signal quality, performance loss, or even data flow control failure. Furthermore, existing asynchronous circuit control methods set the asynchronous control signals (i.e., local clocks) through instructions, declaring the level width of different local clocks and the phase relationship between each stage. Essentially, this work involves setting an ideal virtual asynchronous control chain in the EDA tool, which then synthesizes a suitable asynchronous module based on this ideal condition. The control chain itself is not prioritized during synthesis, leading to deviations between the final control chain and the ideal situation. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention aims to provide a timing constraint analysis method for asynchronous circuit control chains based on data bundling. By applying timing constraints to the control chain constructed using a two-phase data-bundled asynchronous template, a control chain capable of outputting accurate control delay quantities can be obtained.

[0005] The first technical solution adopted in this invention is: a timing constraint analysis method for asynchronous circuit control chains based on data bundling, comprising the following steps:

[0006] The asynchronous handshake structure with two-phase data binding is extended by the LCM module and the PLACM module to output the extended local clock signal.

[0007] The extended local clock signal is constrained by a timing constraint analysis method to obtain a constrained local clock signal. The constraint analysis includes constrain analysis of the local clock signal at the current level and constrain analysis of the local clock signals at the upper and lower levels. The constrained local clock signal includes the local clock signal constrained at the current level and the local clock signals constrained at the upper and lower levels.

[0008] Based on the constrained local clock signal, a timing report is generated and evaluated, and the optimal asynchronous circuit control chain is constructed.

[0009] Furthermore, the asynchronous handshake structure for two-phase data bundling includes a handshake combinational logic module, a phase unit, an Out_Req signal port, an Out_Ack signal port, a local clock signal port, an In_Req signal port, and an In_Ack signal port, wherein:

[0010] The handshake combinational logic module is responsible for handshake signal processing;

[0011] The phase unit is responsible for recording the handshake state and breaking the loop in timing to generate a trigger signal;

[0012] The Out_Req signal port is used to send a request signal to the lower-level handshake structure;

[0013] The Out_Ack signal port is used to send an acknowledgment signal to the upper-level handshake structure.

[0014] The local clock signal port is used to generate a local clock signal for handshaking, which drives the asynchronous module.

[0015] The In_Req signal port is used to receive request signals sent by the upper-level handshake structure;

[0016] The In_Ack signal port is used to receive the response signal sent by the lower-level handshake structure.

[0017] Furthermore, the step of extending the asynchronous handshake structure of the two-phase data binding using the LCM and PLACM modules to output the extended local clock signal specifically includes:

[0018] Based on the asynchronous handshake structure of the two-phase data binding, an LCM module is inserted to extend and delay the level width of the local clock signal of the asynchronous handshake structure of the two-phase data binding, so as to obtain a preliminary extended local clock signal.

[0019] Insert a PLCM module to adjust the phase information of the local clock signal of the asynchronous handshake structure of the two-phase data binding, and output the extended local clock signal.

[0020] Furthermore, the trigger signal generated by the phase unit includes a first signal and a second signal. The first signal serves as a request signal and a response signal and is transmitted to the upper-level asynchronous handshake structure and the lower-level asynchronous handshake structure through a first path. The second signal is transmitted to the handshake combinational logic module through a second path to continue the handshake processing.

[0021] Furthermore, the LCM module is used to extend the level width of the local clock signal without affecting the phase information of the local clock signal, and the PLCM module is used to extend the level width of the local clock signal and automatically balance the phase delay between local clock signals.

[0022] Furthermore, the PLCM module is inserted at the first path, and the LCM module is inserted at the second path.

[0023] Furthermore, the step of local clock signal constraint analysis at this level specifically includes:

[0024] Define the local path of the asynchronous handshake structure of the two-phase data binding, wherein the local path is phase unit - handshake combinational logic module - local clock signal port;

[0025] The total path delay at this level is obtained by constraining the path at this level using the set_max_delay and set_min_delay instructions.

[0026] Based on the EDA tool, the total path delay of this level is analyzed to obtain the constrained local clock signal of this level.

[0027] Furthermore, the step of constraining and analyzing the upper and lower level local clock signals specifically includes:

[0028] Define the upper and lower level paths of the asynchronous handshake structure of the two-phase data binding, wherein the upper and lower level paths are: phase unit of this level - local clock signal port of this level - handshake combinational logic module of the upper level or handshake combinational logic module of the lower level - local clock signal port of the upper level or local clock signal port of the lower level.

[0029] The set_max_delay and set_min_delay instructions are used to constrain the upper and lower level paths to obtain the total path delay of the upper and lower levels.

[0030] The total path delay of the upper and lower levels is analyzed by the report_timing instruction to obtain the local clock signal after upper and lower level constraints.

[0031] Furthermore, the total path delay of the upper and lower levels and the total path delay of the current level are both equal to the delay between the rising edge and the falling edge of the local clock signal.

[0032] Furthermore, the step of synthesizing and generating a timing report based on the constrained local clock signal, and then evaluating and providing feedback based on the timing report to construct the optimal asynchronous circuit control chain, specifically includes:

[0033] The constrained local clock signal is synthesized to obtain the synthesized local clock signal;

[0034] The synthesized local clock signal is checked using the report_timing instruction to generate a timing report, which includes the level width and phase information of the synthesized local clock signal.

[0035] Determine whether the level width of the synthesized local clock signal meets the preset level width requirement and whether the phase information of the synthesized local clock signal meets the preset phase information requirement;

[0036] If the requirements are not met, a feedback signal is generated to perform delay adjustment processing on the LCM module and the PLACM module until the requirements are met, resulting in the adjusted LCM module and the adjusted PLACM module.

[0037] Set the "don't touch" attribute to the adjusted LCM module and the adjusted PLACM module to construct the optimal asynchronous circuit control chain.

[0038] The beneficial effects of the method of this invention are as follows: This invention expands the asynchronous handshake structure of two-phase data bundling using LCM and PLACM modules. The LCM module can expand the level width of the local clock generated by the handshake so that the handshake signal generated by the asynchronous control chain meets the preset requirements. The PLACM module can adjust the phase delay between local clocks while expanding the level width, keeping the phase relationship between local clocks at each level unchanged. These two modules provide an adjustment platform for the asynchronous control chain to generate accurate control signals. Furthermore, constraint analysis is performed using timing constraint analysis methods. The level width of each local clock and the phase relationship between each clock level can be analyzed through timing reports. The status of asynchronous control signals is reflected in the timing reports and then fed back. By modifying the synthesis constraints and optimizing the quality of control signals using PLACM and LCM, the gaps in the analysis, constraint, and feedback of two-phase data bundling control chains are filled. By applying timing constraints to the control chain built by the two-phase data bundling asynchronous template, the EDA tool is guided to include the asynchronous control chain and its generated control signals within the scope of synthesis constraints during synthesis, resulting in a control chain that can output accurate control delay amounts. Attached Figure Description

[0039] Figure 1 This is a flowchart illustrating the steps of an asynchronous circuit control chain timing constraint analysis method based on data bundling, according to an embodiment of the present invention.

[0040] Figure 2 This is a schematic diagram of the communication actions in a four-way handshake protocol;

[0041] Figure 3 This is a schematic diagram of the communication actions in a two-way handshake protocol;

[0042] Figure 4 This is a schematic diagram of single-track encoding for an asynchronous circuit;

[0043] Figure 5 This is a schematic diagram of a dual-track encoding for an asynchronous circuit;

[0044] Figure 6 This is a schematic diagram of a conventional asynchronous circuit handshake structure model with two-phase data binding.

[0045] Figure 7 This is a schematic diagram of the asynchronous control chain and LCM and PLCM modules for phase data bundling in a specific embodiment of the present invention;

[0046] Figure 8 This is a waveform diagram showing the voltage level width extension of the LCM module in a specific embodiment of the present invention;

[0047] Figure 9 This is a waveform diagram showing the voltage level width extension of the PLCM module in a specific embodiment of the present invention;

[0048] Figure 10 This is a schematic diagram of the timing constraints, analysis path, and method of the asynchronous control chain for phase data bundling in a specific embodiment of the present invention. Detailed Implementation

[0049] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0050] Asynchronous circuits have two key handshake signals: a request signal (Req Signal), which informs other modules that the current handshake is ready to receive data; and an acknowledgment signal (Ack Signal), which responds to the received request signal. Based on the differences between these two handshake signals, asynchronous circuits can be classified into different encoding methods and handshake protocols.

[0051] like Figure 2 The diagram shows a 4-phase handshake protocol: 4-phase refers to four communication actions, as shown below:

[0052] 1. Once the sending end has prepared the data, it will set the request signal high;

[0053] 2. After receiving the data, the receiving end sets the acknowledgment signal high;

[0054] 3. The sending end sets the request signal low as a response (at this time, the data may no longer be valid);

[0055] 4. The receiving end responds by setting the response signal low;

[0056] At this point, the sending end can begin the next communication cycle. This handshake protocol is also known as the "return-to-zero (RTZ) handshake protocol" because in a communication cycle, both the request signal and the response signal undergo a "return-to-zero" process, going from low to high and then back to low.

[0057] like Figure 3 The diagram shows a 2-phase handshake protocol. Unlike a 4-phase handshake protocol, where the control signal needs to transition from low to high and back to low to be considered a "signal event," the 2-phase handshake protocol only requires a single level transition in the control signal to be considered a "signal event." That is, a transition from low to high or from high to low can both be considered a valid control signal.

[0058] Data encoding refers to how data is transmitted in asynchronous logic. The main encoding methods are dual-track encoding and single-track encoding. These two methods are common, but not the only ones.

[0059] like Figure 4 The diagram shows single-track encoding, which is characterized by transmitting request signals, response signals, and data separately. Because the two control signals and the data signal must adhere to certain timing requirements—that is, the data and control signals are "bundled" together through timing constraints—this encoding method is also called "data bundling."

[0060] like Figure 5 The diagram shows dual-track encoding. In the design of control and data transmission methods, request signals and data signals are encoded together to form a signal used for communication. Each information bit is represented by two lines, meaning 2n lines are needed to represent n information bits; hence the name "dual-track".

[0061] Unlike other types of asynchronous circuits, data-bundled asynchronous circuits are timing-sensitive. This timing sensitivity manifests in the need to adjust the control chain manually, such as by inserting buffers, to control the phase information and total delay between each stage of the local clock, ensuring that control signals arrive later than data signals. Furthermore, to guarantee timing accuracy and the accurate flow of control data, data-bundled asynchronous circuits also require high-quality control signals generated by the control chain.

[0062] Currently, researchers have proposed different design methods and processes based on various asynchronous handshake structures. However, these technical solutions focus more on automating the conversion between synchronous and asynchronous code, or iterating different timing constraint methods to synthesize a better asynchronous circuit. As for the asynchronous control chain and the quality of the control signals it generates, they are usually regarded as ideal cases and rarely optimized or designed.

[0063] Given the ongoing development of rapid design processes and methods for data-bundled asynchronous handshake structures, and the increasingly stringent requirements for the generated control signals, while methods for analyzing and constraining the control chain itself remain relatively scarce, this invention proposes a design method for asynchronous control chains based on two-phase bundling. This method serves two purposes: firstly, it extends the asynchronous handshake structure to generate control signals that meet the requirements; secondly, it constrains and analyzes the control chain during the synthesis phase to optimize the control chain synthesis process and improve the quality of the control signals.

[0064] A handshake template for two-phase data bundling asynchronous circuits typically consists of two parts: handshake combinational logic and phase units. The former is responsible for handling the handshake of the request signal (In_Req) ​​passed from the previous stage to this stage and the response signal (Out_Ack) passed from the subsequent stage, generating a local clock to drive each asynchronous module and updating the state of the phase units. Its basic structural model is as follows: Figure 6 As shown, common asynchronous circuit handshake templates for two-phase data bundling, such as the Click structure and Mousetrap structure, can be modeled and analyzed using this structure.

[0065] Analyzing the asynchronous circuit with two-phase data bundling, the asynchronous handshake structure comprises two important parts: first, the combinational logic section responsible for handshake signal processing, called the handshake combinational logic module; and second, the phase unit responsible for recording the state. The phase unit is responsible for breaking the loop in timing and recording the handshake state. The phase unit can be a register, a latch, or a specially designed sequential circuit structure. The two-phase data bundling asynchronous handshake structure typically includes five ports: the output request signal (Out_Req) ​​and output acknowledge signal (Out_Ack) generated by the current handshake structure; the input request signal (In_Req) ​​and input acknowledge signal (In_Ack) generated by the upper and lower handshake structures; and the local clock signal generated through the handshake. Detailed descriptions are shown in Table 1 below.

[0066] Table 1. Function Table of Asynchronous Circuit Ports for 2-Phase Data Bundling

[0067] port name Port properties Port function Out_Req Output port Send a request signal to the lower-level handshake structure. Out_Ack Output port Send a response signal to the higher-level handshake structure Local clock Output port The handshake generates a local clock signal to drive the asynchronous module. In_Req Input port Receive request signals sent by the upper-level handshake structure. In_Ack Input port Receive the response signal sent by the lower-level handshake structure.

[0068] Furthermore, such as Figure 6 As shown, In_Req and In_Ack serve as input ports connected to the handshake combinational logic. When the level of either signal changes, the handshake combinational logic initiates a handshake. On one hand, it outputs a local clock to the local clock port to drive the asynchronous module. On the other hand, it serves as a drive signal for the phase unit, which updates its state and outputs the new state to two locations, Out_Req and Out_Ack, at the output (Q terminal), informing the upper and lower level handshake modules to update the handshake information. The output is then returned to the handshake combinational logic, prompting the handshake combinational logic module to update its signal and prepare for the next handshake.

[0069] Based on this, refer to Figure 1 This invention provides a method for timing constraint analysis of asynchronous circuit control chains based on data bundling, the method comprising the following steps:

[0070] S1. Perform extended processing of the asynchronous handshake structure with two-phase data binding using the LCM and PLCM modules, and output the extended local clock signal.

[0071] In this embodiment, since the asynchronous circuit for data bundling is timing-sensitive, parameters such as phase and level width need to be considered, wherein:

[0072] Phase information:

[0073] The delay between different levels of local clocks must be greater than the delay of the data path to ensure the correctness of asynchronous functions. The delay relationship between local clocks is defined as phase information. When constructing a control chain using an asynchronous handshake structure, delay cells need to be inserted to ensure timing correctness.

[0074] Level width:

[0075] The high-level length generated by each asynchronous handshake template is fixed, determined by the handshake combinational logic and the devices of the phase unit (the structure may vary slightly depending on the implementation). Under different loads or process influences, the actual high-level width obtained by synthesis will fluctuate.

[0076] Furthermore, in order to control parameters such as the high-level width and phase of the control signal, this invention extends the asynchronous handshake control structure of the two-phase data bundling to ensure the quality of the local clock at each stage.

[0077] S11. Based on the asynchronous handshake structure of two-phase data binding, insert the LCM module to perform extended delay processing on the level width of the local clock signal of the asynchronous handshake structure of two-phase data binding, and obtain the preliminary extended local clock signal.

[0078] Specifically, the total delay of the LCM insertion delay is the extended level width extension. The advantage of the LCM module is that it can extend the level width without affecting the delay between control signals generated by the control chain, i.e., the phase information, or the width of the pulse signals generated by the upper and lower stages. The changes in the control signals after extension are as follows: Figure 8 As shown. This module can be used when the signal width is insufficient. For example, if the signal width of a certain control level is set to 0.5ns, but the actual generated signal width is 0.2ns, the LCM module can be used to extend the control signal of this level without affecting the local clock of other levels.

[0079] S12. Insert the PLCM module to adjust the phase information of the local clock signal of the asynchronous handshake structure with two-phase data binding, and output the extended local clock signal.

[0080] Specifically, such as Figure 9As shown, the PCLM module can also extend the pulse width by inserting delay units. Unlike LCM, the delay inserted by the PCLM also affects the control signals between the upper and lower levels. It automatically balances the delays between each level while extending the pulse width of one level, preventing the phase of the control signals at each level from being affected when extending the pulse width of one level. For example, in some designs, the original timing settings are too tight, leading to data flow errors. In such cases, a delay can be inserted using a PCLM module. This ensures phase stability while also relaxing the timing of the asynchronous modules at each level.

[0081] In this embodiment, the structure of the handshake module is expanded by adding a Level Control Module (LCM) and a Phase and Level Control Module (PLCM) to achieve control over the level width and phase. Both modules are built by inserting buffer units, inverters, or other structures, and their main function is to provide controllable delay. The positions of the two extended modules in the handshake structure model are as follows: Figure 7 As shown.

[0082] The positions of the LCM and PLCM modules will be further explained. After the phase unit is triggered, the signal generated will act on two paths, namely the first path and the second path. The first path is to be passed to the upper and lower level handshake modules as part of the request and response signals. The second path is to output the signal to the handshake combinational logic to continue the handshake process. The PLCM module is inserted in the first path, and the LCM module is inserted in the second path.

[0083] S2. Constraint analysis is performed on the extended local clock signal using timing constraint analysis methods to obtain the constrained local clock signal;

[0084] Specifically, existing methods for judging control signal quality are rather coarse. Generally, this involves analyzing waveforms from post-simulation, measuring various control signal parameters, judging signal quality, and then adjusting the total delay of delay units in the circuit. This approach is labor-intensive and has a long analysis and adjustment cycle. This invention uses timing constraints and analysis methods to constrain the control signals and preliminarily judge the synthesized signal condition, feeding back to the LCM and PLACM modules for adjustment. This improves the synthesis quality of the control chain and shortens the design process. The timing method of this invention consists of two steps: constraint and analysis. The purpose of these two steps is to control and adjust the local clocks at each stage by constraining and analyzing the path traversed by the control signals.

[0085] S21. Constraint analysis of local clock signal at this level;

[0086] S211. Define the local path of the asynchronous handshake structure for two-phase data binding. The local path is phase unit - handshake combinational logic module - local clock signal port.

[0087] S212. Constrain the path at this level using the set_max_delay and set_min_delay instructions to obtain the total path delay at this level;

[0088] S213. Based on the EDA tool, perform level width analysis on the total path delay of this level to obtain the constrained local clock signal of this level.

[0089] In this embodiment, the voltage level width is constrained and analyzed. When performing asynchronous timing constraints, the voltage level width is... Figure 10 The solid line path in the code is constrained by the `set_max_delay` and `set_min_delay` instructions. The path is: phase unit - handshake combinational logic - local clock output port. The starting point of the constraint is the register output, constrained with the "-from" option; the ending point is the handshake signal output point of the Click asynchronous handshake structure, constrained with the "-to" option. Analysis shows that the total delay of this path is approximately equal to the delay between the rising and falling edges of the control signal. When constraining, a preset level width is used as the constraint parameter, plus a certain margin, to ensure that the EDA tool takes into account the level width of the control signal generated by the handshake during synthesis.

[0090] After applying constraints, level width analysis can be performed after initial synthesis using EDA tools. Typically, this step involves using gate-level netlist simulation or post-simulation waveforms to determine the quality of the control signal. However, this method allows for level width determination after initial synthesis by adding the aforementioned constraint path using the `report_timing` option, simplifying the process length. If the level width is insufficient or there are excessive delays inserted by LCM or PLACM, this will be displayed in a timing report, allowing for evaluation and adjustment.

[0091] S22, Constraint analysis of local clock signals between upper and lower levels;

[0092] S221. Define the upper and lower level paths of the asynchronous handshake structure for two-phase data binding. The upper and lower level paths are: phase unit of this level - local clock signal port of this level - handshake combinational logic module of the upper level or handshake combinational logic module of the lower level - local clock signal port of the upper level or local clock signal port of the lower level.

[0093] S222. Constrain the upper and lower level paths using the set_max_delay and set_min_delay instructions to obtain the total path delay of the upper and lower levels.

[0094] S223. The total path delay of the upper and lower levels is analyzed by the report_timing instruction to obtain the local clock signal after upper and lower level constraints.

[0095] Specifically, constraints and analyses are performed on the delays between different asynchronous control signals. Data-bundled asynchronous circuits are timing-sensitive, requiring the control signals in the control path to arrive later than the data in the data path. This is achieved by manually inserting delay units between the two levels of control signals. However, existing techniques do not constrain or rapidly analyze the asynchronous control chain to ensure the quality of multi-level control signals.

[0096] This invention relates to Figure 10 The path indicated by the dashed line is constrained by the `set_max_delay` and `set_min_delay` instructions. The path is: current-level phase unit - current-level control signal output port - handshake combinational logic of the upper or lower level - local clock output port of the upper or lower level. The timing path starts at the register output of the current module and ends at the local clock output of the next-level module. It is also constrained and analyzed using the "-from" and "-to" options. The length of the timing report approximates the total delay between the two control signals. This method incorporates the delays inserted by the PCM and the delays of the inserted Delay Cells into the analysis, improving the accuracy of the analysis and facilitating the analysis and accurate control of delay amounts in the PCM.

[0097] S3. Based on the constrained local clock signal, perform synthesis and generate a timing report, and evaluate and provide feedback based on the timing report to construct the optimal asynchronous circuit control chain.

[0098] Specifically, the constrained local clock signal is synthesized to obtain a synthesized local clock signal; the synthesized local clock signal is checked using the report_timing instruction to generate a timing report, which includes the voltage level and phase information of the synthesized local clock signal; it is determined whether the voltage level and phase information of the synthesized local clock signal meet the preset voltage level and phase information requirements; if they do not meet the requirements, a feedback signal is generated to adjust the delay of the LCM module and the PLC module until the requirements are met, resulting in the adjusted LCM module and the adjusted PLC module; the "don't touch" attribute is set on the adjusted LCM module and the adjusted PLC module to construct the optimal asynchronous circuit control chain.

[0099] In this embodiment, synthesis is performed after the constraints are completed;

[0100] The `report_timing` command checks the path of the constraints mentioned above. The timing report provides a preliminary estimate of the level width and phase information between local clocks.

[0101] Based on the preliminary estimate in Step 4, if the preset conditions are met, proceed to the next step; otherwise, adjust the delay values ​​of the LCM module and the PLACM module, and return to step S3.

[0102] Set the "don't touch" property to the adjusted LCM and PLCM modules to form the correct control chain, output the netlist file, and end the steps of this solution.

[0103] In summary, this invention can be divided into two parts: circuit design and timing constraints / analysis methods. The circuit design part is used to adjust and control the high-level width of the handshake signal and the phase information between each stage of the local clock. The timing constraint-analysis method guides EDA tools to synthesize the control chain and analyzes the synthesized control chain to preliminarily determine parameters such as the phase and level width of the control signals, thereby guiding modifications to the circuit. This method can be combined with existing rapid design flows or timing constraint methods without significant modifications to the handshake structure, and can be implemented at the Verilog level and in commercial EDA tools.

[0104] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A method for timing constraint analysis of asynchronous circuit control chains based on data bundling, characterized in that, Includes the following steps: The asynchronous handshake structure with two-phase data binding is extended by the LCM module and the PLACM module to output the extended local clock signal; wherein, the asynchronous handshake structure with two-phase data binding includes a handshake combinational logic module, a phase unit, an Out_Req signal port, an Out_Ack signal port, a local clock signal port, an In_Req signal port, and an In_Ack signal port; The extended local clock signal is constrained by a timing constraint analysis method to obtain a constrained local clock signal. The constraint analysis includes constrain analysis of the local clock signal at the current level and constrain analysis of the local clock signals at the upper and lower levels. The constrained local clock signal includes the local clock signal constrained at the current level and the local clock signals constrained at the upper and lower levels. Based on the constrained local clock signal, a timing report is generated and evaluated, and the optimal asynchronous circuit control chain is constructed. The trigger signal generated by the phase unit includes a first signal and a second signal. The first signal serves as a request signal and a response signal and is transmitted to the upper-level asynchronous handshake structure and the lower-level asynchronous handshake structure through a first path. The second signal is transmitted to the handshake combinational logic module through a second path to continue the handshake processing. The LCM module is used to extend the level width of the local clock signal without affecting the phase information of the local clock signal, and the PLCM module is used to extend the level width of the local clock signal and automatically balance the phase delay between local clock signals. The PLACM module is inserted at the first path, and the LCM module is inserted at the second path.

2. The asynchronous circuit control chain timing constraint analysis method based on data bundling according to claim 1, characterized in that, The handshake combinational logic module is responsible for handshake signal processing; The phase unit is responsible for recording the handshake state and breaking the loop in timing to generate a trigger signal; The Out_Req signal port is used to send a request signal to the lower-level handshake structure; The Out_Ack signal port is used to send an acknowledgment signal to the upper-level handshake structure. The local clock signal port is used to generate a local clock signal for handshaking, which drives the asynchronous module. The In_Req signal port is used to receive request signals sent by the upper-level handshake structure; The In_Ack signal port is used to receive the response signal sent by the lower-level handshake structure.

3. The asynchronous circuit control chain timing constraint analysis method based on data bundling according to claim 1, characterized in that, The step of constraining the local clock signal at this level specifically includes: Define the local path of the asynchronous handshake structure of the two-phase data binding, wherein the local path is phase unit - handshake combinational logic module - local clock signal port; The total path delay at this level is obtained by constraining the path at this level using the set_max_delay and set_min_delay instructions. Based on the EDA tool, the total path delay of this level is analyzed to obtain the constrained local clock signal of this level.

4. The asynchronous circuit control chain timing constraint analysis method based on data bundling according to claim 3, characterized in that, The step of constraining analysis of the upper and lower level local clock signals specifically includes: Define the upper and lower level paths of the asynchronous handshake structure of the two-phase data binding, wherein the upper and lower level paths are: phase unit of this level - local clock signal port of this level - handshake combinational logic module of the upper level or handshake combinational logic module of the lower level - local clock signal port of the upper level or local clock signal port of the lower level. The set_max_delay and set_min_delay instructions are used to constrain the upper and lower level paths to obtain the total path delay of the upper and lower levels. The total path delay of the upper and lower levels is analyzed by the report_timing instruction to obtain the local clock signal after upper and lower level constraints.

5. The asynchronous circuit control chain timing constraint analysis method based on data bundling according to claim 4, characterized in that, The total path delay of the upper and lower levels and the total path delay of the current level are both equal to the delay between the rising edge and the falling edge of the local clock signal.

6. The asynchronous circuit control chain timing constraint analysis method based on data bundling according to claim 5, characterized in that, The step of synthesizing and generating a timing report based on the constrained local clock signal, and then evaluating and providing feedback based on the timing report to construct the optimal asynchronous circuit control chain, specifically includes: The constrained local clock signal is synthesized to obtain the synthesized local clock signal; The synthesized local clock signal is checked using the report_timing instruction to generate a timing report, which includes the level width and phase information of the synthesized local clock signal. Determine whether the level width of the synthesized local clock signal meets the preset level width requirement and whether the phase information of the synthesized local clock signal meets the preset phase information requirement; If the requirements are not met, a feedback signal is generated to perform delay adjustment processing on the LCM module and the PLACM module until the requirements are met, resulting in the adjusted LCM module and the adjusted PLACM module. Set the "don't touch" attribute to the adjusted LCM module and the adjusted PLACM module to construct the optimal asynchronous circuit control chain.

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