Analog chip automatic layout model training method and automatic layout method

Abstract

The present application relates to the technical field of analog chip design, and provides an analog chip automatic layout model training method and an automatic layout method, the training method synchronously trains the strategy network corresponding to each sample layout agent, can realize the centralized training of the analog chip automatic layout model, and improves the convergence efficiency and stability of reinforcement learning. The training method can obtain the analog chip automatic layout model configured in each target layout agent, realizes decentralized layout decision, can improve the subsequent analog chip layout efficiency and layout effect, can obtain a layout result with performance equivalent to that of manual layout in seconds without a large amount of layout data, so as to realize automatic layout, and further help subsequent analog chip wiring, and provide convenience for rapid production and batch application of analog chips.

Description

Technical Field

[0001] This invention relates to the field of analog chip design technology, and in particular to an automated placement model training method and an automated placement method for analog chips. Background Technology

[0002] In analog chip design, placement is a crucial step. Placement refers to the process of arranging various components (such as transistors, capacitors, and resistors) within the corresponding metal layers of the analog chip to achieve the circuit's functionality and performance requirements. The quality of the analog chip placement directly affects the circuit's performance, power consumption, noise characteristics, and overall reliability.

[0003] Analog chip placement faces numerous challenges. First, analog circuits are typically sensitive to the interactions and placement of electronic components; therefore, analog chip placement must meet specific requirements of circuit designers, such as maintaining low noise, minimizing power supply jitter, and maximizing circuit bandwidth. Second, analog circuits contain a large number of interconnects, the length, shape, and location of which introduce parasitic parameters to varying degrees, affecting circuit performance, thus necessitating precise placement and location planning. Furthermore, analog circuits often require consideration of symmetrical placement between devices; therefore, paired devices must be strategically placed during analog chip placement to reduce unnecessary coupling and interference.

[0004] However, existing analog chip placement processes suffer from problems such as long automated placement times and poor availability of placement results, resulting in low placement efficiency and unsatisfactory placement effects. Summary of the Invention

[0005] This invention provides a method for training an automated placement model for analog chips and an automated placement method, in order to overcome the deficiencies in the existing technology.

[0006] This invention provides a method for training an automated placement model for a simulated chip, comprising:

[0007] The sample information of the simulated chip sample is obtained, and based on the sample information, the sample layout agents corresponding to the simulated chip sample, the sample layout environment of the simulated chip sample, and the initial state of each sample layout agent are determined; each sample layout agent is used to characterize one or more devices in the simulated chip sample.

[0008] The initial state of each sample layout agent is input into the corresponding policy network to obtain the initial prediction action of each sample layout agent. The initial state and initial prediction action of each sample layout agent are then input into the value network to obtain the value result corresponding to each sample layout agent.

[0009] Based on each sample layout agent, the corresponding initial prediction action is interacted with the sample layout environment to calculate the total reward value corresponding to each sample layout agent. Based on the value result and total reward value corresponding to each sample layout agent, the loss function is calculated.

[0010] Based on the loss function, the structural parameters of each policy network and value network are iteratively updated, and each trained policy network is used as a simulated chip automated placement model configured in a target placement intelligent body.

[0011] According to the present invention, an automated placement model training method for a simulated chip is provided, wherein the sample information includes sample constraint information, sample netlist information, symmetry information of each device in the simulated chip sample, and size information of each sample placement agent; the step of determining each sample placement agent corresponding to the simulated chip sample, the sample placement environment of the simulated chip sample, and the initial state of each sample placement agent based on the sample information includes:

[0012] Based on the symmetry information of each device in the simulated chip sample, at least two devices with symmetric relationships in the simulated chip sample are used as a sample layout agent, and a single device without symmetric relationships in the simulated chip sample is used as a sample layout agent.

[0013] Based on the sample constraint information, the sample netlist information, and the size information of each sample layout agent, the sample layout environment is determined, and based on the sample constraint information, the initial state of each sample layout agent is determined.

[0014] According to the present invention, an automated placement model training method for simulated chips includes, based on each sample placement agent, interacting with the sample placement environment by the corresponding initial prediction action, and calculating the total reward value corresponding to each sample placement agent, including:

[0015] Based on each sample layout agent, the corresponding initial prediction action is interacted with the sample layout environment to obtain the updated state of each sample layout agent.

[0016] For any sample layout agent, based on the update state and size information of each sample layout agent, calculate the distance information, overlap area information and wiredability information between the sample layout agent and other sample layout agents respectively.

[0017] The total reward value is calculated based on the distance information, overlap area information, and wiredability information corresponding to each sample layout agent.

[0018] According to the present invention, an automated placement model training method for analog chips is provided, wherein the overlap area information is determined based on the following steps:

[0019] Determine the sequence of intersection points within the overlapping region between any sample layout agent and any other sample layout agent;

[0020] The three adjacent intersection points in the intersection point sequence are taken as a group of triangles, and the total area of ​​all triangles in the overlapping area is used as the overlapping area information between any sample layout agent and any other sample layout agent.

[0021] According to the present invention, an automated placement model training method for analog chips is provided, wherein the value network includes a first-layer perceptron and a second-layer perceptron; the step of inputting the initial state and initial prediction action of each sample placement agent into the value network to obtain the value result corresponding to each sample placement agent includes:

[0022] The initial state and initial prediction action of each sample layout agent are input into the first layer perceptron to obtain the perception results of each sample layout agent.

[0023] For any sample layout agent, based on the perception results of each sample layout agent, an attention mechanism is used to calculate the attention features between the any sample layout agent and other sample layout agents.

[0024] The perception result and corresponding attention features of any sample layout agent are input into the second-layer perceptron to obtain the value result corresponding to any sample layout agent.

[0025] The present invention also provides an automated placement method for analog chips, comprising:

[0026] Obtain target information of the simulated chip to be laid out, and based on the target information, determine each target layout agent corresponding to the simulated chip to be laid out, the target layout environment of the simulated chip to be laid out, and the initial state of each target layout agent; each target layout agent is used to characterize one or more devices in the simulated chip to be laid out.

[0027] The initial state of each target layout agent is input into the simulated chip automated layout model configured within it to obtain the predicted action information of each target layout agent;

[0028] Based on each target layout agent, the corresponding predicted action information is interacted with the target layout environment to complete the automated layout of the simulated chip to be laid out.

[0029] According to the present invention, an automated placement method for a simulated chip is provided, wherein the target information includes target constraint information, target netlist information, symmetry information of each device in the simulated chip to be placed, and size information of each target placement agent;

[0030] The step of determining, based on the target information, each target layout agent corresponding to the simulated chip to be laid out, the target layout environment of the simulated chip to be laid out, and the initial state of each target layout agent includes:

[0031] Based on the symmetry information of each device in the simulation chip to be laid out, at least two devices in the simulation chip to be laid out that have a symmetric relationship are taken as a target layout agent, and a single device in the simulation chip to be laid out that does not have a symmetric relationship is taken as a target layout agent.

[0032] Based on the target constraint information, the target netlist information, and the size information of each target layout agent, the target layout environment is determined, and based on the target constraint information, the initial state of each target layout agent is determined.

[0033] According to the present invention, an automated placement method for a simulated chip is provided, wherein the target constraint information includes target placement boundary information, and the initial state of each target placement agent includes initial position information; the step of determining the initial state of each target placement agent based on the target constraint information includes:

[0034] The initial position information of each target layout agent is determined to be the same position information that satisfies the target layout boundary information.

[0035] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the analog chip automated placement model training method or the analog chip automated placement method as described above.

[0036] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the analog chip automated placement model training method or the analog chip automated placement method as described above.

[0037] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the analog chip automated placement model training method or the analog chip automated placement method as described above.

[0038] This invention provides a training method for an automated placement model of analog chips and an automated placement method. The training method simultaneously trains the policy network corresponding to each sample placement agent, enabling centralized training of the automated placement model and improving the convergence efficiency and stability of reinforcement learning. This training method yields an automated placement model of the analog chip configured within each target placement agent, achieving decentralized placement decisions. This improves the efficiency and effectiveness of subsequent analog chip placement, and can obtain a placement result with performance comparable to manual placement within milliseconds, without requiring a large amount of placement data. This automated placement facilitates subsequent analog chip routing, providing convenience for the rapid production and mass application of analog chips. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on the drawings described below without creative effort.

[0040] Figure 1 This is one of the flowcharts illustrating the automated layout model training method for analog chips provided by the present invention;

[0041] Figure 2 This is a schematic diagram of the value network structure in the simulated chip automated layout model training method provided by the present invention;

[0042] Figure 3 This is the second flowchart of the simulated chip automated layout model training method provided by the present invention;

[0043] Figure 4 This is a schematic diagram illustrating the connection relationship between each policy network and the value network in the simulated chip automated layout model training method provided by this invention;

[0044] Figure 5 This is a flowchart illustrating the automated placement method for analog chips provided by the present invention;

[0045] Figure 6 This is a schematic diagram illustrating the interaction between each target layout agent and the target layout environment in the simulated chip automated layout method provided by the present invention.

[0046] Figure 7 This is a schematic diagram of the structure of the simulated chip automated layout model training device provided by the present invention;

[0047] Figure 8 This is a schematic diagram of the structure of the analog chip automated placement device provided by the present invention;

[0048] Figure 9 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0050] The terms "first" and "second" in the specification and claims of this invention may explicitly or implicitly include one or more of those features. In the description of the invention, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0051] Existing analog chip placement processes suffer from problems such as long automated placement times and poor usability of placement results, resulting in low placement efficiency and unsatisfactory placement effects. Therefore, this invention provides a method for training an automated placement model for analog chips. This method trains an automated placement model for analog chips with shorter execution times, higher efficiency, stronger usability of placement results, and better placement effects, thereby facilitating the rapid production and mass application of analog chips.

[0052] Figure 1 This is a flowchart illustrating a method for training an automated placement model for a simulated chip, as provided in an embodiment of the present invention. Figure 1 As shown, the training method includes:

[0053] S11, obtain sample information of the analog chip sample, and based on the sample information, determine each sample layout agent corresponding to the analog chip sample, the sample layout environment of the analog chip sample, and the initial state of each sample layout agent; each sample layout agent is used to characterize one or more devices in the analog chip sample.

[0054] S12, input the initial state of each sample layout agent into the corresponding policy network to obtain the initial prediction action of each sample layout agent, and input the initial state and initial prediction action of each sample layout agent into the value network to obtain the value result corresponding to each sample layout agent.

[0055] S13, based on each sample layout agent, the corresponding initial prediction action is interacted with the sample layout environment to calculate the total reward value corresponding to each sample layout agent, and the loss function is calculated based on the value result and total reward value corresponding to each sample layout agent.

[0056] S14, based on the loss function, the structural parameters of each policy network and value network are iteratively updated, and each trained policy network is used as a simulated chip automated placement model configured in a target placement intelligent body.

[0057] Specifically, the simulated chip automated layout model training method provided in this embodiment of the invention is executed by a simulated chip automated layout model training device, which can be configured in a computer. The computer can be a local computer or a cloud computer. The local computer can be a computer, tablet, etc., and no specific limitation is made here.

[0058] First, step S11 is executed to obtain sample information of the simulated chip sample. The simulated chip sample refers to the simulated chip that has not been laid out and is used to train the automated placement model of the simulated chip.

[0059] The sample information may include sample constraint information, sample netlist information, symmetry information of each device in the analog chip sample, and size information of each sample layout agent.

[0060] Sample constraint information may include sample layout boundary information and DRC rule information for the analog chip sample. Sample layout boundary information is generally determined by the dimensions of the analog chip sample and is represented by a layout bounding box. Sample layout boundary information can be used for boundary bounce-back. DRC rule information may include design rule checks, electrical rule checks, and short-circuit checks.

[0061] The sample netlist information can include the required connections between the devices in the analog chip sample.

[0062] The symmetry information of each device in the analog chip sample refers to which devices in the analog chip sample have symmetrical relationships and the axis of symmetry. The size information of each device in the analog chip sample refers to the width, height and other information of each device in the analog chip sample.

[0063] Furthermore, by utilizing the sample information, the sample layout environment of the simulated chip sample, the intelligent agents corresponding to each sample layout of the simulated chip sample, and their initial states can be determined.

[0064] The sample layout environment can be determined through sample information, which may include sample constraint information, sample netlist information, symmetry information of each device in the analog chip sample, and size information of each sample layout agent.

[0065] Understandably, each sample layout agent is used to represent one or more devices in the analog chip sample. When a sample layout agent represents one device in the analog chip sample, it means that there are no other devices in the analog chip sample that are symmetrical to that device. When a sample layout agent represents multiple devices in the analog chip sample, it means that these devices have a symmetrical relationship. In other words, based on the symmetry information of each device in the analog chip sample, at least two devices in the analog chip sample that have a symmetrical relationship can be used as one sample layout agent, and a single device in the analog chip sample that does not have a symmetrical relationship can be used as another sample layout agent. The reason is that symmetry constraints are hard constraints, and failure to meet them will lead to an increase in parasitic parameters. Therefore, all devices with symmetrical relationships are laid out as a whole.

[0066] Furthermore, the initial state of each sample layout agent can be determined based on the sample constraint information. The initial state of each sample layout agent can include the initial position information of each sample layout agent, the initial overlap area information between each sample layout agent and other sample layout agents, and the initial wiring capability information. Therefore, the initial position information of each sample layout agent can be directly determined as the same position information that satisfies the sample layout boundary information in the sample constraint information. That is, the layable region in the analog chip sample is determined based on the sample constraint information, and the initial position information of each sample layout agent is determined as the same position information in the layable region.

[0067] The initial overlap area information for each sample layout agent can be determined based on the initial position and size information of each sample layout agent. The initial wiredability information for each sample layout agent can be determined by the half-circumference of the signal line obtained by the router.

[0068] The size information of each sample layout agent can be determined based on the size information of the device corresponding to the sample layout agent. For example, if there is only one device corresponding to the sample layout agent, the size of the sample layout agent is equal to the size information of the corresponding device. If there are multiple devices corresponding to the sample layout agent, the size of the sample layout agent can be determined based on the axis of symmetry of the corresponding device and the size information of the corresponding device.

[0069] For example, if the sample layout agent corresponds to 2 devices, and the axis of symmetry is parallel to the width direction, then the height of the sample layout agent is equal to twice the sum of the height of the corresponding single device and the distance to the axis of symmetry, and the width of the sample layout agent is equal to the width of the corresponding single device.

[0070] Then, step S12 is executed, introducing a Deep Q-network (DQN). This Deep Q-network refers to a Q-learning algorithm based on deep learning, combining value function approximation with neural network techniques, and using a target network and experiential replay method for network training. Here, the Deep Q-network used can be a Double DQN. This Deep Q-network is the value network.

[0071] Before training each policy network and value network, the sample simulated chip layout is defined to correspond to the sample state space and sample action space of deep reinforcement learning; the reward calculation function, value network, policy network and related parameters applicable to the sample simulated chip layout are defined.

[0072] The sample's motion space can include, but is not limited to, 10 actions such as: up, down, left, right, rotate 45°, rotate 90°, rotate 135°, x-axis mirroring, y-axis mirroring, and stationary.

[0073] The sample state space can be a three-dimensional space, with the three dimensions being the two-dimensional position information (x, y) of the sample layout agent and the overlap area information between the sample layout agent and other sample layout agents.

[0074] In this embodiment of the invention, the number of policy networks is equal to the number of sample layout agents. The initial state of each sample layout agent is input into the corresponding policy network to obtain the initial prediction action of each sample layout agent.

[0075] For each sample layout agent, the structural parameters of the value network are shared, and the policy network corresponding to each sample layout agent can be deployed within that agent. For example, if there are N sample layout agents, the initial state of the i-th agent can be input into the corresponding policy network to obtain the initial prediction action of the i-th agent.

[0076] Then, the initial state and initial prediction action of each sample layout agent are input into the value network to obtain the value result corresponding to each sample layout agent. For example, inputting the initial state and initial prediction action of the i-th sample layout agent into the value network can yield the value result corresponding to the i-th sample layout agent.

[0077] Subsequently, step S13 is executed, whereby each sample layout agent interacts with the sample layout environment to obtain the updated state of each sample layout agent by using the corresponding initial prediction action.

[0078] Furthermore, the total reward value corresponding to each sample layout agent can be calculated. Then, using the value results and total reward value corresponding to each sample layout agent, the loss function can be calculated.

[0079] Finally, step S14 is executed, using the loss function to iteratively update the structural parameters of each policy network and value network. Gradient descent can be used to iteratively update the structural parameters until the iteration termination condition is met, at which point the iteration process ends, resulting in the trained policy networks and value networks. Here, the iteration termination condition can be the convergence of the loss function or the reaching of a preset number of iterations.

[0080] The following process can be performed during the iterative update of the structural parameters of the value network:

[0081] Initialize the value network replay buffer;

[0082]

[0083]

[0084] Updating the structural parameters of the value network and each policy network may include the following process:

[0085] Samples are extracted from the playback buffer to obtain (o t ,a t ,r t ,o t+1 ,done),o t Let a be the state at time t. t Let r be the action at time t. t Let o be the total reward value at time t. t+1 This represents the state at time t+1, where done indicates that the item has been retrieved.

[0086] The structural parameters of a value network can be represented as w now The structural parameters of the target network can be expressed as:

[0087] The value result is calculated for each sample placement agent. For example, the value result of the i-th sample placement agent at time t can be expressed as:

[0088] The value result corresponding to the layout of all samples of the agent is:

[0089]

[0090] The target network is used to compute the value of the i-th sample placement agent at time t+1:

[0091] The value result corresponding to the layout of all samples of the agent is:

[0092]

[0093] Computing Temporal Difference (TD) Objective and TD error (i.e., loss function) δ t :

[0094]

[0095]

[0096] Update the structural parameters of the value network:

[0097]

[0098] Update the structural parameters of the target network:

[0099]

[0100] Update the structure parameters of the policy network corresponding to the i-th sample placement agent:

[0101]

[0102] After obtaining the trained policy networks and value networks, each trained policy network can be used as a simulated automated chip placement model configured within a target placement agent. The input of this simulated automated chip placement model is the state of the target placement agent at each time step, and the output is the predicted action of the target placement agent. Automated placement can be achieved through this predicted action.

[0103] The simulated chip automated placement model training method provided in this embodiment of the invention first acquires sample information of simulated chip samples, and based on the sample information, determines the sample placement environment of the simulated chip samples, the corresponding sample placement agents and their initial states; then, the initial state of each sample placement agent is input into the corresponding policy network to obtain the initial prediction action of each sample placement agent, and the initial state and initial prediction action of each sample placement agent are input into the value network to obtain the value result corresponding to each sample placement agent; subsequently, each sample placement agent interacts with the sample placement environment using the corresponding initial prediction action to calculate the total reward value corresponding to each sample placement agent, and calculates the loss function based on the value result and total reward value corresponding to each sample placement agent; finally, the loss function is used to iteratively update the structural parameters of each policy network and the value network, and each trained policy network is used as a simulated chip automated placement model configured in a target placement agent. This training method trains the policy network corresponding to each sample placement agent simultaneously, which can realize centralized training of the simulated chip automated placement model and improve the convergence efficiency and stability of reinforcement learning. This training method can obtain an automated placement model of the analog chip configured in each target placement intelligent body, realize decentralized placement decision, improve the efficiency and effect of subsequent analog chip placement, and obtain a placement result with performance comparable to manual placement in milliseconds without requiring a large amount of placement data, thereby realizing automated placement, which in turn helps subsequent analog chip routing and provides convenience for the rapid production and mass application of analog chips.

[0104] Based on the above embodiments, the step of interacting the corresponding initial prediction action with the sample layout environment based on each sample layout agent, and calculating the total reward value corresponding to each sample layout agent, includes:

[0105] Based on each sample layout agent, the corresponding initial prediction action is interacted with the sample layout environment to obtain the updated state of each sample layout agent.

[0106] For any sample layout agent, based on the update state and size information of each sample layout agent, calculate the distance information, overlap area information and wiredability information between the sample layout agent and other sample layout agents respectively.

[0107] The total reward value is calculated based on the distance information, overlap area information, and wiredability information corresponding to each sample layout agent.

[0108] Specifically, in this embodiment of the invention, the total reward value corresponding to each sample layout agent can be calculated using the following reward value calculation function:

[0109]

[0110] Where, r t Let represent the total reward value at time t, Agents represent the set of agents in the sample layout, and Actions represent the set of actions. This represents the distance information between the i-th sample layout agent and other sample layout agents when the i-th sample layout agent attempts the k-th action. This represents the overlap area information between the i-th sample layout agent and other sample layout agents when the i-th sample layout agent attempts the k-th action. w represents the wireability information between the i-th sample layout agent and other sample layout agents when the i-th sample layout agent attempts the k-th action. d w o and w r They represent as well as The weighting coefficients. Here, w d w o They can be set to 1.0 and 10000 respectively.

[0111] It can be calculated using the following formula:

[0112]

[0113] It can be calculated using the following formula:

[0114]

[0115] The signal line can be characterized by the half-circumference obtained through the router algorithm.

[0116] Where, x i y i Let x represent the two-dimensional position information of the i-th sample layout agent at time t, and x represent the position information of the i-th sample layout agent at time t. j y j S represents the two-dimensional position information of the j-th sample layout agent at time t. i S represents the area of ​​the i-th sample layout agent at time t. j Let represent the area of ​​the j-th sample layout agent at time t.

[0117] In this embodiment of the invention, the total reward value takes into account the distance information, overlap area information and wiredability information between individual sample layout agents, which can further improve the layout effect of the trained simulated chip automated layout model and facilitate subsequent wiring operations.

[0118] Based on the above embodiments, the overlapping area information is determined according to the following steps:

[0119] Determine the sequence of intersection points within the overlapping region between any sample layout agent and any other sample layout agent;

[0120] The three adjacent intersection points in the intersection point sequence are taken as a group of triangles, and the total area of ​​all triangles in the overlapping area is used as the overlapping area information between any sample layout agent and any other sample layout agent.

[0121] Specifically, when calculating the overlap area information between the i-th sample layout agent and the j-th sample layout agent, a polygon overlap area calculation method can be designed first to calculate the overlap area information between the i-th sample layout agent and the j-th sample layout agent.

[0122] Here, we can first determine the sequence of intersection points within the overlapping region between the i-th sample layout agent and the j-th sample layout agent, and then group three adjacent intersection points in the sequence into a triangle. The sum of the areas of all triangles is the overlapping area information between the i-th sample layout agent and the j-th sample layout agent, as shown in the following formula:

[0123]

[0124] Where Area represents the overlapping region, and i, j, k represent the intersection points within the overlapping region. The total overlapping area is calculated by summing the points in groups of three using the triangle formula.

[0125] If the number of intersection points within the overlapping region is less than 3, it indicates that there is no overlapping region, and the overlapping area information is empty. O =0.

[0126] Based on the above embodiments, the value network includes a first-layer perceptron and a second-layer perceptron; the step of inputting the initial state and initial prediction action of each sample layout agent into the value network to obtain the value result corresponding to each sample layout agent includes:

[0127] The initial state and initial prediction action of each sample layout agent are input into the first layer perceptron to obtain the perception results of each sample layout agent.

[0128] For any sample layout agent, based on the perception results of each sample layout agent, an attention mechanism is used to calculate the attention features between the any sample layout agent and other sample layout agents.

[0129] The perception result and corresponding attention features of any sample layout agent are input into the second-layer perceptron to obtain the value result corresponding to any sample layout agent.

[0130] Specifically, such as Figure 2 As shown, the value network has a two-layer perceptron network, including a first-layer perceptron and a second-layer perceptron. The network structure of the first-layer perceptron includes: a fully connected layer (input dimension: 2*hidden_dim, output dimension: hidden_dim), a LeakyReLU layer, and another fully connected layer (input dimension: hidden_dim, output dimension: number of action spaces). The network structure of the second-layer perceptron includes: a normalization layer, a fully connected layer (input dimension: the dimension of the state space, output dimension: hidden_dim), and a LeakyReLU layer. The specific value of hidden_dim is related to the number of agents in each sample layout and the difficulty of the task.

[0131] For the i-th sample placement agent, the value network can be represented by the following formula: Q i (o,a)=f(g(o i ,a i ),b i ), b i =∑ j≠i α j h(Vg(o j ,a j )).

[0132] Among them, o i ,a i Let o represent the state and action of the i-th sample layout agent, respectively. j ,a j Let g represent the state and action of the i-th sample layout agent, g be the first-layer perceptron, f be the second-layer perceptron, and b be the third-layer perceptron. i Let α be the attention feature between the i-th sample layout agent and other sample layout agents, representing the sum of the weighted vectors of the i-th sample layout agent and other sample layout agents. j Let be the attention weight between the j-th sample layout agent and the i-th sample layout agent, represent the state similarity between the j-th sample layout agent and the i-th sample layout agent, h be the LeakyReLU activation function, and V be the value matrix determined based on the attention mechanism.

[0133] The LeakyReLU activation function can be expressed as:

[0134]

[0135] like Figure 3 The diagram shown is a flowchart illustrating an automated layout model training method for a simulated chip provided in an embodiment of the present invention. The method includes:

[0136] Determine the sample information of the simulated chip sample, and use the sample information to determine the sample layout environment of the simulated chip sample, the corresponding sample layout agents and their initial states.

[0137] Calculate the total reward value corresponding to each sample layout agent, and use N sample layout agents to input the actions in the action space into the sample layout environment;

[0138] By exploring the globally optimal strategy through multi-agent collaboration and iteratively updating the state of each sample layout agent, the structural parameters of each policy network and value network are updated iteratively.

[0139] like Figure 4 The diagram shown illustrates the structure of a value network in an automated chip placement model training method provided in this embodiment of the invention. This value network can be connected to N policy networks, namely policy network 1, policy network 2, ..., policy network N. The inputs are the states o1, o2, ..., o2 of the corresponding sample placement agents. N The outputs are the actions a1, a2, ..., a of the corresponding sample layout agents. N .

[0140] The input to the value network consists of the states θ1, o2, ..., o of N sample agents. N And the actions a1, a2, ..., a of the N sample layout agents. N The outputs are the value results Q1, Q2, ..., Q corresponding to the N sample layout agents. N .

[0141] like Figure 5 As shown, based on the above embodiments, this embodiment of the invention also provides a method for automated placement of simulated chips, the method comprising:

[0142] S21, obtain target information of the simulation chip to be laid out, and based on the target information, determine each target layout agent corresponding to the simulation chip to be laid out, the target layout environment of the simulation chip to be laid out, and the initial state of each target layout agent; each target layout agent is used to characterize one or more devices in the simulation chip to be laid out.

[0143] S22, input the initial state of each target layout agent into the simulated chip automated layout model configured therein to obtain the predicted action information of each target layout agent;

[0144] S23, based on each target layout agent, the corresponding predicted action information is interacted with the target layout environment to complete the automated layout of the simulation chip to be laid out.

[0145] Specifically, the analog chip automated placement method provided in this embodiment of the invention is executed by an analog chip automated placement device, which can be configured in a computer. The computer can be a local computer or a cloud computer. The local computer can be a computer, tablet, etc., and no specific limitation is made here.

[0146] First, step S21 is executed to obtain the target information of the simulation chip to be laid out. The target information may include target constraint information, target netlist information, symmetry information of each device in the simulation chip to be laid out, and size information of each target layout agent.

[0147] Target constraint information may include target placement boundary information and DRC rule information for the simulated chip to be placed. Target placement boundary information can be determined based on the size of the simulated chip and can be represented by a placement bounding box. Target placement boundary information can be used for boundary bounce. DRC rule information may include design rule checks, electrical rule checks, and short-circuit checks.

[0148] The target netlist information can include the required connection relationships between the devices in the simulation chip to be laid out. The symmetry information of the devices in the simulation chip to be laid out refers to which devices in the simulation chip have symmetrical relationships and the axis of symmetry. The size information of the devices in the simulation chip to be laid out refers to the width, height and other information of each device in the target symmetry information.

[0149] Furthermore, by utilizing the target information, the target layout environment of the simulation chip to be laid out, the target layout agents corresponding to the simulation chip to be laid out, and their initial states can be determined.

[0150] The target layout environment can be determined by target information, which may include target constraint information, target netlist information, symmetry information of each device in the simulation chip to be laid out, and size information of each target layout agent.

[0151] Understandably, each target placement agent is used to represent one or more devices in the simulation chip to be placed. When a target placement agent represents one device in the simulation chip, it means that there are no other devices in the simulation chip that are symmetrical to that device. When a target placement agent represents multiple devices in the simulation chip, it means that these devices are symmetrical. In other words, based on the symmetry information of the devices in the simulation chip, at least two devices in the simulation chip that have a symmetrical relationship can be used as one target placement agent, and a single device in the simulation chip that does not have a symmetrical relationship can be used as another target placement agent.

[0152] Furthermore, the initial state of each target layout agent can be determined based on the target constraint information. The initial state of each target layout agent can include the initial position information of each target layout agent, the initial overlap area information between each target layout agent and other target layout agents, the initial wireability information, etc. Therefore, the initial position information of each target layout agent can be directly determined as the same position information that satisfies the target layout boundary information in the target constraint information. That is, the layable region in the simulation chip to be laid out is determined according to the target constraint information, and the initial position information of each target layout agent is determined as the same position information in the layable region.

[0153] The initial overlap area information for each target layout agent can be determined based on the initial position and size information of each target layout agent. The initial wiredability information for each target layout agent can be determined by the half-circumference of the signal line obtained by the router.

[0154] The size information of each target layout agent can be determined based on the size information of the device corresponding to the target layout agent. For example, if there is only one device corresponding to the target layout agent, the size of the target layout agent is equal to the size information of the corresponding device. If there are multiple devices corresponding to the target layout agent, the size of the target layout agent can be determined based on the axis of symmetry of the corresponding device and the size information of the corresponding device.

[0155] Then, step S22 is executed, where the initial state of each target layout agent is input into the simulated chip automated layout model configured within it, to obtain the predicted action information for each target layout agent. The number of target layout agents can be N, and their structural parameters are θ. 1 ,θ 2 ,…,θ N The states of each target layout agent can be represented as o 1 ,o 2 ,…,o N The actions of each target layout agent are a. 1,a 2 ,…,a N The action of each target layout agent can be determined through the corresponding target layout agent, i.e., a 1 ~π(·|o 1 ;θ 1 ), a 2 ~π(·|o 2 ;θ 2 ), ..., a N ~π(·|o N ;θ N ), π(·|o 1 ;θ 1 ),π(·|o 2 ;θ 2 ),…,π(·|o N ;θ N ) represent the 1st, 2nd, ..., Nth target layout agents respectively.

[0156] Finally, execute step S23, as follows: Figure 6 As shown, each target layout agent interacts with the target layout environment with its corresponding predicted action information, thereby obtaining the final state of each target layout agent and completing the automated layout of the simulated chip to be laid out.

[0157] The automated placement method for analog chips provided in this embodiment of the invention first acquires the target information of the analog chip to be placed, and based on the target information, determines the target placement environment of the analog chip, the corresponding target placement agents and their initial states; then, the initial state of each target placement agent is input into the automated placement model of the analog chip configured within it to obtain the predicted action information of each target placement agent; finally, based on each target placement agent, the corresponding predicted action information is interacted with the target placement environment to complete the automated placement of the analog chip to be placed. This placement method utilizes the automated placement model of the analog chip configured within each target placement agent to synchronously place each device in the analog chip to be placed, which can improve the efficiency and effect of subsequent analog chip placement. It can obtain a placement result with performance comparable to manual placement within milliseconds without requiring a large amount of placement data, thereby achieving automated placement and facilitating subsequent analog chip routing, thus providing convenience for the rapid production and mass application of analog chips.

[0158] like Figure 7 As shown, based on the above embodiments, this embodiment of the invention provides a simulated chip automated layout model training device, comprising:

[0159] The first information acquisition module 71 is used to acquire sample information of the analog chip sample, and based on the sample information, determine each sample layout agent corresponding to the analog chip sample, the sample layout environment of the analog chip sample, and the initial state of each sample layout agent; each sample layout agent is used to characterize one or more devices in the analog chip sample.

[0160] Network module 72 is used to input the initial state of each sample layout agent into the corresponding policy network to obtain the initial prediction action of each sample layout agent, and input the initial state and initial prediction action of each sample layout agent into the value network to obtain the value result corresponding to each sample layout agent.

[0161] The loss function calculation module 73 is used to interact with the sample layout environment based on each sample layout agent, calculate the total reward value corresponding to each sample layout agent, and calculate the loss function based on the value result and total reward value corresponding to each sample layout agent.

[0162] The iterative training module 74 is used to iteratively update the structural parameters of each policy network and value network based on the loss function, and to use each trained policy network as a simulated chip automated placement model configured in a target placement intelligent body.

[0163] Based on the above embodiments, the simulated chip automated layout model training device provided in this embodiment of the invention includes sample constraint information, sample netlist information, symmetry information of each device in the simulated chip sample, and size information of each sample layout agent.

[0164] The first information acquisition module is specifically used for:

[0165] Based on the symmetry information of each device in the simulated chip sample, at least two devices with symmetric relationships in the simulated chip sample are used as a sample layout agent, and a single device without symmetric relationships in the simulated chip sample is used as a sample layout agent.

[0166] Based on the sample constraint information, the sample netlist information, and the size information of each sample layout agent, the sample layout environment is determined, and based on the sample constraint information, the initial state of each sample layout agent is determined.

[0167] Based on the above embodiments, the loss function calculation module of the simulated chip automated layout model training device provided in this embodiment of the invention is specifically used for:

[0168] Based on each sample layout agent, the corresponding initial prediction action is interacted with the sample layout environment to obtain the updated state of each sample layout agent.

[0169] For any sample layout agent, based on the update state and size information of each sample layout agent, calculate the distance information, overlap area information and wiredability information between the sample layout agent and other sample layout agents respectively.

[0170] The total reward value is calculated based on the distance information, overlap area information, and wiredability information corresponding to each sample layout agent.

[0171] Based on the above embodiments, the simulated chip automated layout model training device provided in this embodiment of the invention, wherein the loss function calculation module is further specifically used for:

[0172] Determine the sequence of intersection points within the overlapping region between any sample layout agent and any other sample layout agent;

[0173] The three adjacent intersection points in the intersection point sequence are taken as a group of triangles, and the total area of ​​all triangles in the overlapping area is used as the overlapping area information between any sample layout agent and any other sample layout agent.

[0174] Based on the above embodiments, the simulated chip automated layout model training device provided in this embodiment of the invention includes a value network comprising a first-layer perceptron and a second-layer perceptron; the network module is specifically used for:

[0175] The initial state and initial prediction action of each sample layout agent are input into the first layer perceptron to obtain the perception results of each sample layout agent.

[0176] For any sample layout agent, based on the perception results of each sample layout agent, an attention mechanism is used to calculate the attention features between the any sample layout agent and other sample layout agents.

[0177] The perception result and corresponding attention features of any sample layout agent are input into the second-layer perceptron to obtain the value result corresponding to any sample layout agent.

[0178] Specifically, the functions of each module in the simulated chip automated layout model training device provided in this embodiment of the invention correspond one-to-one with the operation flow of each step in the above method-like embodiments, and the achieved effects are also the same. For details, please refer to the above embodiments, and this will not be repeated in this embodiment of the invention.

[0179] like Figure 8As shown, based on the above embodiments, this embodiment of the invention also provides an automated placement device for analog chips, comprising:

[0180] The second information acquisition module 81 is used to acquire target information of the simulation chip to be laid out, and based on the target information, determine each target layout agent corresponding to the simulation chip to be laid out, the target layout environment of the simulation chip to be laid out, and the initial state of each target layout agent; each target layout agent is used to characterize one or more devices in the simulation chip to be laid out.

[0181] The action prediction module 82 is used to input the initial state of each target layout agent into the simulated chip automated layout model configured therein, so as to obtain the predicted action information of each target layout agent.

[0182] The automated layout module 83 is used to interact with the target layout environment based on the corresponding predicted action information of each target layout agent to complete the automated layout of the simulation chip to be laid out.

[0183] Based on the above embodiments, the automated placement device for analog chips provided in this embodiment of the invention includes target constraint information, target netlist information, symmetry information of each device in the analog chip to be placed, and size information of each target placement agent; the second information acquisition module is specifically used for:

[0184] Based on the symmetry information of each device in the simulation chip to be laid out, at least two devices in the simulation chip to be laid out that have a symmetric relationship are taken as a target layout agent, and a single device in the simulation chip to be laid out that does not have a symmetric relationship is taken as a target layout agent.

[0185] Based on the target constraint information, the target netlist information, and the size information of each target layout agent, the target layout environment is determined, and based on the target constraint information, the initial state of each target layout agent is determined.

[0186] Based on the above embodiments, the second information acquisition module in the analog chip automated placement device provided in this embodiment of the invention is further specifically used for:

[0187] The initial position information of each target layout agent is determined to be the same position information that satisfies the target layout boundary information.

[0188] Specifically, the functions of each module in the analog chip automated placement device provided in this embodiment of the invention correspond one-to-one with the operation flow of each step in the above method-like embodiments, and the achieved effects are also the same. For details, please refer to the above embodiments, and this will not be repeated in this embodiment of the invention.

[0189] Figure 9 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 9 As shown, the electronic device may include a processor 910, a communications interface 920, a memory 930, and a communication bus 940, wherein the processor 910, the communications interface 920, and the memory 930 communicate with each other via the communication bus 940. The processor 910 can call logic instructions in the memory 930 to execute the analog chip automated placement model training method or the analog chip automated placement method provided in the above embodiments.

[0190] Furthermore, the logical instructions in the aforementioned memory 930 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0191] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the analog chip automated placement model training method or the analog chip automated placement method provided in the above embodiments.

[0192] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the analog chip automated placement model training method or the analog chip automated placement method provided in the above embodiments.

[0193] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0194] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0195] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for training an automated placement model for a simulated chip, characterized in that, include: The sample information of the simulated chip sample is obtained, and based on the sample information, the sample layout agents corresponding to the simulated chip sample, the sample layout environment of the simulated chip sample, and the initial state of each sample layout agent are determined; each sample layout agent is used to characterize one or more devices in the simulated chip sample. The initial state of each sample layout agent is input into the corresponding policy network to obtain the initial prediction action of each sample layout agent. The initial state and initial prediction action of each sample layout agent are then input into the value network to obtain the value result corresponding to each sample layout agent. Based on each sample layout agent, the corresponding initial prediction action is interacted with the sample layout environment to calculate the total reward value corresponding to each sample layout agent. Based on the value result and total reward value corresponding to each sample layout agent, the loss function is calculated. Based on the loss function, the structural parameters of each policy network and value network are iteratively updated, and each trained policy network is used as a simulated chip automated placement model configured in a target placement intelligent body. The sample information includes sample constraint information, sample netlist information, symmetry information of each device in the simulated chip sample, and size information of each sample layout agent; the step of determining each sample layout agent corresponding to the simulated chip sample, the sample layout environment of the simulated chip sample, and the initial state of each sample layout agent based on the sample information includes: Based on the symmetry information of each device in the simulated chip sample, at least two devices with symmetric relationships in the simulated chip sample are used as a sample layout agent, and a single device without symmetric relationships in the simulated chip sample is used as a sample layout agent. Based on the sample constraint information, the sample netlist information, and the size information of each sample layout agent, the sample layout environment is determined, and based on the sample constraint information, the initial state of each sample layout agent is determined. The agent based on each sample layout interacts with the sample layout environment with its corresponding initial prediction action to calculate the total reward value for each sample layout agent, including: Based on each sample layout agent, the corresponding initial prediction action is interacted with the sample layout environment to obtain the updated state of each sample layout agent. For any sample layout agent, based on the update state and size information of each sample layout agent, calculate the distance information, overlap area information and wiredability information between the sample layout agent and other sample layout agents respectively. The total reward value is calculated based on the distance information, overlap area information, and wiredability information corresponding to each sample layout agent.

2. The method for training an automated layout model for analog chips according to claim 1, characterized in that, The overlapping area information is determined based on the following steps: Determine the sequence of intersection points within the overlapping region between any sample layout agent and any other sample layout agent; The three adjacent intersection points in the intersection point sequence are taken as a group of triangles, and the total area of ​​all triangles in the overlapping area is used as the overlapping area information between any sample layout agent and any other sample layout agent.

3. The method for training an automated layout model for an analog chip according to any one of claims 1-2, characterized in that, The value network includes a first-layer perceptron and a second-layer perceptron; the process of inputting the initial state and initial prediction action of each sample layout agent into the value network to obtain the value result corresponding to each sample layout agent includes: The initial state and initial prediction action of each sample layout agent are input into the first layer perceptron to obtain the perception results of each sample layout agent. For any sample layout agent, based on the perception results of each sample layout agent, an attention mechanism is used to calculate the attention features between the any sample layout agent and other sample layout agents. The perception result and corresponding attention features of any sample layout agent are input into the second-layer perceptron to obtain the value result corresponding to any sample layout agent.

4. A method for automated placement of analog chips, characterized in that, include: Obtain target information of the simulated chip to be laid out, and based on the target information, determine each target layout agent corresponding to the simulated chip to be laid out, the target layout environment of the simulated chip to be laid out, and the initial state of each target layout agent. Each target layout agent is used to characterize one or more devices in the simulated chip to be laid out; The initial state of each target placement agent is input into the simulated chip automated placement model configured therein to obtain the predicted action information of each target placement agent; the simulated chip automated placement model is trained based on the simulated chip automated placement model training method as described in any one of claims 1-3. Based on each target layout agent, the corresponding predicted action information is interacted with the target layout environment to complete the automated layout of the simulated chip to be laid out.

5. The automated placement method for analog chips according to claim 4, characterized in that, The target information includes target constraint information, target netlist information, symmetry information of each device in the simulation chip to be laid out, and size information of each target layout agent. The step of determining, based on the target information, each target layout agent corresponding to the simulated chip to be laid out, the target layout environment of the simulated chip to be laid out, and the initial state of each target layout agent includes: Based on the symmetry information of each device in the simulation chip to be laid out, at least two devices in the simulation chip to be laid out that have a symmetric relationship are taken as a target layout agent, and a single device in the simulation chip to be laid out that does not have a symmetric relationship is taken as a target layout agent. Based on the target constraint information, the target netlist information, and the size information of each target layout agent, the target layout environment is determined, and based on the target constraint information, the initial state of each target layout agent is determined.

6. The automated placement method for analog chips according to claim 5, characterized in that, The target constraint information includes target layout boundary information, and the initial state of each target layout agent includes initial position information; determining the initial state of each target layout agent based on the target constraint information includes: The initial position information of each target layout agent is determined to be the same position information that satisfies the target layout boundary information.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the analog chip automated placement model training method as described in any one of claims 1-3, or the analog chip automated placement method as described in any one of claims 4-6.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the analog chip automated placement model training method as described in any one of claims 1-3, or the analog chip automated placement method as described in any one of claims 4-6.

Images