Power system secondary circuit model file standardization error prevention checking method and device

Abstract

The application discloses a kind of power system secondary circuit model file standardization error prevention verification methods, obtain the secondary circuit model file of target power system to be verified;Establish the standardization wiring table of pre-set;The elements in standardization difference area are verified;The elements in standardization directional area are verified;The elements in standardization logic area are verified, and the application also discloses power system secondary circuit model file standardization error prevention verification device.The application aims at preventing the electrical system safety risk caused by power system secondary circuit model file error, improving the correctness of the secondary circuit model file of the power system to be verified, shortening engineering debugging time, enhancing system stability to solve the problem that existing power system secondary circuit model file verification function is not comprehensive, and verification means is single.

Description

Technical Field

[0001] This invention relates to the technical field of power system digitization, and in particular to a method for standardizing and preventing errors in power system secondary circuit model files, as well as a device for standardizing and preventing errors in power system secondary circuit model files. Background Technology

[0002] As the intelligence level of power systems gradually improves and their digitalization level significantly increases, the digitization of secondary circuit information in power systems is an inevitable requirement for the construction of digital grids, against the backdrop of new technologies such as the Internet of Things, artificial intelligence, and digital twins.

[0003] The secondary circuit model file of the power system is created in the early stage of the power system on-site construction and is mainly generated by integration tools. However, there may be situations where the on-site wiring is modified during the later stages of the power system construction. In order to ensure that the on-site power system secondary circuit model file remains consistent with the actual wiring throughout the entire life cycle of the project, the power system secondary circuit model file needs to be verified. The power system secondary circuit model file is in Extensible Markup Language (XML) format. The number of lines in a single substation XML file can exceed 100,000 lines. Manual verification is very difficult and carries the possibility of errors and security risks, which bring risks to the subsequent digital operation and maintenance of the power system.

[0004] Traditional methods of manually verifying power system secondary circuit model files based on model text are difficult, inaccurate, and inefficient. Existing methods for verifying model files generally involve extracting data features from the model file and performing syntactic and semantic checks on these features. Alternatively, they may be based on industry standard rules to verify the correctness, consistency, and completeness of the model file.

[0005] The above verification methods usually require manual intervention, which can lead to human error or subjective judgment. Although there are some automated scripts, tools or software for model file verification, their automation capabilities are still limited. At the same time, the verification of substation secondary circuit model files is usually carried out once or periodically, which means that changes and updates to the model files may not be detected and corrected in time during the verification process, resulting in a delay between the verification results and the actual state.

[0006] As complex model files serve as the data source for advanced substation applications, their accuracy becomes paramount. However, current model verification methods remain in a traditional and fragmented state, lacking comprehensive verification functions and employing limited methods. Therefore, there is an urgent need to research a verification method that can comprehensively check the data of substation secondary circuit model files throughout the entire lifecycle of substation model creation, modification, editing, import, and updates. This would improve the accuracy of the substation data source, reduce frequent updates to advanced applications due to model file changes, shorten the engineering commissioning and operation cycle, and enhance the stability of substation system operation. Summary of the Invention

[0007] The purpose of this invention is to address the aforementioned problems in the prior art by providing a method for standardizing and verifying power system secondary circuit model files to prevent errors, and also to provide a device for standardizing and verifying power system secondary circuit model files to prevent errors.

[0008] The above-mentioned objectives of the present invention are achieved through the following technical means:

[0009] A standardized method for preventing errors in power system secondary circuit model files includes the following steps:

[0010] Step 1: Obtain the secondary loop model file of the target power system to be verified. The secondary loop model file of the target power system to be verified is divided into a standardized difference region, a standardized orientation region, and a standardized logic region.

[0011] Step 2: Establish a pre-defined standardized wiring form;

[0012] Step 3: Compare and verify the elements in the standardized difference area of ​​the secondary circuit model file of the target power system with the contents of the standardized wiring table;

[0013] Step 4: Configure the orientation verification mode for the attributes of the elements in the standardized orientation area. The orientation verification mode can be either required, optional, 3D, label, or security measure. Perform orientation verification on the attributes of each element in the standardized orientation area.

[0014] Step 5: Perform general validation logic on the attributes of elements in the standardized logic area. The general validation logic includes connection relationship validation logic, board width summation validation logic, board terminal port quantity validation logic, and duplicate name validation logic.

[0015] As mentioned above, the standardized difference areas include: terminal block elements, pressure plate elements, terminal block terminal elements, and device terminal elements;

[0016] Standardized directional areas include: small room elements, cabinet elements, equipment elements, circuit board elements, circuit board port elements, circuit board terminal elements, circuit breaker elements, handle elements, button elements, component elements, device terminal elements, internal fiber optic connection elements, internal cable connection elements, inter-cabinet cable elements, fiber optic core elements, and cable core elements.

[0017] The standardized logic area includes: device elements, board elements, board port elements, board terminal elements, fiber optic connection elements within the cabinet, cable connection elements within the cabinet, cable elements between cabinets, fiber optic core elements, and cable core elements.

[0018] As mentioned above, the standardized wiring tables include: a standardized right terminal block wiring table, a standardized left terminal block wiring table, and a standardized pressure plate arrangement table;

[0019] The headers of the standardized right terminal block wiring table, from left to right, include the access circuit definition, internal wiring, terminal number, external wiring, and remarks.

[0020] The headers of the standardized left-side terminal block wiring table, from left to right, include the access circuit definition, external wiring, terminal number, internal wiring, and remarks, respectively.

[0021] The standardized pressure plate layout table arranges the pressure plate numbers and corresponding descriptions in the order of the actual standard pressure plate layout.

[0022] The comparison verification in step 3 as described above includes: verification of the standardization differences of the standardized right terminal block wiring table, verification of the standardization differences of the standardized left terminal block wiring table, and verification of the standardization differences of the standardized pressure plate arrangement table.

[0023] The standardization difference verification for both the standardized right terminal block wiring table and the standardized left terminal block wiring table includes:

[0024] Compare the differences between the contents of the loop definition column in the header of the standardized right terminal block wiring table and the attribute values ​​of the terminal block terminal description of the terminal block terminal element in the target power system secondary loop model file;

[0025] Compare the differences between the contents of the internal wiring column in the header of the standardized right terminal block wiring table and the attribute values ​​of the cabinet terminals of the terminal block terminal elements in the target power system secondary circuit model file;

[0026] Compare the differences between the content in the terminal number column of the header of the standardized right terminal block wiring table and the attribute value of the terminal block terminal number of the terminal block terminal element in the target power system secondary circuit model file;

[0027] Compare the differences between the contents of the external wiring column in the header of the standardized right terminal block wiring table and the attribute values ​​of the external terminals of the terminal block terminal elements in the target power system secondary circuit model file;

[0028] Compare the differences between the content in the remarks column of the header of the standardized right terminal block wiring table and the attribute value of the terminal block terminal type of the terminal block terminal element in the target power system secondary circuit model file;

[0029] The order of terminal numbers in the standardized right terminal block wiring table is compared with the order of terminal block terminal attributes in the terminal block terminal element of the target power system secondary circuit model file.

[0030] Standardization discrepancy verification of the standardized pressure plate layout table includes:

[0031] Compare the attribute values ​​of the pressure plate numbers in the standardized pressure plate arrangement table with the pressure plate numbers of the pressure plate elements in the target power system secondary circuit model file;

[0032] A comparison was made between the attribute values ​​of the pressure plate descriptions in the standardized pressure plate layout table and the pressure plate element descriptions in the secondary loop model file.

[0033] A comparison was made between the order of the pressure plate numbers in the standardized pressure plate arrangement table and the order of the pressure plate number attributes in the target power system secondary circuit model file.

[0034] As described above, step 4 involves performing orientation validation on the attributes of each element in the standardized orientation region, including:

[0035] Required attributes must not be empty; an alarm will be triggered if an attribute is empty.

[0036] 3D, label, and security measures are three directional verification modes with specified function configurations. When a specified function configuration is selected, the corresponding attribute of this function configuration must not be empty; otherwise, an alarm will be triggered.

[0037] As mentioned above, the connection relationship verification logic in step 5 is as follows: the connection relationship must satisfy the condition that board terminal element A is connected to board terminal element B, then board terminal element B and board terminal element A must be connected.

[0038] As mentioned above, the logic for summing and verifying the board width is: the width of the device element is equal to the sum of the widths of the next level board elements.

[0039] As mentioned above, the logic for verifying the number of board terminal ports is as follows: each board element with the same board model attribute contains the same number of board terminal elements and board port elements.

[0040] As mentioned above, the duplicate name verification logic includes: the uniqueness of the device name attribute of the device element, the uniqueness of the number attribute of the board terminal element, and the uniqueness of the inter-cabinet cable number attribute of the inter-cabinet cable element.

[0041] A standardization and error-proofing verification device for power system secondary circuit model files includes:

[0042] The secondary loop model file acquisition module is used in step 1 above;

[0043] A standardized wiring form creation module is used for step 2 above;

[0044] The standardized difference region verification module is used in step 3 above.

[0045] A standardized directional verification module is used in step 4 above;

[0046] The standardized logical region verification module is used in step 5 above.

[0047] Compared with the prior art, the present invention has the following advantages:

[0048] This invention aims to prevent electrical system safety risks caused by errors in power system secondary circuit model files, improve the accuracy of power system secondary circuit model files to be verified, shorten engineering commissioning time, and enhance system stability, thereby solving the problems of incomplete verification functions and single verification methods in existing power system secondary circuit model files. Attached Figure Description

[0049] Figure 1 This is a flowchart of the present invention;

[0050] Figure 2 This is a schematic diagram of the standardized right terminal block wiring table provided in an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of the standardized left terminal block wiring table provided in an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of the standardized pressure plate arrangement table provided in the embodiments of the present invention;

[0053] Figure 5 This is a partial schematic diagram of the standardized directional region element attribute configuration table provided in an embodiment of the present invention;

[0054] Figure 6 This is a schematic diagram of the directional verification provided in an embodiment of the present invention. Detailed Implementation

[0055] To facilitate understanding and implementation of the present invention by those skilled in the art, the present invention will be further described in detail below with reference to embodiments. It should be understood that the embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0056] Example 1:

[0057] Figure 1 This is a flowchart illustrating the implementation of a standardized anti-misoperation verification method for secondary circuit model files in a power system, provided in an embodiment of the present invention. (Refer to...) Figure 1 Specifically, it includes the following steps:

[0058] Step 1: Obtain the secondary circuit model file of the target power system to be verified.

[0059] In this embodiment, the secondary circuit model file of the target power system is a description file based on XML format that describes the physical information of the secondary circuit of the power system.

[0060] The hierarchical structure of the secondary circuit model file contains power system elements; power system elements include Region, Cubicle, Unit, Board, Port, Terminal, Terminal Block, CTerminal, AirSwitch, Strap, ChangeSwitch, ResetButton, Component, DTerminal, InCore (in-cabinet fiber optic connection), InWire (in-cabinet cable connection), Cable (between cabinets), Core (fiber optic core), and Wire (cable core).

[0061] According to the above hierarchical architecture, the secondary loop model file can be divided into three regions: the standardized difference region, the standardized orientation region, and the standardized logic region.

[0062] Standardized difference areas correspond to standardized difference verification, including terminal block element TerminalBlock, pressure plate element Strap, terminal block terminal element CTerminal, and device terminal element DTerminal.

[0063] Standardized orientation areas correspond to standardized orientation verification, including the following elements: Region, Cubicle, Unit, Board, Port, Terminal, AirSwitch, ChangeSwitch, ResetButton, Component, DTerminal, InCore (in-cabinet fiber optic connection), InWire (in-cabinet cable connection), Cable (between cabinets), Core (fiber optic core), and Wire (cable core).

[0064] The standardized logic area corresponds to standardized logic verification, including the device element Unit, board element Board, board port element Port, board terminal element Terminal, in-cabinet fiber optic connection element InCore, in-cabinet cable connection element InWire, inter-cabinet cable element Cable, fiber optic core element Core, and cable core element Wire.

[0065] Step 2: As Figure 2-4 As shown, a pre-defined standardized wiring table is established.

[0066] Standardized wiring diagrams include standardized terminal block wiring diagrams and standardized pressure plate arrangement diagrams.

[0067] The standardized terminal block wiring table includes a standardized right terminal block wiring table and a standardized left terminal block wiring table.

[0068] The headers of the standardized right terminal block wiring table, from left to right, include the access circuit definition, internal wiring, terminal number, external wiring, and remarks.

[0069] The headers of the standardized left-side terminal block wiring table, from left to right, include the access circuit definition, external wiring, terminal number, internal wiring, and remarks, respectively.

[0070] The standardized right terminal block wiring table and the standardized left terminal block wiring table contain the same content, only the column header order is different.

[0071] The standardized pressure plate layout table can arrange the pressure plate numbers and corresponding pressure plate descriptions in the order of the actual standard pressure plate layout.

[0072] Step 3: Compare the elements in the standardized difference area of ​​the target power system secondary circuit model file with the contents of the standardized wiring table in Step 2 to achieve standardized difference verification.

[0073] Step 3.1, Standardization difference verification of the standardized right terminal block wiring table includes:

[0074] Compare the differences between the contents of the loop definition column in the header of the standardized right terminal block wiring table and the attribute values ​​of the terminal block terminal description desc of the terminal block terminal element CTerminal in the target power system secondary loop model file;

[0075] Compare the contents of the internal wiring column in the header of the standardized right terminal block wiring table with the attribute value of the cabinet terminal oppositeIn1 of the terminal block terminal element CTerminal in the target power system secondary circuit model file.

[0076] Compare the differences between the content in the terminal number column of the header of the standardized right terminal block wiring table and the attribute value of the terminal block terminal number name of the terminal block terminal element CTerminal in the target power system secondary circuit model file;

[0077] Compare the contents of the external wiring column in the header of the standardized right terminal block wiring table with the attribute value of the external terminal oppositeOut1 of the terminal block terminal element CTerminal in the target power system secondary circuit model file.

[0078] Compare the differences between the content in the remarks column of the header of the standardized right terminal block wiring table and the attribute value of the terminal block terminal type of the terminal block terminal element CTerminal in the target power system secondary circuit model file;

[0079] The order of terminal numbers in the standardized right terminal block wiring table is compared with the order of terminal name attributes in the terminal block CTerminal element of the target power system secondary circuit model file.

[0080] Step 3.2, Standardization difference verification of the standardized left terminal block wiring table includes:

[0081] Compare the differences between the contents of the loop definition column in the header of the standardized left terminal block wiring table and the attribute values ​​of the terminal block terminal description desc of the terminal block terminal element CTerminal in the target power system secondary loop model file;

[0082] Compare the contents of the internal wiring column in the header of the standardized left terminal block wiring table with the attribute value of the cabinet terminal oppositeIn1 of the terminal block terminal element CTerminal in the target power system secondary circuit model file.

[0083] Compare the differences between the content in the terminal number column of the header of the standardized left terminal block wiring table and the attribute value of the terminal block terminal number name of the terminal block terminal element CTerminal in the target power system secondary circuit model file;

[0084] Compare the contents of the external wiring column in the header of the standardized left terminal block wiring table with the attribute value of the external terminal oppositeOut1 of the terminal block terminal element CTerminal in the target power system secondary circuit model file.

[0085] Compare the differences between the content in the remarks column of the header of the standardized left terminal block wiring table and the attribute value of the terminal block terminal type of the terminal block terminal element CTerminal in the target power system secondary circuit model file;

[0086] The order of terminal numbers in the table of standardized left terminal block wiring is compared with the order of terminal name attributes of the terminal block terminal CTerminal element in the target power system secondary circuit model file.

[0087] Step 3.3, the standardization difference verification of the standardized pressure plate layout table includes:

[0088] A comparison is made between the pressure plate numbers in the standardized pressure plate arrangement table and the attribute value of the pressure plate number name of the pressure plate element Strap in the target power system secondary circuit model file;

[0089] A comparison was made between the attribute values ​​of the pressure plate description in the standardized pressure plate layout table and the pressure plate description desc of the pressure plate element Strap in the secondary loop model file.

[0090] The order of the pressure plate numbers in the standardized pressure plate arrangement table is compared with the order of the name attribute of the pressure plate number in the Strap element of the target power system secondary circuit model file.

[0091] Step 4: Implement standardized orientation verification, construct a standardized orientation area element attribute configuration table, configure the orientation verification mode for the attributes of elements in the standardized orientation area, and the orientation verification mode can be required, optional, three-dimensional, label, or safety measure. Perform orientation verification on the attributes of each element in the standardized orientation area.

[0092] In the configuration of the five targeted verification modes: required, optional, 3D, tag, and security measures:

[0093] All required attributes must be non-empty; an alarm will be triggered if an attribute is empty.

[0094] The optional attributes can be empty or not;

[0095] 3D, label, and security measures are three function-specific configurations for targeted verification modes. When a specific function configuration is selected, the corresponding attribute of this function configuration must not be empty; otherwise, an alarm will be triggered. The attributes of other unselected function configurations can be empty or not empty.

[0096] For example, the system validates the attributes of elements within a standardized directional region of a selected directional validation mode. For instance, if attribute A of an element is configured as "3D," selecting "3D" as the directional validation mode will validate whether the attribute of all elements with "3D" as the directional validation mode has a value. If no value is found, a validation result warning is issued.

[0097] In this embodiment, as Figure 5 The diagram shown is a partial schematic of the standardized directional region element attribute configuration table provided in this embodiment of the invention. This table is used to self-configure the attributes of elements in the standardized directional region of the secondary loop model file of the target power system to be verified, including:

[0098] The name attribute of the Region element is defined as required, the desc attribute as optional, the area attribute as optional, and the voltage level attribute as optional.

[0099] The Cubicle element of the cabinet is defined as follows: the name attribute is required, the desc attribute is optional, the type attribute is three-dimensional, the class attribute is required, the manufacturer attribute is optional, and the color attribute is optional.

[0100] The device element Unit has the following parameters: name (number), desc (description), iedName (device name), type (model), class (type), manufacturer (manufacturer), height (height), and width (width).

[0101] The Board element is defined as follows: the name attribute is required, the desc attribute is optional, the type attribute is three-dimensional, the class attribute is optional, the slot attribute is three-dimensional, the height attribute is three-dimensional, and the width attribute is three-dimensional.

[0102] The name attribute of the Port element of the board is defined as required, the desc attribute is defined as optional, the direction attribute is defined as three-dimensional, the plug attribute is defined as three-dimensional, the usage attribute is defined as optional, and the opposite port attribute is defined as three-dimensional.

[0103] The name attribute of the terminal element on the board is defined as required, the desc attribute is defined as optional, the class attribute is defined as optional, and the opposite port attribute is defined as optional.

[0104] For the AirSwitch element, the name attribute is defined as required, the desc attribute as optional, the type attribute as three-dimensional, the class attribute as optional, the manufacturer attribute as optional, the model attribute as required, and the space attribute as three-dimensional.

[0105] The name attribute of the handle element Strap is defined as required, the desc attribute as optional, the type attribute as three-dimensional, the class attribute as optional, the manufacturer attribute as optional, the model attribute as required, and the space attribute as three-dimensional.

[0106] The ResetButton element is defined as follows: the name attribute is required, the desc attribute is optional, the type attribute is 3D, the class attribute is optional, the manufacturer attribute is optional, the model attribute is required, and the space attribute is 3D.

[0107] The component element's name attribute is defined as required, the desc attribute as optional, the type attribute as three-dimensional, the class attribute as optional, the manufacturer attribute as optional, the model attribute as required, and the space attribute as three-dimensional.

[0108] The device terminal element DTerminal has the following attributes: name (number), desc (description), matchTer (pairing terminal), djTer (short-circuit terminal), and opposite port (opposite).

[0109] The name attribute of the fiber optic connection element InCore in the cabinet is defined as required, the portA attribute is defined as optional, the portB attribute is defined as optional, and the type attribute is defined as optional.

[0110] The number attribute nam of the InWire cable connection element in the cabinet is defined as required, the terminal A attribute terminalA is defined as optional, the terminal B attribute terminalB is defined as optional, the model attribute type is defined as optional, the loop description attribute loopFun is defined as optional, and the loop number attribute loopNum is defined as optional.

[0111] The cable element in the cabinet is defined as follows: the name attribute is required, the desc attribute is optional, the coreNum attribute is optional, the length attribute is optional, the cubeA attribute for cable connection to cabinet A is required, the cubeB attribute for cable connection to cabinet B is required, and the type attribute is optional.

[0112] The no attribute of the fiber optic core element in the cabinet is defined as mandatory, the reserve attribute is defined as optional, the portA path attribute of connection port A is defined as mandatory, and the portB path attribute of connection port B is defined as mandatory.

[0113] The following parameters are defined for the Wire element of the inter-cabinet cable core: the number no is required, the reserve attribute reserve is optional, the terminal A path attribute terminalA is required, the terminal B path attribute terminalB is required, the loop description attribute loopFun is optional, the loop number attribute loopNum is optional, and the loop type attribute loopType is optional.

[0114] In this embodiment, as Figure 6 As shown in the schematic diagram of the directional verification provided in this embodiment of the invention, the directional verification of the attributes of each element in the standardized directional region includes:

[0115] Because the targeted verification mode is self-configurable, it can be flexibly configured and adjusted according to specific environments and needs, and new targeted verification modes can be added. It can adapt to different work scenarios and changing requirements, improving the flexibility and adaptability of the application. Resources and functions can be flexibly added or removed to meet the needs of different scales and requirements, further simplifying the management and maintenance process and reducing management complexity.

[0116] Step 5: Perform general validation logic on the attributes of elements in the standardized logical area. The general validation logic includes connection relationship validation logic, board width summation validation logic, board terminal port quantity validation logic, and name duplication validation logic.

[0117] The connection relationship verification logic can be divided into mutual verification of connection terminals, mutual verification of mating terminals, and mutual verification of short-circuit terminals.

[0118] In the secondary circuit model file of the power system, the connection relationship must satisfy the rule that if board terminal element A is connected to board terminal element B, then board terminal element B must be connected to board terminal element A. This rule can be used to verify the correctness of the connection relationship.

[0119] The `opposite` property of board terminal element A will contain the path to the other board terminal element B it connects to, in the format "Region name.Cubicle name.Unit name.Board name.Terminal name". Similarly, the `opposite` property of board terminal element B will contain the path to the other board terminal element A it connects to, in the format "Region name.Cubicle name.Unit name.Board name.Terminal name". In other words, the value entered in the `opposite` property of board terminal A corresponds to board terminal element B, indicating that board terminal element A is connected to board terminal element B, and the value entered in the `opposite` property of board terminal element B corresponds to board terminal element A, indicating that board terminal element B is connected to board terminal element A. A connection where board terminal element A is connected to board terminal element B and board terminal element B is connected to board terminal element A is considered correct. If only board terminal element A is connected to board terminal element B and board terminal element B is not connected to board terminal element A, it is considered an error and an alarm is triggered.

[0120] The board width summation and verification logic is as follows: when the device width value of the device element Unit is 1, the sum of the widths of the board elements at the next level of this device element is equal to 84T, where 1T = 44.45mm; when the device width value of the device element Unit is 1 / 2, the sum of the widths of the board elements at the next level of this device element is equal to 42T; when the device width value of the device element Unit is 1 / 3, the sum of the widths of the board elements at the next level of this device element is equal to 28T. This rule can be used to verify the correctness of the board width.

[0121] The logic for verifying the number of board terminal ports is as follows: If multiple board elements (Board) in the power system secondary circuit model file have the same board model attribute (type), then the number of board terminal elements (Terminal) and board port elements (Port) contained in their board elements (Board) must be the same. This rule can be used to verify the correctness of the number of board terminal ports.

[0122] The duplicate name verification logic can be divided into duplicate name verification for the device name attribute IedName of the device element (Unit), duplicate name verification for the number attribute name of the board terminal element (Terminal), and duplicate name verification for the inter-cabinet cable number attribute Cable of the inter-cabinet cable element (InWire). The device name attribute IedName of the device element, the number attribute name of the board terminal element, and the inter-cabinet cable number attribute Cable of the inter-cabinet cable element in the power system secondary circuit model file must be unique. Through this rule, the correctness of duplicate names can be verified.

[0123] This invention follows the principle of standardized verification and is applied to the whole-system management process of secondary circuit models at power plant terminals. It reduces the difficulty of verifying power system secondary circuit model files, the verification results are less affected by subjective factors, the verification accuracy is high, and the target power system secondary circuit model file after verification is consistent with the actual field data, effectively ensuring the correctness of power system secondary circuit model file data and realizing safe, stable, standardized, and efficient operation and maintenance of power grid automation data.

[0124] Example 2:

[0125] A standardization and error prevention verification device for secondary circuit model files of power systems, comprising:

[0126] The secondary loop model file acquisition module is used to implement step 1 of embodiment 1;

[0127] A standardized wiring form creation module is used to implement step 2 of embodiment 1;

[0128] The standardized difference region verification module is used to implement step 3 of Example 1.

[0129] A standardized orientation verification module is used to implement step 4 of embodiment 1;

[0130] The standardized logical region verification module is used to implement step 5 of embodiment 1.

[0131] Example 3:

[0132] A computer-readable recording medium records the procedure described in steps 1-5 of embodiment 1.

[0133] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for standardizing and preventing errors in power system secondary circuit model files, characterized in that, Includes the following steps: Step 1: Obtain the secondary loop model file of the target power system to be verified. The secondary loop model file of the target power system to be verified is divided into a standardized difference region, a standardized orientation region, and a standardized logic region. Step 2: Establish a pre-defined standardized wiring form; Step 3: Compare and verify the elements in the standardized difference area of ​​the secondary circuit model file of the target power system with the contents of the standardized wiring table; Step 4: Configure the orientation verification mode for the attributes of the elements in the standardized orientation area. The orientation verification mode can be either required, optional, 3D, label, or security measure. Perform orientation verification on the attributes of each element in the standardized orientation area. Step 5: Perform general validation logic on the attributes of elements in the standardized logical area. This general validation logic includes connection relationship validation, board width summation validation, board terminal port quantity validation, and name duplication validation. The standardized difference areas include: terminal block elements, pressure plate elements, terminal block terminal elements, and device terminal elements; The standardized directional areas include: small room elements, cabinet elements, equipment elements, board elements, board port elements, board terminal elements, circuit breaker elements, handle elements, button elements, component elements, device terminal elements, fiber optic connection elements inside the cabinet, cable connection elements inside the cabinet, cable elements between cabinets, fiber optic core elements, and cable core elements. The standardized logic area includes: device elements, board elements, board port elements, board terminal elements, fiber optic connection elements within the cabinet, cable connection elements within the cabinet, cable elements between cabinets, fiber optic core elements, and cable core elements.

2. The method for standardizing and preventing errors in power system secondary circuit model files according to claim 1, characterized in that, The standardized wiring tables include: a standardized right terminal block wiring table, a standardized left terminal block wiring table, and a standardized pressure plate arrangement table; The headers of the standardized right terminal block wiring table, from left to right, include the access circuit definition, internal wiring, terminal number, external wiring, and remarks. The headers of the standardized left-side terminal block wiring table, from left to right, include the access circuit definition, external wiring, terminal number, internal wiring, and remarks. The standardized pressure plate layout table arranges the pressure plate numbers and corresponding descriptions in the order of the actual standard pressure plate layout.

3. The method for standardizing and preventing errors in power system secondary circuit model files according to claim 2, characterized in that, The comparison verification in step 3 includes: standardization difference verification of the standardized right terminal block wiring table, standardization difference verification of the standardized left terminal block wiring table, and standardization difference verification of the standardized pressure plate arrangement table. The standardization difference verification for both the standardized right terminal block wiring table and the standardized left terminal block wiring table includes: Compare the differences between the contents of the loop definition column in the header of the standardized right terminal block wiring table and the attribute values ​​of the terminal block terminal description of the terminal block terminal element in the target power system secondary loop model file; Compare the differences between the contents of the internal wiring column in the header of the standardized right terminal block wiring table and the attribute values ​​of the cabinet terminals of the terminal block terminal elements in the target power system secondary circuit model file; Compare the differences between the content in the terminal number column of the header of the standardized right terminal block wiring table and the attribute value of the terminal block terminal number of the terminal block terminal element in the target power system secondary circuit model file; Compare the differences between the contents of the external wiring column in the header of the standardized right terminal block wiring table and the attribute values ​​of the external terminals of the terminal block terminal elements in the target power system secondary circuit model file; Compare the differences between the content in the remarks column of the header of the standardized right terminal block wiring table and the attribute value of the terminal block terminal type of the terminal block terminal element in the target power system secondary circuit model file; The order of terminal numbers in the standardized right terminal block wiring table is compared with the order of terminal block terminal attributes in the terminal block terminal element of the target power system secondary circuit model file. Standardization discrepancy verification of the standardized pressure plate layout table includes: Compare the attribute values ​​of the pressure plate numbers in the standardized pressure plate arrangement table with the pressure plate numbers of the pressure plate elements in the target power system secondary circuit model file; A comparison was made between the attribute values ​​of the pressure plate descriptions in the standardized pressure plate layout table and the pressure plate element descriptions in the secondary loop model file. A comparison was made between the order of the pressure plate numbers in the standardized pressure plate arrangement table and the order of the pressure plate number attributes in the target power system secondary circuit model file.

4. The method for standardizing and preventing errors in power system secondary circuit model files according to claim 3, characterized in that, Step 4, which involves performing orientation verification on the attributes of each element in the standardized orientation region, includes: Required attributes must not be empty; an alarm will be triggered if an attribute is empty. 3D, label, and security measures are three directional verification modes with specified function configurations. When a specified function configuration is selected, the corresponding attribute of this function configuration must not be empty; otherwise, an alarm will be triggered.

5. The method for standardizing and preventing errors in power system secondary circuit model files according to claim 4, characterized in that, The connection relationship verification logic in step 5 is as follows: the connection relationship must satisfy that board terminal element A is connected to board terminal element B, then board terminal element B and board terminal element A must be connected.

6. The method for standardizing and preventing errors in power system secondary circuit model files according to claim 5, characterized in that, The logic for summing and verifying the board width is as follows: the width of the device element is equal to the sum of the widths of the board elements at the next lower level.

7. The method for standardizing and preventing errors in power system secondary circuit model files according to claim 6, characterized in that, The logic for verifying the number of board terminal ports is as follows: each board element with the same board model attribute contains the same number of board terminal elements and board port elements.

8. The method for standardizing and preventing errors in power system secondary circuit model files according to claim 7, characterized in that, The duplicate name verification logic includes: the uniqueness of the device name attribute of the device element, the uniqueness of the number attribute of the board terminal element, and the uniqueness of the inter-cabinet cable number attribute of the inter-cabinet cable element.

9. A standardization and error-proofing verification device for power system secondary circuit model files, including: A secondary loop model file acquisition module is used to implement step 1 of claim 8; A standardized wiring form creation module is used to implement step 2 of claim 8; A standardized difference region verification module is used to implement step 3 of claim 8; A standardized orientation verification module is used to implement step 4 of claim 8; A standardized logical region verification module is used to implement step 5 of claim 8.

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