Architectures and methods for NAND memory operations

Abstract

In a method for reading a memory device including a first string of memory cells, a first verify voltage is applied to a gate terminal of a selected memory cell of the first string of memory cells during a pre-verify phase, wherein the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied to a gate terminal of at least one unprogrammed memory cell of the first string of memory cells. A second verify voltage is applied to the gate terminal of the selected memory cell of the first string of memory cells during a verify phase. A second bias voltage is applied to the gate terminal of the at least one unprogrammed memory cell of the first string of memory cells, wherein the second bias voltage is less than the first bias voltage.

Description

[0001] This application is a divisional application of Chinese patent application filed on December 15, 2020, with application number 202080003973.4 and entitled "Architecture and Method for NAND Memory Operation". Background Technology

[0002] Flash memory devices have recently experienced rapid development. They can retain stored data for extended periods without the application of voltage. Furthermore, flash memory devices offer relatively high read speeds and are easy to erase and rewrite. Therefore, flash memory devices are widely used in microcomputers, automated control systems, and other applications. To increase the bit density and reduce the bit cost of flash memory devices, three-dimensional (3D) NAND (Not AND) flash memory devices have been developed.

[0003] 3D NAND flash memory devices may include multiple strings of memory cells. Each string of memory cells may include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series. A method for verifying / reading a programmed memory cell of a 3D-NAND flash memory device may include a pre-pulse scheme (or stage) and a verification / read scheme (or stage). In the pre-pulse scheme, a pass voltage (such as 6.8 volts) may be applied to the word line (WL) of a memory cell in a selected string of memory cells, while the gate terminals of the TSG transistors may be turned on at unselected strings of memory cells. In the verification / read scheme, the pass voltage may be further maintained at unselected WLs in the selected strings of memory cells, and a verification voltage may be applied to the WL of selected memory cells in the selected strings of memory cells. Summary of the Invention

[0004] This disclosure describes embodiments of apparatus and methods generally relating to verifying / reading memory cells of a 3D-NAND memory device, for reducing hot carrier injection-induced edge summation (ESUM) losses and reducing power consumption during the verification / reading of memory cells of a 3D-NAND memory device.

[0005] According to one aspect of this disclosure, a method for reading a memory device is provided. The memory device may include a first memory cell string and a second memory cell string, wherein the first memory cell string may include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series, and the second memory cell string may include a BSG transistor, a memory cell, and a TSG transistor connected in series. In this method, during a pre-verification phase, a first verification voltage may be applied to the gate terminal of a selected memory cell in the first memory cell string, wherein the selected memory cell may be programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. During the pre-verification phase, a first bias voltage may be applied to the gate terminal of at least one memory cell in the first memory cell string located between the first adjacent memory cell of the selected memory cell in the first memory cell string and the TSG transistor of the first memory cell string. During the verification phase, a second verification voltage may be applied to the gate terminal of the selected memory cell in the first memory cell string. Furthermore, during the verification phase, a second bias voltage can be applied to the gate terminal of at least one memory cell located between a first adjacent memory cell of a selected memory cell in the first memory cell string and the TSG transistor of the first memory cell string. This second bias voltage is less than the first bias voltage.

[0006] In some embodiments, the second bias voltage is 20% to 30% lower than the first bias voltage.

[0007] In this method, during the pre-verification phase, a first gate voltage can be applied to the gate terminal of the TSG transistor in the second memory cell string. A first pass voltage can be applied to the gate terminal of a first adjacent memory cell of a selected memory cell in the first memory cell string. A first read voltage can be applied to the gate terminal of a second adjacent memory cell of a selected memory cell in the first memory cell string. Furthermore, during the verification phase, a second gate voltage can be applied to the gate terminal of the TSG transistor in the second memory cell string. A second pass voltage can be applied to the gate terminal of a first adjacent memory cell of a selected memory cell in the first memory cell string. A second read voltage can be applied to the gate terminal of a second adjacent memory cell of a selected memory cell in the first memory cell string. Moreover, at least one of the second pass voltage and the second read voltage can be greater than the second gate voltage.

[0008] In this method, during the pre-verification and verification phases, a bottom bias voltage can be applied to the gate terminals of the BSG transistors of the first memory cell string. During the pre-verification and verification phases, a top bias voltage can be applied to the gate terminals of the TSG transistors of the first memory cell string. During the pre-verification and verification phases, a positive voltage can be applied to the gate terminals of any memory cell located between a second adjacent memory cell of a selected memory cell in the first memory cell string and the BSG transistors of the first memory cell string.

[0009] In some embodiments, the first verification voltage may be less than the second verification voltage.

[0010] In some embodiments, within a first portion of the pre-verification phase, a first bias voltage may be increased from an initial voltage and then decreased to a second bias voltage, wherein within a second portion of the pre-verification phase, the first bias voltage may be equal to the second bias voltage. Within the pre-verification phase, a first pass voltage may be increased from the initial voltage to the second pass voltage. Within the pre-verification phase, a first read voltage may be increased from the initial voltage to the second read voltage. Within the first portion of the pre-verification phase, a first gate voltage may be increased from the initial voltage to a voltage maintained for a period of time, and then decreased to a second gate voltage, wherein within the second portion of the pre-verification phase, the first gate voltage may be equal to the second gate voltage.

[0011] In some embodiments, the bottom bias voltage can be increased from the initial voltage to a voltage maintained throughout the second part of the pre-verification phase and the verification phase. The top bias voltage can be increased from the initial voltage to a voltage maintained throughout the second part of the pre-verification phase and the verification phase. During the pre-verification phase, the positive voltage can be increased from the initial voltage.

[0012] According to another aspect of this disclosure, a method for reading a memory device is provided. The memory device may include a first memory cell string and a second memory cell string. The first memory cell string may include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series. The second memory cell string may include a BSG transistor, a memory cell, and a TSG transistor connected in series. In this method, during a pre-verification phase, a first verification voltage may be applied to the gate terminal of a selected memory cell in the first memory cell string, wherein the selected memory cell may be programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. During the pre-verification phase, a first bias voltage is applied to the gate terminal of at least one memory cell in the first memory cell string located between the second adjacent memory cell of the selected memory cell in the first memory cell string and the BSG transistor of the first memory cell string. During the verification phase, a second verification voltage may be applied to the gate terminal of the selected memory cell in the first memory cell string. Furthermore, during the verification phase, a second bias voltage can be applied to the gate terminal of at least one memory cell located between a second adjacent memory cell of a selected memory cell in the first memory cell string and the BSG transistor of the first memory cell string. This second bias voltage can be less than the first bias voltage.

[0013] In some embodiments, the second bias voltage is 20% to 30% lower than the first bias voltage.

[0014] In this method, during the pre-verification phase, a first gate voltage can be applied to the gate terminal of the TSG transistor in the second memory cell string. A first pass voltage can be applied to the gate terminal of the first adjacent memory cell of a selected memory cell in the first memory cell string. A first read voltage can be applied to the gate terminal of the second adjacent memory cell of the selected memory cell in the first memory cell string. Furthermore, during the verification phase, a second gate voltage can be applied to the gate terminal of the TSG transistor in the second memory cell string. A second pass voltage can be applied to the gate terminal of the first adjacent memory cell of the selected memory cell in the first memory cell string. A second read voltage can be applied to the gate terminal of the second adjacent memory cell of the selected memory cell in the first memory cell string. Moreover, at least one of the second pass voltage and the second read voltage can be greater than the second gate voltage.

[0015] In this method, during the pre-verification and verification phases, a bottom bias voltage can be applied to the gate terminals of the BSG transistors of the first memory cell string. During the pre-verification and verification phases, a top bias voltage can be applied to the gate terminals of the TSG transistors of the first memory cell string. During the pre-verification and verification phases, a positive voltage can be applied to the gate terminals of any memory cell located between a first adjacent memory cell of a selected memory cell in the first memory cell string and the TSG transistor of the first memory cell string.

[0016] In some embodiments, the first verification voltage may be less than the second verification voltage.

[0017] In some embodiments, within a first portion of the pre-verification phase, a first bias voltage may be increased from an initial voltage and then decreased to a second bias voltage. Within a second portion of the pre-verification phase, the first bias voltage may be equal to the second bias voltage. Within the pre-verification phase, a first pass voltage may be increased from the initial voltage to the second pass voltage. Within the pre-verification phase, a first read voltage may be increased from the initial voltage to the second read voltage. Within the first portion of the pre-verification phase, a first gate voltage may be increased from the initial voltage to a voltage maintained for a certain duration, and then decreased to a second gate voltage. Within the second portion of the pre-verification phase, the first gate voltage may be equal to the second gate voltage.

[0018] In some embodiments, the bottom bias voltage can be increased from the initial voltage to a voltage maintained throughout the second part of the pre-verification phase and the verification phase. The top bias voltage can be increased from the initial voltage to a voltage maintained throughout the second part of the pre-verification phase and the verification phase. During the pre-verification phase, the positive voltage can be increased from the initial voltage.

[0019] According to another aspect of this disclosure, an apparatus for reading a memory device is provided. The memory device may include a first memory cell string and a second memory cell string. The first memory cell string may include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series. The second memory cell string may include a BSG transistor, a memory cell, and a TSG transistor connected in series. The apparatus may include processing circuitry configured to: during a pre-verification phase, apply a first verification voltage to the gate terminal of selected memory cells in the first memory cell string, wherein the selected memory cells may be programmed and arranged between first adjacent memory cells and second adjacent memory cells. The processing circuitry may also be configured to: during the pre-verification phase, apply a first bias voltage to the gate terminal of at least one unprogrammed memory cell in the first memory cell string. During a verification phase, the processing circuitry may be configured to: apply a second verification voltage to the gate terminal of selected memory cells in the first memory cell string. Furthermore, the processing circuitry is configured to: during the verification phase, apply a second bias voltage to the gate terminal of the at least one unprogrammed memory cell in the first memory cell string. The second bias voltage can be less than the first bias voltage.

[0020] In some embodiments, the at least one memory cell of the first memory cell string that receives the first bias voltage and the second bias voltage may be located between a first adjacent memory cell of a selected memory cell of the first memory cell string and the TSG transistor of the first memory cell string.

[0021] In some embodiments, the at least one memory cell of the first memory cell string that receives the first bias voltage and the second bias voltage is located between a second adjacent memory cell of a selected memory cell of the first memory cell string and the BSG transistor of the first memory cell string.

[0022] During the pre-verification phase, the processing circuit may further be configured to: apply a first gate voltage to the gate terminal of the TSG transistor of the second memory cell string. The processing circuit may also be configured to: apply a first pass voltage to the gate terminal of a first adjacent memory cell of a selected memory cell in the first memory cell string. The processing circuit may further be configured to: apply a first read voltage to the gate terminal of a second adjacent memory cell of a selected memory cell in the first memory cell string. During the verification phase, the processing circuit may be configured to: apply a second gate voltage to the gate terminal of the TSG transistor of the second memory cell string. The processing circuit may further be configured to: apply a second pass voltage to the gate terminal of a first adjacent memory cell of a selected memory cell in the first memory cell string. The processing circuit may further be configured to: apply a second read voltage to the gate terminal of a second adjacent memory cell of a selected memory cell in the first memory cell string, wherein at least one of the second pass voltage and the second read voltage may be greater than the second gate voltage.

[0023] In an embodiment, the processing circuit can be configured to: apply a bottom bias voltage to the gate terminal of the BSG transistor of the first memory cell string during the pre-verification and verification phases. The processing circuit can be configured to: apply a top bias voltage to the gate terminal of the TSG transistor of the first memory cell string during the pre-verification and verification phases. The processing circuit can be configured to: apply a positive voltage to the gate terminal of any memory cell located between a second adjacent memory cell of a selected memory cell in the first memory cell string and the BSG transistor of the first memory cell string during the pre-verification and verification phases.

[0024] In another embodiment, the processing circuit can be configured to apply a bottom bias voltage to the gate terminal of the BSG transistor of the first memory cell string during the pre-verification and verification phases. The processing circuit can also be configured to apply a top bias voltage to the gate terminal of the TSG transistor of the first memory cell string during the pre-verification and verification phases. Furthermore, the processing circuit can be configured to apply a positive voltage to the gate terminal of any memory cell located between a first adjacent memory cell of a selected memory cell in the first memory cell string and the TSG transistor of the first memory cell string during the pre-verification and verification phases.

[0025] Various aspects of this disclosure also provide a non-transitory computer-readable medium for storing instructions that, when executed by a computer for verifying / reading the storage device, cause the computer to perform one or more of the methods described above. Attached Figure Description

[0026] Various aspects of this disclosure can be understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased for clarity of discussion.

[0027] Figure 1 This is a schematic diagram of a 3D-NAND storage device according to an exemplary embodiment of the present disclosure.

[0028] Figure 2 This is a cross-sectional view of a 3D-NAND storage device according to an exemplary embodiment of the present disclosure.

[0029] Figure 3 This is a schematic diagram of a NAND memory cell string according to an exemplary embodiment of the present disclosure.

[0030] Figure 4 This is a first schematic diagram of a verification / read storage unit in a relevant example of an exemplary embodiment of the present disclosure.

[0031] Figure 5 This is a second schematic diagram of a verification / read storage unit in a relevant example of an exemplary embodiment of the present disclosure.

[0032] Figure 6 This is a first schematic diagram of a storage cell programmed in a forward sequence for verification / reading according to an exemplary embodiment of the present disclosure.

[0033] Figure 7 This is a second schematic diagram of a storage cell programmed in a forward sequence for verification / reading according to an exemplary embodiment of the present disclosure.

[0034] Figure 8 This is a first schematic diagram of a storage cell programmed in reverse order for verification / reading according to an exemplary embodiment of the present disclosure.

[0035] Figure 9 This is a second schematic diagram of a storage cell programmed in reverse order for verification / reading according to an exemplary embodiment of the present disclosure.

[0036] Figure 10 This is a flowchart of a method for verifying / reading a storage unit according to an exemplary embodiment of the present disclosure.

[0037] Figure 11 This is a block diagram of an electronic system according to exemplary embodiments of the present disclosure. Detailed Implementation

[0038] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the description below of forming a first feature on or above a second feature may include embodiments where the first and second features can directly contact each other, and may also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0039] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0040] In a relevant example, to verify / read programmed memory cells of a 3D-NAND memory device, a pre-pulse scheme (or stage) and a verification / read scheme (or stage) can be included in the verification / read operation. In the pre-pulse scheme, a pass voltage (such as 6.8 volts) can be applied to the word line (WL) of a memory cell in a selected memory cell string, while the gate terminal of the TSG transistor can be turned on at an unselected memory cell string. In the verification / read scheme, the pass voltage can be further maintained at an unselected WL in the selected memory cell string, and a verification voltage can be applied to the WL of a selected memory cell in the selected memory cell string.

[0041] When a sufficient pre-pulse time is applied in the pre-pulse scheme, the through voltage can be fully developed before the TSG transistor at the unselected memory cell string is switched off. Therefore, when the TSG transistor of the unselected memory cell string is switched off in the verification / read scheme, a significant gradient of channel potential is not induced by subsequent verification / read voltages in the verification / read scheme, even though the drain-side channel (or terminal) of the unselected memory cell string is isolated from the bit line coupled to the unselected memory cell string. Correspondingly, no hot carrier injection (HCI) is generated from the selected memory cell in the selected memory cell string to the upper memory cell of that selected memory cell. Therefore, edge summation (ESUM) losses can be prevented. ESUM can be associated with the read margin of the 3D-NAND memory device.

[0042] However, when an insufficient pre-pulse time is applied in the pre-pulse scheme, the through voltage may not develop sufficiently before the TSG transistor at the unselected memory cell string is turned off. In the verification / read scheme, when the TSG transistor at the unselected memory cell string is turned off, the through voltage applied to the WL of the memory cell above the selected memory cell in the selected memory cell string may still develop toward the target value (such as 6.8 volts). Therefore, in the verification / read scheme, increasing the through voltage may additively boost the drain-side channel of the unselected memory cell string, which may in turn lead to HCI between the selected memory cell and its upper adjacent memory cell, and result in ESUM losses.

[0043] In this disclosure, to verify / read programmed memory cells of a 3D-NAND memory device, a pre-pulse voltage can be applied to at least one memory cell in a selected memory cell string located above an upper adjacent memory cell in the selected memory cell string during a pre-verification scheme. During the verification / read scheme, a pass voltage smaller than the pre-pulse voltage can be applied to the at least one memory cell in the selected memory cell string located above an upper adjacent memory cell. Furthermore, the pass voltage applied to one of the upper and lower adjacent memory cells of the selected memory cell in the verification / read scheme can be greater than the bias voltage applied to the TSG transistor of an unselected memory cell string, wherein the bias voltage is applied to turn off the TSG transistor of the unselected memory cell string. Accordingly, hot carrier injection (HCI)-induced ESUM losses can be prevented, and power consumption during the verification / reading of memory cells of the 3D-NAND memory device can be reduced.

[0044] A 3D-NAND device may include multiple planes. Each of these planes may include multiple blocks. Figure 1 This is an exemplary embodiment of the 3D-NAND device 100 (or device 100). For example... Figure 1 As shown, device 100 may include planes 102 and 104. Each of planes 102 and 104 may include two corresponding blocks. For example, plane 102 may include two blocks 106 and 108, and plane 104 may include two blocks 110 and 112. Furthermore, each of the blocks may include a plurality of memory cell strings, in which memory cells are arranged sequentially and in series on the substrate along the height direction of device 100. Of course, it should be noted that... Figure 1 This is merely an example, and device 100 may include any number of planes, and each of the planes may include any number of blocks depending on the device design.

[0045] In device 100, each of the planes can be coupled to a corresponding cache structure, such as a dynamic data cache (DDC) or a static page buffer (SPB). For example, block 106 can be coupled to cache structure 114, and block 108 can be coupled to cache structure 116. The cache structure may include a sense amplifier coupled to bit lines and signals configured to read operations of the 3D-NAND device 100, such as verifying / reading, programming, or erasing memory cells of the 3D-NAND device 100. Device 100 may also include peripheral circuitry 122, which may include decoder structures, driver structures, charging structures, and other structures for operating memory cells.

[0046] In device 100, each of the blocks may include a stepped region and an array region formed in a stacked layer of word line layer and insulating layer. Figure 2 This is an exemplary embodiment of block 106 of device 100. Figure 2 As shown, block 106 may include array regions 200A and stepped regions 200B-200C arranged in dielectric layer 24. Array regions 200A may be arranged between stepped regions 200B-200C and in a stacked layer formed on substrate 10, consisting of alternating word line layers 12a-12p and insulating layers 14a-14q. Word line layers 12a-12p may include one or more bottom select gate (BSG) layers, gate layers (or word line layers), and one or more top select gate (TSG) layers arranged sequentially on substrate 10. For example, word line layer 12a may be a BSG layer, and word line layer 120p may be a TSG layer in device 100.

[0047] In some embodiments, device 100 may include one or more bottom dielectric trenches (e.g., 26 and 28) formed in one or more BSGs (e.g., formed in word line layer 12a). Bottom dielectric trenches 26 and 28 may extend along the X direction of substrate 10 to divide the BSG into multiple sub-BSGs (e.g., 12a-1, 12a-2, and 12a-3). Furthermore, one or more top dielectric trenches (e.g., 30 and 32) may be formed in one or more TSGs (e.g., in word line layer 12p). Top dielectric trenches 30 and 32 may also extend along the X direction of substrate 10 to divide the TSG into multiple sub-TSGs (e.g., 12p-1, 12p-2, and 12p-3). The sub-BSGs and sub-TSGs can divide device 100 into multiple sub-blocks. Each sub-block may have a corresponding sub-BSG and a corresponding sub-TSG. Therefore, the memory cell strings in the corresponding sub-block can be operated individually by controlling the corresponding sub-BSG and the corresponding sub-TSG.

[0048] Array region 200A may include a plurality of channel structures 18. Each of the channel structures 18 may include a corresponding top channel contact 19 and a corresponding bottom channel contact 21. Each of the channel structures 18 may extend through the stacked layers and may be coupled to word line layers 12a-12p to form a corresponding vertical NAND memory cell string. The vertical NAND memory cell string may include one or more bottom select transistors (BSTs), a plurality of memory cells (MCs), and one or more top select transistors (TSTs) arranged sequentially in series on the substrate 10 along the height direction (e.g., the Z direction) of the substrate. The one or more BSTs may be formed by the channel structure and one or more BSG layers, the MCs may be formed by the channel structure and the word line layers, and the one or more TSTs may be formed by the channel structure and the one or more TSG layers.

[0049] In device 100, each memory cell can store one or more logic bits, depending on the device design. For example, a memory cell can be a single-level cell (SLC), a multi-level cell (MLC), or a three-level cell (TLC). Accordingly, each memory cell can store one, two, or three logic bits.

[0050] Still referencing Figure 2 Word line layers 12a-12p can be formed in step regions 200A-200B in a stepped configuration, and multiple word line contacts 22 can be formed along the height direction and coupled to word line layers 12a-12p. Therefore, a gate voltage can be applied to the gate of the memory cell through the word line contacts 22 coupled to word line layers 12a-12p.

[0051] Furthermore, each of the channel structures can also be coupled to a corresponding bit line (or bit line structure). In some embodiments, the bit line can be connected to the top channel contact 19 of the channel structure 18 and configured to apply a bias voltage when operating the channel structure (such as programming, erasing, or reading the channel structure). Device 100 can have multiple slot structures (or gate line slot structures). For example, in Figure 2 The device 100 includes two slot structures 20a-20b. Slot structures 20a-20b may be composed of a conductive material and are located on the array common source (ACS) region 16 to serve as contacts. The ACS region is formed in the substrate 10 to serve as the common source of the device 100.

[0052] Figure 3 This is a schematic diagram of NAND memory cell strings (or strings) 300A and 300B that can be formed in device 100. For example... Figure 3 As shown, string 300A may include a bottom select transistor (BST) or bottom select gate (BSG) transistor 302A, a plurality of memory cells (MCs) 304A, and a top select transistor (TST) or top select gate (TSG) transistor 306A arranged sequentially in series on the substrate along the height direction (e.g., the Z direction) of the substrate 10. Similarly, string 300B may include a bottom select transistor (BST) or bottom select gate (BSG) transistor 302B, a plurality of memory cells (MCs) 304B, and a top select transistor (TST) or top select gate (TSG) transistor 306B arranged sequentially in series on the substrate along the height direction (e.g., the Z direction) of the substrate 10. String 300A may be coupled to bit line 308A via the drain terminal of TST 306A and to ACS (e.g., 16) via the source terminal of BST 302A. String 300B can be coupled to bit line 308B via the drain terminal of TST 306B and to the ACS (e.g., 16) via the source terminal of BST 302B. During operation of device 100, appropriate voltages can be applied to bit lines 308A and 308B, to the gates of TST 306A and 306B via sub-TSG layers (e.g., 12p-1, 12p-2, and 12p-3), to the gates of MC 304A and 304B via WL layers (e.g., 12b-12o), to the gates of BST 302A and 302B via sub-BSG layers (e.g., 12a-1, 12a-2, and 12a-3), and to the ACS via a gap structure (e.g., 20a or 20b).

[0053] When a selected cell in a 3D-NAND memory device is programmed, a verification / read operation can be performed to verify whether the selected cell (e.g., MCn) has been successfully programmed. During the verification / read operation, a bias voltage (or through voltage) can be applied to the gate terminal (or gate) of the TSG transistor via the TSG layer, a bias voltage (or through voltage) can be applied to the BSG transistor via the BSG layer, and a bias voltage (or through voltage) can be applied to the unselected MC via the WL layer. This bias voltage can be sufficient (e.g., 6.8 volts) to turn on the TSG transistor, the BSG transistor, and the unselected MC. Furthermore, a read (or verification) voltage can be applied to the gate terminal (or gate) of the selected cell MCn via the WL layer (e.g., WLn) coupled to the selected cell MCn. This read voltage can be equal to the threshold voltage of the selected cell when it is not programmed. The threshold voltage can be increased when the selected cell (e.g., MCn) is programmed. Therefore, when a selected memory cell (e.g., MCn) is successfully programmed, the read voltage cannot turn on the selected memory cell (e.g., MCn). Accordingly, the sense amplifier does not detect the current flowing from the ACS region (e.g., 16) to the bit line through the memory cell string. When a selected memory cell (e.g., MCn) is not successfully programmed, the read voltage can turn on the selected memory cell (e.g., MCn), and the sense amplifier can detect the current flowing from the ACS region (e.g., 16) to the bit line through the memory cell string.

[0054] Figure 4 This is a first schematic diagram of a verification / read operation for a memory cell in a 3D-NAND memory device (e.g., device 100) in a relevant example. Figure 4 As shown, the verification / read operation may include an initialization phase, a pre-pulse phase, a verification / read phase, a post-pulse phase, and a recovery phase. The verification / read operation verifies whether the memory cell has been successfully programmed by applying appropriate bias voltages to the word line layer of the memory cell, the TSG layer of the TSG transistor, and the BSG layer of the BSG transistor. Figure 4 In an exemplary embodiment, the memory cells of device 100 can be programmed in a forward sequence. Therefore, memory cells in the memory cell string are programmed from the bottom MC adjacent to the BSG transistor to the top MC adjacent to the TSG transistor. For example, in memory cell string 300A, memory cells are programmed sequentially from MC0 to the top MC adjacent to the TSG transistor 306A.

[0055] Figure 4There is illustrated bias voltages applied to two exemplary memory cell strings including a selected memory cell string (e.g., 300A) and an unselected memory cell string (300B). The selected memory cell string may comprise a selected TSG layer coupled to a TSG transistor (e.g., 306A), a selected word line layer WLn coupled to a selected memory cell (e.g., MCn), a word line layer WLn+1 coupled to a memory cell MCn+1 which is an upper adjacent memory cell of the selected memory cell MCn, a word line layer WLn-1 coupled to a memory cell MCn-1 which is a lower adjacent memory cell of the selected memory cell MCn, a word line layer WL(>n+1) coupled to unselected memory cells (unprogrammed memory cells) located above the memory cell MCn+1, a word line layer WL(<n-1) coupled to unselected memory cells (programmed memory cells) located below the memory cell MCn-1, and a BSG layer coupled to a BSG transistor (e.g., 302A). The TSG transistor (or TST) 306A, the memory cells and the BSG transistor (BST) 302A are connected in series, which can be as Figure 3 illustrated.

[0056] Still referring to Figure 4 , an unselected memory cell string (e.g., 300B) may comprise an unselected TSG layer coupled to a TSG transistor (e.g., 306B), a selected word line layer WLn coupled to a selected memory cell (e.g., MCn), a word line layer WLn+1 coupled to a memory cell MCn+1 which is an upper adjacent memory cell of the selected memory cell MCn, a word line layer WLn-1 coupled to a memory cell MCn-1 which is a lower adjacent memory cell of the selected memory cell MCn, a word line layer WL(>n+1) coupled to unselected memory cells (unprogrammed memory cells) located above the memory cell MCn+1, a word line layer WL(<n-1) coupled to unselected memory cells (programmed memory cells) located below the memory cell MCn-1, and a BSG layer coupled to a BSG transistor (e.g., 302B). As Figure 3 illustrated, the TSG transistor (or TST) 306B, the memory cells and the BSG transistor (BST) 302B are connected in series.

[0057] In some embodiments, for example, the selected TSG layer and the unselected TSG layer may each be one of sub-TSG layers 12p-1, 12p-2 and 12p-3 that are spaced apart from each other by top dielectric trenches 30 and 32. In some embodiments, the word line layer in the selected memory cell string and the word line layer in the unselected memory cell string may be Figure 2the word line layers 12b-12o shown in. Therefore, memory cells of a selected memory cell string are coupled to memory cells in corresponding positions of unselected memory cell strings. For example, the selected memory cell MCn of the selected memory cell string 300A is coupled to the selected memory cell MCn of the unselected memory cell string 300B through the same word line layer.

[0058] At the start of the verify / read operation, in Figure 4 the initial stage of the verify / read operation shown in , an initial voltage such as zero volts may be applied to the selected TSG layer, the unselected TSG layer, WL(>n+1) (word line layers coupled to unprogrammed memory cells), WLn+1, WLn, WL(<n-1) (word line layers coupled to programmed memory cells) and the BSG layer. Furthermore, appropriate bias voltages may be applied to the selected TSG layer, the unselected TSG layer, WL(>n+1) (word line layers coupled to unprogrammed memory cells), WLn+1, WLn, WL(<n-1) (word line layers coupled to programmed memory cells) and the BSG layer respectively during the pre-pulse phase. For example, a bias voltage (or a top bias voltage) such as 5 volts may be applied to the selected TSG layer of the selected memory cell string. A bias voltage (or a gate voltage) such as 5 volts may be applied to the unselected TSG layer of the unselected memory cell string. A bias voltage such as 6.8 volts may be applied to WL(>n+1). A bias voltage (or a pass voltage) such as 6.8 volts may be applied to WLn+1. A bias voltage (or a verify voltage) such as 6.8 volts may be applied to the selected word line layer WLn. A bias voltage (or a read voltage) such as 6.8 volts may be applied to WLn-1. A bias voltage (or a positive voltage) such as 6.8 volts may be applied to WL(<n-1). Furthermore, a bias voltage (or a bottom bias voltage) such as 5 volts may be applied to the BSG layer. The pre-pulse phase may be configured to apply sufficient bias voltages to form conductive channels in the selected memory cell string and the unselected memory cell strings respectively.

[0059] When a verify / read operation proceeds to the verify / read phase, the bias voltage (or top bias voltage) applied to the selected TSG layer of the selected memory cell string is maintained. The bias voltage (or gate voltage) applied to the unselected TSG layer of the unselected memory cell string can be reduced to a lower voltage, such as zero volts, to turn off the TSG transistor (e.g., 306B) of the unselected memory cell string. Accordingly, the unselected memory cell string is isolated from the bit line (e.g., 308B). The bias voltage applied to WL(>n+1) can be maintained to keep the channel of the selected memory cell string conductive. The bias voltage (or pass voltage) applied to WLn+1 can be increased from the bias voltage applied in the pre-pulse phase, for example, increased by one volt. In addition, the bias voltage (or read voltage) applied to WLn-1 can be increased from the bias voltage applied in the pre-pulse phase, for example, increased by one volt. The higher bias voltages applied to WLn+1 and WLn-1 can contribute to forming the source / drain regions of the selected memory cell MCn.

[0060] Still referring to Figure 4 , the bias voltage (or verify voltage) applied to the selected word line layer WLn can be reduced to a program verify (PV) level. In some embodiments, the PV level can be in a range from zero volts to one volt. The bias voltage (or positive voltage) applied to WL(<n-1) can be maintained to keep the channel of the selected memory cell string conductive. In addition, the bias voltage (or bottom bias voltage) applied to the BSG layer can be maintained to keep the channel of the selected memory cell string conductive. As mentioned above, the bias voltage (or verify voltage) applied to the selected word line layer WLn can be equal to the threshold voltage of the selected memory cell when the selected memory cell is not programmed. When the selected memory cell is programmed, the threshold voltage can increase. Therefore, when the selected memory cell is successfully programmed, the read voltage does not turn on the selected memory cell. Accordingly, the sense amplifier cannot detect the current flowing from the ACS region to the bit line through the memory cell string. When the selected memory cell is not successfully programmed, the read voltage can turn on the selected memory cell, and the sense amplifier can detect the current flowing from the ACS region to the bit line through the memory cell string.

[0061] It should be noted that in Figure 4In, a long pre-pulse time is applied during the pre-pulse phase, for example, in a range from 1 ns to 10 us. When the long pre-pulse time is sufficient to fully develop the bias voltage before the TSG transistor at the unselected memory cell strings is turned off, the subsequent verify / read pulse in the verify / read phase may not induce a significant channel potential gradient. Therefore, no hot carrier injection (HCI) from the selected memory cell in the selected memory cell string to the upper adjacent memory cell of the selected memory cell is generated. However, when the long pre-pulse time is insufficient to fully develop the bias voltage before the TSG transistor at the unselected memory cell strings is turned off within the pre-pulse phase, the subsequent verify / read pulse in the verify / read phase may induce a significant channel potential gradient, and may generate HCI from the selected memory cell in the selected memory cell string to the upper adjacent memory cell of the selected memory cell.

[0062] Figure 5 is a second schematic diagram of a verify / read operation for verifying / reading memory cells that are also programmed in a forward sequence in a 3D-NAND memory device (e.g., device 100) in a related example. The verify / read operation may have a pre-pulse phase using a short pre-pulse time. The short pre-pulse time is insufficient for the bias voltages applied to WL(>n+1), WLn+1, WLn, WLn-1 and WL(<n-1) to be fully developed in the pre-pulse phase. For example, as Figure 5 shown, the bias voltage is less than a target value, such as 6.8 volts. The bias voltage can still develop to the target value, such as 6.8 volts, in the verify / read phase. Therefore, the drain-side channel of the unselected memory cell strings can be additively boosted by increasing the bias voltage within the verify / read phase, which may cause HCI between the selected memory cell (WLn) and the upper adjacent memory cell (WLn+1) of the selected memory cell, and lead to ESUM loss.

[0063] Figure 6 is a first schematic diagram of a verify / read operation for verifying / reading memory cells of a 3D-NAND memory device (e.g., device 100) according to an exemplary embodiment of the present disclosure. As Figure 6 shown, the memory cells can be programmed in a forward sequence, and the verify / read operation may include a long pre-pulse time within the pre-pulse phase. In Figure 6 the exemplary embodiment, memory cells MC0-MCn are programmed (e.g., Figure 4 MC0-MCn-1 in are programmed memory cells, Figure 4 MCn in is programmed and selected to receive a verify / read operation), memory cells above MCn are not programmed (e.g., Figure 4MCn+1 and above are unprogrammed memory cells. Furthermore, memory cells MCn coupled to WLn are selected to receive authentication / read operations.

[0064] and Figure 4 Compared to the verification / read operation, the bias voltage applied to WL(>n+1) (the word line layer coupled to the unprogrammed memory cell) during the verification / read phase is lower than the bias voltage applied to WL(>n+1) during the pre-pulse phase. Figure 6 In an exemplary embodiment, the bias voltage applied to WL(>n+1) during the verification / read phase may be 3 volts, and the bias voltage applied to WL(>n+1) during the pre-pulse phase may be 6.8 volts. In some embodiments, the bias voltage applied to WL(>n+1) during the verification / read phase is a certain percentage (e.g., from 20% to 30%) lower than the bias voltage applied to WL(>n+1) during the pre-pulse phase. In some embodiments, each of the memory cells (unprogrammed memory cells) located above the upper adjacent memory cell of the selected memory cell MCn may receive a bias voltage lower than the bias voltage in the pre-pulse phase via WL(>n+1) during the verification / read phase. In some embodiments, at least one memory cell located between the upper adjacent memory cell of the selected memory cell MCn and the TSG transistor may receive a bias voltage lower than the bias voltage in the pre-pulse phase via WL(>n+1) during the verification / read phase. For example, a memory cell adjacent to a TSG transistor can receive a bias voltage lower than the bias voltage during the pre-pulse phase during the verification / read phase.

[0065] By introducing a lower bias voltage in the memory cell above the upper adjacent memory cell MCn+1 of the selected memory cell MCn during the verification / read phase, the channel potential gradient of the selected memory cell string can be reduced. Consequently, no HCI is generated from the selected memory cell in the selected memory cell string to the upper adjacent memory cell of that selected memory cell. Therefore, ESUM losses can be prevented.

[0066] Figure 7 This is a second schematic diagram illustrating a verification / read operation of a memory cell in a 3D-NAND memory device (e.g., device 100) according to an exemplary embodiment of the present disclosure. Figure 7 As shown, the memory cells can be programmed in forward order, and the verification / read operation can include a short pre-pulse time within the pre-pulse phase. Figure 7 As shown, the pre-pulse phase may include a first part T1 and a second part T2. Figure 5 Compared to the verification / read operations in [the context of the previous sentence], in [the context of the previous sentence] Figure 7, the bias voltage applied during the pre-pulse period can be fully developed to (or completely reach) the target value. For example, the bias voltage applied to WL(>n+1) can be fully developed during the pre-pulse period. As Figure 7 shows, the bias voltage applied to WL(>n+1) can be increased from the initial voltage to the target value during the first part of the pre-pulse period. For example, the target value can be 6.8 volts. Then, the bias voltage can be reduced to a lower value equal to the bias voltage in the verify / read phase, e.g., 3 volts, during the first part of the pre-verify period. The bias voltage is further maintained during the second part of the pre-verify period.

[0067] Still referring to Figure 7 , the pass voltage applied to WLn+1 during the pre-verify period can be increased from an initial voltage to a target value, e.g., 7.8 volts, where the target value is equal to the pass voltage in the verify / read phase. The read voltage applied to WLn-1 during the pre-verify period can be increased from an initial voltage to a target value, e.g., 7.8 volts, where the target value is equal to the read voltage in the verify / read phase. The gate voltage applied to unselected TSGs can be increased from an initial voltage to a target value (e.g., 5 volts) during the first part of the pre-pulse period. Then, this gate voltage can be maintained for a duration, and then reduced to a value equal to the gate voltage of the verify / read phase during the first part of the pre-verify period. The gate voltage can be maintained equal to the gate voltage of the verify / read phase during the second part of the pre-verify period.

[0068] The bottom bias voltage applied to the BSG transistor during the first part of the pre-pulse period can be increased from an initial voltage to a target value, e.g., 5 volts, where the target value is equal to the bottom bias voltage of the verify / read phase. The bottom bias voltage can be maintained throughout the second part of the pre-verify period and the verify period. Similarly, the top bias voltage applied to the selected TSG transistor during the first part of the pre-pulse period can be increased from an initial voltage to a target value, e.g., 5 volts. The top bias voltage can further be maintained throughout the second part of the pre-verify period and the verify period. The positive voltage applied to WL(<n-1) during the pre-pulse period can be increased from the initial voltage in the pre-verify period to a target value, e.g., 6.8 volts, where the target value is equal to the positive voltage applied during the verify / read phase.

[0069] In the Figure 7 verify / read operation, the bias voltage applied to WL(>n+1) during the verify / read phase can be lower than the bias voltage applied to WL(>n+1) during the pre-pulse period. In Figure 7In an exemplary embodiment, the bias voltage applied to WL(>n+1) during the verification / read phase may be 3 volts, and the bias voltage applied to WL(>n+1) during the pre-pulse phase may be 6.8 volts. In some embodiments, each of the memory cells located above the upper adjacent memory cell MCn+1 of the selected memory cell MCn may receive a bias voltage lower than the bias voltage during the pre-pulse phase via WL(>n+1) during the verification / read phase. In some embodiments, at least one of the memory cells located between the upper adjacent memory cell MCn+1 of the selected memory cell MCn and the TSG transistor may receive a bias voltage lower than the bias voltage during the pre-pulse phase via WL(>n+1) during the verification / read phase. For example, the memory cell adjacent to the TSG transistor may receive a bias voltage lower than the bias voltage during the pre-pulse phase during the verification / read phase.

[0070] In addition, Figure 7 During the verification / read operation, at least one of the upper adjacent memory cell MCn+1 and the lower adjacent memory cell MCn-1 of the selected memory cell MCn can receive a bias voltage higher than the bias voltage applied to the unselected TSG transistor during the verification / read phase.

[0071] and Figure 5 Compared to the verification / read operations in [the context of the previous sentence], in [the context of the previous sentence] Figure 7 The bias voltage applied during the pre-pulse phase of the verification / read operation is sufficiently developed to the target value. Furthermore, a lower bias voltage is introduced during the verification / read phase for memory cells located above the upper adjacent memory cells of the selected memory cell MCn. Accordingly, the channel potential gradient of the selected memory cell string can be reduced, and the formation of HCI from the selected memory cell in the selected memory cell string to the upper adjacent memory cell of that selected memory cell can be prevented. Therefore, ESUM losses can be prevented.

[0072] Figure 8 This is a first schematic diagram illustrating a verification / read operation for verifying / reading a memory cell programmed in reverse order, according to an exemplary embodiment of the present disclosure. Figure 8 As shown, the memory cells can be programmed in reverse order because they are programmed in the order from the top memory cell adjacent to the TSG transistor to the bottom memory cell adjacent to the BSG transistor (e.g., MC0). Figure 8 In an exemplary embodiment, the selected memory cell MCn and the memory cell above the selected memory cell MCn are programmed (e.g., Figure 4 In the middle, memory units of MCn+1 and above are already programmed memory units. Figure 4MCn is programmed and selected to receive a verify / read operation). In addition, Figure 8 the pre-pulse phase of the verify / read operation can have a long pre-pulse time.

[0073] As shown in Figure 8 , compared with the verify / read operation for verifying / reading memory cells programmed in a forward order shown in Figure 6 , the bias voltage applied to WL(<n-1) during the verify / read phase is lower than the bias voltage applied to WL(<n-1) during the pre-pulse phase. In some embodiments, each of the memory cells located between the lower adjacent memory cell MCn-1 of the selected memory cell MCn and the BSG transistor can receive a bias voltage lower than that in the pre-pulse phase through WL(<n-1) during the verify / read phase. In some embodiments, at least one memory cell among the memory cells located between the lower adjacent memory cell MCn-1 of the selected memory cell MCn and the BSG transistor can receive a bias voltage lower than that in the pre-pulse phase through WL(<n-1) during the verify / read phase. For example, the memory cell adjacent to the BSG transistor can receive a bias voltage lower than that in the pre-pulse phase during the verify / read phase.

[0074] Figure 9 is a second schematic diagram of a verify / read operation for verifying / reading memory cells programmed in a reverse order according to an exemplary embodiment of the present disclosure. Compared with the verify / read operation for verifying / reading memory cells programmed in a forward order shown in Figure 7 , the bias voltage applied to WL(<n-1) during the verify / read phase is lower than the bias voltage applied to WL(<n-1) during the pre-pulse phase. In some embodiments, each of the memory cells located below the lower adjacent memory cell MCn-1 of the selected memory cell MCn can receive a bias voltage lower than that in the pre-pulse phase through WL(<n-1) during the verify / read phase. In some embodiments, at least one memory cell among the memory cells located between the lower adjacent memory cell MCn-1 of the selected memory cell MCn and the BSG transistor can receive a bias voltage lower than that in the pre-pulse phase through WL(<n-1) during the verify / read phase. For example, the memory cell adjacent to the BSG transistor can receive a bias voltage lower than that in the pre-pulse phase during the verify / read phase.

[0075] Similar to the verify / read operation shown in Figure 6 and Figure 7 , Figure 8 and Figure 9The verification / read operation shown includes a bias voltage that can be sufficiently developed during the pre-pulse phase. Furthermore, the bias voltage applied to at least one of the unprogrammed memory cells during the pre-pulse phase can be lower than the bias voltage applied during the verification / read phase. Accordingly, the channel potential gradient of the selected memory cell string can be reduced, and the formation of HCI from the selected memory cell MCn in the selected memory cell string to its lower adjacent memory cell MCn-1 can be prevented. Therefore, ESUM losses can be prevented.

[0076] Figure 10 This is a flowchart of a method 1000 for reading a memory device comprising a first memory cell string and a second memory cell string. The first memory cell string may include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series. The second memory cell string may include a BSG transistor, a memory cell, and a TSG transistor connected in series. Figure 10 As shown, method 1000 may begin at S1002 and proceed to S1004, in which, during the pre-verification phase, a first verification voltage may be applied to the gate terminal of a selected memory cell in the first memory cell string. The selected memory cell may be programmed and arranged between a first adjacent memory cell and a second adjacent memory cell.

[0077] In S1004, during the pre-verification phase, a first bias voltage may be applied to the gate terminal of at least one unprogrammed memory cell in the first memory cell string.

[0078] In S1006, during the verification phase, a second verification voltage may be applied to the gate terminal of a selected memory cell in the first memory cell string.

[0079] In S1008 of method 1000, during the verification phase, a second bias voltage may be applied to the gate terminal of the at least one unprogrammed memory cell of the first memory cell string, wherein the second bias voltage is less than the first bias voltage.

[0080] In some embodiments, the at least one memory cell of the first memory cell string that receives the first bias voltage and the second bias voltage may be located between a first adjacent memory cell of a selected memory cell of the first memory cell string and the TSG transistor of the first memory cell string.

[0081] In some embodiments, the at least one memory cell of the first memory cell string that receives the first bias voltage and the second bias voltage may be located between a second adjacent memory cell of a selected memory cell of the first memory cell string and the BSG transistor of the first memory cell string.

[0082] In method 1000, during the pre-verification phase, a first gate voltage may be applied to the gate terminal of the TSG transistor of the second memory cell string. A first pass voltage (third pass voltage) may be applied to the gate terminal of a first adjacent memory cell of a selected memory cell in the first memory cell string. A first read voltage (fourth pass voltage) may be applied to the gate terminal of a second adjacent memory cell of a selected memory cell in the first memory cell string. Furthermore, during the verification phase, a second gate voltage may be applied to the gate terminal of the TSG transistor of the second memory cell string. A second pass voltage (second pass voltage) may be applied to the gate terminal of a first adjacent memory cell of a selected memory cell in the first memory cell string. A second read voltage (first pass voltage) may be applied to the gate terminal of a second adjacent memory cell of a selected memory cell in the first memory cell string. Moreover, at least one of the second pass voltage (second pass voltage) and the second read voltage (first pass voltage) may be greater than the second gate voltage.

[0083] Figure 11 This is a simplified block diagram of a storage device 1001 according to an embodiment of the present disclosure, and embodiments on which the present disclosure may be implemented. The storage device 1001 may include a storage array 1004 arranged in rows and columns. The storage array 1004 may include a multi-channel structure (e.g., Figure 2 The memory cell formed by the channel structure 18 in the middle ( Figure 3 MC 304 in the middle). The channel structure can be formed on alternating word line layers (e.g., Figure 2 12) and insulating layer (e.g., Figure 2 In the stacked layer consisting of 14), row decoding circuitry 1008 and column decoding circuitry 1010 are provided to decode the address signals provided to the storage device 1001. The address signals are received and decoded to access the storage array 1004. The storage device 1001 may also include input / output (I / O) control circuitry 1012 to manage inputs of commands, addresses, and data to the storage device 1001, as well as outputs of data and status information from the storage device 1001. Address register 1014 is coupled between the I / O control circuitry 1012 and the row decoding circuitry 1008 and column decoding circuitry 1010 to latch the address signals before decoding. Command register 1024 is coupled between the I / O control circuitry 1012 and control logic 1016 to latch incoming commands.

[0084] Control logic 1016 can control access to memory array 1004 in response to commands and generate status information for external processor 1030. Control logic 1016 is coupled to row decoding circuitry 1008 and column decoding circuitry 1010 to control row decoding circuitry 1008 and column decoding circuitry 1010 in response to an address. For example, control logic 1016 can apply a bias voltage to selected memory cells via row decoding circuitry 1008 and column decoding circuitry 1010 to operate on selected memory cells, such as reading, writing, or erasing them. Control logic 1016 can also be coupled to sense amplifier and latch circuitry 1018 to control sense amplifier and latch circuitry 1018 in response to commands and generate status information for external processor 1030. Sense amplifier and latch circuitry 1018 can be coupled to memory array 1004 and can latch incoming or outgoing data in the form of analog voltage levels. The readout amplifier and latch circuit 1018 can be configured to read the signal of the memory cell when the memory cell is operated.

[0085] Still referencing Figure 11 Status register 1022 can be coupled between I / O control circuitry 1012 and control logic 1016 to latch status information for output to external processor 1030. Storage device 1001 receives control signals on control link 1032 at control logic 1016. Control signals may include chip enable CE#, command latch enable CLE, address latch enable ALE, and write enable WE#. Storage device 1001 can receive commands in the form of command signals, addresses in the form of address signals, and data in the form of data signals from an external processor on multiplexed input / output (I / O) bus 1034, and can output data to an external processor on I / O bus 1034.

[0086] The various embodiments described herein offer several advantages over methods in related examples used to verify / read programmed memory cells of a 3D-NAND memory device. In related examples, hot carrier injection (HCI) may occur between a selected memory cell and one of its adjacent memory cells, leading to ESUM losses. In this disclosure, HCI-induced edge summation (ESUM) losses can be prevented, and power consumption during verification / reading of memory cells in a 3D-NAND memory device can be reduced.

[0087] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will recognize that they can readily use this disclosure as a basis to design or modify other processes or structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent designs do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for verifying a memory device comprising a first memory cell string and a second memory cell string, the first memory cell string comprising a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series, and the second memory cell string comprising a BSG transistor, a memory cell, and a TSG transistor connected in series, the method comprising: During the pre-verification phase, a first verification voltage is applied to the word lines coupled to selected memory cells in the first memory cell string, the selected memory cells being arranged between a first adjacent memory cell and a second adjacent memory cell. During the pre-verification phase, a first bias voltage is applied to a word line coupled between at least one memory cell in the first memory cell string and the TSG transistor of the first memory cell string, where the first adjacent memory cell of the selected memory cell in the first memory cell string is coupled to the first memory cell string. During the verification phase, a second verification voltage is applied to the word line coupled to the selected memory cell in the first memory cell string; During the verification phase, a first pass voltage is applied to the word line coupled to the second adjacent memory cell of the selected memory cell in the first memory cell string; During the verification phase, a second pass voltage is applied to the word line coupled to the first adjacent memory cell of the selected memory cell in the first memory cell string; as well as During the verification phase, a second bias voltage is applied to the word line of at least one memory cell coupled between the first adjacent memory cell of the selected memory cell in the first memory cell string and the TSG transistor of the first memory cell string. Wherein, the second bias voltage is less than the first bias voltage; At least one of the first through voltage and the second through voltage is greater than the second bias voltage.

2. The method according to claim 1, wherein, The second bias voltage is 20% to 30% lower than the first bias voltage.

3. The method according to claim 1, wherein, The second bias voltage is less than or equal to 3 volts.

4. The method according to claim 1, wherein, At least one of the first through voltage and the second through voltage is greater than the first bias voltage.

5. The method according to claim 1, further comprising: During the pre-verification phase, a first gate voltage is applied to the gate terminal of the TSG transistor in the second memory cell string. During the pre-verification phase, a third pass voltage is applied to the word line coupled to the first adjacent memory cell of the selected memory cell in the first memory cell string, and During the pre-verification phase, a fourth pass voltage is applied to the word line coupled to the second adjacent memory cell of the selected memory cell in the first memory cell string; as well as During the verification phase, a second gate voltage is applied to the gate terminal of the TSG transistor in the second memory cell string; Wherein, at least one of the first through voltage and the second through voltage is greater than the second gate voltage.

6. The method according to claim 5, further comprising: During the pre-verification phase and the verification phase, a bottom bias voltage is applied to the gate terminals of the BSG transistors in the first memory cell string; During the pre-verification phase and the verification phase, a top bias voltage is applied to the gate terminals of the TSG transistors in the first memory cell string; as well as During the pre-verification phase and the verification phase, a positive voltage is applied to the word line of any memory cell coupled between the second adjacent memory cell of the selected memory cell in the first memory cell string and the BSG transistor of the first memory cell string.

7. The method according to claim 1, wherein, The first verification voltage is greater than the second verification voltage.

8. The method according to claim 1, wherein, In the first part of the pre-verification phase, the voltage applied to the word line of at least one memory cell coupled between the first adjacent memory cell of the selected memory cell in the first memory cell string and the TSG transistor of the first memory cell string increases from an initial voltage to the first bias voltage, then decreases to the second bias voltage, and remains at the second bias voltage in the second part of the pre-verification phase.

9. The method according to claim 8, wherein, The first verification voltage is less than the second verification voltage.

10. The method according to claim 5, wherein, The first gate voltage is greater than the second gate voltage.

11. The method according to claim 10, wherein, In the first part of the pre-verification phase, the voltage applied to the gate terminal of the TSG transistor of the second memory cell string increases from the initial voltage to the first gate voltage, then decreases to the second gate voltage, and remains at the second gate voltage in the second part of the pre-verification phase.

12. The method according to claim 5, wherein, During the pre-verification phase, the third pass voltage is increased from the initial voltage to the second pass voltage; and During the pre-verification phase, the fourth pass voltage is increased from the initial voltage to the first pass voltage.

13. The method according to claim 6, wherein, The bottom bias voltage increases from the initial voltage to a voltage that is maintained throughout the second part of the pre-verification phase and the verification phase. The top bias voltage increases from the initial voltage to a voltage maintained throughout the second part of the pre-verification phase and the verification phase, and During the pre-verification phase, the positive voltage increases from the initial voltage.

14. A method for verifying a memory device comprising a first memory cell string and a second memory cell string, the first memory cell string comprising a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series, and the second memory cell string comprising a BSG transistor, a memory cell, and a TSG transistor connected in series, the method comprising: During the pre-verification phase, a first verification voltage is applied to the word lines coupled to selected memory cells in the first memory cell string, the selected memory cells being arranged between a first adjacent memory cell and a second adjacent memory cell. During the pre-verification phase, a first bias voltage is applied to a word line coupled between at least one memory cell in the first memory cell string and the BSG transistor of the first memory cell string, which is the second adjacent memory cell of the selected memory cell in the first memory cell string. During the verification phase, a second verification voltage is applied to the word line coupled to the selected memory cell in the first memory cell string; During the verification phase, a first pass voltage is applied to the word line coupled to the second adjacent memory cell of the selected memory cell in the first memory cell string; During the verification phase, a second pass voltage is applied to the word line coupled to the first adjacent memory cell of the selected memory cell in the first memory cell string; as well as During the verification phase, a second bias voltage is applied on the word line of at least one memory cell coupled between the second adjacent memory cell of the selected memory cell in the first memory cell string and the BSG transistor of the first memory cell string. Wherein, the second bias voltage is less than the first bias voltage; at least one of the first through voltage and the second through voltage is greater than the second bias voltage.

15. The method according to claim 14, wherein, The second bias voltage is 20% to 30% lower than the first bias voltage.

16. The method of claim 14, wherein, The second bias voltage is less than or equal to 3 volts.

17. The method according to claim 14, wherein, At least one of the first through voltage and the second through voltage is greater than the first bias voltage.

18. The method of claim 14, further comprising: During the pre-verification phase, a first gate voltage is applied to the gate terminal of the TSG transistor in the second memory cell string. During the pre-verification phase, a third pass voltage is applied to the gate terminal of the first adjacent memory cell of the selected memory cell in the first memory cell string, and During the pre-verification phase, a fourth read voltage is applied to the gate terminal of the second adjacent memory cell of the selected memory cell in the first memory cell string; as well as During the verification phase, a second gate voltage is applied to the gate terminal of the TSG transistor in the second memory cell string; Wherein, at least one of the first through voltage and the second through voltage is greater than the second gate voltage.

19. The method of claim 18, further comprising: During the pre-verification phase and the verification phase, a bottom bias voltage is applied to the gate terminals of the BSG transistors in the first memory cell string; During the pre-verification phase and the verification phase, a top bias voltage is applied to the gate terminals of the TSG transistors in the first memory cell string; as well as During the pre-verification phase and the verification phase, a positive voltage is applied to the word line of any memory cell coupled between the first adjacent memory cell of the selected memory cell in the first memory cell string and the TSG transistor of the first memory cell string.

20. The method of claim 14, wherein, The first verification voltage is greater than the second verification voltage.

21. The method according to claim 14, wherein, In the first part of the pre-verification phase, the voltage applied to the word line of at least one memory cell coupled between the second adjacent memory cell of the selected memory cell in the first memory cell string and the BSG transistor of the first memory cell string increases from an initial voltage to the first bias voltage, then decreases to the second bias voltage, and remains at the second bias voltage in the second part of the pre-verification phase.

22. The method according to claim 21, wherein, The first verification voltage is less than the second verification voltage.

23. The method according to claim 18, wherein, The first gate voltage is greater than the second gate voltage.

24. The method according to claim 23, wherein, In the first part of the pre-verification phase, the voltage applied to the gate terminal of the TSG transistor of the second memory cell string increases from the initial voltage to the first gate voltage, then decreases to the second gate voltage, and remains at the second gate voltage in the second part of the pre-verification phase.

25. The method according to claim 18, wherein: During the pre-verification phase, the third through voltage is increased from the initial voltage to the second through voltage, and During the pre-verification phase, the fourth pass voltage is increased from the initial voltage to the first pass voltage.

26. The method according to claim 19, wherein: The bottom bias voltage increases from the initial voltage to a voltage that is maintained throughout the second part of the pre-verification phase and the verification phase. The top bias voltage increases from the initial voltage to a voltage maintained throughout the second part of the pre-verification phase and the verification phase, and During the pre-verification phase, the positive voltage increases from the initial voltage.

27. An apparatus for verifying a memory device including a first memory cell string and a second memory cell string, the first memory cell string including a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series, and the second memory cell string including a BSG transistor, a memory cell, and a TSG transistor connected in series, the apparatus comprising: Processing circuit, the processing circuit being configured to: During the pre-verification phase, a first verification voltage is applied to the word lines coupled to selected memory cells in the first memory cell string, the selected memory cells being arranged between a first adjacent memory cell and a second adjacent memory cell. During the pre-verification phase, a first bias voltage is applied to the word line coupled to at least one unprogrammed memory cell of the first memory cell string; During the verification phase, a second verification voltage is applied to the word line coupled to the selected memory cell in the first memory cell string; During the verification phase, a first pass voltage is applied to the word line coupled to the second adjacent memory cell of the selected memory cell in the first memory cell string; During the verification phase, a second pass voltage is applied to the word line coupled to the first adjacent memory cell of the selected memory cell in the first memory cell string; as well as During the verification phase, a second bias voltage is applied to the word line coupled to at least one unprogrammed memory cell of the first memory cell string; Wherein, the second bias voltage is less than the first bias voltage; At least one of the first through voltage and the second through voltage is greater than the second bias voltage.

28. The apparatus according to claim 27, wherein, The at least one memory cell of the first memory cell string that receives the first bias voltage and the second bias voltage is located between the first adjacent memory cell of the selected memory cell of the first memory cell string and the TSG transistor of the first memory cell string.

29. The apparatus according to claim 27, wherein, The at least one memory cell of the first memory cell string that receives the first bias voltage and the second bias voltage is located between the second adjacent memory cell of the selected memory cell of the first memory cell string and the BSG transistor of the first memory cell string.

30. The apparatus according to claim 27, wherein, The processing circuit is further configured to: During the pre-verification phase, a first gate voltage is applied to the gate terminal of the TSG transistor in the second memory cell string. During the pre-verification phase, a third pass voltage is applied to the word line coupled to the first adjacent memory cell of the selected memory cell in the first memory cell string, and During the pre-verification phase, a fourth pass voltage is applied to the word line coupled to the second adjacent memory cell of the selected memory cell in the first memory cell string; as well as During the verification phase, a second gate voltage is applied to the gate terminal of the TSG transistor in the second memory cell string; Wherein, at least one of the first through voltage and the second through voltage is greater than the second gate voltage.

31. The apparatus according to claim 30, wherein, The processing circuit is further configured to: During the pre-verification phase and the verification phase, a bottom bias voltage is applied to the gate terminals of the BSG transistors in the first memory cell string; During the pre-verification phase and the verification phase, a top bias voltage is applied to the gate terminals of the TSG transistors in the first memory cell string; as well as During the pre-verification phase and the verification phase, a positive voltage is applied to the word line coupled to at least one programmed memory cell of the first memory cell string.

32. The apparatus according to claim 27, wherein, The second bias voltage is 20% to 30% lower than the first bias voltage.

33. The apparatus according to claim 27, wherein, The second bias voltage is less than or equal to 3 volts.

34. The apparatus according to claim 27, wherein, At least one of the first through voltage and the second through voltage is greater than the first bias voltage.

35. The method according to claim 27, wherein, The first verification voltage is less than or greater than the second verification voltage.

36. The method according to claim 27, wherein, In the first part of the pre-verification phase, the voltage applied to the word line coupled to at least one unprogrammed memory cell of the first memory cell string increases from an initial voltage to the first bias voltage, then decreases to the second bias voltage, and remains at the second bias voltage in the second part of the pre-verification phase.

37. The method of claim 36, wherein, The first verification voltage is less than the second verification voltage.

38. The method according to claim 31, wherein, The first gate voltage is greater than the second gate voltage.

39. The method according to claim 38, wherein, In the first part of the pre-verification phase, the voltage applied to the gate terminal of the TSG transistor of the second memory cell string increases from the initial voltage to the first gate voltage, then decreases to the second gate voltage, and remains at the second gate voltage in the second part of the pre-verification phase.

40. The method according to claim 39, wherein, During the pre-verification phase, the third pass voltage increases from the initial voltage to the second pass voltage; During the pre-verification phase, the fourth pass voltage increases from the initial voltage to the first pass voltage; The bottom bias voltage increases from the initial voltage to a voltage that is maintained throughout the second part of the pre-verification phase and the verification phase. The top bias voltage increases from the initial voltage to a voltage maintained throughout the second part of the pre-verification phase and the verification phase, and During the pre-verification phase, the positive voltage increases from the initial voltage.

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