Method for manufacturing a semiconductor structure and semiconductor structure
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-07-05
- Publication Date
- 2026-07-21
Smart Images
Figure CN117423654B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology
[0002] Magnetic random access memory (MRAM) based on spin transfer torque (STT) is a non-volatile memory that uses current to change the state of magnetic tunnel junctions (MTJs) to perform write and read operations. However, the manufacturing process of magnetic random access memory is very complicated, and the design rules of magnetic random access memory limit its integration density.
[0003] Dynamic Random Access Memory (DRAM) offers high integration density. Combining Magnetic Random Access Memory (MRRAM) and DRAM can improve memory read / write capabilities and increase MRRAM density. However, the manufacturing processes for MRRAM and DRAM are difficult to integrate. Currently, MRRAM manufacturing is typically performed in later stages after DRAM fabrication. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.
[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.
[0006] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:
[0007] A substrate is formed, the substrate including a first region and a second region, the first region being provided with a plurality of first active regions, and the second region being provided with a plurality of second active regions;
[0008] Multiple first word lines and multiple first transistors are formed in the first region, and multiple second word lines and multiple second transistors are formed in the second region. The first word lines extend in the substrate along a first direction and intersect the first active region at an angle. The first transistors are located in the first active region and are connected to the first word lines. The second word lines extend in the substrate along the first direction and intersect the second active region. The second transistors are located in the second active region and are connected to the second word lines.
[0009] A plurality of capacitors are formed in the first region, and each capacitor is connected to each of the first transistors;
[0010] Multiple magnetic tunnel junctions are formed in the second region, and each magnetic tunnel junction is connected to each of the second transistors.
[0011] The method includes forming multiple first word lines and multiple first transistors in the first region, and forming multiple second word lines and multiple second transistors in the second region, including:
[0012] The substrate is etched to form a plurality of first word lines in the first region and a plurality of second word lines in the second region. Each first word line passes through a portion of the first active region along the first direction. The first word line divides the first active region into a first source, a first drain, and a first channel region. The first source and the first drain are separated by the first channel region. Each second word line extends along the first direction and passes through a portion of the second active region. The second word line divides the second active region into a second source, a second drain, and a second channel region. The second source and the second drain are separated by the second channel region.
[0013] The first word line is formed in the first word line slot, and the second word line is formed in the second word line slot. The first word line located in the first channel region and the first source and the first drain located on both sides of the first channel region form the first transistor. The second word line located in the second channel region and the second source and the second drain located on both sides of the second channel region form the second transistor.
[0014] The manufacturing method further includes:
[0015] Multiple bit line contact plugs are formed in the first region, and each bit line contact plug is connected to the first drain or the first source. At the same time, multiple source contact plugs are formed in the second region, and each source contact plug is connected to each second source.
[0016] A plurality of lower electrode contacts are formed in the second region, and each lower electrode contact is connected to each of the second drain electrodes;
[0017] Multiple first bit lines are formed in the first region, and multiple source lines and multiple first contact pads are formed in the second region. Each first bit line extends on the substrate along a second direction, which is perpendicular to the first direction. Each first bit line is connected to bit line contact plugs arranged along the second direction. Each source line extends on the substrate along the first direction and is connected to source contact plugs arranged along the first direction. Each lower electrode is correspondingly disposed on each lower electrode contact portion.
[0018] The first region contains multiple bit line contact plugs, and the second region contains multiple source contact plugs, including:
[0019] The first region is etched to remove a portion of the first active region, and a bit line contact hole is formed at the first drain or the first source. At the same time, the second region is etched to remove a portion of the second active region, and a source contact hole is formed at the second source and a lower electrode contact hole is formed at the second drain.
[0020] A conductive material is deposited to fill the bit line contact hole to form the bit line contact plug, the conductive material is filled to fill the source contact hole to form the source contact plug, and the conductive material is filled to fill the lower electrode contact hole.
[0021] The manufacturing method further includes:
[0022] The conductive material is deposited to cover the conductive material located in the lower electrode contact hole, forming the lower electrode contact portion, wherein the top surface of the lower electrode contact portion is higher than the top surface of the source contact plug.
[0023] Among them, multiple magnetic tunnel junctions are formed in the second region, including:
[0024] Multiple first magnetic material layers are formed in the second region, each first magnetic material layer extending along the first direction, and each first magnetic material layer is connected to the lower electrode contact portion arranged along the first direction;
[0025] A tunneling material layer is formed, which covers the first magnetic material layer and fills the gaps between adjacent first magnetic material layers;
[0026] Multiple second magnetic material layers are formed, each second magnetic material layer extending along the second direction, and the projection of each second magnetic material layer on the substrate and the projection of the lower electrode arranged along the second direction on the substrate have an overlap portion;
[0027] The first magnetic material layer and the second magnetic material layer form multiple intersections in the space above the substrate. The first magnetic material layer, the tunneling material layer and the second magnetic material layer at each intersection form the magnetic tunnel junction. The magnetic tunnel junction is connected through the lower electrode and the second drain electrode.
[0028] The manufacturing method further includes:
[0029] Multiple second bit lines are formed in the second region, each second bit line extending along the second direction, and each second bit line is connected to the magnetic tunnel junctions arranged along the second direction.
[0030] The manufacturing method further includes:
[0031] Multiple upper electrodes are formed in the second region, each upper electrode covering the top surface of each magnetic tunnel junction, and the upper electrode is disposed between the magnetic tunnel junction and the second bit line.
[0032] The first region contains a plurality of capacitors, including:
[0033] The first region is etched to remove part of the first active region, and a capacitor contact hole is formed at the first source or the first drain.
[0034] A capacitor contact plug is formed in the capacitor contact hole;
[0035] A conductive contact pad is formed, and the conductive contact pad is correspondingly disposed on the capacitor contact plug;
[0036] The capacitor is formed on each of the conductive contact pads, and the capacitor is connected to the first source or the first drain via the capacitive contact plug.
[0037] The manufacturing method further includes:
[0038] An electrode plate is formed in the first region, the electrode plate covers the top surface of a plurality of capacitors, and the plurality of capacitors are connected through the electrode plate.
[0039] The substrate provided includes:
[0040] Provide initial substrate;
[0041] The initial substrate is partially removed by etching, and a first trench is formed in the first region. The first trench divides the initial substrate in the first region into a plurality of first active regions. The first active regions extend along a third direction and intersect the first direction non-perpendicularly. At the same time, a second trench is formed in the second region. The second trench divides the initial substrate in the second region into a plurality of second active regions. The second active regions extend along a second direction and are perpendicular to the first direction.
[0042] An isolation structure is formed, filling the first trench and the second trench.
[0043] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:
[0044] The substrate includes a first region and a second region, wherein the first region is provided with a plurality of first active regions and the second region is provided with a plurality of second active regions;
[0045] The first region includes multiple first word lines, multiple first transistors, and multiple capacitors. The first word lines extend in the substrate along a first direction. The first word lines intersect the first active region at an angle. The first transistors are located within the first active region. The first transistors are connected to the first word lines. Each capacitor is connected to each of the first transistors.
[0046] The second region includes multiple second word lines, multiple second transistors, and multiple magnetic tunnel junctions. The second word lines extend in the substrate along the first direction and intersect with the second active region. The second transistors are located within the second active region and are connected to the second word lines. Each magnetic tunnel junction is connected to each of the second transistors.
[0047] The first transistor includes a first gate, a first source, and a first drain. The first gate is connected to the first word line, and the first source and the first drain are disposed in the first active region on both sides of the first gate. The first region further includes:
[0048] Multiple bit line contact plugs are connected to the first drain or the first source.
[0049] Multiple first bit lines, each first bit line extending along a second direction perpendicular to the first direction, and each first bit line being connected to a bit line contact plug arranged along the second direction.
[0050] The second transistor includes a second gate, a second source, and a second drain. The second gate is connected to the second word line, and the second source and the second drain are disposed in the second active region on both sides of the second gate. The second region further includes:
[0051] Multiple source contact plugs, each of which is connected to each of the second sources;
[0052] Multiple source lines, each source line extending along the first direction, and each source line connected to source contact plugs arranged along the first direction.
[0053] The second region also includes:
[0054] Multiple lower electrode contacts, each of which is connected to each of the second drain electrodes;
[0055] Multiple lower electrodes, each of which covers the top surface of each lower electrode contact portion, and the lower electrodes are disposed between the lower electrode contact portion and the magnetic tunnel junction;
[0056] Multiple upper electrodes, each of which covers the top surface of each magnetic tunnel junction;
[0057] Multiple second bit lines, each second bit line extending along a second direction perpendicular to the first direction, and each second bit line connected to the magnetic tunnel junction arranged along the second direction.
[0058] The semiconductor structure fabrication method and semiconductor structure disclosed herein form a first word line and a first transistor, a second word line and a second transistor in the same process, reducing the number of process steps in forming the semiconductor structure. Furthermore, non-volatile data storage functionality is implemented on the semiconductor structure, improving its storage capacity.
[0059] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0060] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.
[0061] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.
[0062] Figure 2 This is a schematic diagram illustrating the layout of a semiconductor structure according to an exemplary embodiment.
[0063] Figure 3 This is a schematic diagram of an initial substrate according to an exemplary embodiment.
[0064] Figure 4 This is a schematic diagram illustrating the formation of a first active region and a second active region according to an exemplary embodiment.
[0065] Figure 5 This is a schematic diagram illustrating the formation of a substrate according to an exemplary embodiment.
[0066] Figure 6 This is a top view of the first and second regions shown according to an exemplary embodiment.
[0067] Figure 7 This is a top view illustrating the formation of a first character groove and a second character groove according to an exemplary embodiment.
[0068] Figure 8 yes Figure 7 A cross-sectional view of section BB.
[0069] Figure 9 yes Figure 7 A cross-sectional view of the CC section.
[0070] Figure 10 This is a top view illustrating the formation of the first and second character lines according to an exemplary embodiment.
[0071] Figure 11 yes Figure 10 A cross-sectional view of section BB.
[0072] Figure 12 yes Figure 10 A cross-sectional view of the CC section.
[0073] Figure 13 This is a cross-sectional view of the BB section forming a bit line contact hole according to an exemplary embodiment.
[0074] Figure 14 This is a cross-sectional view of the CC section forming the source contact hole and the lower electrode contact hole according to an exemplary embodiment.
[0075] Figure 15 This is a cross-sectional view of a BB section forming a bit line contact plug, according to an exemplary embodiment.
[0076] Figure 16This is a cross-sectional view of the CC section showing the formation of the source contact plug and the lower electrode contact portion according to an exemplary embodiment.
[0077] Figure 17 This is a top view illustrating the formation of a bit line contact plug, a source contact plug, and a lower electrode contact portion according to an exemplary embodiment.
[0078] Figure 18 This is a top view illustrating the formation of the first electrode line, the source contact line, and the lower electrode according to an exemplary embodiment.
[0079] Figure 19 yes Figure 18 A cross-sectional view of section BB.
[0080] Figure 20 yes Figure 18 A cross-sectional view of the CC section.
[0081] Figure 21 This is a cross-sectional view of the BB section forming a capacitor contact hole, according to an exemplary embodiment.
[0082] Figure 22 This is a cross-sectional view of a BB section forming a capacitive contact plug, according to an exemplary embodiment.
[0083] Figure 23 This is a cross-sectional view of a BB section forming a conductive contact pad, according to an exemplary embodiment.
[0084] Figure 24 This is a top view illustrating the formation of a conductive contact pad according to an exemplary embodiment.
[0085] Figure 25 This is a top view illustrating the formation of a capacitor column according to an exemplary embodiment.
[0086] Figure 26 This is a top view illustrating the formation of an electrode plate according to an exemplary embodiment.
[0087] Figure 27 This is a top view illustrating the formation of a first magnetic material layer according to an exemplary embodiment.
[0088] Figure 28 This is a top view illustrating the formation of a second magnetic material layer according to an exemplary embodiment.
[0089] Figure 29 This is a top view illustrating the formation of the upper electrode according to an exemplary embodiment.
[0090] Figure 30 This is a top view illustrating the formation of a first magnetic material layer according to an exemplary embodiment.
[0091] Figure 31 yes Figure 30 A cross-sectional view of section BB.
[0092] Figure 32 yes Figure 30 A cross-sectional view of the CC section.
[0093] Figure label:
[0094] 100a, Initial substrate; 100, Substrate; 10, Dynamic Random Access Memory (DRAM); 101, First region; 102, Second region; 103, Peripheral circuit region; 110, First active region; 111, First source; 112, First drain; 113, First channel region; 114, First gate; 120, Second active region; 121, Second source; 122, Second drain; 123, Second channel region; 124, Second gate; 130, Isolation structure; 140, First trench; 150, Second trench; 20, Magnetic Random Access Memory (DRAM); 201, First word line slot; 202, Second word line slot; 210, First word line; 220, Second word line. 1. Bit line; 230. Isolation layer; 310. First transistor; 320. Second transistor; 401. Bit line contact hole; 402. Source contact hole; 403. Lower electrode contact hole; 410. Bit line contact plug; 420. Source contact plug; 430. Lower electrode contact portion; 510. First bit line; 520. Source line; 530. Lower electrode; 601. Capacitor contact hole; 610. Capacitor contact plug; 620. Conductive contact pad; 630. Capacitor; 640. Electrode plate; 700. Magnetic tunnel junction; 710. First magnetic material layer; 720. Tunneling material layer; 730. Second magnetic material layer; 800. Upper electrode; 900. Second bit line;
[0095] D1, First Direction; D2, Second Direction; D3, Third Direction. Detailed Implementation
[0096] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0097] The exemplary embodiments disclosed herein provide a method for fabricating a semiconductor structure and a semiconductor structure, applying the fabrication process of dynamic random access memory to the fabrication of magnetic random access memory, simplifying the fabrication process of forming magnetic random access memory, improving the integration density of magnetic random access memory, and also improving the storage capacity of the semiconductor structure.
[0098] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 2-32 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 2-32 The methods for fabricating semiconductor structures are introduced.
[0099] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:
[0100] Step S110: Form a substrate, the substrate including a first region and a second region, the first region being provided with a plurality of first active regions, and the second region being provided with a plurality of second active regions.
[0101] Reference Figure 2 As shown, substrate 100 defines a first region 101 and a second region 102, which may be adjacent or independently disposed. Substrate 100 also includes a peripheral circuit region 103 surrounding the first region 101 and the second region 102. The first region 101 and the second region 102 are used for data storage. (Refer to...) Figure 30 In this embodiment, the first region 101 is used to form a volatile dynamic random access memory 10, the second region 102 is used to form a non-volatile magnetic random access memory 20, and the peripheral circuit region 103 is used to form transistors with other functions (such as testing functions) and contact structures, etc.
[0102] like Figure 5 A cross-section AA of the first region 101 and the second region 102 of the substrate 100 is shown (reference). Figure 6 A cross-sectional view, such as Figure 5 A top view of a first region 101 and a second region 102 of a substrate 100 is shown. In this embodiment, providing the substrate 100 includes the following steps:
[0103] First, an initial substrate 100a is provided. For example... Figure 3 A cross-section AA of the first region 101 and the second region 102 of the initial substrate 100a is shown (refer to). Figure 6The cross-sectional view of the substrate 100a shows that the initial substrate 100a can be a semiconductor substrate. The semiconductor substrate material can include semiconductor materials, such as silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC); the semiconductor material can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide and other III-V compounds.
[0104] Then, as Figure 4 A cross-section AA (see reference) shows a first groove 140 formed in the first region 101 and a second groove 150 formed in the second region 102. Figure 6 (See the cross-sectional view of the diagram.) Figure 3 , Figure 5 A portion of the initial substrate 100a is etched away, forming a first trench 140 in the first region 101. The first trench 140 divides the initial substrate 100a in the first region 101 into multiple first active regions 110. The first active regions 110 extend along a third direction D3. At the same time, a second trench 150 is formed in the second region 102, dividing the initial substrate 100a in the second region 102 into multiple second active regions 120. The second active regions 120 extend along a second direction D2. There is an angle between the second direction D2 and the third direction D3, that is, the first active regions 110 and the second active regions 120 are set in different directions.
[0105] Next, as Figure 5 As shown, refer to Figure 4 An isolation structure 130 is formed, which fills the first trench 140 and the second trench 150. For example, an isolation material is deposited using any of the following deposition processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or sputtering. The isolation material fills the first trench 140 and the second trench 150 to form the isolation structure 130. The material of the isolation structure 130 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.
[0106] like Figure 5 , Figure 6 As shown, the first active region 110, the second active region 120 and the isolation structure 130 together form the substrate 100.
[0107] Step S120: Multiple first word lines and multiple first transistors are formed in the first region, and multiple second word lines and multiple second transistors are formed in the second region.
[0108] like Figure 10 As shown, the first word line 210 extends in the substrate 100 along the first direction D1. The first word line 210 and the first active region 110 intersect at an angle. The first transistor 310 is located in the first active region 110 and is connected to the first word line 210.
[0109] like Figure 10 As shown, the second word line 220 extends in the substrate 100 along the first direction D1, intersects with the second active region 120, and the second transistor 320 is located within the second active region 120. The second transistor 320 is connected to the second word line 220. In this embodiment, the first direction D1 and the third direction D3 intersect non-perpendicularly, and the first direction D1 and the second direction D2 are perpendicular.
[0110] In this embodiment, multiple first word lines 210 and multiple first transistors 310 are formed in the first region 101, and multiple second word lines 220 and multiple second transistors 320 are formed in the second region 102, including:
[0111] First, such as Figure 7 As shown, refer to Figure 6 The substrate 100 is etched to remove a portion of the first active region 110, a portion of the second active region 120, and a portion of the isolation structure 130. Multiple first word line slots 201 are formed in the first region 101, and multiple second word line slots 202 are formed in the second region 102. Each first word line slot 201 extends along a first direction D1 and passes through a portion of the first active region 110 along the first direction D1. Figure 7 , Figure 8 As shown, each first active region 110 is traversed by two adjacent first word slots 201. The first word slots 201 divide the first active region 110 into a first source 111, a first drain 112, and a first channel region 113. The first channel region 113 is connected to the first word slots 201, and the first source 111 and the first drain 112 are separated by the first channel region 113. Figure 7 , Figure 9 As shown, each second word groove 202 extends along the first direction D1 and passes through a portion of the second active region 120. The second word groove 202 divides the second active region 120 into a second source 121, a second drain 122, and a second channel region 123. The second channel region 123 is connected to the second word groove 202, and the second source 121 and the second drain 122 are separated by the second channel region 123.
[0112] Then, as Figure 10 As shown, refer to Figure 7 A first character line 210 is formed in the first character line groove 201, and a second character line 220 is formed in the second character line groove 202.
[0113] like Figure 10 , Figure 11 As shown, refer to Figure 7 , Figure 8 In the first direction D1, the first word line 210 covers multiple first channel regions 113. The first word line 210 and the first channel regions 113 are connected. The first word line 210 located in the first channel region 113 serves as the first gate 114 of the first transistor 310. The first gate 114 and the first source 111 and the first drain 112 located on both sides of the first channel region 113 form the first transistor 310. Two first transistors 310 are formed in each first active region 110.
[0114] For example Figure 10 , Figure 12 As shown, refer to Figure 7 , Figure 9 In the first direction D1, the second word line 220 covers a plurality of second channel regions 123. The second word line 220 and the second channel regions 123 are connected. The second word line 220 located in the second channel region 123 serves as the second gate 124. The second gate 124 and the second source 121 and the second drain 122 located on both sides of the second channel region 123 form a second transistor 320. Two second transistors 320 are formed in each second active region 120.
[0115] like Figure 10 , Figure 11 , Figure 12 As shown, the top surfaces of the first word line 210 and the second word line 220 are lower than the top surface of the substrate 100. In this embodiment, after forming the first word line 210 and the second word line 220, an isolation layer 230 is also deposited. The isolation layer 230 covers the top surfaces of the first word line 210 and the second word line 220. The top surface of the isolation layer 230 is flush with the top surface of the substrate 100. The isolation layer 230 is used to prevent short circuits in the semiconductor devices in the substrate 100.
[0116] Step S130: A plurality of bit line contact plugs are formed in the first region, each bit line contact plug being connected to the first source or the first drain. At the same time, a plurality of source contact plugs are formed in the second region, each source contact plug being connected to each second source.
[0117] like Figure 13 , Figure 14 As shown, firstly, the first region 101 and the second region 102 are etched to remove a portion of the first active region 110 and a portion of the second active region 120. Bit line contact holes 401 are formed at the first drain 112 or the first source 111 of each first active region 110, source contact holes 402 are formed at the second source 121 of each second active region 120, and lower electrode contact holes 403 are formed at the second drain 122 of each second active region 120.
[0118] like Figure 15 , Figure 16 , Figure 17 As shown, refer to Figure 13 , Figure 14 Then, a conductive material is deposited using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The conductive material fills the bit line contact holes 401 to form bit line contact plugs 410, fills the source contact holes 402 to form source contact plugs 420, and fills the lower electrode contact holes 403. In this embodiment, the deposited conductive material includes polysilicon, and both the material of the bit line contact plugs 410 and the material of the source contact plugs 420 include polysilicon.
[0119] Step S140: A plurality of lower electrode contacts are formed in the second region, and each lower electrode contact is connected to each second drain electrode.
[0120] Reference Figure 15 , Figure 16 First, a first mask layer (not shown in the figure) is formed, which covers the bit line contact plug 410 and the source contact plug 420, and exposes the conductive material located in the lower electrode contact hole 403.
[0121] like Figure 16 , Figure 17 As shown, refer to Figure 14 Then, conductive material is deposited again using any of the above deposition processes to cover the conductive material located in the lower electrode contact hole 403, forming the lower electrode contact portion 430. The top surface of the lower electrode contact portion 430 is higher than the top surface of the source contact plug 420. In this embodiment, the material of the lower electrode contact portion 430 includes polycrystalline silicon.
[0122] Step S150: Multiple first-position lines are formed in the first region, and multiple source lines and multiple lower electrodes are formed in the second region.
[0123] like Figure 18 , Figure 19 As shown, each first bit line 510 extends on the substrate 100 along the second direction D2, and each first bit line 510 is connected to bit line contact plugs 410 arranged along the second direction D2. In the second direction D2, the first bit line 510 is connected to the first drain 112 or the first source 111 of a plurality of first transistors 310 through the bit line contact plugs 410.
[0124] like Figure 18 , Figure 20As shown, each source line 520 extends on the substrate 100 along the first direction D1, and each source line 520 is connected to the source contact plugs 420 arranged along the first direction D1. The second source 121 of the second transistor 320 is connected to the source line 520, and each lower electrode 530 is correspondingly disposed on each lower electrode contact portion 430.
[0125] The material of the lower electrode 530 may include at least one of conductive metal, conductive metal nitride, and conductive alloy. For example, conductive metals include titanium, tantalum, and tungsten.
[0126] Step S160: A plurality of capacitors are formed in the first region, and each capacitor is connected to each first transistor.
[0127] Reference Figure 18 First, a second mask layer (not shown in the figure) is formed in the second region 102.
[0128] like Figure 21 As shown, refer to Figure 18 , Figure 19 Then, the first region 101 is etched to remove a portion of the first active region 110, forming a capacitor contact hole 601 at the first source 111 or the first drain 112. (Refer to...) Figure 31 As shown, each first transistor 310 has a corresponding capacitor contact hole 601 formed on its first source 111 or first drain 112.
[0129] like Figure 22 As shown, refer to Figure 21 Then, conductive material is deposited to fill the capacitor contact hole 601 using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering, forming a capacitor contact plug 610 in the capacitor contact hole 601. The material of the capacitor contact plug 610 includes semiconductor materials, such as monocrystalline silicon or polycrystalline silicon.
[0130] like Figure 23 , Figure 24 As shown, refer to Figure 18 , Figure 22 A conductive contact pad 620 is formed, which is correspondingly disposed on the capacitor contact plug 610. The material of the conductive contact pad 620 includes metallic materials, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).
[0131] like Figure 25 As shown, refer to Figure 31As shown, a capacitor 630 is formed on each conductive contact pad 620, and the capacitor 630 is connected to the first source 111 or the first drain 112 through a capacitor contact plug 610.
[0132] like Figure 26 As shown, in this embodiment, after forming the capacitor 630, the method further includes the following steps: forming an electrode plate 640 in the first region 101, the electrode plate 640 covering the top surface of the plurality of capacitors 630, and the plurality of capacitors 630 being connected through the electrode plate 640. For example, a conductive material can be deposited by any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The conductive material covers the top surface of the plurality of capacitors 630 and fills the gaps between the capacitors 630 to form the electrode plate 640. In this embodiment, the material of the electrode plate 640 includes germanium silicon.
[0133] After forming the electrode plate 640, the second mask layer located in the second region 102 is removed to expose the second region 102 for subsequent processing.
[0134] Step S170: A plurality of magnetic tunnel junctions are formed in the second region, and each magnetic tunnel junction is connected to each second transistor.
[0135] Before the formation of multiple magnetic tunnel junctions 700, refer to Figure 26 First, a third mask layer (not shown in the figure) is formed in the first region 101. The third mask layer covers the electrode plate 640 to avoid damage to the semiconductor device in the first region 101 by the process of the second region 102 in subsequent steps.
[0136] Then, a medium layer 160 is formed in the second region 102 by depositing medium material (refer to...). Figure 32 As shown, dielectric layer 160 covers source line 520, source contact plug 420, lower electrode 530, and the top surface of substrate 100 of second region 102. Then, the top surface of dielectric layer 160 is planarized to expose the top surface of each lower electrode 530.
[0137] In this embodiment, multiple magnetic tunnel junctions 700 are formed in the second region 102, which can be implemented using the following methods:
[0138] like Figure 27 , Figure 32 As shown, firstly, multiple first magnetic material layers 710 are formed in the second region 102. Each first magnetic material layer 710 extends along the first direction D1, and each first magnetic material layer 710 is connected to the lower electrode 530 arranged along the first direction D1.
[0139] In this embodiment, a first magnetic material can be deposited by magnetron sputtering or arc ion plating (AIP). The first magnetic material covers the top surface of the lower electrode 530 and the top surface of the dielectric layer to form an initial first magnetic material layer (not shown in the figure). Then, the initial first magnetic material layer is patterned to form multiple first magnetic material layers 710, each of which extends along a first direction D1 and covers the top surface of the lower electrodes 530 arranged along the first direction D1.
[0140] Reference Figure 32 As shown, a tunneling material layer 720 is then formed, which covers the first magnetic material layer 710 and fills the gaps between adjacent first magnetic material layers 710.
[0141] In this embodiment, the tunneling material layer 720 can be formed by any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The material of the tunneling material layer 720 includes an insulating material, such as an oxide. For example, the material of the tunneling material layer 720 may include aluminum oxide (AlOx) or magnesium oxide (MgO).
[0142] like Figure 28 , Figure 32 As shown, next, multiple second magnetic material layers 730 are formed, each second magnetic material layer 730 extending along the second direction D2, and the projection of each second magnetic material layer 730 on the substrate 100 and the projection of the lower electrode 530 arranged along the second direction D2 on the substrate 100 have an overlapping portion.
[0143] In this embodiment, a second magnetic material can be deposited by magnetron sputtering or arc ion plating to form an initial second magnetic material layer (not shown in the figure) on the top surface of the tunneling material layer 720. Then, the initial second magnetic material layer is patterned to form multiple second magnetic material layers 730. The second magnetic material layers 730 extend along a second direction D2, and the projection of the second magnetic material layer 730 onto the substrate 100 overlaps with the projection of the lower electrodes 530 arranged along the second direction D2 onto the substrate 100. The first magnetic material and the second magnetic material can include the same or different ferromagnetic alloys. For example, the ferromagnetic alloy can be selected from at least one of nickel (Ni), iron (Fe), cobalt (Co), aluminum (Al), boron (B), molybdenum (Mo), hafnium (Hf), palladium (Pd), platinum (Pt), and copper (Cu).
[0144] like Figure 28 , Figure 32As shown, the first magnetic material layer 710 and the second magnetic material layer 730 form multiple intersections in the space above the substrate 100. The first magnetic material layer 710, the tunneling material layer 720 and the second magnetic material layer 730 at each intersection form a magnetic tunnel junction 700. The magnetic tunnel junction 700 is connected through the lower electrode 530 and the second drain 122.
[0145] In this embodiment, as Figure 28 , Figure 32 As shown, a first magnetic material layer 710, a tunneling material layer 720, and a second magnetic material layer 730 are sequentially formed above the substrate 100 in the second region 102. A magnetic tunnel junction 700 is formed at each intersection of the first magnetic material layer 710 and the second magnetic material layer 720. Multiple magnetic tunnel junctions 700 are arrayed above the substrate 100 along a first direction D1 and a second direction D2. The arrangement rule of the magnetic tunnel junctions 700 is the same as that of the second transistor 320. The magnetic tunnel junctions 700 and the second transistor 320 are connected in a one-to-one correspondence, which can improve the storage density of the second region 102. Furthermore, in this embodiment, it is not necessary to etch the magnetic tunnel junctions 700 into independent pillar structures, increasing the process window for forming the magnetic tunnel junctions 700, reducing damage to the magnetic tunnel junctions 700 during the etching process, ensuring good performance of the magnetic tunnel junctions 700, and improving the yield of the final semiconductor structure.
[0146] Step S180: A plurality of upper electrodes are formed in the second region, each upper electrode covering the top surface of each magnetic tunnel junction, and the upper electrodes are disposed between the magnetic tunnel junction and the second bit line.
[0147] In this embodiment, a plurality of upper electrodes 800 are formed in the second region 102, which can be implemented in the following manner:
[0148] like Figure 29 , Figure 32 As shown, refer to Figure 28 The metal material can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The metal material covers the second magnetic material layer 730 to form a first metal layer (not shown in the figure). Then, the first metal layer is patterned to form a plurality of upper electrodes 800, with one upper electrode 800 corresponding to each magnetic tunnel junction 700. The plurality of upper electrodes 800 and the plurality of magnetic tunnel junctions 700 are arranged in the same pattern, and the plurality of upper electrodes 800 are arrayed along the first direction D1 and the second direction D2.
[0149] Step S190: Form multiple second bit lines in the second region, each second bit line extending along the second direction, and each second bit line connecting to magnetic tunnel junctions arranged along the second direction.
[0150] like Figure 30 , Figure 32 As shown, refer to Figure 29 The second bit line 900 extends along the second direction D2, and each second bit line 900 covers part of the top surface of the upper electrode 800 arranged along the second direction D2. The magnetic tunnel junction 700 is connected through the upper electrode 800 and the second bit line 900.
[0151] Reference Figure 30 , Figure 31 As shown, each first transistor 310 is provided with a corresponding capacitor 630. The first gate 114 of each first transistor 310 is connected to the first word line 210, the first source 111 or the first drain 112 is connected to the capacitor 630, and the first drain 112 or the first source 111 is connected to the first bit line 510. Each first transistor 310 and its corresponding capacitor 630 form a dynamic random access memory 10. The dynamic random access memory 10 is arrayed in the first region 101 along the first direction D1 and the third direction D3.
[0152] like Figure 30 , Figure 32 As shown, each second transistor 320 has a corresponding magnetic tunnel junction 700. The second gate 124 of the second transistor 320 is connected to the second word line 220, the second source 121 is connected to the source line 520, and the second drain 122 is connected to the corresponding magnetic tunnel junction 700. Each second transistor 320, its corresponding magnetic tunnel junction 700, the lower electrode 530 disposed at the bottom of the magnetic tunnel junction 700, and the upper electrode 800 disposed on the top surface of the magnetic tunnel junction 700 together form a magnetic random access memory 20. The magnetic random access memory 20 is arrayed in the second region 102 along the first direction D1 and the second direction D2.
[0153] The fabrication method of this embodiment applies the fabrication process of dynamic random access memory (DRAM) to that of magnetic random access memory (MRMemory). A first word line and a first transistor, a second word line and a second transistor are formed in the same process. A first bit line and a source line are formed in the same process. Capacitors and magnetic tunnel junctions are formed in different processes. Thus, DRAM and MRMemory are formed within the same semiconductor structure, improving the read / write and storage capabilities of the semiconductor structure. Furthermore, in this embodiment, the second active region and the second word line are arranged perpendicularly so that the formed second transistors are arrayed along the first and second directions. A magnetic tunnel junction is formed according to the arrangement rules of the second transistors, increasing the storage density of the second region.
[0154] The fabrication method of this embodiment embeds the second word line into the substrate disposed in the second region, which increases the channel length of the second transistor, thereby improving the channel current and driving capability of the second transistor and ensuring good performance of the submagnetic random access memory.
[0155] According to an exemplary embodiment, this embodiment provides a semiconductor structure, which is formed by the fabrication method of the above embodiments. For example... Figure 2 , Figure 30 , Figure 31 , Figure 32 As shown, the semiconductor structure includes a substrate 100, which includes a first region 101 and a second region 102. The first region 101 is provided with a plurality of dynamic random access memories 10, and the second region 102 is provided with a plurality of magnetic random access memories 20, as shown below. Figure 2 As shown, the semiconductor structure also includes a peripheral circuit region 103, which surrounds the first region 101 and the second region 102. The peripheral circuit region 103 is provided with transistors having other functions (such as testing functions) and contact structures, etc. The semiconductor structure of this embodiment includes a volatile dynamic random access memory 10 and a non-volatile magnetic random access memory 20, which improves the read / write capability and storage capability of the semiconductor structure.
[0156] like Figure 30 , Figure 31 , Figure 32 As shown, the first region 101 is provided with a plurality of first active regions 110, and the second region 102 is provided with a plurality of second active regions 120. The semiconductor structure also includes a plurality of first word lines 210, a plurality of first transistors 310, and a plurality of capacitors 630 located in the first region 101. The first word lines 210 extend in the substrate 100 along a first direction D1. The first word lines 210 and the first active regions 110 intersect at an angle. The first transistors 310 are located within the first active regions 110 and are connected to the first word lines 210. Each capacitor 630 is connected to each first transistor 310. The semiconductor structure also includes multiple second word lines 220, multiple second transistors 320, and multiple magnetic tunnel junctions 700 located in the second region 102. The second word lines 220 extend in the substrate 100 along the first direction D1 and intersect with the second active region 120. The second transistors 320 are located in the second active region 120 and are connected to the second word lines 220. Each magnetic tunnel junction 700 is connected to each second transistor 320.
[0157] According to an exemplary embodiment, such as Figure 31 As shown, the first transistor 310 includes a first gate 114, a first source 111 and a first drain 112. The first gate 114 is connected to the first word line 210, and the first source 111 and the first drain 112 are respectively disposed in the first active regions 110 on both sides of the first gate 114.
[0158] like Figure 31As shown, the first region 101 also includes a plurality of bit line contact plugs 410 and a plurality of first bit lines 510. The bit line contact plugs 410 are connected to the first drain 112 or the first source 111. Each first bit line 510 extends along a second direction D2, which is perpendicular to the first direction D1. Each first bit line 510 is connected to the bit line contact plugs 410 arranged along the second direction D2.
[0159] According to an exemplary embodiment, such as Figure 31 As shown, the first region 101 also includes a plurality of capacitor contact plugs 610 and conductive contact pads 620. The plurality of capacitor contact plugs 610 are disposed in the first active region 110, and each capacitor contact plug 610 is connected to the first drain 112 or the first source 111 of each first transistor 310. The plurality of conductive contact pads 620 and the plurality of capacitor contact plugs 610 are arranged in a one-to-one correspondence. Each conductive contact pad 620 is disposed on its corresponding capacitor contact plug 610 and is disposed between the capacitor contact plug 610 and the capacitor 630 to reduce the contact resistance between the capacitor 630 and the capacitor contact plug 610.
[0160] like Figure 31 As shown, the first region 101 also includes an electrode plate 640, which covers the top surface of a plurality of capacitors 630 and fills the gaps between the capacitors 630, and the plurality of capacitors 630 are connected through the electrode plate 640.
[0161] like Figure 31 As shown, each first transistor 310 and its corresponding capacitor 630 form a dynamic random access memory 10, and multiple dynamic random access memories 10 are arrayed in the first region 101 along the first direction D1 and the third direction D3.
[0162] According to an exemplary embodiment, such as Figure 32 As shown, the second transistor 320 includes a second gate 124, a second source 121, and a second drain 122. The second gate 124 is connected to the second word line 220, and the second source 121 and the second drain 122 are disposed in the second active region 120 on both sides of the second gate 124.
[0163] like Figure 32 As shown, the second region 102 also includes a plurality of source contact plugs 420 and a plurality of source lines 520. Each source contact plug 420 is connected to each second source 121. Each source line 520 extends along the first direction D1 and is connected to the source contact plugs 420 arranged along the first direction D1.
[0164] According to an exemplary embodiment, such as Figure 32As shown, the second region 102 also includes a plurality of lower electrode contacts 430, a plurality of lower electrodes 530, a plurality of upper electrodes 800, and a plurality of second bit lines 900. Each lower electrode contact 430 is correspondingly connected to each second drain 122. Each lower electrode correspondingly covers the top surface of each lower electrode contact 430. The lower electrode 530 is disposed between the lower electrode contact 430 and the magnetic tunnel junction 700. Each lower electrode 530 correspondingly covers the top surface of each magnetic tunnel junction 700. Each second bit line 900 extends along a second direction D2, which is perpendicular to the first direction D1. Each second bit line 900 is connected to the magnetic tunnel junctions 700 arranged along the second direction D2.
[0165] like Figure 32 As shown, each second transistor 320, together with its corresponding magnetic tunnel junction 700, a lower electrode 530 disposed at the bottom of the magnetic tunnel junction 700, and an upper electrode 800 disposed on the top surface of the magnetic tunnel junction 700, forms a magnetic random access memory 20. Multiple magnetic random access memory regions 20 are arrayed in the second region 102 along a first direction D1 and a second direction D2.
[0166] In this embodiment, the semiconductor structure comprises a dynamic random access memory (DRAM) formed by each first transistor and its corresponding capacitor, and a magnetic random access memory (MRMemory) formed by each second transistor, its corresponding magnetic tunnel junction, a lower electrode at the bottom of the magnetic tunnel junction, and an upper electrode on the top surface of the magnetic tunnel junction. The semiconductor structure includes both DRAM and MRMemory, thus improving the storage capacity of the semiconductor structure. The MRMemory is arrayed in the second region along the first and second directions, increasing the storage density of the second region. Furthermore, the second transistors of the MRMemory are embedded transistors, with longer channel lengths and stronger driving capabilities, ensuring excellent performance of the MRMemory.
[0167] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0168] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.
[0169] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.
[0170] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.
[0171] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.
[0172] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.
[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A substrate is formed, the substrate including a first region and a second region, the first region being provided with a plurality of first active regions, and the second region being provided with a plurality of second active regions; Multiple first word lines and multiple first transistors are formed in the first region, and multiple second word lines and multiple second transistors are formed in the second region. The first word lines extend in the substrate along a first direction and intersect the first active region at an angle. The first transistors are located in the first active region and are connected to the first word lines. The second word lines extend in the substrate along the first direction and intersect the second active region. The second transistors are located in the second active region and are connected to the second word lines. A plurality of capacitors and electrode plates are formed in the first region, each capacitor is connected to each of the first transistors, the electrode plates cover the top surfaces of the plurality of capacitors, and the plurality of capacitors are connected through the electrode plates; Multiple magnetic tunnel junctions and multiple upper electrodes are formed in the second region, each magnetic tunnel junction is connected to each of the second transistors, and each upper electrode covers the top surface of each magnetic tunnel junction.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Multiple first word lines and multiple first transistors are formed in the first region, and multiple second word lines and multiple second transistors are formed in the second region, including: The substrate is etched to form a plurality of first word lines in the first region and a plurality of second word lines in the second region. Each first word line passes through a portion of the first active region along the first direction. The first word line divides the first active region into a first source, a first drain, and a first channel region. The first source and the first drain are separated by the first channel region. Each second word line extends along the first direction and passes through a portion of the second active region. The second word line divides the second active region into a second source, a second drain, and a second channel region. The second source and the second drain are separated by the second channel region. The first word line is formed in the first word line slot, and the second word line is formed in the second word line slot. The first word line located in the first channel region and the first source and the first drain located on both sides of the first channel region form the first transistor. The second word line located in the second channel region and the second source and the second drain located on both sides of the second channel region form the second transistor.
3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The manufacturing method further includes: Multiple bit line contact plugs are formed in the first region, and each bit line contact plug is connected to the first drain or the first source. At the same time, multiple source contact plugs are formed in the second region, and each source contact plug is connected to each second source. A plurality of lower electrode contacts are formed in the second region, and each lower electrode contact is connected to each of the second drain electrodes; Multiple first bit lines are formed in the first region, and multiple source lines and multiple first contact pads are formed in the second region. Each first bit line extends on the substrate along a second direction, which is perpendicular to the first direction. Each first bit line is connected to bit line contact plugs arranged along the second direction. Each source line extends on the substrate along the first direction and is connected to source contact plugs arranged along the first direction. Each lower electrode is correspondingly disposed on each lower electrode contact portion.
4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Multiple bit line contact plugs are formed in the first region, and multiple source contact plugs are formed in the second region, including: The first region is etched to remove a portion of the first active region, and a bit line contact hole is formed at the first drain or the first source. At the same time, the second region is etched to remove a portion of the second active region, and a source contact hole is formed at the second source and a lower electrode contact hole is formed at the second drain. A conductive material is deposited to fill the bit line contact hole to form the bit line contact plug, the conductive material is filled to fill the source contact hole to form the source contact plug, and the conductive material is filled to fill the lower electrode contact hole.
5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The manufacturing method further includes: The conductive material is deposited to cover the conductive material located in the lower electrode contact hole, forming the lower electrode contact portion, wherein the top surface of the lower electrode contact portion is higher than the top surface of the source contact plug.
6. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Multiple magnetic tunnel junctions are formed in the second region, including: Multiple first magnetic material layers are formed in the second region, each first magnetic material layer extending along the first direction, and each first magnetic material layer is connected to the lower electrode contact portion arranged along the first direction; A tunneling material layer is formed, which covers the first magnetic material layer and fills the gaps between adjacent first magnetic material layers; Multiple second magnetic material layers are formed, each second magnetic material layer extending along the second direction, and the projection of each second magnetic material layer on the substrate and the projection of the lower electrode arranged along the second direction on the substrate have an overlap portion; The first magnetic material layer and the second magnetic material layer form multiple intersections in the space above the substrate. The first magnetic material layer, the tunneling material layer and the second magnetic material layer at each intersection form the magnetic tunnel junction. The magnetic tunnel junction is connected through the lower electrode and the second drain electrode.
7. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The manufacturing method further includes: Multiple second bit lines are formed in the second region, each second bit line extending along the second direction, and each second bit line is connected to the magnetic tunnel junctions arranged along the second direction.
8. The method for fabricating a semiconductor structure according to claim 7, characterized in that: The upper electrode is disposed between the magnetic tunnel junction and the second bit line.
9. The method for fabricating a semiconductor structure according to claim 2, characterized in that, Multiple capacitors are formed in the first region, including: The first region is etched to remove part of the first active region, and a capacitor contact hole is formed at the first source or the first drain. A capacitor contact plug is formed in the capacitor contact hole; A conductive contact pad is formed, and the conductive contact pad is correspondingly disposed on the capacitor contact plug; The capacitor is formed on each of the conductive contact pads, and the capacitor is connected to the first source or the first drain via the capacitive contact plug.
10. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Provide a substrate, including: Provide initial substrate; The initial substrate is partially removed by etching, and a first trench is formed in the first region. The first trench divides the initial substrate in the first region into a plurality of first active regions. The first active regions extend along a third direction and intersect the first direction non-perpendicularly. At the same time, a second trench is formed in the second region. The second trench divides the initial substrate in the second region into a plurality of second active regions. The second active regions extend along a second direction and are perpendicular to the first direction. An isolation structure is formed, filling the first trench and the second trench.
11. A semiconductor structure, characterized in that, The semiconductor structure includes: The substrate includes a first region and a second region, wherein the first region is provided with a plurality of first active regions and the second region is provided with a plurality of second active regions; The first region includes multiple first word lines, multiple first transistors, multiple capacitors, and an electrode plate. The first word lines extend in the substrate along a first direction and intersect the first active region at an angle. The first transistors are located within the first active region and are connected to the first word lines. Each capacitor is connected to each first transistor. The electrode plate covers the top surface of the multiple capacitors and the multiple capacitors are connected through the electrode plate. The second region includes multiple second word lines, multiple second transistors, multiple magnetic tunnel junctions, and multiple top electrodes. The second word lines extend in the substrate along the first direction and intersect with the second active region. The second transistors are located within the second active region and are connected to the second word lines. Each magnetic tunnel junction is connected to each second transistor, and each top electrode covers the top surface of each magnetic tunnel junction.
12. The semiconductor structure according to claim 11, characterized in that, The first transistor includes a first gate, a first source, and a first drain. The first gate is connected to the first word line, and the first source and the first drain are disposed in the first active region on both sides of the first gate. The first region further includes: Multiple bit line contact plugs are connected to the first drain or the first source. Multiple first bit lines, each first bit line extending along a second direction perpendicular to the first direction, and each first bit line being connected to a bit line contact plug arranged along the second direction.
13. The semiconductor structure according to claim 11, characterized in that, The second transistor includes a second gate, a second source, and a second drain. The second gate is connected to the second word line, and the second source and the second drain are disposed in the second active region on both sides of the second gate. The second region also includes: Multiple source contact plugs, each of which is connected to each of the second sources; Multiple source lines, each source line extending along the first direction, and each source line connected to source contact plugs arranged along the first direction.
14. The semiconductor structure according to claim 13, characterized in that, The second region also includes: Multiple lower electrode contacts, each of which is connected to each of the second drain electrodes; Multiple lower electrodes, each of which covers the top surface of each lower electrode contact portion, and the lower electrodes are disposed between the lower electrode contact portion and the magnetic tunnel junction; Multiple second bit lines, each second bit line extending along a second direction perpendicular to the first direction, and each second bit line connected to the magnetic tunnel junction arranged along the second direction.