Semiconductor device and method of manufacturing the same

Abstract

The present application provides a semiconductor device and a method for fabricating the same. The method includes providing a substrate including a PMOS region and an NMOS region, and forming germanium-silicon layers and silicon layers alternately stacked on the substrate; removing the germanium-silicon layers; germanium-doping the silicon layers in the PMOS region, and performing a heat treatment to convert the germanium-doped silicon layers into germanium-silicon layers. The present application converts the silicon layers into germanium-silicon layers in the PMOS region, while retaining the silicon layers in the NMOS region without conversion, thereby introducing stress into the PMOS region to improve the performance of PMOS devices.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of integrated circuit manufacturing process technology nodes, higher requirements have been placed on the gate control capability, size and power consumption of transistors. Compared with FinFET (Fin Field-Effect Transistor), GAA (Gate All Around) can achieve better transistor performance by wrapping the channel (multiple nanosheets / nanowires) on all four sides by the gate.

[0003] GAA devices are formed by alternating SiGe / Si (germanium-silicon / silicon) layers to create nanosheets or nanowires, and selectively removing SiGe to leave Si as the channel. However, as GAA devices gradually shrink, improving the performance of PMOS devices has become a challenge. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which retains the silicon layer in the NMOS region and converts the silicon layer in the PMOS region into a germanium-silicon layer to improve the performance of the PMOS device.

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0006] A substrate is provided, the substrate including a PMOS region and an NMOS region, and alternating layers of germanium-silicon and silicon are formed on the substrate;

[0007] Remove the germanium-silicon layer; and

[0008] The silicon layer in the PMOS region is doped with germanium and then subjected to heat treatment to transform the germanium-doped silicon layer into a germanium-silicon layer.

[0009] Optionally, the method for germanium doping of the silicon layer within the PMOS region includes:

[0010] A patterned mask layer is formed, which blocks the NMOS region and exposes the PMOS region;

[0011] The silicon layer exposed in the PMOS region is germanium-doped; and

[0012] Remove the graphical mask layer.

[0013] Optionally, a method for forming the patterned mask layer includes:

[0014] A mask layer is formed, the mask layer covering the substrate and the top silicon layer; and

[0015] The mask layer within the PMOS region is removed by etching.

[0016] Optionally, the silicon layer of the PMOS region can be germanium-doped using plasma immersion ion implantation technology.

[0017] Optionally, a method for heat-treating the germanium-doped silicon layer to convert it into a germanium-silicon layer includes:

[0018] A first heat treatment is performed to allow germanium to diffuse from the surface of the silicon layer into the silicon layer; and

[0019] A second heat treatment is performed to rearrange the lattice of the germanium-doped silicon layer, transforming it into a germanium-silicon layer.

[0020] Optionally, the first heat treatment lasts longer than the second heat treatment, and the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

[0021] Optionally, after converting the germanium-doped silicon layer into a germanium-silicon layer, the fabrication method further includes:

[0022] An interface layer is formed, wherein the interface layer respectively covers the germanium-silicon layer of the PMOS region and the silicon layer of the NMOS region; and

[0023] A dielectric layer is formed, which covers the interface layer.

[0024] Optionally, spacers are formed on both sides of the germanium-silicon layer before the germanium-silicon layer is removed.

[0025] Optionally, an epitaxial layer is also formed on the substrate, the epitaxial layer being located on both sides of the spacer and the silicon layer.

[0026] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0027] The semiconductor device and its fabrication method provided by this invention include a substrate comprising a PMOS region and an NMOS region. Alternating layers of germanium-silicon and silicon are formed on the substrate. The germanium-silicon layers are removed, and then the silicon layer in the PMOS region is doped with germanium and subjected to heat treatment to convert the germanium-doped silicon layer into a germanium-silicon layer. This invention converts the silicon layer into a germanium-silicon layer in the PMOS region while retaining the silicon layer in the NMOS region, thereby introducing stress into the PMOS region to improve the performance of the PMOS device. Attached Figure Description

[0028] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0029] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0030] Figures 2 to 9 This is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0031] Figure label:

[0032] 10-Substrate; 11-Germanium-silicon layer; 12-Silicon layer; 13-Spacer; 14-Epipolar layer; 15-Germanium-doped layer; 16-Germanium-silicon layer; 17-Interface layer; 18-Dielectric layer; 19-Gate. Detailed Implementation

[0033] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0034] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0035] To address the aforementioned problems, the inventors discovered that replacing the silicon channel with a germanium-silicon channel in the PMOS region can introduce stress into the PMOS region, further improving the performance of the PMOS device. Through further research, the inventors proposed a semiconductor device and its fabrication method.

[0036] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0037] like Figure 1As shown, the method for fabricating the semiconductor device includes the following steps:

[0038] S1: A substrate is provided, the substrate including a PMOS region and an NMOS region, and alternating layers of germanium-silicon and silicon are formed on the substrate;

[0039] S2: Remove the germanium-silicon layer;

[0040] S3: The silicon layer in the PMOS region is doped with germanium and then subjected to heat treatment to transform the germanium-doped silicon layer into a germanium-silicon layer.

[0041] Figures 2 to 9 This is a schematic diagram illustrating the structural steps of a semiconductor device fabrication method according to an embodiment of the present invention. Next, we will combine... Figure 1 and Figures 2-9 A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.

[0042] It should be noted that, since the substrate includes both PMOS and NMOS regions, and this invention primarily focuses on improving the silicon layer within the PMOS region, the structural diagrams of the PMOS and NMOS regions are not the same in steps S3 and thereafter. Figure 2 and Figure 3 Schematic diagram of PMOS and NMOS regions in the image. Figure 1 Therefore, no distinction was made; Figures 4 to 6 as well as Figure 8 The corresponding diagram is a schematic of the PMOS region. Figure 7 and Figure 9 This corresponds to the structural diagram of the NMOS region.

[0043] In step S1, please refer to Figure 2 As shown, a substrate 10 is provided, the substrate 10 including a PMOS region (not shown) and an NMOS region (not shown), and alternating germanium-silicon layers 11 and silicon layers 12 are formed on the substrate 10.

[0044] The substrate 10 can be made of silicon, germanium, germanium-silicon, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is preferably made of silicon. The substrate 10 includes a PMOS region and an NMOS region, on which PMOS devices are subsequently formed, and on which NMOS devices are subsequently formed.

[0045] Alternating layers of germanium-silicon (SiGe) 11 and silicon 12 are formed on the substrate 10. It is understood that alternating layers of germanium-silicon (SiGe) 11 and silicon 12 are formed on both the PMOS and NMOS regions of the substrate 10. This embodiment shows only three layers of germanium-silicon 11 and three layers of silicon 12; in other embodiments, there may be two, four, or more layers, and this invention is not limited thereto. The silicon-germanium layer 11 serves as a sacrificial layer and will be removed subsequently. The silicon layer 12 in the NMOS region subsequently serves as a channel layer, and the silicon layer 12 in the PMOS region is subsequently converted into a silicon-germanium layer as a channel layer.

[0046] Spacers 13 are formed on both sides of the germanium-silicon layer 11, and an epitaxial layer 14 is formed on the substrate 10, the epitaxial layer 14 being located on both sides of the germanium-silicon layer 11 and the silicon layer 12.

[0047] For example, alternating germanium-silicon layers 11 and silicon layers 12 are sequentially formed on the substrate 10. Then, a portion of the germanium-silicon layers 11 is laterally etched away to form grooves on both sides of the germanium-silicon layers 11, and an insulating material is filled into the grooves to form spacers 13. Finally, an epitaxial layer 14 is formed on both sides of the germanium-silicon layers 11 and silicon layers 12.

[0048] It should be noted that after the alternating layers of germanium-silicon layer 11 and silicon layer 12 are formed, the semiconductor device fabrication method includes multiple high-temperature processes, such as shallow trench isolation annealing. These high-temperature processes cause germanium in the germanium-silicon layer 11 to diffuse into the silicon layer 12, resulting in the formation of a germanium-doped layer 15 at the interface of the silicon layer 12. Figure 2 As shown.

[0049] In step S2, please refer to Figure 3 As shown, the germanium-silicon layer 11 is removed.

[0050] Specifically, taking advantage of the principle that the etching rate of silicon-germanium is much higher than that of silicon, the germanium-silicon layer 11 is selectively etched while the silicon layer 12 is retained. For example, the germanium-silicon layer 11 can be removed by wet etching or dry etching.

[0051] In step S3, please refer to Figure 5 As shown, the silicon layer 12 in the PMOS region is doped with germanium and then subjected to heat treatment to transform the germanium-doped silicon layer 12 into a germanium-silicon layer 16.

[0052] Specifically, first, a mask layer (not shown) is formed, covering the substrate 10 and the top silicon layer 12. In this embodiment, since an epitaxial layer 14 is formed on the substrate 10, the mask layer covers the epitaxial layer 14 and the top silicon layer 12. Next, the mask layer within the PMOS region is etched away to form a patterned mask layer. The patterned mask layer blocks the NMOS region, exposing the PMOS region. For example, the mask layer is made of photoresist, forming a photoresist layer that covers the epitaxial layer and the top silicon layer 12. The photoresist layer is then exposed and developed to form a patterned photoresist layer, which blocks the NMOS region and exposes the PMOS region.

[0053] Next, the silicon layer 12 exposed in the PMOS region is germanium-doped, such as... Figure 4 As shown, the region where the germanium doped layer 15 is located is further increased. Specifically, plasma immersion ion implantation technology can be used to dope the silicon layer 12 of the PMOS region, doping a large dose of germanium into the silicon layer 12 with extremely low energy. The doping dose and doping energy can be determined according to actual needs.

[0054] Next, the patterned mask layer is removed. Then, a heat treatment is performed, such as... Figure 5 As shown, the germanium-doped silicon layer 12 is transformed into a germanium-silicon layer 16. Specifically, firstly, a first heat treatment is performed to diffuse germanium from the surface of the silicon layer 12 into the silicon layer 12. Then, a second heat treatment is performed to rearrange the lattice of the germanium-doped silicon layer 12, transforming it into a germanium-silicon layer 16. The first heat treatment lasts longer than the second heat treatment, and the temperature of the second heat treatment is higher than that of the first heat treatment. The first heat treatment can be performed in a furnace tube, and the second heat treatment can be, for example, rapid thermal processing (RTP).

[0055] It is understood that in this embodiment, due to the presence of the spacer 13, not all of the silicon layers 12 are converted into germanium-silicon layers 16. The silicon layers 12 between adjacent spacers 13, lacking germanium doping, will undergo lateral diffusion of germanium during heat treatment, but due to limited diffusion, not all will be converted into germanium-silicon layers 16. That is, some of the silicon layers 12 between adjacent spacers 13 may be converted into germanium-silicon layers 16. Of course, in other embodiments, the silicon layers 12 between adjacent spacers 13 may be completely converted into germanium-silicon layers 16, and this invention does not limit this.

[0056] Step S3 involves processing the PMOS region, transforming the silicon layer 12 within the PMOS region into the germanium-silicon layer 16. However, in the NMOS region, due to the protection of the patterned mask layer, the silicon layer 12 does not undergo this transformation. In other words, the channel in the PMOS region is transformed from a silicon channel to a germanium-silicon channel, while the channel in the NMOS region remains a silicon channel. This introduces stress into the PMOS region, thereby improving the performance of the PMOS device.

[0057] Next, the fabrication method further includes: forming an interface layer (IL) 17, wherein the interface layer 17 respectively covers the germanium-silicon layer 16 of the PMOS region and the silicon layer 12 of the NMOS region. Please refer to Figure 6 As shown, in the PMOS region, the interface layer 17 covers the germanium-silicon layer 16. Please refer to... Figure 7 As shown, in the NMOS region, the interface layer 17 covers the silicon layer 12. It can be understood that, due to the cross-sectional orientation of the schematic diagram, in... Figure 6 and Figure 7 In this process, the interface layer 17 does not completely cover the germanium-silicon layer 16 or the silicon layer 12.

[0058] The interface layer 17 may be made of silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials. The interface layer 17 may be fabricated by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

[0059] Next, it also includes forming a dielectric layer 18, please refer to Figure 8 As shown, in the PMOS region, the dielectric layer 18 covers the interface layer 17. Please refer to [reference needed]. Figure 9 As shown, in the NMOS region, the dielectric layer 18 covers the interface layer 17. Finally, a gate 19 is formed, which covers the dielectric layer 18. Figure 6 and Figure 7 Similarly, due to the cross-sectional direction of the schematic diagram, Figure 8 and Figure 9The dielectric layer 18 does not completely cover the interface layer 17, and the gate 19 does not completely cover the dielectric layer 18. The dielectric layer 18 is preferably an HK dielectric layer, and the material of the HK dielectric layer may include tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2), etc., preferably hafnium oxide. The HK dielectric layer can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. In some embodiments, ALD is preferred. The gate 19 is made of aluminum or tungsten and can be formed using processes such as chemical vapor deposition and physical vapor deposition.

[0060] In the semiconductor device fabrication method provided by this invention, a substrate 10 includes a PMOS region and an NMOS region. Alternating layers of germanium-silicon 11 and silicon 12 are formed on the substrate 10. The germanium-silicon 11 is removed, and then the silicon layer 12 in the PMOS region is doped with germanium and subjected to heat treatment to convert the germanium-doped silicon layer 12 into a germanium-silicon 16. This invention converts the silicon layer 12 into the germanium-silicon 16 in the PMOS region, while retaining the silicon layer 12 in the NMOS region without conversion, thereby introducing stress into the PMOS region to improve the performance of the PMOS device.

[0061] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0062] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate including a PMOS region and an NMOS region, and alternating layers of germanium-silicon and silicon are formed on the substrate; Remove the germanium-silicon layer; as well as The silicon layer in the PMOS region is doped with germanium and then subjected to heat treatment to transform the germanium-doped silicon layer into a germanium-silicon layer. The NMOS region is not transformed and retains the silicon layer.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The method for germanium doping of the silicon layer within the PMOS region includes: A patterned mask layer is formed, which blocks the NMOS region and exposes the PMOS region; The silicon layer exposed in the PMOS region is germanium-doped; and Remove the graphical mask layer.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The method for forming the patterned mask layer includes: A mask layer is formed, the mask layer covering the substrate and the top silicon layer; and The mask layer within the PMOS region is removed by etching.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The silicon layer of the PMOS region is germanium-doped using plasma immersion ion implantation technology.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, A method for heat-treating the germanium-doped silicon layer to convert it into a germanium-silicon layer includes: A first heat treatment is performed to allow germanium to diffuse from the surface of the silicon layer into the silicon layer; and A second heat treatment is performed to rearrange the lattice of the germanium-doped silicon layer, transforming it into a germanium-silicon layer.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The first heat treatment lasts longer than the second heat treatment, and the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After converting the germanium-doped silicon layer into a germanium-silicon layer, the fabrication method further includes: An interface layer is formed, wherein the interface layer respectively covers the germanium-silicon layer of the PMOS region and the silicon layer of the NMOS region; and A dielectric layer is formed, which covers the interface layer.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Before the germanium-silicon layer is removed, spacers are formed on both sides of the germanium-silicon layer.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, An epitaxial layer is also formed on the substrate, the epitaxial layer being located on both sides of the spacer and the silicon layer.

10. A semiconductor device, characterized in that, It is manufactured using the method for manufacturing a semiconductor device as described in any one of claims 1 to 9.

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