Semiconductor package structure and method of fabrication

Abstract

The embodiments of the present disclosure disclose a semiconductor packaging structure and a preparation method, wherein the semiconductor packaging structure comprises: a first substrate, the first substrate has a first surface; a first chip stack, the first chip stack is located on the first substrate, the first chip stack comprises a plurality of first semiconductor chips stacked in a direction perpendicular to the first substrate, and the first chip stack is electrically connected with the first surface of the first substrate; an interposer, the interposer is located on the first chip stack; the interposer has a first interconnection surface, the first interconnection surface has a first interconnection region and a second interconnection region, the first interconnection region is electrically connected with the first substrate; a molding layer, the molding layer seals the first chip stack, the interposer and the first surface of the first substrate, wherein the first interconnection region is not sealed by the molding layer, the second interconnection region is sealed by the molding layer, and a first material layer is formed on the sidewall between the top surface of the molding layer on the second interconnection region and the first interconnection region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] Across all sectors, industries, and regions, the electronics industry is constantly demanding lighter, faster, smaller, more versatile, more reliable, and more cost-effective products. To meet these growing demands from a wide range of diverse consumers, more circuitry needs to be integrated to provide the required functionality. In virtually every application, there is a growing need for smaller size, improved performance, and enhanced integrated circuit functionality. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor packaging structure and a method for its fabrication.

[0004] According to a first aspect of the present disclosure, a semiconductor packaging structure is provided, comprising:

[0005] A first substrate, the first substrate having a first surface;

[0006] A first chip stack is located on the first substrate. The first chip stack includes a plurality of first semiconductor chips stacked sequentially along a direction perpendicular to the first substrate. The first chip stack is electrically connected to a first surface of the first substrate.

[0007] An interposer layer is located on the first chip stack; the interposer layer has a first interconnect surface, the first interconnect surface has a first interconnect region and a second interconnect region, and the first interconnect region is electrically connected to the first substrate.

[0008] A molding layer is provided, which seals the first chip stack, the interposer, and a first surface of the first substrate. The first interconnect region is not sealed by the molding layer, the second interconnect region is sealed by the molding layer, and a first material layer is formed on the sidewall between the top surface of the molding layer and the first interconnect region on the second interconnect region.

[0009] In some embodiments, the material of the first material layer includes a conductive material or an insulating material.

[0010] In some embodiments, it also includes:

[0011] The second material layer is located on the top surface of the molding layer;

[0012] The material of the second material layer is the same as that of the first material layer.

[0013] In some embodiments, it also includes:

[0014] A first conductive line, wherein each of the first semiconductor chips is electrically connected to the first substrate through the first conductive line;

[0015] The second conductive line connects the second interconnect region to the first substrate via the second conductive line.

[0016] In some embodiments, the first interconnect region includes a plurality of first pads, and the second interconnect region includes a plurality of second pads, wherein the number of second pads is greater than the number of first pads, and the area of ​​the second pads is smaller than the area of ​​the first pads.

[0017] In some embodiments, the angle between the sidewall between the top surface of the molding layer and the first interconnect region and the direction perpendicular to the first substrate is a first angle, wherein the first angle is greater than or equal to 0° and less than 90°.

[0018] In some embodiments, it also includes:

[0019] A second packaging structure, the second packaging structure including a first solder ball, the first solder ball being electrically connected to the first interconnect region;

[0020] The top surface of the molded layer on the second interconnect region has a preset height with respect to the first interconnect region, wherein the height of the first solder ball is greater than the preset height.

[0021] According to a second aspect of the present disclosure, a method for fabricating a semiconductor packaging structure is provided, comprising:

[0022] A first substrate is provided, the first substrate having a first surface;

[0023] A first chip stack is formed on the first substrate. The first chip stack includes a plurality of first semiconductor chips stacked sequentially along a direction perpendicular to the first substrate. The first chip stack is electrically connected to a first surface of the first substrate.

[0024] An interposer layer is formed on the first chip stack, the interposer layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, the first interconnect region being electrically connected to the first substrate;

[0025] A molding layer is formed, which seals the first chip stack, the interposer, and the first surface of the first substrate. The first interconnect region is not sealed by the molding layer, while the second interconnect region is sealed by the molding layer. The top surface of the molding layer on the second interconnect region has a predetermined height with respect to the first interconnect region, and a first material layer is formed on the sidewall between the top surface of the molding layer on the second interconnect region and the first interconnect region.

[0026] In some embodiments, it also includes:

[0027] After the intermediate layer is formed,

[0028] A first conductive line is formed; each of the first semiconductor chips is electrically connected to the first substrate through the first conductive line.

[0029] A second conductive line is formed; the second interconnect region is electrically connected to the first substrate through the second conductive line.

[0030] In some embodiments, it also includes:

[0031] A plurality of first pads are formed on the first interconnect region, and a plurality of second pads are formed on the second interconnect region, wherein the number of second pads is greater than the number of first pads, and the area of ​​the second pads is smaller than the area of ​​the first pads.

[0032] In some embodiments, it also includes:

[0033] After forming the interposer layer, a cover layer is formed on the first interconnect region of the interposer layer. The cover layer includes a first portion and a second portion located on both sides of the first portion. The first portion and the second portion form an inverted U-shape to form a sealed cavity with the interposer layer. The angle between the second portion and the direction perpendicular to the first substrate is a first angle, which is greater than or equal to 0° and less than 90°.

[0034] In some embodiments, the material of the covering layer includes a conductive material or an insulating material.

[0035] In some embodiments, it also includes:

[0036] A molding layer pre-layer is formed to seal the first chip stack, the interposer, the cover layer, and the first surface of the first substrate;

[0037] A portion of the pre-molded layer and a first portion of the cover layer are removed, while the second portion is retained to form a first material layer.

[0038] In some embodiments, it also includes:

[0039] After the molding layer is formed, a second material layer is formed on the top surface of the molding layer, the material of the second material layer being the same as that of the first material layer.

[0040] In some embodiments, it also includes:

[0041] A second package structure is formed, the second package structure including a bonding surface and a first solder ball located on the bonding surface; the first solder ball is electrically connected to the first interconnect region, and the bonding surface is connected to the second material layer.

[0042] In this embodiment, by providing an interposer layer, the subsequent second packaging structure can be connected to the first chip stack and the first substrate through the first interconnect region on the interposer layer. This enables interconnection between chip structures of different types or specifications, making the combination of different chip structures more flexible. Simultaneously, because the first chip stack and the subsequent second packaging structure connected to the first chip stack are independently packaged, testing and failure analysis are easier. Furthermore, a first material layer is formed on the sidewall between the top surface of the molding layer and the first interconnect region, protecting the contact area between the interposer layer and the subsequent second packaging structure connected to the interposer layer. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure;

[0045] Figure 2 This is a schematic diagram of the structure of the first substrate provided in an embodiment of the present disclosure;

[0046] Figure 3 A schematic diagram of the structure of the intermediary layer provided in the embodiments of this disclosure;

[0047] Figure 4a and Figure 4b Other examples of semiconductor packaging structures provided in the embodiments of this disclosure;

[0048] Figure 5 A schematic flowchart illustrating the method for fabricating a semiconductor packaging structure provided in the disclosed embodiments;

[0049] Figures 6a to 6iThis is a schematic diagram of the device structure during the fabrication process of the semiconductor packaging structure provided in the embodiments of this disclosure.

[0050] Explanation of reference numerals in the attached figures:

[0051] 1-Ring; 2-Carrier tape;

[0052] 10-First substrate; 101-First side; 102-Second side; 11-Substrate substrate; 12-Insulating dielectric layer on substrate; 13-Insulating dielectric layer under substrate; 14-Connecting pad on substrate; 15-Connecting pad under substrate; 16-Connecting via on substrate; 17-Connecting bump on substrate; 110-First signal transmission area; 120-Second signal transmission area; 130-Third signal transmission area;

[0053] 20 - First chip stack; 21 - First semiconductor chip; 201 - First connection terminal;

[0054] 30 - Intermediate layer; 31 - First interconnect region; 32 - Second interconnect region; 301 - First interconnect surface; 311 - First pad; 321 - Second pad; 33 - Substrate; 34 - Upper insulating dielectric layer of the intermediate; 35 - Lower insulating dielectric layer of the intermediate;

[0055] 40 - Molded layer; 401 - Top surface; 400 - Molded layer pre-layer;

[0056] 51 - First conductive wire; 52 - Second conductive wire;

[0057] 60 - Adhesive film;

[0058] 70 - Second packaging structure; 701 - Bonding surface; 71 - First solder ball; 72 - Second substrate; 73 - Second molding layer;

[0059] 80 - Covering layer; 801 - First part; 802 - Second part; 81 - First material layer; 82 - Second material layer;

[0060] 91 - First packaging mold; 92 - Second packaging mold. Detailed Implementation

[0061] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0062] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0063] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0064] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0065] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0068] This disclosure provides a semiconductor packaging structure. Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an embodiment of the present disclosure.

[0069] See Figure 1 and Figure 2 The semiconductor packaging structure includes:

[0070] A first substrate 10, the first substrate 10 having a first surface 101;

[0071] A first chip stack 20 is located on the first substrate 10. The first chip stack 20 includes a plurality of first semiconductor chips 21 stacked sequentially along a direction perpendicular to the first substrate 10. The first chip stack 20 is electrically connected to the first surface 101 of the first substrate 10.

[0072] An interposer 30 is located on the first chip stack 20; the interposer 30 has a first interconnect surface 301, the first interconnect surface 301 has a first interconnect region 31 and a second interconnect region 32, and the first interconnect region 31 is electrically connected to the first substrate 10.

[0073] A molding layer 40 is provided, which seals the first chip stack 20, the interposer 30, and the first surface 101 of the first substrate 10. The first interconnect region 31 is not sealed by the molding layer 40, the second interconnect region 32 is sealed by the molding layer 40, and a first material layer 81 is formed on the sidewall between the top surface 401 of the molding layer 40 and the first interconnect region 31 on the second interconnect region 32.

[0074] In this embodiment, by providing an interposer layer, the subsequent second packaging structure can be connected to the first chip stack and the first substrate through the first interconnect region on the interposer layer. This enables interconnection between chip structures of different types or specifications, making the combination of different chip structures more flexible. Simultaneously, because the first chip stack and the subsequent second packaging structure connected to the first chip stack are independently packaged, testing and failure analysis are easier. Furthermore, a first material layer is formed on the sidewall between the top surface of the molding layer and the first interconnect region, protecting the contact area between the interposer layer and the subsequent second packaging structure connected to the interposer layer.

[0075] Figure 2 This is a schematic diagram of the structure of the first substrate provided in an embodiment of this disclosure.

[0076] In some embodiments, the first substrate 10 may be a printed circuit board (PCB) or a redistributed substrate.

[0077] like Figure 2 As shown, the first substrate 10 includes a substrate substrate 11 and an upper insulating dielectric layer 12 and a lower insulating dielectric layer 13 respectively disposed on the upper and lower surfaces of the substrate substrate 11.

[0078] The substrate 11 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0079] The upper insulating dielectric layer 12 and the lower insulating dielectric layer 13 on the substrate can be solder resist layers. For example, the materials of the upper insulating dielectric layer 12 and the lower insulating dielectric layer 13 on the substrate can be green paint.

[0080] In this embodiment of the present disclosure, the first surface 101 of the first substrate 10 is the upper surface of the insulating dielectric layer 12 on the substrate. The first substrate 10 also includes a second surface 102, which is the lower surface of the lower insulating dielectric layer 13 on the substrate.

[0081] The first substrate 10 further includes a substrate upper connection pad 14 located in the upper insulating dielectric layer 12 of the substrate, a substrate lower connection pad 15 located in the lower insulating dielectric layer 13 of the substrate, and a substrate connection via 16 that penetrates the substrate substrate 11 and connects the substrate upper connection pad 14 and the substrate lower connection pad 15 to each other.

[0082] The materials of the bonding pads 14 on the substrate and the bonding pads 15 on the substrate may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold. The substrate connection vias 16 may be through-silicon vias (TSVs).

[0083] The first substrate 10 further includes a substrate connection bump 17, which can electrically connect the semiconductor package structure to an external device, receive at least one of a control signal, a power signal, and a ground signal for operating the first chip stack from the external device, or receive data signals to be stored in the first chip stack from the external device, or provide data in the first chip stack to the external device.

[0084] The substrate connection bump 17 comprises a conductive material. In this embodiment, the substrate connection bump 17 is a solder ball. It is understood that the shape of the substrate connection bump provided in this embodiment is only one lower-level, feasible specific implementation and does not constitute a limitation on this disclosure. The substrate connection bump can also be other shapes and structures. The number, spacing, and position of the substrate connection bumps are not limited to any specific arrangement and can be modified in various ways.

[0085] See also Figure 2 The first substrate 10 further includes a first signal transmission region 110 and a second signal transmission region 120 located on opposite sides of the first substrate 10. The first signal transmission region 110 is electrically connected to the first chip stack 20, and the second signal transmission region 120 is electrically connected to the interposer layer 30.

[0086] The first substrate 10 further includes a third signal transmission region 130 located between the first signal transmission region 110 and the second signal transmission region 120, and the first chip stack 20 is located on the third signal transmission region 130.

[0087] See also Figure 1 The first chip stack structure 20 includes a plurality of first semiconductor chips 21 stacked sequentially along a direction perpendicular to the first substrate 10. In this embodiment, by stacking a plurality of first semiconductor chips sequentially upwards, the horizontal area of ​​the semiconductor packaging structure can be saved.

[0088] In one embodiment of this disclosure, the first semiconductor chip may be a DRAM chip.

[0089] Figure 3 This is a schematic diagram of the structure of the intermediary layer provided in an embodiment of this disclosure.

[0090] like Figure 3 As shown, the intermediary layer 30 includes a substrate 33 and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 respectively disposed on the upper and lower surfaces of the substrate 33.

[0091] The substrate 33 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0092] The upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 can be solder resist layers, for example, the material of the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 can be green paint.

[0093] In one embodiment, the substrate 33 of the interposer 30 has an electromagnetic shielding layer (not shown). By providing an electromagnetic shielding layer within the substrate of the interposer, information interference between the second packaging structure and the first chip stack can be prevented, thus avoiding interference with device operation.

[0094] The interposer layer 30 includes a first interconnect region 31 and a second interconnect region 32. The first interconnect region 31 includes a plurality of first pads 311, and the second interconnect region 32 includes a plurality of second pads 321. The number of second pads 321 is greater than the number of first pads 311, and the area of ​​the second pads 321 is smaller than the area of ​​the first pads 311.

[0095] Because the first pad needs to be matched and interconnected with the second package structure, the layout design is relatively fixed. The second pad carries the interconnection between the second package structure and the first substrate, so the layout design is more flexible. Designing the second pad to be more numerous and smaller in area can improve signal transmission efficiency.

[0096] The materials of the first pad 311 and the second pad 321 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.

[0097] In one embodiment, the first substrate 10 has a first thickness in a direction perpendicular to the first substrate 10, and the interposer layer 30 has a second thickness, wherein the first thickness is greater than the second thickness.

[0098] See also Figure 1 The semiconductor packaging structure further includes: a first conductive line 51, through which each of the first semiconductor chips 21 is electrically connected to the first substrate 10; and a second conductive line 52, through which the second interconnection region 32 is electrically connected to the first substrate 10.

[0099] Specifically, the first semiconductor chip 21 has a first connection terminal 201, which is located on the same side as the first signal transmission area 110. A first conductive line 51 is led out from the first connection terminal 201 to the first transmission area 110 to realize the electrical connection between the first semiconductor chip 21 and the first substrate 10.

[0100] A second pad 321 is formed on the second interconnect region 32, and a second conductive line 52 is led out from the second pad 321 to the second transmission region 120 to realize the electrical connection between the interposer layer 30 and the first substrate 10.

[0101] In this embodiment of the disclosure, the first chip stack and the first substrate are electrically connected by wire bonding, wherein the wire bonding method includes overhang and film on wire (FOW) method.

[0102] Figure 1 In the illustrated embodiment, a suspended wire bonding method is used. Adjacent first semiconductor chips 21 are connected by an adhesive film 60, which does not cover the first connection terminal 201 and the first conductive line 51 on the first semiconductor chip 21 below it, and the adhesive film 60 is offset from the first semiconductor chip 21 below it.

[0103] In other embodiments, wire bonding is performed using a film-on-wire method (not shown). A plurality of the first semiconductor chips are aligned along a direction perpendicular to the first substrate, and an adhesive film between adjacent first semiconductor chips covers the first connection terminals and first conductive lines on the first semiconductor chip layer below them.

[0104] It is understood that the use of wires for electrical connection in the embodiments of this disclosure is only a lower-level and feasible specific implementation method and does not constitute a limitation on this disclosure. Other methods of electrical connection can also be used, such as hybrid bonding or bump interconnect.

[0105] In one embodiment, the angle between the sidewall of the top surface 401 of the molding layer 40 and the first interconnection region 31 and the direction perpendicular to the first substrate 10 is a first angle, which is greater than or equal to 0° and less than 90°.

[0106] For example, in such Figure 1 In the illustrated embodiment, the sidewall between the top surface 401 of the molding layer 40 and the first interconnect region 31 forms a 0° angle with the direction perpendicular to the first substrate 10, meaning the sidewall between the top surface 401 of the molding layer 40 and the first interconnect region 31 is perpendicular to the first substrate 10. Setting the sidewall of the molding layer to a vertical shape simplifies the manufacturing process.

[0107] In such Figure 4a In the illustrated embodiment, the angle between the sidewall of the top surface 401 of the molding layer 40 and the first interconnect region 31 and the direction perpendicular to the first substrate 10 is angle α, where angle α is greater than 0° and less than 90°. Setting the sidewall of the molding layer to a non-perpendicular shape facilitates subsequent interconnection with the second packaging structure.

[0108] In one embodiment, the material of the first material layer 81 includes a conductive material or an insulating material. When the material of the first material layer is a conductive material, it can provide electrostatic protection; when the material of the first material layer is an insulating material, it can provide insulation.

[0109] In one embodiment, the semiconductor package structure further includes a second material layer 82 located on the top surface 401 of the molding layer 40; the material of the second material layer 82 is the same as the material of the first material layer 81.

[0110] The second material layer is located between the molding layer and the second packaging structure. It can seal the first chip stack and the second packaging structure, protect the bonding surface between the molding layer and the second packaging structure, and prevent external moisture and electromagnetic interference.

[0111] In one embodiment, when both the first material layer 81 and the second material layer 82 are conductive materials, a heat-conducting channel can be formed from the periphery of the first interconnect region 31 on the intermediary layer to the molding layer 40 to improve the thermal performance of the product. Specifically, the first material layer 81 and the second material layer 82 can be copper, tin, or a copper-tin alloy, etc.

[0112] In one embodiment, when both the first material layer 81 and the second material layer 82 are insulating materials, a sealing protection ring can be formed from the periphery of the first interconnect region 31 on the intermediate layer to the molding layer 40 to improve the structural stability of the product. Specifically, the first material layer 81 and the second material layer 82 can be silicon oxide, silicon nitride, or silicon oxynitride.

[0113] In one embodiment, the first material layer 81 may be copper, tin, or a copper-tin alloy, and the second material layer 82 may be silicon dioxide.

[0114] In one embodiment, the first material layer 81 may be silicon dioxide, and the second material layer 82 may be copper, tin, or a copper-tin alloy, etc.

[0115] In one embodiment, the semiconductor package structure further includes: a second package structure 70, the second package structure 70 including a first solder ball 71, the first solder ball 71 being electrically connected to the first interconnect region 31; the top surface 401 of the molding layer 40 on the second interconnect region 32 having a preset height h between it and the first interconnect region 31, wherein the height H of the first solder ball 71 is greater than the preset height h.

[0116] In this embodiment of the disclosure, by setting the height of the first solder ball to be greater than the height between the top surface of the molding layer and the first interconnect region, the second packaging structure can be tightly connected to the interposer. At the same time, after the second packaging structure is connected to the interposer, there can be a gap between the second packaging structure and the molding layer. This can increase the heat dissipation efficiency of the controller and reduce the impact of heat on the chip.

[0117] The second packaging structure 70 also includes a second substrate 72. The structure of the second substrate 72 may be the same as or different from that of the substrate 10, which will not be described in detail here.

[0118] In embodiments of this disclosure, the second packaging structure 70 further includes a bonding surface 701, on which the first solder ball 71 is located and electrically connected to the second substrate 72 through the bonding surface 701.

[0119] In embodiments of this disclosure, such as Figure 1 As shown, the material of the bonding surface 701 can be silicon dioxide. When the material of the bonding surface 701 is silicon dioxide, the second material layer 82 on the molding layer 40 is a silicon dioxide layer. With this setting, when the first solder ball 71 is bonded to the first solder pad 311, the bonding between the molding layer 40 and the second packaging structure 70 is achieved through the second material layer 82.

[0120] In embodiments of this disclosure, such as Figure 4bAs shown, the second material layer 82 can be a copper layer, a tin layer, or a copper-tin layer. When the second material layer 82 is a copper layer, a tin layer, or a copper-tin layer, a copper layer, a tin layer, or a copper-tin layer is provided at the position corresponding to the second material layer 82 on the bonding surface 701. When the first solder ball 71 is bonded to the first solder pad 311, the bonding between the molding layer 40 and the second packaging structure 70 is achieved through the second material layer 82.

[0121] In one embodiment, the molding layer 40 has a first thickness in a direction perpendicular to the first substrate 10; the second packaging structure 70 includes a second molding layer 73, which has a second thickness in a direction perpendicular to the first substrate 10; wherein the first thickness is greater than or equal to the second thickness. This thickness setting effectively prevents warping after the second packaging structure is bonded to the interposer.

[0122] The second packaging structure 70 also includes a second semiconductor chip structure (not shown), which may be the same as or different from the first chip stack 20. The second semiconductor chip structure in the second packaging structure 70 is electrically connected to the second substrate 72.

[0123] For example, the second semiconductor chip structure can be a universal flash memory chip (UFS).

[0124] The semiconductor packaging structure provided in this disclosure can be applied to multi-chip packages (UFS Multi-Chip Package, UMCP) with a package-on-package (PoP) structure.

[0125] This disclosure also provides a method for fabricating a semiconductor packaging structure; please refer to the appendix for details. Figure 5 As shown in the figure, the method includes the following steps:

[0126] Step 501: Provide a first substrate, the first substrate having a first surface;

[0127] Step 502: A first chip stack is formed on the first substrate. The first chip stack includes a plurality of first semiconductor chips stacked sequentially along a direction perpendicular to the first substrate. The first chip stack is electrically connected to a first surface of the first substrate.

[0128] Step 503: An interposer layer is formed on the first chip stack, the interposer layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, the first interconnect region being electrically connected to the first substrate;

[0129] Step 504: Form a molding layer, wherein the molding layer seals the first chip stack, the interposer, and the first surface of the first substrate, wherein the first interconnect region is not sealed by the molding layer, the second interconnect region is sealed by the molding layer, the top surface of the molding layer on the second interconnect region has a preset height with the first interconnect region, and a first material layer is formed on the sidewall between the top surface of the molding layer on the second interconnect region and the first interconnect region.

[0130] The method for fabricating the semiconductor packaging structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0131] Figures 6a to 6i This is a schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure during the fabrication process.

[0132] First, see Figure 6a Step 501 is executed, providing a first substrate 10, the first substrate 10 having a first surface 101.

[0133] In some embodiments, the first substrate 10 may be a printed circuit board (PCB) or a redistributed substrate.

[0134] like Figure 2 As shown, the first substrate 10 includes a substrate substrate 11 and an upper insulating dielectric layer 12 and a lower insulating dielectric layer 13 respectively disposed on the upper and lower surfaces of the substrate substrate 11.

[0135] The substrate 11 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0136] The upper insulating dielectric layer 12 and the lower insulating dielectric layer 13 on the substrate can be solder resist layers. For example, the materials of the upper insulating dielectric layer 12 and the lower insulating dielectric layer 13 on the substrate can be green paint.

[0137] In this embodiment of the present disclosure, the first surface 101 of the first substrate 10 is the upper surface of the insulating dielectric layer 12 on the substrate. The first substrate 10 also includes a second surface 102, which is the lower surface of the lower insulating dielectric layer 13 on the substrate.

[0138] The first substrate 10 further includes a substrate upper connection pad 14 located in the upper insulating dielectric layer 12 of the substrate, a substrate lower connection pad 15 located in the lower insulating dielectric layer 13 of the substrate, and a substrate connection via 16 that penetrates the substrate substrate 11 and connects the substrate upper connection pad 14 and the substrate lower connection pad 15 to each other.

[0139] The materials of the bonding pads 14 on the substrate and the bonding pads 15 on the substrate may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold. The substrate connection vias 16 may be through-silicon vias (TSVs).

[0140] The first substrate 10 further includes a first signal transmission region 110 and a second signal transmission region 120 located on opposite sides of the first substrate 10. The first signal transmission region 110 is electrically connected to a subsequently formed first chip stack, and the second signal transmission region 120 is electrically connected to a subsequently formed interposer layer.

[0141] In some embodiments, the first signal transmission region 110 and the second signal transmission region 120 are not interconnected.

[0142] The first substrate 10 also includes a third signal transmission region 130 located between the first signal transmission region 110 and the second signal transmission region 120, and the subsequent first chip stack is located on the third signal transmission region 130.

[0143] In some embodiments, the first signal transmission region 110 is interconnected with the third signal transmission region 130, and the third signal transmission region 130 is not interconnected with the second signal transmission region 120.

[0144] Next, see Figure 6b In step 502, a first chip stack 20 is formed on the first substrate 10. The first chip stack 20 includes a plurality of first semiconductor chips 21 stacked sequentially along a direction perpendicular to the first substrate 10. The first chip stack 20 is electrically connected to the first surface 101 of the first substrate 10.

[0145] In this embodiment of the disclosure, by stacking multiple first semiconductor chips upwards in sequence, the horizontal area of ​​the semiconductor packaging structure can be saved.

[0146] Adjacent chips 21 are connected by an adhesive film 60, and the chip stack structure 20 is also connected to the substrate 10 by an adhesive film 60.

[0147] Next, see Figure 6c and Figure 6dIn step 503, an intermediary layer 30 is formed on the first chip stack 20. The intermediary layer 30 has a first interconnect surface 301. The first interconnect surface 301 has a first interconnect region 31 and a second interconnect region 32. The first interconnect region 31 is electrically connected to the first substrate 10.

[0148] Specifically, see first. Figure 6c A carrier tape 2 is attached to the ring 1, then an adhesive film 60 is attached to the carrier tape 2, and then an intermediate layer is attached to the adhesive film 60. At this point, the intermediate layer is a whole strip. The intermediate layer is cut to form a shape as shown in the figure. Figure 6c The units shown are individual units.

[0149] Next, see Figure 6d An intermediary layer 30 is formed on the first chip stack 20.

[0150] Specifically, an adhesion layer 60 is first formed on the first chip stack 20, and then... Figure 6c The single intermediate layer 30 formed in the middle is attached to the adhesive layer 60.

[0151] like Figure 3 As shown, the intermediary layer 30 includes a substrate 33 and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 respectively disposed on the upper and lower surfaces of the substrate 33.

[0152] The substrate 33 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0153] The upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 can be solder resist layers, for example, the material of the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 can be green paint.

[0154] In one embodiment, the substrate 33 of the interposer 30 has an electromagnetic shielding layer (not shown). By providing an electromagnetic shielding layer within the substrate of the interposer, information interference between the second packaging structure and the first chip stack can be prevented, thus avoiding interference with device operation.

[0155] In one embodiment, the method further includes: forming a plurality of first pads 311 on the first interconnect region 31 and forming a plurality of second pads 321 on the second interconnect region 32, wherein the number of second pads 321 is greater than the number of first pads 311 and the area of ​​the second pads 321 is smaller than the area of ​​the first pads 311.

[0156] Because the first pad needs to be matched and interconnected with the second package structure, the layout design is relatively fixed. The second pad carries the interconnection between the second package structure and the first substrate, so the layout design is more flexible. Designing the second pad to be more numerous and smaller in area can improve signal transmission efficiency.

[0157] The materials of the first pad 311 and the second pad 321 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.

[0158] In one embodiment, the first substrate 10 has a first thickness in a direction perpendicular to the first substrate 10, and the interposer layer 30 has a second thickness, wherein the first thickness is greater than the second thickness.

[0159] Next, see [link / reference] Figure 6d After the intermediate layer 30 is formed, a cover layer 80 is formed on the first interconnect region 31 of the intermediate layer 30. The cover layer 80 includes a first portion 801 and a second portion 802 located on both sides of the first portion 801. The first portion 801 and the second portion 802 form an inverted U-shape to form a sealed cavity with the intermediate layer 30. The angle between the second portion 802 and the direction perpendicular to the first substrate 10 is a first angle, which is greater than or equal to 0° and less than 90°.

[0160] exist Figure 6d In the embodiment shown, the second portion 802 of the cover layer 80 forms an angle of 0° with the direction perpendicular to the first substrate 10, and the structure of the formed molding layer is as follows: Figure 1 As shown, in other embodiments, the second portion of the cover layer forms an angle greater than 0° and less than 90° with the direction perpendicular to the first substrate, and the structure of the resulting molding compound is as follows. Figure 4a As shown.

[0161] In this embodiment of the disclosure, by forming a cover layer on the first interconnect region of the intermediate layer, after the molding layer is subsequently formed, in order to expose the first interconnect region, there is no need to use a non-standard packaging mold. Instead, the first interconnect region can be exposed directly by removing the first part of the cover layer. Non-standard packaging molds are expensive to manufacture and have more complex processes. Therefore, by forming a cover layer on the first interconnect region, the cost can be reduced and the forming process is also simpler.

[0162] In one embodiment, the material of the cover layer 80 includes a conductive material or an insulating material.

[0163] After the cover layer 80 is formed, the interlayer attached to the ring 1 needs to be cleaned to remove impurities and dust, so as to avoid the interlayer being unclean and affecting the performance of the semiconductor packaging structure.

[0164] Next, after forming the interposer layer 30, a first conductive line 51 is formed; each of the first semiconductor chips 21 is electrically connected to the first substrate 10 through the first conductive line 51; a second conductive line 52 is formed; the second interconnect region 32 is electrically connected to the first substrate 10 through the second conductive line 52.

[0165] Specifically, the first semiconductor chip 21 has a first connection terminal 201, which is located on the same side as the first signal transmission area 110. A first conductive line 51 is led out from the first connection terminal 201 to the first transmission area 110 to realize the electrical connection between the first semiconductor chip 21 and the first substrate 10.

[0166] A second pad 321 is formed on the second interconnect region 32, and a second conductive line 52 is led out from the second pad 321 to the second transmission region 120 to realize the electrical connection between the interposer layer 30 and the first substrate 10.

[0167] In this embodiment of the disclosure, the first chip stack and the first substrate are electrically connected by wire bonding, wherein the wire bonding method includes overhang and film on wire (FOW) method.

[0168] Figure 6d In the illustrated embodiment, a suspended wire bonding method is used. Adjacent first semiconductor chips 21 are connected by an adhesive film 60, which does not cover the first connection terminal 201 and the first conductive line 51 on the first semiconductor chip 21 below it, and the adhesive film 60 is offset from the first semiconductor chip 21 below it.

[0169] In other embodiments, wire bonding is performed using a film-on-wire method (not shown). A plurality of the first semiconductor chips are aligned along a direction perpendicular to the first substrate, and an adhesive film between adjacent first semiconductor chips covers the first connection terminals and first conductive lines on the first semiconductor chip layer below them.

[0170] Next, see Figures 6e to 6gStep 504 is executed to form a molding layer 40, which seals the first chip stack 20, the interposer 30 and the first surface 101 of the first substrate 10. The first interconnect region 31 is not sealed by the molding layer 40, and the second interconnect region 32 is sealed by the molding layer 40. The top surface 401 of the molding layer 40 on the second interconnect region 32 has a preset height h with the first interconnect region 31, and a first material layer 81 is formed on the sidewall between the top surface 401 of the molding layer 40 on the second interconnect region 32 and the first interconnect region 31.

[0171] Specifically, see first. Figure 6e After the cover layer 80 is formed, a first packaging mold 91 and a second packaging mold 92 are formed; the surface of the first packaging mold 91 is parallel to the surface of the first substrate 10, the first packaging mold 91 is located above the cover layer 80 and there is a certain distance between the first packaging mold 91 and the cover layer 80; the second packaging mold 92 is located below the first substrate 10 and is parallel to the surface of the first substrate 10.

[0172] Next, see Figure 6f The method further includes: using the first packaging mold 91 and the second packaging mold 92 as masks to form a molding layer pre-layer 400 that seals the first chip stack 20, the intermediary layer 30, the cover layer 80 and the first surface 101 of the first substrate 10.

[0173] In one embodiment, the molding layer prelayer 400 includes an EMC material.

[0174] After forming the molding layer pre-layer 400, the first packaging mold 91 and the second packaging mold 92 are removed.

[0175] Next, see Figure 6g Remove a portion of the molding prelayer 400 and the first portion 801 of the cover layer 80, retaining the second portion 802, to form the first material layer 81.

[0176] Specifically, a grinding process can be used to grind the surface of the molding compound pre-layer 400 to remove part of the molding compound pre-layer 400 and the first part 801 of the cover layer 80.

[0177] See also Figure 6g After forming the molding layer 40, a substrate connection bump 17 is formed on the second surface 102 of the first substrate 10, the substrate connection bump 17 comprising a conductive material.

[0178] Next, see Figure 6hThe method further includes: after forming the molding layer 40, forming a second material layer 82 on the top surface 401 of the molding layer 40, wherein the material of the second material layer 82 is the same as the material of the first material layer 81.

[0179] Specifically, a second material layer pre-layer (not shown) can be formed first on the top surface 401 of the molding layer 40 and on the surface of the intermediate layer 30. Then, the second material layer pre-layer on the surface of the intermediate layer 30 is removed, while the second material layer pre-layer on the top surface 401 of the molding layer 40 is retained to form the second material layer 82.

[0180] Next, see Figure 6i The method further includes: forming a second package structure 70, the second package structure 70 including a bonding surface 701 and a first solder ball 71 located on the bonding surface 701; electrically connecting the first solder ball 71 to the first interconnect region 31; and connecting the bonding surface 701 to the second material layer 82.

[0181] In one embodiment, the height H of the first solder ball 71 is greater than the preset height h between the top surface 401 of the molding layer 40 and the first interconnect region 31.

[0182] In this embodiment of the disclosure, by setting the height of the first solder ball to be greater than the height between the top surface of the molding layer and the first interconnect region, the second packaging structure can be tightly connected to the interposer. At the same time, after the second packaging structure is connected to the interposer, there can be a gap between the second packaging structure and the molding layer. This can increase the heat dissipation efficiency of the controller and reduce the impact of heat on the chip.

[0183] The second packaging structure 70 also includes a second substrate 72, the structure of which may be the same as or different from that of the substrate 10, and will not be described in detail here.

[0184] In embodiments of this disclosure, the second packaging structure 70 further includes a bonding surface 701, on which the first solder ball 71 is located and electrically connected to the second substrate 72 through the bonding surface 701.

[0185] In embodiments of this disclosure, such as Figure 6i As shown, the material of the bonding surface 701 can be silicon dioxide. When the material of the bonding surface 701 is silicon dioxide, the second material layer 82 on the molding layer 40 is a silicon dioxide layer. With this setting, when the first solder ball 71 is bonded to the first solder pad 311, the bonding between the molding layer 40 and the second packaging structure 70 is achieved through the second material layer 82.

[0186] In embodiments of this disclosure, such as Figure 4bAs shown, the second material layer 82 can be a copper layer, a tin layer, or a copper-tin layer. When the second material layer 82 is a copper layer, a tin layer, or a copper-tin layer, a copper layer, a tin layer, or a copper-tin layer is provided at the position corresponding to the second material layer 82 on the bonding surface 701. When the first solder ball 71 is bonded to the first solder pad 311, the bonding between the molding layer 40 and the second packaging structure 70 is achieved through the second material layer 82.

[0187] In one embodiment, the molding layer 40 has a first thickness in a direction perpendicular to the first substrate 10; the second packaging structure 70 includes a second molding layer 73, which has a second thickness in a direction perpendicular to the first substrate 10; wherein the first thickness is greater than or equal to the second thickness. In one embodiment, the second molding layer 73 includes an EMC material.

[0188] The second packaging structure 70 also includes a second semiconductor chip structure (not shown), which may be the same as or different from the first chip stack 20. The second semiconductor chip structure in the second packaging structure 70 is electrically connected to the second substrate 72.

[0189] For example, the second semiconductor chip structure can be a universal flash memory chip (UFS).

[0190] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor packaging structure, characterized in that, include: A first substrate is provided, the first substrate having a first surface; A first chip stack is formed on the first substrate. The first chip stack includes a plurality of first semiconductor chips stacked sequentially along a direction perpendicular to the first substrate. The first chip stack is electrically connected to a first surface of the first substrate. An interposer layer is formed on the first chip stack, the interposer layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, the first interconnect region being electrically connected to the first substrate; A molding layer is formed, which seals the first chip stack, the interposer, and the first surface of the first substrate. The first interconnect region is not sealed by the molding layer, the second interconnect region is sealed by the molding layer, the top surface of the molding layer on the second interconnect region has a predetermined height with the first interconnect region, and a first material layer is formed on the sidewall between the top surface of the molding layer on the second interconnect region and the first interconnect region. Also includes: After forming the interposer layer, a cover layer is formed on the first interconnect region of the interposer layer. The cover layer includes a first portion and a second portion located on both sides of the first portion. The first portion and the second portion form an inverted U-shape to form a sealed cavity with the interposer layer. The angle between the second portion and the direction perpendicular to the first substrate is a first angle, which is greater than or equal to 0° and less than 90°.

2. The method according to claim 1, characterized in that, Also includes: After the intermediate layer is formed, A first conductive line is formed; each of the first semiconductor chips is electrically connected to the first substrate through the first conductive line. Form a second conductive line; The second interconnect region is electrically connected to the first substrate via the second conductive line.

3. The method according to claim 1, characterized in that, Also includes: A plurality of first pads are formed on the first interconnect region, and a plurality of second pads are formed on the second interconnect region, wherein the number of second pads is greater than the number of first pads, and the area of ​​the second pads is smaller than the area of ​​the first pads.

4. The method according to claim 1, characterized in that, The material of the covering layer includes conductive or insulating materials.

5. The method according to claim 1, characterized in that, Also includes: A molding layer pre-layer is formed to seal the first chip stack, the interposer, the cover layer, and the first surface of the first substrate; A portion of the molding layer pre-layer and a first portion of the cover layer are removed, while the second portion is retained to form a first material layer.

6. The method according to claim 1, characterized in that, Also includes: After the molding layer is formed, a second material layer is formed on the top surface of the molding layer, the material of the second material layer being the same as that of the first material layer.

7. The method according to claim 6, characterized in that, Also includes: A second package structure is formed, the second package structure including a bonding surface and a first solder ball located on the bonding surface; Electrically connect the first solder ball to the first interconnect region; The bonding surface is connected to the second material layer.

8. A semiconductor package structure formed by the method according to any one of claims 1 to 7, characterized in that, include: A first substrate, the first substrate having a first surface; A first chip stack is located on the first substrate. The first chip stack includes a plurality of first semiconductor chips stacked sequentially along a direction perpendicular to the first substrate. The first chip stack is electrically connected to a first surface of the first substrate. An interposer layer is located on the first chip stack; the interposer layer has a first interconnect surface, the first interconnect surface has a first interconnect region and a second interconnect region, and the first interconnect region is electrically connected to the first substrate. A molding layer is provided, which seals the first chip stack, the interposer, and a first surface of the first substrate. The first interconnect region is not sealed by the molding layer, the second interconnect region is sealed by the molding layer, and a first material layer is formed on the sidewall between the top surface of the molding layer and the first interconnect region on the second interconnect region.

9. The semiconductor packaging structure according to claim 8, characterized in that, The material of the first material layer includes conductive or insulating materials.

10. The semiconductor packaging structure according to claim 8, characterized in that, Also includes: The second material layer is located on the top surface of the molding layer; The material of the second material layer is the same as that of the first material layer.

11. The semiconductor packaging structure according to claim 8, characterized in that, Also includes: A first conductive line, wherein each of the first semiconductor chips is electrically connected to the first substrate through the first conductive line; The second conductive line connects the second interconnect region to the first substrate via the second conductive line.

12. The semiconductor packaging structure according to claim 8, characterized in that, The first interconnect region includes a plurality of first pads, and the second interconnect region includes a plurality of second pads, wherein the number of second pads is greater than the number of first pads, and the area of ​​the second pads is smaller than the area of ​​the first pads.

13. The semiconductor packaging structure according to claim 8, characterized in that, The angle between the sidewall of the top surface of the molding layer and the first interconnection area and the direction perpendicular to the first substrate is a first angle, which is greater than or equal to 0° and less than 90°.

14. The semiconductor packaging structure according to claim 8, characterized in that, Also includes: A second packaging structure, the second packaging structure including a first solder ball, the first solder ball being electrically connected to the first interconnect region; The top surface of the molded layer on the second interconnect region has a preset height with respect to the first interconnect region, wherein the height of the first solder ball is greater than the preset height.

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