A semiconductor package

Abstract

The embodiments of the present disclosure disclose a semiconductor package, wherein the semiconductor package comprises: a first substrate, the first substrate having a first surface, the first surface comprising a first signal transmission area and a second signal transmission area; a first semiconductor structure located on the first surface of the first substrate and electrically connected with the first signal transmission area; a second substrate located on the first substrate, the second substrate comprising a base and a first interconnection surface located on the base, the first interconnection surface of the second substrate facing away from the first surface of the first substrate, the first interconnection surface having a first interconnection area and a second interconnection area in communication with each other, the first interconnection area being electrically connected with the second signal transmission area; and a filling layer sealing the first semiconductor structure, the second substrate and the first surface of the first substrate, wherein the first interconnection area is not sealed by the filling layer, the second interconnection area is sealed by the filling layer, and a top surface of the filling layer on the second interconnection area has a preset height from the first interconnection area.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor package. Background Technology

[0002] Across all sectors, industries, and regions, the electronics industry is constantly demanding lighter, faster, smaller, more versatile, more reliable, and more cost-effective products. To meet these growing demands from a wide range of diverse consumers, more circuitry needs to be integrated to provide the required functionality. In virtually every application, there is a growing need for smaller size, improved performance, and enhanced integrated circuit functionality. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor package.

[0004] According to a first aspect of the present disclosure, a semiconductor package is provided, comprising:

[0005] A first substrate, the first substrate having a first surface, the first surface including a first signal transmission area and a second signal transmission area;

[0006] A first semiconductor structure is located on a first surface of the first substrate and is electrically connected to the first signal transmission area.

[0007] The second substrate is located on the first substrate. The second substrate includes a base and a first interconnect surface located on the base. The first interconnect surface of the second substrate is opposite to a first surface of the first substrate. The first interconnect surface has a first interconnect region and a second interconnect region that are interconnected. The first interconnect region is electrically connected to the second signal transmission region.

[0008] A filler layer is provided to seal the first semiconductor structure, the second substrate, and a first surface of the first substrate. The first interconnect region is not sealed by the filler layer, the second interconnect region is sealed by the filler layer, and the top surface of the filler layer on the second interconnect region has a predetermined height with respect to the first interconnect region.

[0009] In some embodiments, the first surface of the first substrate further includes a third signal transmission region located between the first signal transmission region and the second signal transmission region, and the first semiconductor structure is located on the third signal transmission region.

[0010] In some embodiments, the first side of the first substrate further includes a fourth signal transmission region, the second substrate is located on the fourth signal transmission region, and the second signal transmission region is electrically connected to the fourth signal transmission region.

[0011] In some embodiments, the second substrate is located on the first semiconductor structure, and the first interconnect region is electrically connected to the second signal transmission region through the second interconnect region; the third signal transmission region includes a first sub-signal region and a second sub-signal region, the first sub-signal region is interconnected with the first signal transmission region and located in the adjacent region of the first signal transmission region, and the second sub-signal region is interconnected with the second signal transmission region and located in the adjacent region of the second signal transmission region.

[0012] In some embodiments, the fourth signal transmission region is electrically connected to the first interconnect region.

[0013] In some embodiments, the first signal transmission region and the second signal transmission region are located on opposite sides of the first substrate, the first semiconductor structure has a first connection terminal, the first connection terminal is located on the same side as the first signal transmission region, and the first connection terminal and the first signal transmission region are interconnected by a lead, the second interconnection region is located on the same side as the second signal transmission region, and the second interconnection region and the second signal transmission region are interconnected by a lead.

[0014] In some embodiments, the first semiconductor structure and the first signal transmission region are interconnected in a direction perpendicular to the first substrate.

[0015] In some embodiments, the first semiconductor structure and the third signal transmission region are interconnected in a direction perpendicular to the first substrate, and the first signal transmission region and the third signal transmission region are interconnected.

[0016] In some embodiments, the second substrate further includes a second interconnect surface located on another side of the substrate, the substrate having a channel connecting the first interconnect region and the second interconnect surface, the first interconnect region being interconnected with the second signal transmission region in a direction perpendicular to the first substrate via the channel.

[0017] In some embodiments, the substrate of the second substrate has an electromagnetic shielding layer.

[0018] In some embodiments, an electromagnetic shielding structure is provided between the first sub-signal region and the second sub-signal region of the first substrate.

[0019] In some embodiments, the first substrate has a second surface opposite to the first surface, a circuit channel exists between the first surface and the second surface, and a plurality of first connection pads are provided on the second surface of the first substrate;

[0020] The first interconnect region of the second substrate has a plurality of second connection pads, the area of ​​the second connection pads being greater than or equal to the area of ​​the first connection pads.

[0021] In some embodiments, the second interconnect region of the second substrate has a plurality of third connection pads, the area of ​​which is smaller than the area of ​​the second connection pads.

[0022] In some embodiments, the first signal transmission area of ​​the first substrate has a plurality of fourth connection pads, the area of ​​which is less than or equal to the area of ​​the first connection pad.

[0023] In some embodiments, the number of the third connecting pads is greater than the number of the second connecting pads.

[0024] In some embodiments, the first substrate has a first thickness in a direction perpendicular to the first substrate, and the second substrate has a second thickness in a direction perpendicular to the second substrate, wherein the first thickness is less than the second thickness.

[0025] In some embodiments, a second package is further included, the second package having a contact surface, the second package being interconnected with the first interconnect region via the contact surface.

[0026] In some embodiments, the contact surface of the second package has a first contact structure, the first contact structure having a first height protruding from the contact surface in a direction perpendicular to the contact surface, the first height being greater than the preset height.

[0027] In some embodiments, the first connecting pad of the first substrate has a second contact structure protruding from the first substrate, the second contact structure having a second height protruding from the first substrate in a direction perpendicular to the first substrate, the second height being less than or equal to the first height.

[0028] In some embodiments, the second package includes a second semiconductor structure, which may be of the same or different type from the first semiconductor structure.

[0029] In this embodiment, by providing a second substrate, subsequent other semiconductor structures can be connected to the first semiconductor structure and the first substrate through the first interconnect region on the second substrate. This enables interconnection between semiconductor structures of different types or specifications, making the combination of different semiconductor structures more flexible. Simultaneously, because the first semiconductor structure and other semiconductor structures subsequently connected to the first semiconductor structure are independently packaged, testing and failure analysis are easier. Furthermore, since there is a preset height between the first interconnect region of the second substrate and the top surface of the filler layer, other semiconductor structures can be placed on the first interconnect region within the area enclosed by the filler layer, thereby reducing the overall structure's height and size. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a semiconductor package provided in an embodiment of this disclosure;

[0032] Figure 2 This is a schematic diagram of the structure of the first substrate provided in an embodiment of the present disclosure;

[0033] Figure 3 This is a schematic diagram of the structure of the second substrate provided in an embodiment of the present disclosure;

[0034] Figures 4 to 6 Other examples of semiconductor packages provided in the embodiments of this disclosure;

[0035] Figure 7 A schematic flowchart of a method for fabricating a semiconductor package provided in a disclosed embodiment;

[0036] Figures 8a to 8g This is a schematic diagram of the semiconductor package provided in the embodiments of this disclosure during the manufacturing process.

[0037] Explanation of reference numerals in the attached figures:

[0038] 1-Ring; 2-Carrier tape;

[0039] 10-First substrate; 101-First surface; 102-Second surface; 11-First signal transmission area; 12-Second signal transmission area; 13-Third signal transmission area; 131-First sub-signal area; 132-Second sub-signal area; 14-Fourth signal transmission area; 15-First substrate; 16-First upper insulating dielectric layer; 17-First lower insulating dielectric layer; 18-Second contact structure; 111-Fourth connecting pad; 151-Circuit channel; 161-Sixth connecting pad; 171-First connecting pad;

[0040] 20 - First semiconductor structure; 21 - First semiconductor chip; 201 - First connector; 211 - First channel; 212 - First chip connection pad; 213 - Second chip connection pad; 214 - First solder ball;

[0041] 30-Second substrate; 31-First interconnect region; 32-Second interconnect region; 33-Substrate; 34-Upper insulating dielectric layer; 35-Lower insulating dielectric layer; 36-Channel; 37-Fifth connection pad; 38-Second solder ball; 301-First interconnect surface; 302-Second interconnect surface; 311-Second connection pad; 321-Third connection pad;

[0042] 40 - Filler layer;

[0043] 50-lead wire;

[0044] 60 - Adhesive film;

[0045] 70 - Second package; 71 - First contact structure; 701 - Contact surface;

[0046] 91-First packaging mold; 911-First part; 912-Second part; 913-Third part; 92-Second packaging mold. Detailed Implementation

[0047] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0048] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0049] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0050] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0051] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0053] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0054] Current semiconductor packaging technologies generally employ either discrete or multi-chip package (UMCP) methods. Discrete packaging involves separating DRAM and NAND chips into individual packages. Multi-chip packaging, on the other hand, integrates memory chips and controller chips within a single package structure. Discrete packaging results in a larger footprint on the PCB, while multi-chip packaging makes testing and failure analysis more difficult, hinders controller heat dissipation, and restricts the flexibility of combining chips with different capacities.

[0055] Based on this, embodiments of the present disclosure provide a semiconductor package. Figure 1 This is a schematic diagram of the structure of a semiconductor package provided in an embodiment of this disclosure.

[0056] See Figure 1 The semiconductor package includes:

[0057] A first substrate 10 has a first surface 101, which includes a first signal transmission region 11 and a second signal transmission region 12.

[0058] A first semiconductor structure 20 is located on a first surface 101 of the first substrate 10 and is electrically connected to the first signal transmission area 11.

[0059] The second substrate 30 is located on the first substrate 10. The second substrate 30 includes a base 33 and a first interconnect surface 301 located on the base 33. The first interconnect surface 301 of the second substrate 30 is opposite to the first surface 101 of the first substrate 10. The first interconnect surface 301 has a first interconnect region 31 and a second interconnect region 32 that are interconnected. The first interconnect region 31 is electrically connected to the second signal transmission region 32.

[0060] A filling layer 40 is provided to seal the first semiconductor structure 20, the second substrate 30, and the first surface 101 of the first substrate 10. The first interconnect region 31 is not sealed by the filling layer 40, the second interconnect region 32 is sealed by the filling layer 40, and there is a preset height h between the top surface of the filling layer 40 on the second interconnect region 32 and the first interconnect region 31.

[0061] By providing a second substrate, subsequent semiconductor structures can be connected to the first semiconductor structure and the first substrate via the first interconnect region on the second substrate. This enables interconnection between semiconductor structures of different types or specifications, making the combination of different semiconductor structures more flexible. Furthermore, because the first semiconductor structure and other semiconductor structures connected to it are independently packaged, testing and failure analysis are easier. Additionally, due to the predetermined height between the first interconnect region of the second substrate and the top surface of the fill layer, other semiconductor structures can be placed on the first interconnect region within the area enclosed by the fill layer, thereby reducing the overall structure's height and size.

[0062] Figure 2 This is a schematic diagram of the structure of the first substrate provided in an embodiment of this disclosure.

[0063] In some embodiments, the first substrate 10 may be a printed circuit board (PCB) or a redistributed substrate.

[0064] like Figure 2 As shown, the first substrate 10 includes a first base 15, and a first upper insulating dielectric layer 16 and a first lower insulating dielectric layer 17 respectively located on the upper and lower surfaces of the first base 15.

[0065] The first substrate 15 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon insulator), etc.

[0066] The first upper insulating dielectric layer 16 and the first lower insulating dielectric layer 17 can be solder resist layers, for example, the material of the first upper insulating dielectric layer 16 and the first lower insulating dielectric layer 17 can be green paint.

[0067] In one embodiment, the first substrate 10 has a second surface 102 opposite to the first surface 101, a circuit channel 151 exists between the first surface 101 and the second surface 102, and a plurality of first connection pads 171 are provided on the second surface 102 of the first substrate 10.

[0068] The first substrate 10 has a plurality of sixth connection pads 161 on its first surface, and the circuit channel 151 connects the sixth connection pads 161 and the first connection pads 171.

[0069] In one embodiment, the first signal transmission region 11 of the first substrate 10 has a plurality of fourth connection pads 111, the area of ​​which is less than or equal to the area of ​​the first connection pad 171. In this embodiment, by designing that the area of ​​the fourth connection pad 111 is smaller than that of the first connection pad 171, a more efficient signal transmission efficiency is achieved between the first semiconductor structure 20 and the first signal transmission region 11 of the first substrate 10, reducing the chip area. In addition, by designing that the area of ​​the first connection pad 171 is larger than that of the fourth connection pad 111, the conductivity and thermal conductivity between the first semiconductor structure 20 and the first substrate 10 are improved, and the electrical connection between the first signal transmission region of the first substrate 10 and the second surface is achieved.

[0070] The first connecting pad 171 of the first substrate 10 has a second contact structure 18 that protrudes from the first substrate 10.

[0071] The second contact structure 18 can electrically connect the semiconductor package to an external device, receive at least one of a control signal, a power signal, and a ground signal for operating the first semiconductor structure from the external device, or receive data signals to be stored in the first semiconductor structure from the external device, or provide data in the first semiconductor structure to the external device.

[0072] The second contact structure 18 includes a conductive material. In this embodiment, the second contact structure 18 is a solder ball. It is understood that the shape of the second contact structure provided in this embodiment is only one subordinate and feasible specific implementation and does not constitute a limitation on this disclosure. The second contact structure may also be other shapes. The number, spacing, and position of the second contact structures are not limited to any specific arrangement and can be modified in various ways.

[0073] The first surface 101 of the first substrate 10 includes a first signal transmission region 11 and a second signal transmission region 12. The first signal transmission region 11 is electrically connected to the first semiconductor structure 20, and the second signal transmission region 12 is electrically connected to the second substrate 30.

[0074] In one embodiment, the first signal transmission region 11 and the second signal transmission region 12 are not interconnected.

[0075] In one embodiment, the first surface 101 of the first substrate 10 further includes a third signal transmission region 13 located between the first signal transmission region 11 and the second signal transmission region 12, and the first semiconductor structure 20 is located on the third signal transmission region 13. In this embodiment, by disposing the first semiconductor structure 20 directly above the third signal transmission region 13, the first signal transmission region 11 is located outside the first semiconductor structure 20, thereby increasing the connection stability between the first signal transmission region 11 and the first semiconductor structure 20.

[0076] In one embodiment, the area of ​​the first signal transmission region 11 distributed on the first substrate 10 may be smaller than the area of ​​the third signal transmission region 13 distributed on the first substrate 10, thereby reducing the lateral dimension of the first package and improving the integration.

[0077] The first semiconductor structure 20 includes a plurality of first semiconductor chips 21 stacked sequentially along a direction perpendicular to the first substrate 10. In this embodiment, by stacking multiple first semiconductor chips upwards sequentially, the horizontal area of ​​the semiconductor package can be saved. The first semiconductor chips may be DRAM chips.

[0078] In one embodiment, such as Figure 1 and Figure 2As shown, the second substrate 30 is located on the first semiconductor structure 20, and the first interconnect region 31 is electrically connected to the second signal transmission region 12 through the second interconnect region 32; the third signal transmission region 13 includes a first sub-signal region 131 and a second sub-signal region 132, the first sub-signal region 131 is interconnected with the first signal transmission region 11 and is located in the adjacent region of the first signal transmission region 11, and the second sub-signal region 132 is interconnected with the second signal transmission region 12 and is located in the adjacent region of the second signal transmission region 12.

[0079] In one embodiment, the first sub-signal region 131 and the second sub-signal region 132 are not interconnected.

[0080] In one embodiment, an electromagnetic shielding structure (not shown) is provided between the first sub-signal region 131 and the second sub-signal region 132 of the first substrate 10.

[0081] Because the first sub-signal region 131 is interconnected with the first signal transmission region 11, and the second sub-signal region 132 is interconnected with the second signal transmission region, while the first signal transmission region is interconnected with the first semiconductor structure and the second signal transmission region is indirectly interconnected with the second package through interconnection with the second substrate, an electromagnetic shielding structure is provided between the first sub-signal region and the second sub-signal region to prevent signal interference between the first semiconductor structure and the second package.

[0082] Figure 3 This is a schematic diagram of the structure of the second substrate provided in an embodiment of this disclosure.

[0083] like Figure 3 As shown, the second substrate 20 includes a substrate 33, and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 respectively located on the upper and lower surfaces of the substrate 33.

[0084] The substrate 33 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0085] The upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 can be solder resist layers, for example, the material of the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 can be green paint.

[0086] The first interconnect region 31 of the second substrate 30 has a plurality of second connection pads 311, the area of ​​the second connection pads 311 being greater than or equal to the area of ​​the first connection pads 171.

[0087] By setting the area of ​​the second connecting pad 311 to a larger area, the contact area between the second package and the second connecting pad 311 can be increased. If the contact area is small, it will be difficult to disassemble after soldering. Therefore, increasing the contact area facilitates subsequent disassembly and reassembly.

[0088] In one embodiment, the second interconnect region 32 of the second substrate 30 has a plurality of third connection pads 321, the area of ​​the third connection pads 321 being smaller than the area of ​​the second connection pads 311.

[0089] The number of the third connecting pads 321 is greater than the number of the second connecting pads 311.

[0090] Because the second connecting pad needs to be matched and interconnected with the second package, the layout design is relatively fixed. The third connecting pad carries the interconnection between the second package and the first substrate, so the layout design is more flexible. Designing the third connecting pad to be more numerous and smaller in area can improve signal transmission efficiency and increase the integration of the first package.

[0091] In one embodiment, the substrate 33 of the second substrate 30 has an electromagnetic shielding layer (not shown). By providing an electromagnetic shielding layer within the substrate of the second substrate, information interference between the second package and the first semiconductor structure can be prevented, thus avoiding interference with device operation.

[0092] Figure 4 This is a schematic diagram of the structure of a semiconductor package provided in another embodiment of the present disclosure.

[0093] like Figure 4 As shown, in this embodiment, the second substrate 30 is not located above the first semiconductor structure 20, but is located directly on the first substrate 10.

[0094] In one embodiment, the first surface 101 of the first substrate 10 further includes a fourth signal transmission region 14, the second substrate 30 is located on the fourth signal transmission region 14, and the second signal transmission region 12 is electrically connected to the fourth signal transmission region 14.

[0095] In one embodiment, the fourth signal transmission region 14 is electrically connected to the first interconnection region 31.

[0096] In one embodiment, the fourth signal transmission region 14 is not interconnected with the first signal transmission region 11.

[0097] Specifically, the first interconnection region 31 is electrically connected to the second signal transmission region 12 through the second interconnection region 32, and the second signal transmission region 12 is electrically connected to the fourth signal transmission region 14. Therefore, the fourth signal transmission region 14 is electrically connected to the first interconnection region through the second signal transmission region 12 and the second interconnection region 32.

[0098] In this embodiment of the disclosure, the electrical connection between the first semiconductor structure 20 and the second substrate 30 and the first substrate 10 includes wire bonding and through-silicon via (TSV) interconnection.

[0099] See Figure 1 The first semiconductor structure 20 and the second substrate 30 are electrically connected to the first substrate 10 by wire bonding.

[0100] The first signal transmission region 11 and the second signal transmission region 12 are located on opposite sides of the first substrate 10. The first semiconductor structure 20 has a first connection terminal 201, which is located on the same side as the first signal transmission region 11 and is interconnected with the first connection terminal 201 and the first signal transmission region 11 by a lead 50. The second interconnection region 32 is located on the same side as the second signal transmission region 12 and is interconnected with the second interconnection region 32 and the second signal transmission region 12 by a lead 50.

[0101] The first semiconductor structure 20 and the first substrate 10 are electrically connected by wire bonding in two ways: a dangling method and a film-on-wire (FOW) method.

[0102] Figure 1 In the illustrated embodiment, a suspended wire bonding method is used. Adjacent first semiconductor chips 21 are connected by an adhesive film 60, which does not cover the first connection terminal 201 and the lead 50 on the first semiconductor chip 21 below it, and the adhesive film is offset from the first semiconductor chip 21 below it.

[0103] In other embodiments, wire bonding is performed using a film-on-wire method (not shown). A plurality of the first semiconductor chips are aligned perpendicular to the first substrate, and an adhesive film between adjacent first semiconductor chips covers the first connection terminals and leads on the first semiconductor chip layer below them.

[0104] In other embodiments, see Figure 5 and Figure 6The first semiconductor structure 20 and the first substrate 10 are electrically connected by a through silicon via (TSV) interconnect.

[0105] like Figure 5 As shown, the first semiconductor chip 21 includes a first chip connection pad 212 and a second chip connection pad 213 located on the upper and lower surfaces, respectively, and a first channel 211 penetrating the first semiconductor chip 21 and connecting the first chip connection pad 212 and the second chip connection pad 213. The first channel 211 includes a through-silicon via (TSV).

[0106] The two adjacent first semiconductor chips 21, and the first semiconductor structure 20 and the first substrate 10 are electrically connected through the first chip connection pad 212, the second chip connection pad 213, the first channel 211 and the first solder ball 214.

[0107] The first semiconductor structure 20 and the first signal transmission region 11 are interconnected in a direction perpendicular to the first substrate 10.

[0108] The first semiconductor structure 20 and the third signal transmission region 13 are interconnected in a direction perpendicular to the first substrate 10, and the first signal transmission region 11 and the third signal transmission region 13 are interconnected.

[0109] In this embodiment, since the first semiconductor structure and the first substrate are electrically connected through silicon via interconnect, no wire bonding is required, so the first signal transmission area and the third signal transmission area can be merged into one area.

[0110] like Figure 6 As shown, the second substrate 30 further includes a second interconnect surface 302 located on the other side of the substrate 33. The substrate 33 has a channel 36 connecting the first interconnect region 31 and the second interconnect surface 302. The first interconnect region 31 is interconnected with the second signal transmission region 12 in a direction perpendicular to the first substrate 10 via the channel 36.

[0111] The second substrate 30 includes a second connection pad 311 located within a first interconnect region 31, a fifth connection pad 37 located on a second interconnect surface 302 of the second substrate 30, and a channel 36 penetrating the substrate 33 and connecting the second connection pad 311 and the fifth connection pad 37. The channel 36 includes a through-silicon via (TSV). A second solder ball 38 is also included between the second substrate 30 and the first substrate 10.

[0112] The second substrate 30 is electrically connected to the first substrate 10 through the second connecting pad 311, the channel 36, the fifth connecting pad 37 and the second solder ball 38.

[0113] In this embodiment, since the second substrate and the first substrate are electrically connected through silicon via interconnect, no wire bonding is required, so the second signal transmission area and the fourth signal transmission area can be merged into one area.

[0114] In one embodiment, the first substrate 10 has a first thickness in a direction perpendicular to the first substrate 10, and the second substrate 30 has a second thickness in a direction perpendicular to the second substrate 30. The first thickness is less than the second thickness. With this configuration, when the filling layer seals the first substrate and the second substrate, the warping of the second substrate 30 due to the size difference between the first substrate 10 and the second substrate 30 can be avoided, thus preventing the sealing effect from being affected.

[0115] In one embodiment, the semiconductor package further includes a second package 70 having a contact surface 701, and the second package 70 being interconnected with the first interconnect region 31 via the contact surface 701.

[0116] The second package 70 has a first contact structure 71 on the contact surface 701. The first contact structure 71 has a first height H protruding from the contact surface 701 in a direction perpendicular to the contact surface 701. The first height H is greater than the preset height h.

[0117] In this embodiment of the disclosure, by setting the first height to be greater than the preset height, the second package can be tightly connected to the second substrate. At the same time, after the second package is connected to the second substrate, there can be a gap between the second package and the filler layer. This can increase the heat dissipation efficiency of the controller and reduce the impact of heat dissipation on the chip.

[0118] In one embodiment, see Figure 2 The first connecting pad 171 of the first substrate 10 has a second contact structure 18 protruding from the first substrate 10. The second contact structure 18 has a second height protruding from the first substrate 10 in a direction perpendicular to the first substrate 10, and the second height is less than or equal to the first height. This configuration enables a more stable bonding effect between the second package, supported by the first contact structure 71, and the first package.

[0119] In one embodiment, the second package 70 includes a second semiconductor structure (illustrated), which may be of the same or different type from the first semiconductor structure 20.

[0120] For example, the second semiconductor structure can be a universal flash memory chip (UFS).

[0121] In the semiconductor package provided in this disclosure, the second semiconductor structure in the second package 70 is interconnected with the second signal transmission area on the first substrate 10 through the second substrate 30; the first semiconductor structure 20 is interconnected with the first signal transmission area on the first substrate 10. By distributing the transmission paths of the first semiconductor structure and the second semiconductor structure in different areas of the first substrate, mutual interference between the first semiconductor structure and the second semiconductor structure is prevented, and signal transmission stability is improved.

[0122] The semiconductor package provided in this disclosure can be applied to multi-chip packages (UFS Multi-Chip Package, UMCP) with a package-on-package (PoP) structure.

[0123] This disclosure also provides a method for fabricating a semiconductor package, as detailed in the appendix. Figure 7 As shown in the figure, the method includes the following steps:

[0124] Step 701: Provide a first substrate, the first substrate having a first surface, the first surface including a first signal transmission area and a second signal transmission area;

[0125] Step 702: A first semiconductor structure is formed on a first surface of the first substrate, and the first semiconductor structure is electrically connected to the first signal transmission area;

[0126] Step 703: Form a second substrate on the first substrate. The second substrate includes a base and a first interconnect surface located on the base. The first interconnect surface of the second substrate is opposite to a first surface of the first substrate. The first interconnect surface has a first interconnect region and a second interconnect region that are interconnected. The first interconnect region is electrically connected to the second signal transmission region.

[0127] Step 704: Form a fill layer that seals the first semiconductor structure, the second substrate, and the first surface of the first substrate, wherein the first interconnect region is not sealed by the fill layer, the second interconnect region is sealed by the fill layer, and the top surface of the fill layer on the second interconnect region has a preset height with respect to the first interconnect region.

[0128] The method for preparing the semiconductor package provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0129] Figures 8a to 8g This is a schematic diagram of the semiconductor package provided in the embodiments of this disclosure during the manufacturing process.

[0130] First, see Figure 8a In step 701, a first substrate 10 is provided. The first substrate 10 has a first surface 101, which includes a first signal transmission region 11 and a second signal transmission region 12.

[0131] The first substrate 10 includes a first base 15, and a first upper insulating dielectric layer 16 and a first lower insulating dielectric layer 17 respectively located on the upper and lower surfaces of the first base 15.

[0132] The first substrate 15 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon insulator), etc.

[0133] The first upper insulating dielectric layer 16 and the first lower insulating dielectric layer 17 can be solder resist layers, for example, the material of the first upper insulating dielectric layer 16 and the first lower insulating dielectric layer 17 can be green paint.

[0134] The first substrate 10 has a second surface 102 opposite to the first surface 101, and there is a circuit channel 151 between the first surface 101 and the second surface 102. The second surface 102 of the first substrate 10 has a plurality of first connection pads 171.

[0135] The first substrate 10 has a plurality of sixth connection pads 161 on its first surface, and the circuit channel 151 connects the sixth connection pads 161 and the first connection pads 171.

[0136] In one embodiment, the first signal transmission area 11 of the first substrate 10 has a plurality of fourth connection pads 111, the area of ​​the fourth connection pads 111 being less than or equal to the area of ​​the first connection pads 171.

[0137] The first surface 101 of the first substrate 10 includes a first signal transmission region 11 and a second signal transmission region 12. The first signal transmission region 11 is electrically connected to the subsequently formed first semiconductor structure 20, and the second signal transmission region 12 is electrically connected to the subsequently formed second substrate 30.

[0138] In one embodiment, the first surface 101 of the first substrate 10 further includes a third signal transmission region 13 located between the first signal transmission region 11 and the second signal transmission region 12, and the subsequently formed first semiconductor structure 20 is located on the third signal transmission region 13.

[0139] In some other embodiments, such as Figure 4 As shown, the first substrate 10 further includes a fourth signal transmission region 14, and the second substrate 30 subsequently formed is located on the fourth signal transmission region 14. The second signal transmission region 12 is electrically connected to the fourth signal transmission region 14.

[0140] Next, see Figure 8b In step 702, a first semiconductor structure 20 is formed on the first surface 101 of the first substrate 10, and the first semiconductor structure 20 is electrically connected to the first signal transmission region 11.

[0141] The first semiconductor structure 20 includes a plurality of first semiconductor chips 21 stacked sequentially along a direction perpendicular to the first substrate 10.

[0142] The two adjacent first semiconductor chips 21 are connected by an adhesive film 60, and the first semiconductor structure 20 is also connected to the first substrate 10 by an adhesive film 60.

[0143] Next, see Figure 8c and Figure 8d Step 703 is executed, in which a second substrate 30 is formed on the first substrate 10. The second substrate 30 includes a base 33 and a first interconnect surface 301 located on the base 33. The first interconnect surface 301 of the second substrate 30 is opposite to the first surface 101 of the first substrate 10. The first interconnect surface 301 has a first interconnect region 31 and a second interconnect region 32 that are interconnected. The first interconnect region 31 is electrically connected to the second signal transmission region 12.

[0144] Specifically, see first. Figure 8c A carrier tape 2 is attached to the ring 1, and then an adhesive film 60 is attached to the carrier tape 2. The second substrate is then attached to the adhesive film 60. At this point, the second substrate is a single strip. The second substrate is then cut to form... Figure 8c The units shown are individual units.

[0145] Next, see Figure 8d A second substrate 30 is formed on the first semiconductor structure 20.

[0146] Specifically, an adhesion layer 60 is formed on the first semiconductor structure 20, and then... Figure 8cA single second substrate formed therein is attached to the first semiconductor structure 20.

[0147] In some other embodiments, such as Figure 4 As shown, the second substrate 30 is not formed on the first semiconductor structure 20, but is formed directly on the first substrate 10.

[0148] See Figure 3 The second substrate 20 includes a substrate 33, and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 respectively located on the upper and lower surfaces of the substrate 33.

[0149] The substrate 33 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0150] The upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 can be solder resist layers, for example, the material of the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 can be green paint.

[0151] The first interconnect region 31 of the second substrate 30 has a plurality of second connection pads 311, the area of ​​the second connection pads 311 being greater than or equal to the area of ​​the first connection pads 171.

[0152] By setting the area of ​​the second connecting pad 311 to a larger area, the contact area between the second package and the second connecting pad 311 can be increased. If the contact area is small, it will be difficult to disassemble after soldering. Therefore, increasing the contact area facilitates subsequent disassembly and reassembly.

[0153] In one embodiment, the second interconnect region 32 of the second substrate 30 has a plurality of third connection pads 321, the area of ​​the third connection pads 321 being smaller than the area of ​​the second connection pads 311.

[0154] The number of the third connecting pads 321 is greater than the number of the second connecting pads 311.

[0155] Because the second connecting pad needs to be matched and interconnected with the second package, the layout design is relatively fixed. The third connecting pad carries the interconnection between the second package and the first substrate, so the layout design is more flexible. Designing the third connecting pad to be more numerous and smaller in area can improve signal transmission efficiency.

[0156] In one embodiment, the substrate 33 of the second substrate 30 has an electromagnetic shielding layer (not shown). By providing an electromagnetic shielding layer within the substrate of the second substrate, information interference between the second package and the first semiconductor structure can be prevented, thus avoiding interference with device operation.

[0157] See also Figure 8d After the second substrate 20 is formed, the first semiconductor structure 20 and the second substrate 30 are electrically connected to the first substrate 10 by wire bonding.

[0158] The first signal transmission region 11 and the second signal transmission region 12 are located on opposite sides of the first substrate 10. The first semiconductor structure 20 has a first connection terminal 201, which is located on the same side as the first signal transmission region 11 and is interconnected with the first connection terminal 201 and the first signal transmission region 11 by a lead 50. The second interconnection region 32 is located on the same side as the second signal transmission region 12 and is interconnected with the second interconnection region 32 and the second signal transmission region 12 by a lead 50.

[0159] In some other embodiments, the first semiconductor structure 20 and the second substrate 30 are electrically connected to the first substrate 10 via through-silicon vias (TSVs).

[0160] like Figure 5 As shown, the first semiconductor chip 21 includes a first chip connection pad 212 and a second chip connection pad 213 located on the upper and lower surfaces, respectively, and a first channel 211 penetrating the first semiconductor chip 21 and connecting the first chip connection pad 212 and the second chip connection pad 213. The first channel 211 includes a through-silicon via (TSV).

[0161] The two adjacent first semiconductor chips 21, and the first semiconductor structure 20 and the first substrate 10 are electrically connected through the first chip connection pad 212, the second chip connection pad 213, the first channel 211 and the first solder ball 214.

[0162] like Figure 6As shown, the second substrate 30 further includes a second interconnect surface 302 located on the other side of the substrate 33. The substrate 33 has a channel 36 connecting the first interconnect region 31 and the second interconnect surface 302. The first interconnect region 31 is interconnected with the second signal transmission region 12 in a direction perpendicular to the first substrate 10 via the channel 36.

[0163] The second substrate 30 includes a second connection pad 311 located within a first interconnect region 31, a fifth connection pad 37 located on a second interconnect surface 302 of the second substrate 30, and a channel 36 penetrating the substrate 33 and connecting the second connection pad 311 and the fifth connection pad 37. The channel 36 includes a through-silicon via (TSV). A second solder ball 38 is also included between the second substrate 30 and the first substrate 10.

[0164] The second substrate 30 is electrically connected to the first substrate 10 through the second connecting pad 311, the channel 36, the fifth connecting pad 37 and the second solder ball 38.

[0165] Next, see Figure 8e and Figure 8f Step 704 is executed to form a filling layer 40, which seals the first semiconductor structure 20, the second substrate 30 and the first surface 101 of the first substrate 10. The first interconnect region 31 is not sealed by the filling layer 40, the second interconnect region 32 is sealed by the filling layer 40, and there is a preset height h between the top surface of the filling layer 40 on the second interconnect region 32 and the first interconnect region 31.

[0166] Specifically, see first. Figure 8e A first packaging mold 91 is formed. The first packaging mold 91 includes a first part 911 and a second part 912 located on both sides of the first part 911, and a third part 913 connecting the first part 911 and the second part 912. The surface of the second part 912 is higher than the surface of the first part 911. The surfaces of the second part 912 and the first part 911 are both parallel to the surface of the substrate 10. The first part 911 is located on the first interconnection region 31 of the second substrate 30.

[0167] The method further includes forming a second packaging mold 92, the second packaging mold 92 being located below the first substrate 10 and parallel to the surface of the first substrate 10.

[0168] Next, see Figure 8fUsing the first packaging mold 91 and the second packaging mold 92 as masks, a filling layer 40 is formed; after forming the filling layer 40, the method further includes: removing the first packaging mold 91 and the second packaging mold 92 to expose the first interconnect region 31 covered by the first portion 911.

[0169] See also Figure 8f After the filling layer 40 is formed, a second contact structure 18 protruding from the first substrate 10 is formed on the first connecting pad 171 of the first substrate 10. The second contact structure 18 includes a conductive material.

[0170] Next, see Figure 8g A second package 70 is formed, the second package 70 having a contact surface 701, and the second package 70 being interconnected with the first interconnect region 31 through the contact surface 701.

[0171] The second package 70 has a first contact structure 71 on the contact surface 701. The first contact structure 71 has a first height H protruding from the contact surface 701 in a direction perpendicular to the contact surface 701. The first height H is greater than the preset height h.

[0172] In one embodiment, the second contact structure 18 on the first substrate 10 has a second height protruding from the first substrate 10 in a direction perpendicular to the first substrate 10, the second height being less than or equal to the first height.

[0173] In one embodiment, the second package 70 includes a second semiconductor structure (not shown) that may be of the same or different type from the first semiconductor structure 20.

[0174] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor package, characterized in that, include: A first substrate, the first substrate having a first surface, the first surface including a first signal transmission area and a second signal transmission area; A first semiconductor structure is located on a first surface of the first substrate and is electrically connected to the first signal transmission area. The second substrate is located on the first substrate. The second substrate includes a base and a first interconnect surface located on the base. The first interconnect surface of the second substrate is opposite to a first surface of the first substrate. The first interconnect surface has a first interconnect region and a second interconnect region that are interconnected. The first interconnect region is electrically connected to the second signal transmission region. A filling layer is provided to seal the first semiconductor structure, the second substrate, and a first surface of the first substrate. The first interconnect region is not sealed by the filling layer, the second interconnect region is sealed by the filling layer, and the top surface of the filling layer on the second interconnect region has a predetermined height with respect to the first interconnect region. The first surface of the first substrate further includes a third signal transmission region located between the first signal transmission region and the second signal transmission region, and the first semiconductor structure is located on the third signal transmission region; The second substrate is located on the first semiconductor structure, and the first interconnect region is electrically connected to the second signal transmission region through the second interconnect region; the third signal transmission region includes a first sub-signal region and a second sub-signal region, the first sub-signal region is interconnected with the first signal transmission region and is located in the adjacent region of the first signal transmission region, and the second sub-signal region is interconnected with the second signal transmission region and is located in the adjacent region of the second signal transmission region.

2. The semiconductor package according to claim 1, characterized in that, The first side of the first substrate further includes a fourth signal transmission area, the second substrate is located on the fourth signal transmission area, and the second signal transmission area is electrically connected to the fourth signal transmission area.

3. The semiconductor package according to claim 2, characterized in that, The fourth signal transmission area is electrically connected to the first interconnection area.

4. The semiconductor package according to claim 1, characterized in that, The first signal transmission region and the second signal transmission region are located on opposite sides of the first substrate. The first semiconductor structure has a first connection terminal, which is located on the same side as the first signal transmission region and is interconnected with the first signal transmission region by a lead. The second interconnection region is located on the same side as the second signal transmission region and is interconnected with the second signal transmission region by a lead.

5. The semiconductor package according to claim 1, characterized in that, The first semiconductor structure and the first signal transmission region are interconnected in a direction perpendicular to the first substrate.

6. The semiconductor package according to claim 5, characterized in that, The first semiconductor structure and the third signal transmission region are interconnected in a direction perpendicular to the first substrate, and the first signal transmission region and the third signal transmission region are interconnected.

7. The semiconductor package according to claim 2, characterized in that, The second substrate further includes a second interconnect surface located on the other side of the substrate, the substrate having a channel connecting the first interconnect region and the second interconnect surface, the first interconnect region being interconnected with the second signal transmission region in a direction perpendicular to the first substrate via the channel.

8. The semiconductor package according to claim 1, characterized in that, The substrate of the second substrate has an electromagnetic shielding layer.

9. The semiconductor package according to claim 1, characterized in that, An electromagnetic shielding structure is provided between the first sub-signal region and the second sub-signal region of the first substrate.

10. The semiconductor package according to claim 1, characterized in that, The first substrate has a second surface opposite to the first surface, and there is a circuit channel between the first surface and the second surface. The second surface of the first substrate has a plurality of first connection pads. The first interconnect region of the second substrate has a plurality of second connection pads, the area of ​​the second connection pads being greater than or equal to the area of ​​the first connection pads.

11. The semiconductor package according to claim 10, characterized in that, The second interconnect region of the second substrate has a plurality of third connection pads, the area of ​​which is smaller than that of the second connection pads.

12. The semiconductor package according to claim 10, characterized in that, The first signal transmission area of ​​the first substrate has a plurality of fourth connection pads, the area of ​​which is less than or equal to the area of ​​the first connection pad.

13. The semiconductor package according to claim 11, characterized in that, The number of the third connecting pads is greater than the number of the second connecting pads.

14. The semiconductor package according to claim 1, characterized in that, The first substrate has a first thickness in a direction perpendicular to the first substrate, and the second substrate has a second thickness in a direction perpendicular to the second substrate, wherein the first thickness is less than the second thickness.

15. The semiconductor package according to claim 1, characterized in that, It also includes a second package having a contact surface, the second package being interconnected with the first interconnect region via the contact surface.

16. The semiconductor package according to claim 15, characterized in that, The second package has a first contact structure on its contact surface, and the first contact structure has a first height protruding from the contact surface in a direction perpendicular to the contact surface, the first height being greater than the preset height.

17. The semiconductor package according to claim 16, characterized in that, The first connecting pad of the first substrate has a second contact structure protruding from the first substrate. The second contact structure has a second height protruding from the first substrate in a direction perpendicular to the first substrate. The second height is less than or equal to the first height.

18. The semiconductor package according to claim 15, characterized in that, The second package includes a second semiconductor structure, which may be of the same or different type as the first semiconductor structure.

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