A semiconductor device, a manufacturing method thereof, and an electronic device

Abstract

A semiconductor device and a preparation method thereof, and an electronic device, the semiconductor device comprising a third semiconductor layer arranged on a substrate, a first semiconductor layer and a second semiconductor layer arranged on a side of the third semiconductor layer away from the substrate; a first gate electrode penetrating through the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounding the first gate electrode; a second gate electrode penetrating through the second semiconductor layer and the third semiconductor layer, a second gate insulating layer surrounding the second gate electrode; a first electrode and a second electrode in contact with the first semiconductor layer; a third electrode and a fourth electrode in contact with the second semiconductor layer, the third electrode being electrically connected to the second electrode; a fifth electrode in contact with the third semiconductor layer, the fifth electrode being electrically connected to the fourth electrode. The scheme provided by the embodiment can realize three-dimensional stacking by sharing the first gate electrode and the second gate electrode, can reduce the area occupied by a logic circuit, thereby increasing the device density, and the process is simple.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, semiconductor device technology, and particularly to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0002] NOR gates, as a crucial component of logic processors, are widely used in consumer electronics, the Internet of Things (IoT), communications, automotive, and industrial sectors, accounting for a significant proportion of the semiconductor industry. Currently, major companies are implementing NOR gates using planar structures, increasing density by reducing gate length, which places high demands on fabrication processes. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a semiconductor device and its fabrication method, as well as an electronic device, which can simplify the process and reduce costs.

[0005] This disclosure provides a semiconductor device, including:

[0006] A third semiconductor layer disposed on a substrate, a first semiconductor layer and a second semiconductor layer disposed on the side of the third semiconductor layer away from the substrate, the first semiconductor layer including a first source contact region and a first drain contact region, the second semiconductor layer including a second source contact region and a second drain contact region, and the third semiconductor layer including a third source contact region and a third drain contact region;

[0007] A first gate penetrating the first semiconductor layer and the third semiconductor layer, and a first gate insulating layer surrounding the first gate;

[0008] A second gate penetrating the second semiconductor layer and the third semiconductor layer, and a second gate insulating layer surrounding the second gate;

[0009] A first electrode that contacts the first source contact region of the first semiconductor layer; a second electrode that contacts the first drain contact region of the first semiconductor layer; a third electrode that contacts the second source contact region of the second semiconductor layer; and a fourth electrode that contacts the second drain contact region of the second semiconductor layer, wherein the third electrode is electrically connected to the second electrode.

[0010] A fifth electrode is in contact with the third drain contact region of the third semiconductor layer, and the fifth electrode is electrically connected to the fourth electrode.

[0011] In an exemplary embodiment, the materials of the third semiconductor layer, the first semiconductor layer, and the second semiconductor layer include polycrystalline silicon semiconductor materials or monocrystalline silicon semiconductor materials.

[0012] In an exemplary embodiment, the first drain contact region is disposed on the side of the first gate near the second gate, and the second source contact region is disposed on the side of the second gate near the first gate.

[0013] In one exemplary embodiment, the first semiconductor layer and the second semiconductor layer are disposed on the same layer.

[0014] In an exemplary embodiment, the first electrode and the second electrode are disposed on the side of the first semiconductor layer away from the third semiconductor layer.

[0015] In one exemplary embodiment, the third electrode and the fourth electrode are disposed on the side of the second semiconductor layer away from the third semiconductor layer.

[0016] In one exemplary embodiment, the fifth electrode is disposed on the side of the third semiconductor layer away from the substrate.

[0017] In an exemplary embodiment, the orthographic projection of the first gate overlaps with the orthographic projection of the second gate on a plane perpendicular to the substrate and perpendicular to the extension direction of the third semiconductor layer.

[0018] In one exemplary embodiment, the third semiconductor layer is an NPN stacked structure, the first semiconductor layer is a PNP stacked structure, and the second semiconductor layer is a PNP stacked structure.

[0019] This disclosure provides a method for fabricating a semiconductor device, comprising:

[0020] Provide substrate;

[0021] A third semiconductor layer is formed on the substrate, and a first semiconductor layer and a second semiconductor layer are formed on the side of the third semiconductor layer away from the substrate; and a first gate is formed penetrating the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounding the first gate, a second gate is formed penetrating the second semiconductor layer and the third semiconductor layer, and a second gate insulating layer surrounding the second gate; wherein the first semiconductor layer includes a first source contact region and a first drain contact region, the second semiconductor layer includes a second source contact region and a second drain contact region, and the third semiconductor layer includes a third source contact region and a third drain contact region;

[0022] A first electrode is formed on the side of the first semiconductor layer away from the third semiconductor layer, contacting a first source contact region of the first semiconductor layer and a second electrode is formed on the side of the first semiconductor layer away from the third semiconductor layer, contacting a second source contact region of the second semiconductor layer and a fourth electrode is formed on the side of the second semiconductor layer away from the third semiconductor layer, the third electrode being electrically connected to the second electrode; and a fifth electrode is formed on the side of the third semiconductor layer away from the substrate, contacting a third drain contact region of the third semiconductor layer, the fifth electrode being electrically connected to the fourth electrode.

[0023] In an exemplary embodiment, the third semiconductor layer is formed on the substrate, and a first semiconductor layer and a second semiconductor layer are formed on the side of the third semiconductor layer away from the substrate, a first gate is formed through the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounds the first gate, a second gate is formed through the second semiconductor layer and the third semiconductor layer, and the second gate insulating layer surrounding the second gate includes:

[0024] A third semiconductor layer is formed on the substrate.

[0025] A first insulating layer thin film is formed on the side of the third semiconductor layer away from the substrate;

[0026] A first channel film is formed on the side of the first insulating layer film away from the third semiconductor layer;

[0027] A first via and a second via are formed that penetrate the third semiconductor layer, the first insulating layer film, and the first channel film; a first gate insulating film and a first metal film are sequentially deposited on the sidewall of the first via to form the first gate insulating layer and the first gate; a second gate insulating film and a second metal film are sequentially deposited on the sidewall of the second via to form the second gate insulating layer and the second gate.

[0028] The first channel thin film is patterned to form the first semiconductor layer and the second semiconductor layer.

[0029] In an exemplary embodiment, the third semiconductor layer is formed on the substrate, and a first semiconductor layer and a second semiconductor layer are formed on the side of the third semiconductor layer away from the substrate, a first gate is formed through the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounds the first gate, a second gate is formed through the second semiconductor layer and the third semiconductor layer, and the second gate insulating layer surrounding the second gate includes:

[0030] A third semiconductor layer is formed on the substrate;

[0031] A sacrificial layer thin film is formed on the side of the third semiconductor layer away from the substrate;

[0032] A first channel film is formed on the side of the sacrificial layer film away from the third semiconductor layer;

[0033] A support layer is formed by patterning the first channel thin film to expose the third semiconductor layer;

[0034] A third insulating film is deposited within the holes of the support layer to form the support layer;

[0035] The sacrificial layer film is etched, and a fourth insulating film is deposited at the location of the etched sacrificial layer film to form a third insulating layer disposed between the third semiconductor layer and the first channel film.

[0036] A first via and a second via are formed that penetrate the third semiconductor layer, the third insulating layer, and the first channel film; a first gate insulating film and a first metal film are sequentially deposited on the sidewall of the first via to form the first gate insulating layer and the first gate; a second gate insulating film and a second metal film are sequentially deposited on the sidewall of the second via to form the second gate insulating layer and the second gate.

[0037] The first channel thin film is patterned to form the first semiconductor layer and the second semiconductor layer.

[0038] This disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments.

[0039] In one exemplary embodiment, the electronic device includes a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal.

[0040] This disclosure includes a semiconductor device and its fabrication method, as well as an electronic device. The semiconductor device includes: a third semiconductor layer disposed on a substrate; a first semiconductor layer and a second semiconductor layer disposed on the side of the third semiconductor layer away from the substrate; a first gate penetrating the first semiconductor layer and the third semiconductor layer; a first gate insulating layer surrounding the first gate; a second gate penetrating the second semiconductor layer and the third semiconductor layer; a second gate insulating layer surrounding the second gate; a first electrode contacting a first source contact region of the first semiconductor layer; a second electrode contacting a first drain contact region of the first semiconductor layer; a third electrode contacting a second source contact region of the second semiconductor layer; and a fourth electrode contacting a second drain contact region of the second semiconductor layer, wherein the third electrode is electrically connected to the second electrode; and a fifth electrode contacting the third drain contact region of the third semiconductor layer, wherein the fifth electrode is electrically connected to the fourth electrode. The solution provided in this embodiment allows two transistors in the semiconductor device to share a first gate, and the other two transistors to share a second gate, enabling three-dimensional stacking of transistors without having to lay all transistors flat on a single plane. Therefore, it reduces the area occupied by the semiconductor device, thereby increasing the semiconductor device density, and simplifies the manufacturing process.

[0041] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings.

[0042] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0043] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions.

[0044] Figure 1 A schematic diagram of a semiconductor device provided as an exemplary embodiment;

[0045] Figure 2 An equivalent circuit diagram of a semiconductor device provided for an exemplary embodiment;

[0046] Figure 3A A schematic cross-sectional view of the formation of a sixth semiconductor thin film, provided as an exemplary embodiment;

[0047] Figure 3B for Figure 3A Top view of the structure shown;

[0048] Figure 4AA cross-sectional schematic diagram provided for an exemplary embodiment after forming the first via and the second via;

[0049] Figure 4B for Figure 4A Top view of the structure shown;

[0050] Figure 5A A schematic cross-sectional view provided for an exemplary embodiment after forming the first gate and the second gate;

[0051] Figure 5B for Figure 5A Top view of the structure shown;

[0052] Figure 6A A cross-sectional schematic diagram provided for an exemplary embodiment after forming the third and fourth vias;

[0053] Figure 6B for Figure 6A Top view of the structure shown;

[0054] Figure 7A A schematic cross-sectional view of the second insulating layer after its formation, provided as an exemplary embodiment;

[0055] Figure 7B for Figure 7A Top view of the structure shown;

[0056] Figure 8A A cross-sectional schematic diagram provided for an exemplary embodiment after forming an electrode connection layer;

[0057] Figure 8B for Figure 8A Top view of the structure shown;

[0058] Figure 9A A schematic cross-sectional view of the electrode after its formation is provided as an exemplary embodiment;

[0059] Figure 9B for Figure 9A Top view of the structure shown;

[0060] Figure 10A A schematic cross-sectional view of the formed lead-out electrode provided as an exemplary embodiment;

[0061] Figure 10B for Figure 10A Top view of the structure shown;

[0062] Figure 11A A schematic cross-sectional view of the formation of a sixth semiconductor thin film, provided as an exemplary embodiment;

[0063] Figure 11B for Figure 11A Top view of the structure shown;

[0064] Figure 12A A schematic cross-sectional view of the seventh via provided as an exemplary embodiment;

[0065] Figure 12B for Figure 12A Top view of the structure shown;

[0066] Figure 13A A cross-sectional schematic diagram of the support layer after its formation is provided as an exemplary embodiment;

[0067] Figure 13B for Figure 13A Top view of the structure shown;

[0068] Figure 14A A schematic cross-sectional view of the third insulating layer provided as an exemplary embodiment;

[0069] Figure 14B for Figure 14A Top view of the structure shown;

[0070] Figure 15A A cross-sectional schematic diagram provided for an exemplary embodiment after forming the first via and the second via;

[0071] Figure 15B for Figure 15A Top view of the structure shown;

[0072] Figure 16A A schematic cross-sectional view provided for an exemplary embodiment after forming the first gate and the second gate;

[0073] Figure 16B for Figure 16A Top view of the structure shown;

[0074] Figure 17A A cross-sectional schematic diagram provided for an exemplary embodiment after forming the third and fourth vias;

[0075] Figure 17B for Figure 17A Top view of the structure shown;

[0076] Figure 18A A schematic cross-sectional view of the second insulating layer after its formation, provided as an exemplary embodiment;

[0077] Figure 18B for Figure 18A Top view of the structure shown;

[0078] Figure 19A A cross-sectional schematic diagram provided for an exemplary embodiment after forming an electrode connection layer;

[0079] Figure 19B for Figure 19ATop view of the structure shown;

[0080] Figure 20A A schematic cross-sectional view of the electrode after its formation is provided as an exemplary embodiment;

[0081] Figure 20B for Figure 20A Top view of the structure shown;

[0082] Figure 21A A schematic cross-sectional view of the formed lead-out electrode provided as an exemplary embodiment;

[0083] Figure 21B for Figure 21A Top view of the structure shown;

[0084] Figure 22 A flowchart illustrating a method for fabricating a semiconductor device, provided as an exemplary embodiment. Detailed Implementation

[0085] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0086] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0087] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the accompanying drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0088] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0089] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0090] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0091] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0092] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0093] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0094] The phrase "A and B are set on the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0095] The shift from planar to three-dimensional thinking in the field of 3D NAND gates makes it possible to increase the storage density of nor gates through stacking. In the exemplary embodiments disclosed herein, combining the architecture and concepts of planar nor gates and 3D NAND, a shared gate is used. Utilizing multi-channel polysilicon or monocrystalline silicon, and through thin-film stacking, a stacked semiconductor device structure can be achieved compared to planar nor gates, thereby increasing device density, effectively upgrading the process node, and saving production costs.

[0096] Figure 1 A schematic diagram of a semiconductor device provided for an exemplary embodiment. (See diagram below.) Figure 1As shown, the semiconductor device provided in this embodiment includes:

[0097] A third semiconductor layer 43 is disposed on a substrate 1, and a first semiconductor layer 41 and a second semiconductor layer 42 are disposed on the side of the third semiconductor layer 43 away from the substrate 1; the first semiconductor layer 41 includes a first source contact region and a first drain contact region, the second semiconductor layer 42 includes a second source contact region and a second drain contact region, and the third semiconductor layer 43 includes a third source contact region and a third drain contact region.

[0098] A first gate 33 penetrates the first semiconductor layer 41 and the third semiconductor layer 43, and a first gate insulating layer 31 surrounds the first gate 33;

[0099] A second gate 34 that penetrates the second semiconductor layer 42 and the third semiconductor layer 43, and a second gate insulating layer 32 that surrounds the second gate 34;

[0100] A first electrode 11 that is in contact with the first source contact region of the first semiconductor layer 41 and a second electrode 12 that is in contact with the first drain contact region of the first semiconductor layer 41;

[0101] A third electrode 13 is in contact with the second source contact region of the second semiconductor layer 42 and a fourth electrode 14 is in contact with the second drain contact region of the second semiconductor layer 42, wherein the third electrode 13 is electrically connected to the second electrode 12.

[0102] The fifth electrode 15 is in contact with the third drain contact region of the third semiconductor layer 43, and the fifth electrode 15 is electrically connected to the fourth electrode 14.

[0103] The solution provided in this embodiment is that the first transistor, composed of the first electrode 11, the second electrode 12, the first semiconductor layer 41, and the first gate 33, shares the first gate 33 with the third transistor, composed of the third semiconductor layer, the electrode connecting the third semiconductor layer 43 (such as the fifth electrode 15 and the substrate 1), and the first gate 33; the second transistor, composed of the third electrode 13, the fourth electrode 14, the second semiconductor layer 42, and the second gate 34, shares the second gate 34 with the fourth transistor, composed of the third semiconductor layer 43, the electrode connecting the third semiconductor layer 43 (such as the fifth electrode 15 and the substrate 1), and the second gate 34, thereby realizing the three-dimensional stacking of transistors. Compared with the solution of laying all transistors on a plane, the area occupied by semiconductor devices can be reduced, thereby increasing device density, effectively improving the process node, and the process is simple.

[0104] In an exemplary embodiment, the materials of the third semiconductor layer 43, the first semiconductor layer 41, and the second semiconductor layer 42 may include polycrystalline silicon semiconductor materials.

[0105] In an exemplary embodiment, the materials of the third semiconductor layer 43, the first semiconductor layer 41, and the second semiconductor layer 42 may include single-crystal silicon semiconductor materials.

[0106] In one exemplary embodiment, the first semiconductor layer 41 and the second semiconductor layer 42 may be disposed on the same layer. However, the embodiments disclosed herein are not limited to this, and the first semiconductor layer 41 and the second semiconductor layer 42 may be formed by different patterning processes. The first semiconductor layer 41 and the second semiconductor layer 42 may be disposed on the same layer, and the first semiconductor layer 41 and the second semiconductor layer 42 may be fabricated in a single patterning process, which can simplify the process and reduce costs.

[0107] In an exemplary embodiment, the first electrode 11 and the second electrode 12 may be disposed on the side of the first semiconductor layer 41 away from the third semiconductor layer 43. Disposing the first electrode 11 and the second electrode 12 on the side of the first semiconductor layer 41 away from the third semiconductor layer 43 eliminates the need for drilling holes, making the process simpler compared to disposing them on the side of the first semiconductor layer 41 closer to the third semiconductor layer 43.

[0108] In an exemplary embodiment, the third electrode 13 and the fourth electrode 14 may be disposed on the side of the second semiconductor layer 42 away from the third semiconductor layer 43. Disposing the third electrode 13 and the fourth electrode 14 on the side of the second semiconductor layer 42 away from the third semiconductor layer 43 eliminates the need for drilling holes, making the process simpler compared to disposing them on the side of the second semiconductor layer 42 closer to the third semiconductor layer 43.

[0109] In an exemplary embodiment, the fifth electrode 15 may be disposed on the side of the third semiconductor layer 43 away from the substrate 1. Compared to disposing the fifth electrode 15 on the side of the third semiconductor layer 43 closer to the substrate 1, the solution provided in this embodiment can reduce the hole depth and simplify the process.

[0110] In one exemplary embodiment, the first gate 33 may extend along a first direction, which may intersect the substrate 1. In one exemplary embodiment, the first direction may be perpendicular to the substrate 1, but the embodiments of this disclosure are not limited thereto, and the first direction may not be perpendicular to the substrate 1.

[0111] In one exemplary embodiment, the second gate 34 may extend along a second direction, which may intersect the substrate 1. In one exemplary embodiment, the second direction may be perpendicular to the substrate 1, but the embodiments of this disclosure are not limited thereto, and the second direction may not be perpendicular to the substrate 1.

[0112] In an exemplary embodiment, on a plane perpendicular to the substrate 1 and perpendicular to the extension direction of the third semiconductor layer 43, the orthographic projections of the first gate 33 and the second gate 34 may overlap. That is, the first gate 33 and the second gate 34 may be distributed along the extension direction of the third semiconductor layer 43. Compared with a solution where the first gate 33 and the second gate 34 are not distributed along the extension direction of the third semiconductor layer 43, the solution provided in this embodiment can reduce the size of the semiconductor device in the direction parallel to the substrate 1 and perpendicular to the extension direction of the third semiconductor layer 43, thereby minimizing the size of the semiconductor device.

[0113] In an exemplary embodiment, the third semiconductor layer 43 may be an NPN type stacked structure, the first semiconductor layer 41 may be a PNP type stacked structure, and the second semiconductor layer 42 may be a PNP type stacked structure. For example, the third semiconductor layer 43 may include a first semiconductor thin film 2, a second semiconductor thin film 3, and a third semiconductor thin film 4 stacked on the substrate 1. The first semiconductor thin film 2 may be an N-type semiconductor thin film, the second semiconductor thin film 3 may be a P-type semiconductor thin film, and the third semiconductor thin film 4 may be an N-type semiconductor thin film. The first semiconductor layer 41 may include a fourth semiconductor layer 61, a fifth semiconductor layer 71, and a sixth semiconductor layer 81. The fourth semiconductor layer 61 may be a P-type semiconductor layer, the fifth semiconductor layer 71 may be an N-type semiconductor layer, and the sixth semiconductor layer 81 may be a P-type semiconductor layer. The second semiconductor layer 42 may include a seventh semiconductor layer 62, an eighth semiconductor layer 72, and a ninth semiconductor layer 82. The seventh semiconductor layer 62 may be a P-type semiconductor layer, the eighth semiconductor layer 72 may be an N-type semiconductor layer, and the ninth semiconductor layer 82 may be a P-type semiconductor layer. However, the present disclosure is not limited to this. In another exemplary embodiment, a first semiconductor layer 41 and a second semiconductor layer 42 may be formed on the substrate 1, and then a third semiconductor layer 43 may be formed on the side of the first semiconductor layer 41 and the second semiconductor layer 42 away from the substrate 1.

[0114] In an exemplary embodiment, the second electrode 12 and the third electrode 13 may be disposed between the first gate 33 and the second gate 34.

[0115] In one exemplary embodiment, such as Figure 1As shown, the first electrode 11 can contact the sixth semiconductor layer 81, the second electrode 12 can contact the fourth semiconductor layer 61, the third electrode 13 can contact the ninth semiconductor layer 82, and the fourth electrode 12 can contact the seventh semiconductor layer 62. In another exemplary embodiment, the first electrode 11 can contact the fourth semiconductor layer 61, the second electrode 12 can contact the sixth semiconductor layer 81, the third electrode 13 can contact the seventh semiconductor layer 62, and the fourth electrode 14 can contact the ninth semiconductor layer 82. The aforementioned multiple electrodes contacting the corresponding semiconductor layers can be connected via an electrode connection layer to reduce contact resistance.

[0116] In an exemplary embodiment, the fifth electrode 15 may contact the third semiconductor thin film 4.

[0117] In an exemplary embodiment, one of the first electrode 11 and the second electrode 12 is a source electrode, and the other is a drain electrode. One of the third electrode 13 and the fourth electrode 14 is a source electrode, and the other is a drain electrode. The fifth electrode 15 can be a drain electrode. Specifically, identifying the source or drain electrode in a product requires determination based on the direction of current flow. For example, the source electrode described in this embodiment may also be interpreted as a drain electrode based on the direction of current flow; correspondingly, the source contact area in contact with the source electrode may be interpreted as a drain contact area.

[0118] In an exemplary embodiment, the third electrode 13 and the second electrode 12 can be electrically connected by a connecting electrode 23 disposed on the side of the third electrode 13 and the second electrode 12 away from the substrate 1.

[0119] In an exemplary embodiment, the fourth electrode 14 and the fifth electrode 15 can be electrically connected by a fourth lead-out electrode 25 disposed on the side of the fourth electrode 14 and the fifth electrode 15 away from the substrate 1.

[0120] In an exemplary embodiment, the semiconductor device may further include: a first lead-out electrode 21 electrically connected to the first electrode 11, a second lead-out electrode 22 electrically connected to the first gate 33, and a third lead-out electrode 24 electrically connected to the second gate 34.

[0121] Figure 2 This is a schematic diagram of an equivalent circuit of a semiconductor device provided for an exemplary embodiment. Figure 2As shown, the semiconductor device may include a first transistor P1, a second transistor P2, a third transistor N1, and a fourth transistor N2. The first transistor P1 includes a first gate 33, a first electrode 11, and a second electrode 12. The second transistor P2 includes a second gate 34, a third electrode 13, and a fourth electrode 14. The third transistor N1 includes a fifth electrode 15, a sixth electrode 16, and a first gate 33. The fourth transistor N2 includes a seventh electrode 17, an eighth electrode 18, and a second gate 34. The first electrode 11 is electrically connected to a first voltage terminal VDD. The first gate 33 is electrically connected to a first input terminal Input1. The second gate 34 is electrically connected to a second input terminal Input2. The second electrode 12 is electrically connected to the third electrode 13. The fourth electrode 14 is electrically connected to the fifth electrode 15 and is also electrically connected to the output terminal Output. The fifth electrode 15 is electrically connected to the seventh electrode 17. The sixth electrode 16 is electrically connected to the eighth electrode 18. The sixth electrode 16 and the eighth electrode 18 are electrically connected to a second voltage terminal, which may be ground (GND), for example, through the substrate 1. In this embodiment, the first transistor P1 and the third transistor N1 share the first gate 33, and the second transistor P2 and the fourth transistor N2 share the second gate 34. Thus, the first transistor P1 and the third transistor N1 can be stacked in three dimensions, and the second transistor P2 and the fourth transistor N2 can be stacked in three dimensions. Compared with the scheme in which the first transistor P1, the third transistor N1, the second transistor P2 and the fourth transistor N2 are arranged in a planar manner, the size of the semiconductor device can be reduced, the density of the semiconductor device can be increased, and the requirements for the fabrication process are low, making it easy to implement.

[0122] In an exemplary embodiment, when multiple semiconductor devices are present, the first electrodes 11 of the multiple semiconductor devices can be electrically connected to the same first voltage terminal VDD.

[0123] In an exemplary embodiment, the first transistor P1 and the second transistor P2 may be P-type transistors, and the third transistor N1 and the fourth transistor N2 may be N-type transistors.

[0124] This disclosure also provides an electronic device, including any of the semiconductor devices described above. The electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This disclosure does not impose any special limitations on the specific form of the described electronic device.

[0125] The technical solution of this embodiment is further illustrated below through the fabrication process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0126] In one exemplary embodiment, the semiconductor device includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the fabrication process of the semiconductor device may include:

[0127] 101) A substrate 1 is provided, on which a stacked structure comprising a first semiconductor thin film 2, a second semiconductor thin film 3, a third semiconductor thin film 4, a first insulating thin film 5, a fourth semiconductor thin film 6, a fifth semiconductor thin film 7, and a sixth semiconductor thin film 8 is sequentially stacked, as follows: Figure 3A and Figure 3B As shown, where, Figure 3A This is a cross-sectional view. Figure 3B This is a top view.

[0128] The first semiconductor thin film 2, the second semiconductor thin film 3, and the third semiconductor thin film 4 constitute the third semiconductor layer 43. The fourth semiconductor thin film 6, the fifth semiconductor thin film 7, and the sixth semiconductor thin film 8 constitute the first channel film.

[0129] In an exemplary embodiment, the substrate 1 may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0130] In one exemplary embodiment, the substrate 1 is, for example, a silicon substrate.

[0131] In an exemplary embodiment, the first semiconductor thin film 2 and the third semiconductor thin film 4 may be first polar semiconductor thin films; the second semiconductor thin film 3 may be a second polar semiconductor thin film; for example, the first semiconductor thin film 2 and the third semiconductor thin film 4 may be N++ poly (N++ type polycrystalline silicon) thin films, and the second semiconductor thin film 3 may be a P type polycrystalline silicon thin film;

[0132] In an exemplary embodiment, the fourth semiconductor thin film 6 and the sixth semiconductor thin film 8 may be second polar semiconductor thin films; the fifth semiconductor thin film 7 may be a first polar semiconductor thin film; for example, the fourth semiconductor thin film 6 and the sixth semiconductor thin film 8 may be P++poly (P++ type polycrystalline silicon) thin films, and the fifth semiconductor thin film 7 may be an N-type polycrystalline silicon thin film.

[0133] In an exemplary embodiment, the first insulating film may be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).

[0134] In one exemplary embodiment, the material of the semiconductor thin film may include an oxide semiconductor.

[0135] In an exemplary embodiment, the oxide semiconductor may include at least one of indium oxide, tin oxide, indium zinc (In-Zn) oxides, tin zinc (Sn-Zn) oxides, aluminum zinc (Al-Zn) oxides, indium gallium (In-Ga) oxides, indium gallium zinc (In-Ga-Zn) oxides, indium aluminum zinc (In-Al-Zn) oxides, indium tin zinc (In-Sn-Zn) oxides, tin gallium zinc (Sn-Ga-Zn) oxides, aluminum gallium zinc (Al-Ga-Zn) oxides, and tin aluminum zinc (Sn-Al-Zn) oxides.

[0136] In an exemplary embodiment, the first semiconductor thin film 2, the second semiconductor thin film 3, the third semiconductor thin film 4, the first insulating thin film 5, the fourth semiconductor thin film 6, the fifth semiconductor thin film 7, and the sixth semiconductor thin film 8 can be formed by a growth process.

[0137] 102) A first via K1 and a second via K2 are formed through the first semiconductor thin film 2, the second semiconductor thin film 3, the third semiconductor thin film 4, the first insulating thin film 5, the fourth semiconductor thin film 6, the fifth semiconductor thin film 7, and the sixth semiconductor thin film 8. When fabricating multiple semiconductor devices, multiple slots C1 can also be formed. The multiple slots C1 cut the stacked structure into multiple independent units so that multiple semiconductor devices can be formed subsequently, such as... Figure 4A and Figure 4B As shown, where Figure 4B This is a top view. Figure 4A for Figure 4B Cross-sectional view along the AA' direction.

[0138] In one exemplary embodiment, the cross-section of the first via K1 and the cross-section of the second via K2 can be circular on a plane parallel to the substrate 1. However, the embodiments disclosed herein are not limited to this. The cross-sections of the first via K1 and the second via K2 can be square, elliptical, etc.

[0139] In one exemplary embodiment, such as Figure 4B As shown, the shape of the orthographic projection of the unit on a plane parallel to the substrate 1 can be rectangular, but the embodiments disclosed herein are not limited to this and can be other shapes.

[0140] 103) A first gate insulating film and a first metal film are sequentially deposited on the sidewalls of the first via K1 and the second via K2 to form a first gate insulating layer 31, a second gate insulating layer 32, a first gate 33, and a second gate 34, respectively. The first gate 33 fills the first via K1, and the second gate 34 fills the second via K2. The first gate insulating layer 31 surrounds the first gate 33, and the second gate insulating layer 34 surrounds the second gate 34. The first gate insulating layer 31 serves as the gate insulating layer for the first transistor P1 and the third transistor N1, the second gate insulating layer 32 serves as the gate insulating layer for the second transistor P2 and the fourth transistor N2, the first gate 33 serves as the gate for the first transistor P1 and the third transistor N1, and the second gate 34 serves as the gate for the second transistor P2 and the fourth transistor N2. Figure 5A and 5B As shown, where Figure 5A This is a cross-sectional view. Figure 5B This is a top view.

[0141] In one exemplary embodiment, the first gate insulating film may be a High-K dielectric material, including but not limited to at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, etc.

[0142] In an exemplary embodiment, the first metal thin film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).

[0143] In an exemplary embodiment, the first gate insulating layer 31, the second gate insulating layer 32, the first gate 33, and the second gate 34 can be formed by an atomic layer deposition (ALD) process.

[0144] 104) A third via K3 and a fourth via K4 are formed, wherein the third via K3 exposes the fourth semiconductor film 6 and the first insulating film 5, and the fourth via K4 exposes the fourth semiconductor film 6 and the first insulating film 5. The third via K3 is disposed between the first via K1 and the second via K2, and the fourth via K4 is disposed on the side of the second via K2 away from the third via K3, such as... Figure 6A and Figure 6B As shown, where Figure 6A This is a cross-sectional view. Figure 6B This is a top view. The third via K3 cuts the first channel film formed by the fourth semiconductor film 6, the fifth semiconductor film 7, and the sixth semiconductor film 8 into a first semiconductor layer 41 and a second semiconductor layer 42 that are disconnected from each other. The third via K3 exposes a portion of the fourth semiconductor film 6 located in the first semiconductor layer 41.

[0145] In one exemplary embodiment, the cross-section of the third via K3 and the fourth via K4 may be square on a plane parallel to the substrate 1. However, the embodiments disclosed herein are not limited to this, and the cross-section of the third via K3 and the fourth via K4 may be other shapes.

[0146] 105) On the substrate 1 where the aforementioned pattern is formed, a second insulating film is deposited to form a second insulating layer 9, such as... Figure 7A and Figure 7B As shown, where Figure 7A This is a cross-sectional view. Figure 7B This is a top view. The second insulating layer 9 covers the sixth semiconductor film 8, the fourth semiconductor film 6, and the first insulating film 5.

[0147] In one exemplary embodiment, the second insulating layer 9 can be formed by, but is not limited to, a chemical vapor deposition (CVD) process.

[0148] In one exemplary embodiment, the second insulating film may be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).

[0149] In one exemplary embodiment, the second insulating film may be made of the same or different material as the first insulating film.

[0150] 106) Forming a first electrode connection layer 111 contacting the sixth semiconductor thin film 8 included in the first semiconductor layer 41, a second electrode connection layer 121 contacting the fourth semiconductor thin film 6 included in the first semiconductor layer 41, a third electrode connection layer 131 contacting the sixth semiconductor thin film 8 included in the second semiconductor layer 42, a fourth electrode connection layer 141 contacting the fourth semiconductor thin film 6 included in the second semiconductor layer 42, and a fifth electrode connection layer 151 contacting the third semiconductor thin film 4, as follows. Figure 8A and Figure 8B As shown, where Figure 8A This is a cross-sectional view. Figure 8B This is a top view. The first electrode connection layer 111 to the fifth electrode connection layer 151 can reduce the contact resistance between the electrode and the semiconductor layer.

[0151] In an exemplary embodiment, the first electrode connection layer 111 to the fifth electrode connection layer 151 can be formed by a silicide process.

[0152] In an exemplary embodiment, the first electrode connection layer 111 to the fifth electrode connection layer 151 may be metal silicides, such as titanium (Ti), cobalt (Co) and nickel-platinum (NiPt) silicides, such as titanium disilicide (TiSi2), cobalt disilicide (CoSi2) and nickel-platinum silicide (NiPtSi).

[0153] In an exemplary embodiment, on a plane parallel to the substrate 1, the orthographic projection of the first electrode connection layer 111 can be square, the orthographic projection of the second electrode connection layer 121 can be square, the orthographic projection of the third electrode connection layer 131 can be square, the orthographic projection of the fourth electrode connection layer 141 can be square, and the orthographic projection of the fifth electrode connection layer 151 can be square. However, the embodiments disclosed herein are not limited to this and can be other shapes.

[0154] 107) A second metal thin film is deposited on the surface of the first electrode connection layer 111 to form a first electrode 11; a second metal thin film is deposited on the surface of the second electrode connection layer 121 to form a second electrode 12; a second metal thin film is deposited on the surface of the third electrode connection layer 131 to form a third electrode 13; a second metal thin film is deposited on the surface of the fourth electrode connection layer 141 to form a fourth electrode 14; and a second metal thin film is deposited on the surface of the fifth electrode connection layer 151 to form a fifth electrode 15, as follows. Figure 9A and Figure 9B As shown. Among them. Figure 9A This is a cross-sectional view. Figure 9B This is a top view.

[0155] In an exemplary embodiment, the second metal thin film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).

[0156] In an exemplary embodiment, the first electrode 11 to the fifth electrode 15 can be formed by, but is not limited to, a CVD process. One of the first electrode 11 and the second electrode 12 is the source electrode of the first transistor P1, and the other is the drain electrode of the first transistor P1. One of the third electrode 13 and the fourth electrode 14 is the source electrode of the second transistor P2, and the other is the drain electrode of the second transistor P2. The fifth electrode 15 is an electrode of the fourth transistor N2, for example, as a drain electrode.

[0157] In an exemplary embodiment, on a plane parallel to the substrate 1, the orthographic projection of the first electrode 11 can be square, the orthographic projection of the second electrode 12 can be square, the orthographic projection of the third electrode 13 can be square, the orthographic projection of the fourth electrode 14 can be square, and the orthographic projection of the fifth electrode 15 can be square, but the embodiments of this disclosure are not limited to this and can be other shapes.

[0158] 108) Form a first lead-out electrode 21 connecting the first electrode 11, a second lead-out electrode 22 connecting the first gate electrode 33, a connecting electrode 23 connecting the second electrode 12 and the third electrode 13, a third lead-out electrode 24 connecting the second gate electrode 34, and a fourth lead-out electrode 25 connecting the fourth electrode 14 and the fifth electrode 15, as follows. Figure 10A and Figure 10B As shown, where, Figure 10A This is a cross-sectional view. Figure 10B This is a top view.

[0159] Before forming the second lead-out electrode 22 and the third lead-out electrode 23, a fifth via exposing the first gate 33 and a sixth via exposing the second gate 34 may be formed, the second lead-out electrode 22 is formed in the fifth via, and the third lead-out electrode 23 is formed in the sixth via.

[0160] The first lead electrode 21 can be connected to the first voltage terminal VDD, the second lead electrode 22 can be connected to the first input terminal input1, the third lead electrode 24 can be connected to the second input terminal input2, and the fourth lead electrode 25 can be connected to the output terminal output.

[0161] In an exemplary embodiment, when multiple semiconductor devices are present, the first lead-out electrodes 21 of the multiple semiconductor devices can be electrically connected to the same first voltage terminal VDD.

[0162] In an exemplary embodiment, the first lead-out electrode 21, the second lead-out electrode 22, the connecting electrode 23, the third lead-out electrode 24, and the fourth lead-out electrode 25 may be made of metal materials such as copper, aluminum, tungsten, and titanium.

[0163] In one exemplary embodiment, the first electrode 11, the second electrode 12, the third electrode 13, the fourth electrode 14, and the fifth electrode 15 are not limited to those described above. Figure 9A The location shown can be set to other locations.

[0164] In another exemplary embodiment, the fabrication process of the semiconductor device may include:

[0165] 201) A substrate 1 is provided, on which a first semiconductor thin film 2, a second semiconductor thin film 3, a third semiconductor thin film 4, a sacrificial layer thin film 10, a fourth semiconductor thin film 6, a fifth semiconductor thin film 7, and a sixth semiconductor thin film 8 are sequentially stacked, as follows: Figure 11A and Figure 11B As shown, where, Figure 11A This is a cross-sectional view. Figure 11B This is a top view.

[0166] The first semiconductor thin film 2, the second semiconductor thin film 3, and the third semiconductor thin film 4 constitute the third semiconductor layer 43. The fourth semiconductor thin film 6, the fifth semiconductor thin film 7, and the sixth semiconductor thin film 8 constitute the first channel film.

[0167] In one exemplary embodiment, the substrate 1 may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one exemplary embodiment, the substrate may be, for example, a silicon substrate.

[0168] In an exemplary embodiment, the first semiconductor thin film 2 and the third semiconductor thin film 4 may be first polar semiconductor thin films; the second semiconductor thin film 3 may be a second polar semiconductor thin film; for example, the first semiconductor thin film 2 and the third semiconductor thin film 4 may be N++Si (N++ type single crystal silicon) thin films, and the second semiconductor thin film 3 may be a P type single crystal silicon thin film.

[0169] In an exemplary embodiment, the fourth semiconductor thin film 6 and the sixth semiconductor thin film 8 may be second polar semiconductor thin films; the fifth semiconductor thin film 7 may be a first polar semiconductor thin film; for example, the fourth semiconductor thin film 6 and the sixth semiconductor thin film 8 may be P++Si (P++ type single crystal silicon) thin films, and the fifth semiconductor thin film 7 may be an N-type single crystal silicon thin film.

[0170] In one exemplary embodiment, the sacrificial layer film 10 may be germanium silicon (GeSi), but is not limited thereto, and may be other materials that can be grown by epitaxial processes.

[0171] In one exemplary embodiment, the material of the semiconductor thin film may include an oxide semiconductor.

[0172] In an exemplary embodiment, the oxide semiconductor may include at least one of indium oxide, tin oxide, indium zinc (In-Zn) oxides, tin zinc (Sn-Zn) oxides, aluminum zinc (Al-Zn) oxides, indium gallium (In-Ga) oxides, indium gallium zinc (In-Ga-Zn) oxides, indium aluminum zinc (In-Al-Zn) oxides, indium tin zinc (In-Sn-Zn) oxides, tin gallium zinc (Sn-Ga-Zn) oxides, aluminum gallium zinc (Al-Ga-Zn) oxides, and tin aluminum zinc (Sn-Al-Zn) oxides.

[0173] In an exemplary embodiment, the first semiconductor thin film 2, the second semiconductor thin film 3, the third semiconductor thin film 4, the sacrificial layer thin film 10, the fourth semiconductor thin film 6, the fifth semiconductor thin film 7, and the sixth semiconductor thin film 8 can be formed by a reduced pressure chemical vapor deposition (RPCVD) process, but not limited to.

[0174] 202) A seventh via K7 (or support layer via) is formed, which penetrates the sacrificial layer film 10, the fourth semiconductor film 6, the fifth semiconductor film 7, and the sixth semiconductor film 8. The seventh via K7 includes a second sub-via K72 penetrating the sacrificial layer film 10 and a first sub-via K71 penetrating the fourth semiconductor film 6, the fifth semiconductor film 7, and the sixth semiconductor film 8, with the orthographic projection of the first sub-via K71 located within the orthographic projection of the second sub-via K72. When fabricating multiple semiconductor devices, multiple slots C1 can also be formed, which cut the stacked structure into multiple independent units for subsequent fabrication of multiple semiconductor devices, such as... Figure 12A and Figure 12B As shown, where, Figure 12A This is a cross-sectional view. Figure 12BThis is a top view.

[0175] In one exemplary embodiment, such as Figure 12B As shown, the planar shape of the unit can be rectangular, but the embodiments disclosed herein are not limited to this and can be other shapes.

[0176] 203) A third insulating film is deposited on the seventh via K7 to form a support layer 50, as shown below. Figure 13A and Figure 13B As shown, where, Figure 13A This is a cross-sectional view. Figure 13B This is a top view. The support layer 50 serves to support the material during the subsequent etching of the sacrificial layer film 10.

[0177] In an exemplary embodiment, the third insulating film may be a low-K dielectric material, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).

[0178] 204) Etch the sacrificial layer film 10, and deposit a fourth insulating film at the location where the etched sacrificial layer film 10 is located to form a third insulating layer 51, such as... Figure 14A and Figure 14B As shown, where, Figure 14A This is a cross-sectional view. Figure 14B This is a top view.

[0179] 205) A first via K1 and a second via K2 are formed through the first semiconductor thin film 2, the second semiconductor thin film 3, the third semiconductor thin film 4, the third insulating layer 51, the fourth semiconductor thin film 6, the fifth semiconductor thin film 7, and the sixth semiconductor thin film 8, as shown in the diagram. Figure 15A and Figure 15B As shown, where, Figure 15A This is a cross-sectional view. Figure 15B This is a top view.

[0180] In one exemplary embodiment, the cross-section of the first via K1 and the cross-section of the second via K2 can be circular on a plane parallel to the substrate 1. However, the embodiments disclosed herein are not limited to this. The cross-sections of the first via K1 and the second via K2 can be square, elliptical, etc.

[0181] 206) A first gate insulating film and a first metal film are sequentially deposited on the sidewalls of the first via K1 and the second via K2 to form a first gate insulating layer 31, a second gate insulating layer 32, a first gate 33, and a second gate 34, respectively. The first gate 33 fills the first via K1, and the second gate 34 fills the second via K2. The first gate insulating layer 31 surrounds the first gate 33, and the second gate insulating layer 34 surrounds the second gate 34. The first gate insulating layer 31 serves as the gate insulating layer for the first transistor P1 and the third transistor N1, the second gate insulating layer 32 serves as the gate insulating layer for the second transistor P2 and the fourth transistor N2, the first gate 33 serves as the gate for the first transistor P1 and the third transistor N1, and the second gate 34 serves as the gate for the second transistor P2 and the fourth transistor N2. Figure 16A and 16B As shown, where Figure 16A This is a cross-sectional view. Figure 16B This is a top view.

[0182] In one exemplary embodiment, the first gate insulating film may be a High-K dielectric material, including but not limited to at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, etc.

[0183] In an exemplary embodiment, the first metal thin film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).

[0184] In an exemplary embodiment, the first gate insulating layer 31, the second gate insulating layer 32, the first gate 33, and the second gate 34 can be formed by an atomic layer deposition (ALD) process.

[0185] 207) An eighth via K8 and a fourth via K4 are formed, wherein the eighth via K8 exposes the fourth semiconductor thin film 6, and the fourth via K4 exposes the fourth semiconductor thin film 6 and the third insulating layer 51. The eighth via K8 is disposed between the first via K1 and the support layer 50, and the fourth via K4 is disposed on the side of the second via K2 away from the eighth via K8, such as... Figure 17A and Figure 17B As shown, where Figure 17A This is a cross-sectional view. Figure 17B This is a top view. At this time, the first channel film formed by the fourth semiconductor film 6, the fifth semiconductor film 7, and the sixth semiconductor film 8 is cut into a first semiconductor layer 41 and a second semiconductor layer 42 that are disconnected from each other.

[0186] In one exemplary embodiment, the cross-section of the eighth via K8 and the fourth via K4 may be square on a plane parallel to the substrate 1. However, the embodiments disclosed herein are not limited to this, and the cross-section of the eighth via K8 and the fourth via K4 may be other shapes.

[0187] 208) On the substrate 1 where the aforementioned pattern is formed, a second insulating film is deposited to form a second insulating layer 9, such as... Figure 18A and Figure 18B As shown, where Figure 18A This is a cross-sectional view. Figure 18B This is a top view. The second insulating layer 9 covers the sixth semiconductor thin film 8, the fourth semiconductor thin film 6, the support layer 50, and the third insulating layer 51.

[0188] In one exemplary embodiment, the second insulating layer 9 can be formed by, but is not limited to, a CVD process.

[0189] In one exemplary embodiment, the second insulating film may be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).

[0190] In one exemplary embodiment, the second insulating film may be made of the same or different material as the first insulating film.

[0191] 209) Form a first electrode connection layer 111 contacting the sixth semiconductor thin film 8 included in the first semiconductor layer 41, a second electrode connection layer 121 contacting the fourth semiconductor thin film 6 included in the first semiconductor layer 41, a third electrode connection layer 131 contacting the sixth semiconductor thin film 8 included in the second semiconductor layer 42, a fourth electrode connection layer 141 contacting the fourth semiconductor thin film 6 included in the second semiconductor layer 42, and a fifth electrode connection layer 151 contacting the third semiconductor thin film 4, as follows. Figure 19A and Figure 19B As shown, where, Figure 19A This is a cross-sectional view. Figure 19B This is a top view. The first electrode connection layer 111 to the fifth electrode connection layer 151 can reduce the contact resistance between the electrode and the semiconductor layer.

[0192] In an exemplary embodiment, the first electrode connection layer 111 to the fifth electrode connection layer 151 can be formed by a silicide process.

[0193] In an exemplary embodiment, the first electrode connection layer 111 to the fifth electrode connection layer 151 may be metal silicides, such as titanium (Ti), cobalt (Co) and nickel-platinum (NiPt) silicides, such as titanium disilicide (TiSi2), cobalt disilicide (CoSi2) and nickel-platinum silicide (NiPtSi).

[0194] In an exemplary embodiment, on a plane parallel to the substrate 1, the orthographic projection of the first electrode connection layer 111 can be square, the orthographic projection of the second electrode connection layer 121 can be square, the orthographic projection of the third electrode connection layer 131 can be square, the orthographic projection of the fourth electrode connection layer 141 can be square, and the orthographic projection of the fifth electrode connection layer 151 can be square. However, the embodiments of this disclosure are not limited to this, and the orthographic projection of the first electrode connection layer 111 onto the orthographic projection of the fifth electrode connection layer 151 can be other shapes.

[0195] 210) A second metal thin film is deposited on the surface of the first electrode connection layer 111 to form a first electrode 11; a second metal thin film is deposited on the surface of the second electrode connection layer 121 to form a second electrode 12; a second metal thin film is deposited on the surface of the third electrode connection layer 131 to form a third electrode 13; a second metal thin film is deposited on the surface of the fourth electrode connection layer 141 to form a fourth electrode 14; and a second metal thin film is deposited on the surface of the fifth electrode connection layer 151 to form a fifth electrode 15, as follows. Figure 20A and Figure 20B As shown, where Figure 20A This is a cross-sectional view. Figure 20B This is a top view.

[0196] In an exemplary embodiment, the second metal thin film may include, but is not limited to, at least one of the following: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).

[0197] In an exemplary embodiment, the first electrode 11 to the fifth electrode 15 can be formed by, but is not limited to, a CVD process. One of the first electrode 11 and the second electrode 12 is the source electrode of the first transistor P1, and the other is the drain electrode of the first transistor P1. One of the third electrode 13 and the fourth electrode 14 is the source electrode of the second transistor P2, and the other is the drain electrode of the second transistor P2. The fifth electrode 15 is an electrode of the fourth transistor N2, for example, as a drain electrode.

[0198] In an exemplary embodiment, on a plane parallel to the substrate 1, the orthographic projection of the first electrode 11 can be square, the orthographic projection of the second electrode 12 can be square, the orthographic projection of the third electrode 13 can be square, the orthographic projection of the fourth electrode 14 can be square, and the orthographic projection of the fifth electrode 15 can be square, but the embodiments of this disclosure are not limited to this and can be other shapes.

[0199] 211) Form a first lead-out electrode 21 connecting the first electrode 11, a second lead-out electrode 22 connecting the first gate 33, a connection electrode 23 connecting the second electrode 12 and the third electrode 13, a third lead-out electrode 24 connecting the second gate 34, and a fourth lead-out electrode 25 connecting the fourth electrode 14 and the fifth electrode 15, as follows. Figure 21A and Figure 21B As shown. Among them. Figure 21A This is a cross-sectional view. Figure 21B This is a top view.

[0200] Before forming the second lead-out electrode 22 and the third lead-out electrode 24, a fifth via exposing the first gate 33 and a sixth via exposing the second gate 34 can be patterned, with the second lead-out electrode 22 formed in the fifth via and the third lead-out electrode 24 formed in the sixth via.

[0201] The first lead electrode 21 can be connected to the first voltage terminal VDD, the second lead electrode 22 can be connected to the first input terminal Input1, the third lead electrode 24 can be connected to the second input terminal Input2, and the fourth lead electrode 25 can be connected to the output terminal Output. The substrate 1 can be connected to a second voltage terminal, such as ground (GND).

[0202] In an exemplary embodiment, the first lead-out electrode 21, the second lead-out electrode 22, the connecting electrode 23, the third lead-out electrode 24, and the fourth lead-out electrode 25 may be made of metal materials such as copper, aluminum, tungsten, and titanium.

[0203] In one exemplary embodiment, the first electrode 11, the second electrode 12, the third electrode 13, the fourth electrode 14, and the fifth electrode 15 are not limited to those described above. Figure 20A The location shown can be set to other locations.

[0204] Figure 22 This disclosure provides a flowchart of a method for fabricating a semiconductor device according to an embodiment. For example... Figure 22 As shown, the method for fabricating the semiconductor device provided in this embodiment includes:

[0205] Step 2201: Provide a substrate, form a third semiconductor layer on the substrate, and form a first semiconductor layer and a second semiconductor layer on the side of the third semiconductor layer away from the substrate; and form a first gate penetrating the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounding the first gate, a second gate penetrating the second semiconductor layer and the third semiconductor layer, and a second gate insulating layer surrounding the second gate; wherein the first semiconductor layer includes a first source contact region and a first drain contact region, the second semiconductor layer includes a second source contact region and a second drain contact region, and the third semiconductor layer includes a third source contact region and a third drain contact region;

[0206] Step 2202: A first electrode is formed on the side of the first semiconductor layer away from the third semiconductor layer, contacting a first source contact region of the first semiconductor layer and a second electrode is formed on the side of the first semiconductor layer away from the third semiconductor layer, contacting a second source contact region of the second semiconductor layer and a fourth electrode is formed on the side of the second semiconductor layer away from the third semiconductor layer, the third electrode being electrically connected to the second electrode; and a fifth electrode is formed on the side of the third semiconductor layer away from the substrate, contacting a third drain contact region of the third semiconductor layer, the fifth electrode being electrically connected to the fourth electrode.

[0207] In an exemplary embodiment, the third semiconductor layer is formed on the substrate, and a first semiconductor layer and a second semiconductor layer are formed on the side of the third semiconductor layer away from the substrate; and a first gate is formed penetrating the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounds the first gate, a second gate is formed penetrating the second semiconductor layer and the third semiconductor layer, and the second gate insulating layer surrounding the second gate includes:

[0208] A third semiconductor layer is formed on the substrate.

[0209] A first insulating layer thin film is formed on the side of the third semiconductor layer away from the substrate;

[0210] A first channel film is formed on the side of the first insulating layer film away from the third semiconductor layer;

[0211] A first via and a second via are formed that penetrate the third semiconductor layer, the first insulating layer film, and the first channel film; a first gate insulating film and a first metal film are sequentially deposited on the sidewall of the first via to form the first gate insulating layer and the first gate; a second gate insulating film and a second metal film are sequentially deposited on the sidewall of the second via to form the second gate insulating layer and the second gate.

[0212] The first channel thin film is patterned to form the first semiconductor layer and the second semiconductor layer.

[0213] In an exemplary embodiment, the third semiconductor layer is formed on the substrate, and a first semiconductor layer and a second semiconductor layer are formed on the side of the third semiconductor layer away from the substrate; and a first gate is formed penetrating the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounds the first gate, a second gate is formed penetrating the second semiconductor layer and the third semiconductor layer, and the second gate insulating layer surrounding the second gate includes:

[0214] A third semiconductor layer is formed on the substrate;

[0215] A sacrificial layer thin film is formed on the side of the third semiconductor layer away from the substrate;

[0216] A first channel film is formed on the side of the sacrificial layer film away from the third semiconductor layer;

[0217] Patterning of the first channel thin film forms a support layer via that exposes the third semiconductor layer;

[0218] A third insulating film is deposited within the vias of the support layer to form a support layer;

[0219] The sacrificial layer film is etched, and a fourth insulating film is deposited at the location of the etched sacrificial layer film to form a third insulating layer disposed between the third semiconductor layer and the first channel film.

[0220] A first via and a second via are formed that penetrate the third semiconductor layer, the third insulating layer, and the first channel film; a first gate insulating film and a first metal film are sequentially deposited on the sidewall of the first via to form the first gate insulating layer and the first gate; a second gate insulating film and a second metal film are sequentially deposited on the sidewall of the second via to form the second gate insulating layer and the second gate.

[0221] The first channel thin film is patterned to form the first semiconductor layer and the second semiconductor layer.

[0222] The semiconductor device fabrication method provided in this disclosure allows for three-dimensional stacking, reducing the planar size of logic units and increasing device density. This fabrication method can be implemented using existing mature fabrication equipment, requires minimal modification to existing processes, is highly compatible with existing fabrication processes, is simple to implement, easy to execute, has high production efficiency, low production cost, and high yield.

[0223] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A third semiconductor layer disposed on a substrate, a first semiconductor layer and a second semiconductor layer disposed on the side of the third semiconductor layer away from the substrate, the first semiconductor layer including a first source contact region and a first drain contact region, the second semiconductor layer including a second source contact region and a second drain contact region, and the third semiconductor layer including a third source contact region and a third drain contact region; A first gate penetrating the first semiconductor layer and the third semiconductor layer, and a first gate insulating layer surrounding the first gate; A second gate penetrating the second semiconductor layer and the third semiconductor layer, and a second gate insulating layer surrounding the second gate; A first electrode that is in contact with a first source contact region of the first semiconductor layer, and a second electrode that is in contact with a first drain contact region of the first semiconductor layer; A third electrode that contacts the second source contact region of the second semiconductor layer and a fourth electrode that contacts the second drain contact region of the second semiconductor layer, wherein the third electrode is electrically connected to the second electrode; A fifth electrode is in contact with the third drain contact region of the third semiconductor layer, and the fifth electrode is electrically connected to the fourth electrode.

2. The semiconductor device according to claim 1, characterized in that, The materials of the third semiconductor layer, the first semiconductor layer, and the second semiconductor layer include polycrystalline silicon semiconductor materials or monocrystalline silicon semiconductor materials.

3. The semiconductor device according to claim 1, characterized in that, The first drain contact region is located on the side of the first gate near the second gate, and the second source contact region is located on the side of the second gate near the first gate.

4. The semiconductor device according to claim 1, characterized in that, The first semiconductor layer and the second semiconductor layer are disposed on the same layer.

5. The semiconductor device according to claim 1, characterized in that, The first electrode and the second electrode are disposed on the side of the first semiconductor layer away from the third semiconductor layer.

6. The semiconductor device according to claim 1, characterized in that, The third and fourth electrodes are disposed on the side of the second semiconductor layer away from the third semiconductor layer.

7. The semiconductor device according to claim 1, characterized in that, The fifth electrode is disposed on the side of the third semiconductor layer away from the substrate.

8. The semiconductor device according to claim 1, characterized in that, On a plane perpendicular to the substrate and perpendicular to the extension direction of the third semiconductor layer, the orthogonal projection of the first gate overlaps with the orthogonal projection of the second gate.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The third semiconductor layer is an NPN stacked structure, the first semiconductor layer is a PNP stacked structure, and the second semiconductor layer is a PNP stacked structure.

10. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A third semiconductor layer is formed on the substrate, and a first semiconductor layer and a second semiconductor layer are formed on the side of the third semiconductor layer away from the substrate; In addition, a first gate is formed penetrating the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounds the first gate, a second gate is formed penetrating the second semiconductor layer and the third semiconductor layer, and a second gate insulating layer surrounds the second gate; wherein the first semiconductor layer includes a first source contact region and a first drain contact region, the second semiconductor layer includes a second source contact region and a second drain contact region, and the third semiconductor layer includes a third source contact region and a third drain contact region; A first electrode is formed on the side of the first semiconductor layer away from the third semiconductor layer, contacting a first source contact region of the first semiconductor layer and a second electrode is formed on the side of the first semiconductor layer away from the third semiconductor layer, contacting a second source contact region of the second semiconductor layer and a fourth electrode is formed on the side of the second semiconductor layer away from the third semiconductor layer, the third electrode being electrically connected to the second electrode; and a fifth electrode is formed on the side of the third semiconductor layer away from the substrate, contacting a third drain contact region of the third semiconductor layer, the fifth electrode being electrically connected to the fourth electrode.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The third semiconductor layer is formed on the substrate, and a first semiconductor layer and a second semiconductor layer are formed on the side of the third semiconductor layer away from the substrate, a first gate is formed penetrating the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounds the first gate, a second gate is formed penetrating the second semiconductor layer and the third semiconductor layer, and the second gate insulating layer surrounding the second gate includes: A third semiconductor layer is formed on the substrate. A first insulating layer thin film is formed on the side of the third semiconductor layer away from the substrate; A first channel film is formed on the side of the first insulating layer film away from the third semiconductor layer; A first via and a second via are formed that penetrate the third semiconductor layer, the first insulating layer film, and the first channel film; a first gate insulating film and a first metal film are sequentially deposited on the sidewall of the first via to form the first gate insulating layer and the first gate; a second gate insulating film and a second metal film are sequentially deposited on the sidewall of the second via to form the second gate insulating layer and the second gate. The first channel thin film is patterned to form the first semiconductor layer and the second semiconductor layer.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that, The third semiconductor layer is formed on the substrate, and a first semiconductor layer and a second semiconductor layer are formed on the side of the third semiconductor layer away from the substrate, a first gate is formed penetrating the first semiconductor layer and the third semiconductor layer, a first gate insulating layer surrounds the first gate, a second gate is formed penetrating the second semiconductor layer and the third semiconductor layer, and the second gate insulating layer surrounding the second gate includes: A third semiconductor layer is formed on the substrate; A sacrificial layer thin film is formed on the side of the third semiconductor layer away from the substrate; A first channel film is formed on the side of the sacrificial layer film away from the third semiconductor layer; Patterning of the first channel thin film forms a support layer via that exposes the third semiconductor layer; A third insulating film is deposited within the vias of the support layer to form a support layer; The sacrificial layer film is etched, and a fourth insulating film is deposited at the location of the etched sacrificial layer film to form a third insulating layer disposed between the third semiconductor layer and the first channel film. A first via and a second via are formed that penetrate the third semiconductor layer, the third insulating layer, and the first channel film; a first gate insulating film and a first metal film are sequentially deposited on the sidewall of the first via to form the first gate insulating layer and the first gate; a second gate insulating film and a second metal film are sequentially deposited on the sidewall of the second via to form the second gate insulating layer and the second gate. The first channel thin film is patterned to form the first semiconductor layer and the second semiconductor layer.

13. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 9.

14. The electronic device according to claim 13, characterized in that, The electronic devices include smartphones, computers, tablets, artificial intelligence, wearable devices, or smart mobile terminals.

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