A multi-gate oxide dual work function super junction lateral diffusion metal oxide semiconductor

Abstract

The application discloses a multi-gate oxide double-function super-junction lateral diffusion metal oxide semiconductor, which mainly comprises a silicon substrate, a P-type drift concentration doped region, a super-junction drift region, a source region, a gate, and a drain region. The multi-gate oxide double-function gate is combined on a conductive channel of the super-junction lateral diffusion metal oxide semiconductor to form a new structure, so that the working frequency of the whole device is improved, and meanwhile, the on-resistance of the conductive channel is further reduced, so that the device has a lower on-resistance in the super-junction drift region, and the resistance of the whole current path is further reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a superjunction laterally diffused metal oxide semiconductor with multiple gate oxide duplex function. Background Technology

[0002] Laterally diffused metal-oxide semiconductor, also known as a lateral diode-diffused field-effect transistor (LDMOS), is a high-voltage device used in integrated circuits. LDMOS is a power device with a double-diffused structure. This technology involves implanting the same source / drain regions twice, with the first implantation having a higher concentration (typically 10⁻⁶). 15 cm -2 Arsenic (As) was injected at a lower concentration in another injection (typical injection dose 10). 13 cm -2 Boron (B) is implanted and then undergoes a high-temperature propagation process. Because boron diffuses faster than arsenic, it diffuses laterally further below the gate boundary, forming a channel with a concentration gradient. The channel length is determined by the difference in distance between these two lateral diffusions. By precisely controlling the diffusion time and temperature, the channel size of the device can be accurately controlled. To increase the breakdown voltage, a drift region exists between the active and drain regions. The drift region in LDMOS is a key design element for this type of device. The impurity concentration in the drift region is relatively low; therefore, when the LDMOS is connected to a high voltage, the drift region, being high-resistance, can withstand higher voltages.

[0003] As a voltage-controlled current-mode device, LDMOS has a large input impedance, resulting in low power consumption in drive applications and easy coupling with front-end circuits. Furthermore, due to its negative temperature characteristic and the lateral flow of charge carriers on the surface, LDMOS automatically evens out leakage current at higher temperatures, reducing the likelihood of hot spots and improving reliability. With the source, drain, and gate all located on the chip surface, LDMOS can be easily integrated with low-voltage signal circuits via internal well contacts or other means, making it ideal for use as a power output device in power chips.

[0004] For high-voltage devices, their characteristic "on" resistance and breakdown voltage are crucial to device performance. LDMOS devices are designed to reduce "on" resistance while still maintaining a high breakdown voltage. However, these two electrical parameters tend to have conflicting prerequisites. Summary of the Invention

[0005] In view of the problems and technical requirements of the existing technology, the purpose of this invention is to provide a superjunction laterally diffused metal oxide semiconductor with multiple gate oxide double function, which combines the gate of the multiple gate oxide double function on the conductive channel of the laterally diffused metal oxide semiconductor with superjunction structure, thereby reducing the impact of on-resistance.

[0006] To achieve the above objectives, the present invention employs the following technical solution:

[0007] A superjunction laterally diffused metal-oxide semiconductor with multiple gate oxide double function includes a silicon substrate, a P-type drift concentration doped region, a superjunction drift region, a source region, a gate region, and a drain region.

[0008] The source region consists of heavily doped P+ and N+ types;

[0009] The superjunction drift region consists of a structure group of pn junctions arranged perpendicularly between the source and drain regions;

[0010] The gate, composed of heavily doped P+ and N+ type regions, is close to the insulating layer and located directly above the gap between the source region and the superjunction drift region.

[0011] A conductive channel is formed between the P-type Drift concentration doped region and the highly N-doped polysilicon below the gate;

[0012] The drain region is composed of N+ type heavily doped regions;

[0013] The gate and drain regions are connected by a superjunction drift region.

[0014] The silicon substrate is a P-type epitaxial substrate, which is a hole structure of the semiconductor substrate doped with excess positive charge carriers.

[0015] The superjunction drift region has lightly doped drains added on both sides near the source region, with the lightly doped drain on the right side being larger than that on the left side, forming a low-voltage condition on the left and a high-voltage condition on the right.

[0016] Silicon dioxide layers are provided on both sides of the gate portion directly above the conductive channel. The thickness and width of the left silicon dioxide layer are smaller than those of the right silicon dioxide layer, but the heights are the same, and it is covered with a layer of metal silicide. The left silicon dioxide layer is directly above the P+ type of the gate, and the right silicon dioxide layer is directly above the N+ type of the gate.

[0017] The metal silicide and the P+ and N+ types of the gate are both surrounded by bias sidewalls, and a sidewall is surrounded on the outside of the bias sidewalls.

[0018] A lightly doped region is formed between the drain region and the conductive channel.

[0019] The source region, drift region, and drain region export settings are enabled.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] This invention discloses a multi-gate oxide double-function superjunction laterally diffused metal-oxide semiconductor. By combining the gate of the multi-gate oxide double-function superjunction with the conductive channel of the laterally diffused metal-oxide semiconductor to form a new structure, the overall operating frequency of the device is improved. At the same time, the influence of the on-resistance of the conductive channel is further reduced, resulting in a lower on-resistance in the superjunction drift region and a further reduction in the resistance of the entire current path.

[0022] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, the following lists specific implementation methods of the present invention.

[0023] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings, but this should not be construed as limiting the invention. Attached Figure Description

[0024] Figure 1 This is a structural diagram of the present invention;

[0025] Figure 2 This is a structural diagram of the gate portion of the present invention;

[0026] Wherein: 1. Silicon substrate; 2. P-class drift concentration doped region; 3. Superjunction drift region; 4. Source region; 5. Gate; 6. Drain region; 7. Lightly doped drain on the left; 8. Lightly doped drain on the right; 9. Silicon dioxide layer on the left; 10. Silicon dioxide layer on the right; 11. Metal silicide; 12. Bias sidewall; 13. Sidewall. Detailed Implementation

[0027] To facilitate understanding of the present invention, a more comprehensive description will be given below. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the present invention.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0029] The specific embodiments provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0030] like Figure 1 As shown, a superjunction lateral diffusion metal-oxide semiconductor with multiple gate oxide double function includes a silicon substrate 1, a P-type drift concentration doped region 2, a superjunction drift region 3, a source region 4, a gate region 5, and a drain region 6.

[0031] The source region consists of heavily doped P+ and N+ types;

[0032] The superjunction drift region consists of a structure group of pn junctions arranged perpendicularly between the source and drain regions;

[0033] In this application, the superjunction drift region, through the introduction of multiple lateral pn junctions, allows the charge in the superjunction drift region to be completely depleted before avalanche breakdown. As the voltage increases, the electric field distribution becomes relatively uniform, reducing the risk of breakdown due to concentration at a single point. By depleting the charge in the superjunction drift region, a lower electric field strength can be achieved at high voltages, thus improving the device's breakdown voltage.

[0034] The gate, composed of heavily doped P+ and N+ type regions, is close to the insulating layer and located directly above the gap between the source region and the superjunction drift region.

[0035] In this application, the process of gate control charge moving from the source region to the drain region increases the channel carrier migration rate and reduces the channel resistance by increasing the work function difference between highly P-doped polysilicon and highly N-doped polysilicon, thereby simultaneously improving the breakdown voltage of the device and further reducing its on-resistance.

[0036] A conductive channel is formed between the P-type Drift concentration doped region and the highly N-doped polysilicon below the gate;

[0037] In this application, when the gate voltage is greater than the turn-on voltage, electrons can be transported from the source region to the drain region.

[0038] The drain region is composed of N+ type heavily doped regions;

[0039] The gate and drain regions are connected by a superjunction drift region.

[0040] The silicon substrate uses a P-type epitaxial substrate, which is a hole structure of the semiconductor substrate doped with excess positive charge.

[0041] In this semiconductor, the substrate portion of the silicon substrate is P-type, where "P" stands for positive. Compared to the N-type substrate, the P-type substrate has different electron mobility properties. In the silicon substrate, electrons move from the hole structure rather than from free electrons.

[0042] like Figure 2 As shown, the superjunction drift region adds lightly doped drains on both sides near the source region, and the lightly doped drain 8 on the right side is larger than the lightly doped drain 7 on the left side, forming a low-voltage condition on the left and a high-voltage condition on the right.

[0043] Silicon dioxide layers are provided on both sides of the gate portion directly above the conductive channel. The thickness and width of the left silicon dioxide layer 9 are smaller than those of the right silicon dioxide layer 10, but the height is the same. A layer of metal silicide 11 is covered to reduce defects at the metal-silicon interface, lower the Schottky barrier, and drive dopant atoms (dopants) toward the interface.

[0044] The silicon dioxide layer on the left is directly above the P+ type of the gate, and the silicon dioxide layer on the right is directly above the N+ type of the gate.

[0045] The metal silicide and both sides of the P+ and N+ type gate are surrounded by bias sidewalls 12, and sidewalls 13 are surrounded on the outside of the bias sidewalls.

[0046] A lightly doped region is formed between the drain region and the conductive channel.

[0047] The source region, drift region, and drain region are set to conduction, i.e., metal electrodes, used to conduct voltage and control the function and use of the device.

[0048] The technical features described in the above examples can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above examples are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The examples described above merely illustrate embodiments of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and non-substantial improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A superjunction laterally diffused metal-oxide semiconductor with multiple gate oxide double function, characterized in that, It includes a silicon substrate (1), a P-type drift concentration doped region (2) located on the substrate, a superjunction drift region (3), a source region (4), a gate region (5), and a drain region (6); Among them, the source region (4) is composed of a P+ type heavily doped region and an N+ type heavily doped region; The superjunction drift region (3) is composed of P-type pillars and N-type pillars that are alternately arranged in the transverse direction of the device between the source and drain regions; The gate (5) is a single continuous polysilicon gate, which is divided into a P+ type heavily doped polysilicon segment near the source region and an N+ type heavily doped polysilicon segment near the drain region along the device lateral direction. The two segments have different work functions, and the gate is located directly above the gap between the source region and the superjunction drift region and close to the gate oxide layer. A conductive channel is formed between the P-type Drift concentration doped region (2) and below the gate; The drain region (6) is composed of N+ type heavily doped regions, and the gate and drain regions are connected through a superjunction drift region; The gate oxide layer covering the conductive channel includes a first silicon dioxide layer (9) located directly above the channel near the source region and a second silicon dioxide layer (10) near the drain region. The vertical height of the first silicon dioxide layer along the substrate normal is the same as that of the second silicon dioxide layer, but the lateral width and vertical thickness of the first silicon dioxide layer are both smaller than those of the second silicon dioxide layer. The first silicon dioxide layer is located directly below the P+ type polysilicon segment, and the second silicon dioxide layer is located directly below the N+ type polysilicon segment. The superjunction drift region has lightly doped drain regions on both sides near the source region. The lightly doped drain region (8) near the drain region has a larger lateral dimension than the lightly doped drain region (7) near the source region, so as to form a low-pressure condition on the source region side and a high-pressure condition on the drain region side. 2.The multi-gate oxide dual work function super junction lateral diffusion metal oxide semiconductor of claim 1, wherein, The silicon substrate (1) is a P-type epitaxial substrate, which is a hole structure of a semiconductor substrate doped with excess positive charge carriers. 3.The multi-gate oxide dual work function super junction lateral diffusion metal oxide semiconductor of claim 1, wherein, The gate P+ type polysilicon segment and N+ type polysilicon segment are covered with metal silicide (11), and the P+ type segment and N+ type segment are respectively wrapped with bias sidewall (12) and outer sidewall (13).

4. The multi-gate oxide dual work function super junction lateral diffusion metal oxide semiconductor of claim 1, wherein, A lightly doped region is formed between the drain region (6) and the conductive channel.

5. The multi-gate oxide dual work function super junction lateral diffusion metal oxide semiconductor of claim 1, wherein, The source region, superjunction drift region, and drain region are set to be active.

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