Gate driving device and electronic equipment
By connecting a switching unit and a resistor in parallel between the gate driving unit and the transistor gate, and utilizing the natural conduction of the switching unit under negative voltage, the problem of voltage drop and circuit damage caused by the Miller effect in SiC transistors is solved, achieving a simple and low-cost Miller effect suppression effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INVENTCHIP TECH CO LTD
- Filing Date
- 2019-12-30
- Publication Date
- 2026-07-21
AI Technical Summary
Existing gate drivers using SiC transistors exhibit a significant Miller effect, leading to excessively fast switching speeds, voltage spikes, and circuit damage, and there is a lack of effective suppression methods.
A switching unit and a resistor are connected in parallel between the gate driving unit and the transistor gate. The switching unit naturally conducts under negative voltage to avoid voltage drop. The transistor gate is directly driven by the switching unit, thus suppressing the Miller effect.
It effectively avoids voltage drop and circuit damage caused by the Miller effect in existing technologies, simplifies the structure, reduces costs, and improves system reliability and efficiency.
Smart Images
Figure CN117424585B_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese patent application filed on December 30, 2019, with application number 201911394606.7 and title "Gate driving device and electronic device". Technical Field
[0002] This disclosure relates to the field of integrated circuit technology, and in particular to a gate driving device and electronic device. Background Technology
[0003] Gate drivers are essential devices in power electronic systems such as power supplies and electric drives. They sit between the weak electrical signals processed by signal processing and the high-power electrical signals, converting weaker control signals into stronger drive signals to power high-power devices and complete energy conversion. More advanced gate drivers also have detection and protection functions to ensure the normal operation of the power electronic system. High-power power supplies driven by gate drivers typically use IGBTs (Insulated Gate Bipolar Transistors) and SiC FETs (Silicon Carbide Field-Effect Transistors). Because SiC has lower parasitic capacitance and on-resistance, power supplies using SiC can achieve higher efficiency and smaller size. With the maturity of SiC technology and the reduction in cost, the application of SiC is becoming increasingly widespread.
[0004] Due to the Miller effect (ME), conventional gate drivers need to provide negative voltage output or Miller clamping function to ensure reliable turn-off. However, since SiC has a faster switching speed, its Miller effect is more pronounced. Therefore, how to effectively suppress the Miller effect has become a major challenge. Summary of the Invention
[0005] In view of this, the present disclosure provides a gate driving device for driving a first transistor, the device comprising a gate driving unit, a first resistor, and a switching unit, wherein:
[0006] The drive output terminal of the gate drive unit is electrically connected to the first terminal of the first resistor and the first terminal of the switch unit, and the second terminal of the first resistor is electrically connected to the gate of the first transistor and the second terminal of the switch unit.
[0007] The drive output terminal of the gate drive unit is used to output a drive signal to drive the first transistor. When the drive signal is a negative voltage, the switch unit is in the on state, and the drive signal is transmitted to the gate of the first transistor through the switch unit.
[0008] In one possible implementation, when the drive signal is a positive voltage, the switching unit is in an off state, and the drive signal is transmitted to the gate of the first transistor through the first resistor.
[0009] In one possible implementation, the switching unit includes a second transistor and a third transistor, wherein:
[0010] The drain of the second transistor is electrically connected to the drive output terminal and the first terminal of the first resistor; the source of the second transistor is electrically connected to the source of the third transistor; the drain of the third transistor is electrically connected to the gate of the first transistor and the second terminal of the first resistor; the gates of the second transistor and the third transistor are grounded or receive a first voltage.
[0011] The drain of the second transistor is the first terminal of the switching unit, and the drain of the third transistor is the second terminal of the switching unit.
[0012] In one possible implementation, the switching unit includes a fourth transistor and a fifth transistor, wherein:
[0013] The source of the fourth transistor is electrically connected to the drive output terminal and the first terminal of the first resistor; the drain of the fourth transistor is electrically connected to the drain of the fifth transistor; the source of the fifth transistor is electrically connected to the gate of the first transistor and the second terminal of the first resistor; the gates of the fourth transistor and the fifth transistor are grounded or receive a second voltage.
[0014] The source of the fourth transistor is the first terminal of the switching unit, and the source of the fifth transistor is the second terminal of the switching unit.
[0015] In one possible implementation, the switching unit includes a sixth transistor and a first diode, wherein:
[0016] The drain of the sixth transistor is electrically connected to the drive output terminal and the first terminal of the first resistor; the source of the sixth transistor is electrically connected to the cathode of the first diode; the anode of the first diode is electrically connected to the gate of the first transistor and the second terminal of the first resistor; and the gate of the sixth transistor is grounded.
[0017] The drain of the sixth transistor is the first terminal of the switching unit, and the anode of the first diode is the second terminal of the switching unit.
[0018] In one possible implementation, the switching unit includes a seventh transistor and a second diode, wherein:
[0019] The source of the seventh transistor is electrically connected to the drive output terminal and the first terminal of the first resistor; the drain of the seventh transistor is electrically connected to the cathode of the second diode; the anode of the second diode is electrically connected to the gate of the first transistor and the second terminal of the first resistor; and the gate of the seventh transistor is grounded.
[0020] The drain of the seventh transistor is the first terminal of the switching unit, and the anode of the second diode is the second terminal of the switching unit.
[0021] In one possible implementation, the switching unit includes an eighth transistor and a third diode, wherein:
[0022] The negative terminal of the third diode is electrically connected to the drive output terminal and the first terminal of the first resistor, the positive terminal of the third diode is electrically connected to the source of the eighth transistor, the drain of the eighth transistor is electrically connected to the gate of the first transistor and the second terminal of the first resistor, and the gate of the eighth transistor is grounded.
[0023] The cathode of the third diode is the first terminal of the switching unit, and the drain of the eighth transistor is the second terminal of the switching unit.
[0024] In one possible implementation, the switching unit includes a ninth transistor and a fourth diode, wherein:
[0025] The negative terminal of the fourth diode is electrically connected to the drive output terminal and the first terminal of the first resistor, the positive terminal of the fourth diode is electrically connected to the drain of the ninth transistor, the source of the ninth transistor is electrically connected to the gate of the first transistor and the second terminal of the first resistor, and the gate of the ninth transistor is grounded.
[0026] The cathode of the fourth diode is the first terminal of the switching unit, and the source and drain of the ninth transistor are the second terminals of the switching unit.
[0027] In one possible implementation, the device further includes a first capacitor, a fifth diode, and a second resistor, and the drive output terminal includes a first drive output terminal and a second drive output terminal, wherein:
[0028] The first drive output terminal is electrically connected to the first terminal of the first capacitor, and the second drive output terminal is electrically connected to the second terminal of the first capacitor, the cathode of the fifth diode, the first terminal of the first resistor, and the first terminal of the switching unit.
[0029] The positive terminal of the fifth diode is electrically connected to the first terminal of the second resistor, and the second terminal of the second resistor is electrically connected to the second terminal of the first resistor, the second terminal of the switching unit, and the gate of the first transistor.
[0030] The voltage difference between the first drive output terminal and the second drive output terminal is the third voltage.
[0031] In one possible implementation, the drive output terminal includes a pull-up output terminal OTH and a pull-down output terminal OUTL. The pull-up output terminal OTH is used to output a high-level drive signal, and the pull-down output terminal OUTL is used to output a low-level drive signal. The pull-down output terminal OUTL is electrically connected to the first end of the first resistor and the first end of the switching unit.
[0032] According to another aspect of this disclosure, an electronic device is provided, the electronic device comprising:
[0033] The aforementioned gate driving device.
[0034] Various aspects of the embodiments of this disclosure can be achieved by configuring a switching unit in parallel with a first resistor. When the driving voltage output by the gate driving unit is negative, the switching unit can naturally conduct, and the first resistor is short-circuited. Therefore, the driving signal directly drives the gate of the first transistor through the switching unit. In this way, the embodiments of this disclosure can avoid the additional voltage drop caused by the first resistor when the gate driving unit outputs a negative voltage, thereby suppressing the Miller effect and protecting the circuit. Furthermore, the gate driver device proposed in the embodiments of this disclosure has a simple structure, low cost, and is easy to promote and utilize. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0035] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0036] Figure 1 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0037] Figure 2 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0038] Figure 3 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0039] Figure 4 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0040] Figure 5 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0041] Figure 6 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0042] Figure 7 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0043] Figure 8 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0044] Figure 9 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown. Detailed Implementation
[0045] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0046] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0047] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0048] Please see Figure 1 , Figure 1 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0049] like Figure 1 As shown, the device is used to drive the first transistor Q1. The device includes a gate driving unit 10, a first resistor R1, and a switching unit 20, wherein:
[0050] The drive output terminal OUT of the gate driving unit 10 is electrically connected to the first terminal of the first resistor R1 and the first terminal of the switching unit 20, and the second terminal of the first resistor R1 is electrically connected to the gate of the first transistor Q1 and the second terminal of the switching unit 20.
[0051] The drive output terminal OUT of the gate drive unit 10 is used to output a drive signal to drive the first transistor Q1. When the drive signal is a negative voltage, the switch unit 20 is in the on state, and the drive signal is transmitted to the gate of the first transistor Q1 through the switch unit 20.
[0052] Through the above-described device, this embodiment of the present disclosure sets the switching unit 20 in parallel with the first resistor R1. When the drive signal output by the output terminal OUT of the gate driving unit 10 is a negative voltage, the switching unit 20 can be turned on by the drive signal (naturally turned on, without the need for an additional control signal), and the first resistor R1 is short-circuited. Therefore, the drive signal directly drives the gate of the first transistor Q1 through the switching unit 20. In this way, this embodiment of the present disclosure can avoid the additional voltage drop caused by the first resistor R1 when the gate driving unit 10 outputs a negative voltage, thereby suppressing the Miller effect and protecting the circuit. Furthermore, the gate driver device proposed in this embodiment of the present disclosure has a simple structure for suppressing the Miller effect, requiring only one switching unit 20 to achieve the suppression of the Miller effect. It is low in cost and easy to promote and utilize. For existing gate driving circuits without Miller clamping function, only one switching unit 20 needs to be added to achieve the suppression of the Miller effect. Furthermore, the switching unit 20 proposed in this embodiment can be turned on naturally when driving the output negative voltage without the need for additional control signals. In contrast, related technologies generally add complex Miller clamping circuits to existing gate-level drive circuits, which usually require the addition of comparators, auxiliary switches, and control units. Moreover, related technologies require dedicated control signals or control logic to control the Miller clamping circuit, which is more complex and costly.
[0053] By connecting a first resistor R1 in series between the output terminal OUT of the gate driving unit 10 and the gate of the first transistor Q1, the present embodiment can adjust the turn-on and turn-off speed of the first transistor Q1, thereby avoiding problems such as switching ringing, excessive stress, and large interference caused by excessive switching speed.
[0054] In one example, when the driving signal is a negative voltage, the switching unit 20 is in a conducting state, which may include: the switching unit 20 being turned on by the driving signal, that is, when the driving signal is a negative voltage, the switching unit 20 is turned on by the driving signal. It can be seen that the embodiments of this disclosure can directly reuse the driving signal output by the gate driving unit 10 as the switching control signal of the switching unit 20, without needing to add an additional control unit or switching control signal to control the switching unit 20. This design can reduce costs and the complexity of the device.
[0055] In one possible implementation, when the drive signal is a positive voltage, the switching unit 20 is in an off state, and the drive signal is transmitted to the gate of the first transistor Q1 through the first resistor R1.
[0056] When the drive signal is a positive voltage, the switching unit 20 is designed to be in the off state. In this way, the switching unit 20 will not affect the drive of the first transistor Q1, nor will it affect the switching speed of the first transistor Q1. While maintaining system performance, the Miller effect can be reduced.
[0057] If the gate driving device proposed in this embodiment is not used, for example, if the switching unit 20 is not connected in parallel with the first resistor R1, the first transistor Q1 will experience transient current due to the Miller effect. If the gate driving unit 10 outputs a negative voltage driving signal, the voltage will further decrease after passing through the first resistor R1. This will cause a voltage spike at the gate of the first transistor Q1. When a positive voltage spike with a rapid increase appears at the drain of the first transistor Q1, it may cause the first transistor Q1 to be mis-turned on, thereby damaging the circuit. However, with the gate driving device in this embodiment, when the driving signal is negative, the switching unit 20 can be turned on by the negative driving signal. Therefore, the driving signal can be transmitted to the gate of the first transistor Q1 through the switching unit 20, thereby avoiding a further decrease in the voltage of the driving signal. In this way, the Miller effect can be suppressed, thereby protecting the circuit and system.
[0058] It should be noted that this disclosure does not limit the specific implementation of the gate driving unit 10. Those skilled in the art can choose according to their needs, as long as it can output a driving signal to control the conduction and disconnection of the first transistor Q1.
[0059] In one example, the first transistor Q1 can be a silicon carbide (SiC) transistor or an IGBT. This disclosure does not limit the specific type of the first transistor Q1 or its operating scenario.
[0060] The switching unit 20 can be implemented in a variety of ways. The following is an example of the possible implementations of the switching unit 20.
[0061] Please see Figure 2 , Figure 2 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0062] In one possible implementation, such as Figure 2 As shown, the switching unit 20 may include a second transistor Q2 and a third transistor Q3, wherein:
[0063] The drain of the second transistor Q2 is electrically connected to the drive output terminal OUT and the first terminal of the first resistor R1. The source of the second transistor Q2 is electrically connected to the source of the third transistor Q3. The drain of the third transistor Q3 is electrically connected to the gate of the first transistor Q1 and the second terminal of the first resistor R1. The gates of the second transistor Q2 and the third transistor Q3 are grounded or receive a first voltage.
[0064] The drain of the second transistor Q2 is the first terminal of the switching unit 20, and the drain of the third transistor Q3 is the second terminal of the switching unit 20.
[0065] When the drive output terminal OUT of the gate drive unit 10 outputs a negative drive signal, since the gates of the second transistor Q2 and the third transistor Q3 are grounded or connected to the first voltage, and their sources are connected, the second transistor Q2 and the third transistor Q3 can be turned on under the negative drive signal. In this way, the drive signal can be transmitted to the gate of the first transistor Q1 through the switching unit 20.
[0066] In one example, for the gate drive unit 10 with a minimum pull-down voltage of 0V, the gates of the second transistor Q2 and the third transistor Q3 must be higher than their threshold voltages to ensure normal turn-on when the output is low, thus suppressing the Miller effect. For example, for a commonly used 1V threshold voltage switch, the gate can be fixedly biased at a value greater than 1V, such as 2V. In this case, the first voltage can be greater than 1V.
[0067] In one example, the second transistor Q2 and the third transistor Q3 can be NMOS (N-Metal-Oxide-Semiconductor Field-Effect-Transistor).
[0068] like Figure 2 As shown, the second transistor Q2 and the third transistor Q3 are connected back to back. The switching unit 20 is realized through the back-to-back NMOS transistors. Since the NMOS transistors conduct when the gate-source voltage is greater than the threshold voltage, this switching unit 20 can conduct naturally when the gate drive unit 10 outputs a negative voltage without the need for additional control signals. Compared with related technologies, it is more efficient, simpler and lower in cost.
[0069] Please see Figure 3 , Figure 3 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0070] In one possible implementation, such as Figure 3As shown, the switching unit 20 includes a fourth transistor Q4 and a fifth transistor Q5, wherein:
[0071] The source of the fourth transistor Q4 is electrically connected to the drive output terminal OUT and the first terminal of the first resistor R1. The drain of the fourth transistor Q4 is electrically connected to the drain of the fifth transistor Q5. The source of the fifth transistor Q5 is electrically connected to the gate of the first transistor Q1 and the second terminal of the first resistor R1. The gates of the fourth transistor Q4 and the fifth transistor Q5 are grounded or receive a second voltage.
[0072] The source of the fourth transistor Q4 is the first terminal of the switching unit 20, and the source of the fifth transistor Q5 is the second terminal of the switching unit 20.
[0073] When the drive output terminal OUT of the gate drive unit 10 outputs a negative drive signal, since the gates of the fourth transistor Q4 and the fifth transistor Q5 are grounded or connected to the second voltage, and their drains are connected, the fourth transistor Q4 and the fifth transistor Q5 can be turned on under the negative drive signal. In this way, the drive signal can be transmitted to the gate of the first transistor Q1 through the switching unit 20.
[0074] In one example, for the gate drive unit 10 with a minimum pull-down voltage of 0V, the gates of the fourth transistor Q4 and the fifth transistor Q5 must be higher than their threshold voltages to ensure normal turn-on when the output is low, thus suppressing the Miller effect. For example, for a commonly used 1V threshold voltage switch, the gate can be fixedly biased at a value greater than 1V, such as 2V. In this case, the second voltage can be greater than 1V.
[0075] In one example, the fourth transistor Q4 and the fifth transistor Q5 can be NMOS transistors, and the fourth transistor Q4 and the fifth transistor Q5 are connected back to back. The switching unit 20 is implemented by the back-to-back NMOS transistors. Since the NMOS transistors conduct when the gate-source voltage is greater than the threshold voltage, this switching unit 20 can conduct naturally when the gate drive unit 10 outputs a negative voltage without the need for additional control signals. Compared with related technologies, it is more efficient, simpler, and lower in cost.
[0076] Please see Figure 4 , Figure 4 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0077] In one possible implementation, such as Figure 4 As shown, the switching unit includes a sixth transistor Q6 and a first diode D1, wherein:
[0078] The drain of the sixth transistor Q6 is electrically connected to the drive output terminal OUT and the first terminal of the first resistor R1. The source of the sixth transistor Q6 is electrically connected to the cathode of the first diode D1. The anode of the first diode D1 is electrically connected to the gate of the first transistor Q1 and the second terminal of the first resistor R1. The gate of the sixth transistor Q6 is grounded.
[0079] The drain of the sixth transistor Q6 is the first terminal of the switching unit 20, and the anode of the first diode D1 is the second terminal of the switching unit 20.
[0080] When the drive output terminal OUT of the gate drive unit 10 outputs a negative drive signal, since the gate of the sixth transistor Q6 is grounded, the sixth transistor Q6 can be turned on under the negative drive signal. In this way, the drive signal can be transmitted to the gate of the first transistor Q1 through the switching unit 20.
[0081] In one example, the sixth transistor Q6 can be an NMOS transistor. Since NMOS transistors conduct when the gate-source voltage is greater than the threshold voltage, this switching unit 20 can naturally conduct when the gate drive unit 10 outputs a negative voltage without the need for additional control signals. Furthermore, by connecting the first diode D1 to the sixth transistor Q6, the current of the first transistor Q1 can be prevented from flowing to the gate drive unit 10, thus protecting the device. Compared with related technologies, this is more efficient, simpler, and lower in cost.
[0082] Please see Figure 5 , Figure 5 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0083] In one possible implementation, such as Figure 5 As shown, the switching unit includes a seventh transistor Q7 and a second diode D2, wherein:
[0084] The source of the seventh transistor Q7 is electrically connected to the drive output terminal OUT and the first terminal of the first resistor R1. The drain of the seventh transistor Q7 is electrically connected to the cathode of the second diode D2. The anode of the second diode D2 is electrically connected to the gate of the first transistor Q1 and the second terminal of the first resistor R1. The gate of the seventh transistor Q7 is grounded.
[0085] The drain of the seventh transistor Q7 is the first terminal of the switching unit 20, and the anode of the second diode D2 is the second terminal of the switching unit 20.
[0086] When the drive output terminal OUT of the gate drive unit 10 outputs a negative drive signal, since the gate of the seventh transistor Q7 is grounded, the seventh transistor Q7 can be turned on under the negative drive signal. In this way, the drive signal can be transmitted to the gate of the first transistor Q1 through the switching unit 20.
[0087] In one example, the seventh transistor Q7 can be an NMOS transistor. Since an NMOS transistor conducts when the gate-source voltage is greater than the threshold voltage, this switching unit 20 can naturally conduct when the gate drive unit 10 outputs a negative voltage without the need for an additional control signal. Furthermore, by connecting the second diode D2 to the seventh transistor Q7, the current of the first transistor Q1 can be prevented from flowing to the gate drive unit 10, thus protecting the device. Compared with related technologies, this is more efficient, simpler, and lower in cost.
[0088] Please see Figure 6 , Figure 6 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0089] In one possible implementation, such as Figure 6 As shown, the switching unit includes an eighth transistor Q8 and a third diode D3, wherein:
[0090] The negative terminal of the third diode D3 is electrically connected to the drive output terminal OUT and the first terminal of the first resistor R1. The positive terminal of the third diode D3 is electrically connected to the source of the eighth transistor Q8. The drain of the eighth transistor Q8 is electrically connected to the gate of the first transistor Q1 and the second terminal of the first resistor R1. The gate of the eighth transistor Q8 is grounded.
[0091] The cathode of the third diode D3 is the first terminal of the switching unit 20, and the drain of the eighth transistor Q8 is the second terminal of the switching unit 20.
[0092] When the drive output terminal OUT of the gate drive unit 10 outputs a negative drive signal, since the gate of the eighth transistor Q8 is grounded, the eighth transistor Q8 can be turned on under the negative drive signal. In this way, the drive signal can be transmitted to the gate of the first transistor Q1 through the switching unit 20.
[0093] In one example, the eighth transistor Q8 can be an NMOS transistor. Since an NMOS transistor conducts when the gate-source voltage is greater than the threshold voltage, this switching unit 20 can naturally conduct when the gate drive unit 10 outputs a negative voltage without the need for an additional control signal. Furthermore, by connecting the third diode D3 to the eighth transistor Q8, the current of the first transistor Q1 can be prevented from flowing to the gate drive unit 10, thus protecting the device. Compared with related technologies, this is more efficient, simpler, and lower in cost.
[0094] Please see Figure 7 , Figure 7 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0095] In one possible implementation, such as Figure 7 As shown, the switching unit includes a ninth transistor Q9 and a fourth diode D4, wherein:
[0096] The negative terminal of the fourth diode D4 is electrically connected to the drive output terminal OUT and the first terminal of the first resistor R1. The positive terminal of the fourth diode D4 is electrically connected to the drain of the ninth transistor Q9. The source of the ninth transistor Q9 is electrically connected to the gate of the first transistor and the second terminal of the first resistor. The gate of the ninth transistor Q9 is grounded.
[0097] The cathode of the fourth diode D4 is the first terminal of the switching unit, and the source and drain of the ninth transistor Q9 are the second terminals of the switching unit.
[0098] When the drive output terminal OUT of the gate drive unit 10 outputs a negative drive signal, since the gate of the ninth transistor Q9 is grounded, the ninth transistor Q9 can be turned on under the negative drive signal. In this way, the drive signal can be transmitted to the gate of the first transistor Q1 through the switching unit 20.
[0099] The above describes possible implementations of the switching unit in the gate driving device. It should be understood that the above description is exemplary and should not be regarded as a limitation of this disclosure.
[0100] In one example, the ninth transistor Q9 can be an NMOS transistor. Since an NMOS transistor conducts when the gate-source voltage is greater than the threshold voltage, this switching unit 20 can naturally conduct when the gate drive unit 10 outputs a negative voltage without the need for an additional control signal. Furthermore, by connecting the fourth diode D4 to the ninth transistor Q9, the current of the first transistor Q1 can be prevented from flowing to the gate drive unit 10, thus protecting the device. Compared with related technologies, this is more efficient, simpler, and lower in cost.
[0101] Please see Figure 8 , Figure 8 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0102] In one possible implementation, such as Figure 8 As shown, the device may further include a first capacitor C1, a fifth diode D5, and a second resistor R2. The drive output terminal includes a first drive output terminal OUT1 and a second drive output terminal NEG, wherein:
[0103] The first drive output terminal OUT1 is electrically connected to the first terminal of the first capacitor C1, and the second drive output terminal NEG is electrically connected to the second terminal of the first capacitor C1, the cathode of the fifth diode D5, the first terminal of the first resistor R1, and the first terminal of the switching unit 20.
[0104] The positive terminal of the fifth diode D5 is electrically connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is electrically connected to the second terminal of the first resistor R1, the second terminal of the switching unit 20, and the gate of the first transistor Q1.
[0105] The voltage difference between the first drive output terminal OUT1 and the second drive output terminal NEG is the third voltage.
[0106] The second terminal of the first capacitor C1 can be used as the drive output terminal OUT.
[0107] This embodiment of the invention, by adding a fifth diode D5, a second resistor R2 connected in parallel with a first resistor R1, can regulate the conduction and turn-off of the first transistor Q1, thereby avoiding problems such as switching ringing, excessive stress, and excessive interference caused by fast switching speed.
[0108] This disclosure does not limit the specific magnitude of the voltage difference (third voltage) across the first capacitor C1. Those skilled in the art can set it as needed. By setting the first capacitor C1, the output drive signal can be made more stable.
[0109] Since the voltage difference across the first capacitor C1 is stable at the third voltage, when the first drive output terminal OUT1 changes, the voltage at the second drive output terminal NEG will change accordingly to maintain the voltage difference across the first capacitor C1 at the third voltage.
[0110] When the voltage output by the second drive output terminal NEG is negative, the switching unit 20 is turned on, thereby short-circuiting the first resistor R1.
[0111] Please see Figure 9 , Figure 9 A schematic diagram of a gate driving device according to an embodiment of the present disclosure is shown.
[0112] In one possible implementation, such as Figure 9 As shown, the drive output terminal OUT may include a pull-up output terminal OUTH and a pull-down output terminal OUTL. The pull-up output terminal OUTH is used to output a high-level drive signal, and the pull-down output terminal OUTL is used to output a low-level drive signal. The pull-down output terminal OUTL is electrically connected to the first end of the first resistor R1 and the first end of the switching unit 20.
[0113] In one example, such as Figure 9 As shown, the device may further include a fifth resistor R5, the first end of which is electrically connected to the drive output terminal OUTH, and the second end of which is electrically connected to the second end of the first resistor R1, the second end of the switching unit 20, and the gate of the first transistor.
[0114] The gate driving device proposed in this disclosure can eliminate the short-circuit risk of the Miller effect, enhance system reliability, reduce maintenance costs, and eliminate the negative compressive stress risk caused by the Miller effect, thereby enhancing system reliability. Using the device, faster switching speeds can be used, thereby improving working efficiency, reducing size, and increasing power.
[0115] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A gate driving device, characterized in that, The device is used to drive a first transistor, and the device includes a gate driving unit, a first resistor, and a switching unit, wherein: The drive output terminal of the gate drive unit is electrically connected to the first terminal of the first resistor and the first terminal of the switch unit, and the second terminal of the first resistor is electrically connected to the gate of the first transistor and the second terminal of the switch unit. The drive output terminal of the gate driving unit is used to output a drive signal to drive the first transistor. When the drive signal is a negative voltage, the switching unit is in the on state, and the drive signal is transmitted to the gate of the first transistor through the switching unit. The switching unit includes a sixth transistor and a first diode, wherein: the drain of the sixth transistor is electrically connected to the drive output terminal and a first terminal of the first resistor; the source of the sixth transistor is electrically connected to the cathode of the first diode; the anode of the first diode is electrically connected to the gate of the first transistor and a second terminal of the first resistor; the gate of the sixth transistor is grounded; the drain of the sixth transistor is the first terminal of the switching unit; and the anode of the first diode is the second terminal of the switching unit; or The switching unit includes a seventh transistor and a second diode, wherein: the source of the seventh transistor is electrically connected to the drive output terminal and the first terminal of the first resistor; the drain of the seventh transistor is electrically connected to the negative terminal of the second diode; the positive terminal of the second diode is electrically connected to the gate of the first transistor and the second terminal of the first resistor; the gate of the seventh transistor is grounded; the drain of the seventh transistor is the first terminal of the switching unit; and the positive terminal of the second diode is the second terminal of the switching unit; or The switching unit includes an eighth transistor and a third diode, wherein: the cathode of the third diode is electrically connected to the drive output terminal and the first terminal of the first resistor; the anode of the third diode is electrically connected to the source of the eighth transistor; the drain of the eighth transistor is electrically connected to the gate of the first transistor and the second terminal of the first resistor; the gate of the eighth transistor is grounded; the cathode of the third diode is the first terminal of the switching unit; and the drain of the eighth transistor is the second terminal of the switching unit; or The switching unit includes a ninth transistor and a fourth diode, wherein: the negative terminal of the fourth diode is electrically connected to the drive output terminal and the first terminal of the first resistor, the positive terminal of the fourth diode is electrically connected to the drain of the ninth transistor, the source of the ninth transistor is electrically connected to the gate of the first transistor and the second terminal of the first resistor, the gate of the ninth transistor is grounded, wherein the negative terminal of the fourth diode is the first terminal of the switching unit, and the source and drain of the ninth transistor are the second terminals of the switching unit.
2. The apparatus of claim 1, wherein, When the driving signal is a positive voltage, the switching unit is in the off state, and the driving signal is transmitted to the gate of the first transistor through the first resistor.
3. The apparatus of claim 1, wherein, The device further includes a first capacitor, a fifth diode, and a second resistor. The drive output terminal includes a first drive output terminal and a second drive output terminal, wherein: The first drive output terminal is electrically connected to the first terminal of the first capacitor, and the second drive output terminal is electrically connected to the second terminal of the first capacitor, the cathode of the fifth diode, the first terminal of the first resistor, and the first terminal of the switching unit. The positive terminal of the fifth diode is electrically connected to the first terminal of the second resistor, and the second terminal of the second resistor is electrically connected to the second terminal of the first resistor, the second terminal of the switching unit, and the gate of the first transistor. The voltage difference between the first drive output terminal and the second drive output terminal is the third voltage.
4. The apparatus of claim 1, wherein, The drive output terminal includes a pull-up output terminal OTH and a pull-down output terminal OUTL. The pull-up output terminal OTH is used to output a high-level drive signal, and the pull-down output terminal OUTL is used to output a low-level drive signal. The pull-down output terminal OUTL is electrically connected to the first end of the first resistor and the first end of the switching unit.
5. An electronic device, comprising: The electronic device includes: The gate driving device as described in any one of claims 1 to 4.