L1 norm minimization problem calculation circuit and image perception device

Abstract

The present application relates to a kind of L1 norm minimization problem computing circuit and image perception device. Including right inverse circuit, first projection circuit, derivation circuit, second projection circuit, first addition circuit, second addition circuit and third addition circuit, using right inverse circuit to calculate and obtain observation matching vector, using first projection circuit to calculate and obtain current state projection, according to sign function using derivation circuit to obtain gradient vector, using second projection circuit to calculate and obtain gradient projection, using addition circuit to process the above result, obtain the update direction of current state vector, then calculate the product of update direction and update step as the incremental vector of current state vector, update current state vector by the method of loop iteration, when incremental vector converges, current state vector is the recovery signal. Through sign function, the gradient calculation of L1 norm minimization problem is carried out, which greatly reduces the demand for operation resources.

Description

Technical Field

[0001] This invention relates to the fields of mathematical optimization, image processing, and integrated circuit design, and in particular to a computational circuit for minimizing the L1 norm problem and an image sensing device. Background Technology

[0002] Optimization problems play a crucial role in engineering applications such as automatic control, signal processing, and pattern recognition. Among these, the L1 norm is particularly important in blind source separation, face recognition, sparse representation, and compressed sensing signal recovery. Taking compressed sensing as an example, a signal x of length n is used to obtain an observation result y of length m through an m*n random observation matrix A, i.e.:

[0003] y = Ax

[0004] Where m < n, signal reconstruction, i.e., the problem of recovering x from the observed value y and the observation matrix A, is a system of underdetermined linear equations with m equations and n unknowns. This problem has infinitely many solutions, and the uniqueness of the solution cannot be guaranteed. Some scholars have pointed out that the sparse signal reconstruction problem is an inverse problem. When the random measurement matrix and the sparse basis satisfy the restricted isometry property (RIP) condition or the Uniform Uncertainty Principle (UUP), and the signal x is sufficiently sparse, it can be guaranteed that x can be uniquely and accurately recovered. That is, by adding a constraint to the underdetermined linear equation system to guarantee the sparsity of x, the problem can be transformed into a minimization problem of the L0 norm.

[0005] min||x||0

[0006] stAx=y

[0007] in, ||x||0 represents the number of all non-zero elements in x, thus the goal is to find the sparsest x that satisfies the equality constraints. However, minimizing the L0 norm is a combinatorial optimization problem, requiring the trying of all combinations to find the optimal solution, making it an NP-hard problem with a lack of fast and efficient solution methods. Some scholars have further discovered that when the observation matrix satisfies the RIP condition and the constraint equidistant constant is within a certain range, the L0 norm can be relaxed to the L1 norm, and the solutions of the two are equivalent, i.e.:

[0008] min||x||1

[0009] stAx=y

[0010] The L1 norm minimization problem is a convex optimization problem, which is easier to solve than other problems, thus leading to the emergence of a large number of optimization algorithms.

[0011] The Basis Pursuit (BP) algorithm is a practical optimization criterion. Essentially, it connects the L1 norm minimization problem with standard linear programming through variable substitution, allowing the problem to be solved using a standard linear programming solver. This algorithm only requires the dictionary to be linearly independent; atoms do not need to be orthogonal. The BP algorithm performs best when the observation matrix satisfies the RIP condition and is generally applicable to different types of signals. However, its runtime has no theoretical boundary, limiting its efficiency. Besides BP, there are many algorithms with polynomial computational complexity, such as the interior-point method, the augmented Lagrange method, the Lagrange dual method, and the gradient projection method. However, these algorithms still have a high computational cost and are difficult to implement in hardware for high-dimensional problems. To reduce implementation difficulty, some researchers have improved the dual ascent method for solving the augmented Lagrange problem by proposing the alternating direction multiplier method. This method decomposes the large-scale optimization problem into multiple small-scale subproblems for distributed solution, significantly reducing computational cost and implementation difficulty.

[0012] To meet the needs of real-time applications, researchers have proposed many solution methods based on recurrent neural networks. In particular, methods based on projective neural networks can effectively solve nonlinear optimization problems. By studying the dynamic behavior of recurrent neural networks, it is possible to make them converge stably to the optimal solution of the optimization problem. The convergence speed depends on the dynamic behavior and does not require repeated iterative calculations like traditional methods, making them suitable for real-time signal processing.

[0013] However, the traditional methods for solving the L1 norm minimization problem have the technical problem of high computational resource consumption. Summary of the Invention

[0014] Therefore, it is necessary to provide a circuit for calculating the L1 norm minimization problem and an image sensing device.

[0015] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0016] On the one hand, a computational circuit for the L1 norm minimization problem is provided, including a right inverse circuit, a first projection circuit, a calculation circuit, a second projection circuit, a first addition circuit, a second addition circuit, and a third addition circuit.

[0017] The input of the right inverse circuit is used to receive the current mapped from the compressed sensing observation results. The inputs of the first projection circuit and the calculation circuit are used to receive the voltage mapped from the current state vector of the signal to be recovered. The output of the calculation circuit is connected to the input of the second projection circuit. The input of the first adder circuit is connected to the outputs of the calculation circuit and the second projection circuit. The input of the second adder circuit is connected to the outputs of the first projection circuit and the first adder circuit. The input of the third adder circuit is connected to the outputs of the right inverse circuit and the second adder circuit. The output of the third adder circuit is used to output the voltage corresponding to the update direction of the current state vector.

[0018] The right inverse circuit is used to calculate the product of the right inverse of the observation matrix and the observation result to obtain the observation matching vector; the first projection circuit is used to calculate the product of the current state vector and the projection matrix to obtain the current state projection; the resultant circuit is used to calculate the partial derivative of the L1 norm of the current state vector with respect to each element according to the sign function to obtain the gradient vector; the second projection circuit is used to calculate the product of the gradient vector and the projection matrix to obtain the gradient projection; the first adder circuit is used to calculate the negative of the sum of the gradient vector and the gradient projection to obtain the orthogonal gradient component; the second adder circuit is used to calculate the negative of the sum of the current state projection and the orthogonal gradient component to obtain the gradient correction; the third adder circuit is used to calculate the negative of the sum of the observation matching vector and the gradient correction to obtain the update direction; the product of the update direction and the update step size is the increment vector of the current state vector. When the increment vector converges, the L1 norm minimization problem calculation circuit outputs the recovery signal.

[0019] On the other hand, an image sensing device is also provided, which is equipped with the aforementioned L1 norm minimization problem calculation circuit.

[0020] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0021] The aforementioned L1 norm minimization problem calculation circuit and image sensing device include a right inverse circuit, a first projection circuit, a calculating circuit, a second projection circuit, a first adder circuit, a second adder circuit, and a third adder circuit. The input terminal of the right inverse circuit is used to connect the current mapped by the compressed sensing observation result. The input terminals of the first projection circuit and the calculating circuit are respectively used to connect the voltage mapped by the current state vector of the signal to be recovered. The right inverse circuit is used to calculate the observation matching vector, the first projection circuit is used to calculate the current state projection, the calculating circuit is used to obtain the gradient vector according to the sign function, the second projection circuit is used to calculate the gradient projection, and then the adder circuit is used to process the above results to obtain the update direction of the current state vector. The product of the update direction and the update step size is then calculated as the increment vector of the current state vector. The current state vector is updated by a cyclic iterative method. When the increment vector converges, the current state vector is the solution to the L1 norm minimization problem, that is, the recovered signal is obtained.

[0022] By using a sign function to calculate the gradient for minimizing the L1 norm, the need to directly calculate the complex expression of the L1 norm is avoided, reducing the computational load of multiplication and summation; the circuit implementation is simplified, requiring only the determination of the positive or negative sign of the input, reducing the consumption of logic resources; and only the sign of the elements needs to be determined, reducing the computational complexity and greatly reducing the demand for computational resources.

[0023] Furthermore, due to their small size, low power consumption, and reconfigurability, memristors can be used to construct right-hand inverse circuits and projection circuits, resulting in a more compact circuit layout and reduced system size. Overall circuit power consumption can be reduced. Online circuit reconfiguration can be performed according to algorithm requirements, improving computational flexibility. Compared with digital computing circuits, they offer higher speed and lower power consumption. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a first schematic diagram of the structure of a computational circuit for the L1 norm minimization problem in one embodiment;

[0026] Figure 2 This is a schematic diagram of the right inverse circuit in one embodiment;

[0027] Figure 3 This is a schematic diagram of the structure of the first projection circuit in one embodiment;

[0028] Figure 4This is a schematic diagram of the conductive path in one embodiment;

[0029] Figure 5 This is a schematic diagram of the structure of the second projection circuit in one embodiment;

[0030] Figure 6 This is a second schematic diagram of the structure of the L1 norm minimization problem calculation circuit in one embodiment;

[0031] Figure 7 This is a schematic diagram of the original image and DCT coefficients in one embodiment, where (a) is the image corresponding to the handwritten digit 7, and (b) is the original DCT coefficient of the handwritten digit 7;

[0032] Figure 8 This is a schematic diagram of the image and DCT coefficients recovered using an L1 norm minimization problem calculation circuit in one embodiment, where (a) is the recovered image and (b) is the corresponding DCT coefficient;

[0033] Figure 9 This is a schematic diagram of an image and DCT coefficients recovered using the OMP algorithm in one embodiment, where (a) is the recovered image and (b) is the corresponding DCT coefficient. Detailed Implementation

[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0036] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first projection circuit may be referred to as a second projection circuit, and similarly, a second projection circuit may be referred to as a first projection circuit. Both the first projection circuit and the second projection circuit are projection circuits, but they are not the same projection circuit.

[0037] It is understood that the term "connection" in the following embodiments should be interpreted as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., transmit electrical signals or data to each other. Furthermore, terms such as "input terminal" and "output terminal" do not limit the corresponding component to having only one input terminal or output terminal; they can also have multiple similar input terminals or output terminals. Multiple sub-input / output ports can also be integrated into a single input / output port, depending on the port settings of the actual component being used.

[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0039] In the process of researching and implementing this application, the inventors pointed out that traditional methods such as the interior-point method or gradient projection method require a large number of derivative operations, and projection neural networks require a large number of matrix inversion and vector matrix projection calculations. When these calculations are implemented in DSPs (Digital Signal Processors) or FPGAs (Field Programmable Gate Arrays), they consume huge resources and are computationally expensive. Taking matrix inversion as an example, existing matrix inversion methods require QR decomposition, LU decomposition, or Cholesky decomposition of the matrix. On a DSP platform, inverting a 16th-order matrix based on QR decomposition requires 74,614 clock cycles, and inverting a 32nd-order matrix requires 10⁶ clock cycles.

[0040] The inventors of this application have discovered that the gradient calculation for the L1 norm minimization problem can be simplified by using a sign function, thereby greatly reducing the difficulty of circuit implementation. In addition, as a novel intelligent information device with small size, low power consumption and reconfigurability, memristors are very suitable for analog computing. Because memristors do not require a digital clock, their calculation results can be obtained in one step through circuit structure design.

[0041] Based on this, the present invention provides a computational circuit for the L1 norm minimization problem and an image sensing device, including a right inverse circuit, a first projection circuit, a calculating circuit, a second projection circuit, a first adder circuit, a second adder circuit, and a third adder circuit. The input terminal of the right inverse circuit is used to connect the current mapped by the compressed sensing observation result. The input terminals of the first projection circuit and the calculating circuit are respectively used to connect the voltage mapped by the current state vector of the signal to be recovered. The right inverse circuit is used to calculate the observation matching vector, the first projection circuit is used to calculate the current state projection, the calculating circuit is used to obtain the gradient vector according to the sign function, the second projection circuit is used to calculate the gradient projection, and then the adder circuit is used to process the above results to obtain the update direction of the current state vector. The product of the update direction and the update step size is then calculated as the increment vector of the current state vector. The current state vector is updated by a cyclic iterative method. When the increment vector converges, the current state vector is the solution to the L1 norm minimization problem, that is, the recovered signal is obtained.

[0042] By using a sign function to calculate the gradient for minimizing the L1 norm, the need to directly calculate the complex expression of the L1 norm is avoided, reducing the computational load of multiplication and summation; the circuit implementation is simplified, requiring only the determination of the positive or negative sign of the input, reducing the consumption of logic resources; and only the sign of the elements needs to be determined, reducing the computational complexity and greatly reducing the demand for computational resources.

[0043] Furthermore, due to their small size, low power consumption, and reconfigurability, memristors can be used to construct right-hand inverse circuits and projection circuits, resulting in a more compact circuit layout and reduced system size. Overall circuit power consumption can be reduced. Online circuit reconfiguration can be performed according to algorithm requirements, improving computational flexibility. Compared with digital computing circuits, they offer higher speed and lower power consumption.

[0044] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0045] In one embodiment, such as Figure 1 As shown in the figure, this application embodiment provides an L1 norm minimization problem calculation circuit 100, including: a right inverse circuit 11, a first projection circuit 12, a calculation circuit 13, a second projection circuit 14, a first addition circuit 15, a second addition circuit 16, and a third addition circuit 17.

[0046] The input terminal of the right inverse circuit 11 is used to receive the current mapped by the compressed sensing observation results. The input terminals of the first projection circuit 12 and the calculation circuit 13 are respectively used to receive the voltage mapped by the current state vector of the signal to be recovered. The output terminal of the calculation circuit 13 is connected to the input terminal of the second projection circuit 14. The input terminal of the first adder circuit 15 is connected to the output terminals of the calculation circuit 13 and the second projection circuit 14 respectively. The input terminal of the second adder circuit 16 is connected to the output terminals of the first projection circuit 12 and the first adder circuit 15 respectively. The input terminal of the third adder circuit 17 is connected to the output terminals of the right inverse circuit 11 and the second adder circuit 16 respectively. The output terminal of the third adder circuit 17 is used to output the voltage corresponding to the update direction of the current state vector.

[0047] The right inverse circuit 11 is used to calculate the negative of the product of the right inverse of the observation matrix and the observation result to obtain the observation matching vector; the first projection circuit 12 is used to calculate the negative of the product of the current state vector and the projection matrix to obtain the current state projection; the resultant circuit 13 is used to calculate the partial derivative of the L1 norm of the current state vector with respect to each element according to the sign function to obtain the gradient vector; the second projection circuit 14 is used to calculate the negative of the product of the gradient vector and the projection matrix to obtain the gradient projection; the first adder circuit 15 is used to calculate the negative of the sum of the gradient vector and the gradient projection to obtain the gradient orthogonal component; the second adder circuit 16 is used to calculate the negative of the sum of the current state projection and the gradient orthogonal component to obtain the gradient correction amount; the third adder circuit 17 is used to calculate the negative of the sum of the observation matching vector and the gradient correction amount to obtain the update direction; the product of the update direction and the update step size is the increment vector of the current state vector. When the increment vector converges, the L1 norm minimization problem calculation circuit 100 outputs the recovery signal.

[0048] It is understandable that this application utilizes the L1 norm minimization problem to compute the circuit 100, employing an iterative method to update the vector. When the iteration reaches stable convergence, the current state vector represents the optimal solution to the L1 norm minimization problem. The discretization of the vector update state equation can be expressed as:

[0049]

[0050] Intermediate quantity:

[0051] q = A T (AA T ) -1 y, P = A T (AA T ) -1 A;

[0052] Where k is the k-th iteration of the current state vector update, Δx k Let x be the current state vector. k The increment vector, g(x) k(x) represents the current state vector. k The update direction, λ k To update the step size, q is the negative of the observed matching vector, and A is the observation matrix. T Let represent the transpose of the observation matrix, y be the observation result from compressed sensing, P be the projection matrix, and I be the identity matrix with all diagonal elements set to 1. For vector x k The L1 norm of vector x k The gradient vector obtained by taking the partial derivatives of each element.

[0053] The current state vector x is an iterative state variable, which is 0 in the first run. Due to the existence of the increment vector Δx, the value of x will change with each iteration until the increment vector Δx converges. The x obtained at this point is the result of the recovered signal, which is the output of the L1 norm minimization problem calculation circuit 100. The convergence of the increment vector Δx can be defined as: in the update cycle of the current state vector x, the difference between two consecutive increment vectors Δx is less than a certain value.

[0054] Furthermore, the gradient vector The partial derivatives of the L1 norm of the vector with respect to each element xi in the current state vector are obtained by using the sign function. get:

[0055]

[0056] The gradient vector can be written as:

[0057] The right inverse circuit 11 can be constructed using a memristor array, operational amplifier, and transconductance amplifier module, as long as the observation matching vector -q can be obtained through calculation: -q = -A T (AA T ) -1 The input of the right inverse circuit 11 is used to connect the current y mapped by the compressed sensing observation result. Then, the product of the right inverse of the observation matrix and the observation result y is calculated to obtain the observation matching vector -q. For each observation result y, the observation matching vector -q only needs to be calculated once. The observation matching vector -q does not need to be changed during the update of the current state vector x.

[0058] The first projection circuit 12 can be constructed using a memristor array, an operational amplifier, and a transconductance amplifier module, as long as the current state projection -Px can be obtained through calculation: -Px = -A T (AA T ) -1Ax. The input terminal of the first projection circuit 12 is used to receive the voltage x mapped by the current state vector of the signal to be recovered, and then the product of the current state vector x and the projection matrix P is calculated to obtain the current state projection -Px. The current state projection -Px needs to be calculated once for each iteration update of the current state vector x.

[0059] Circuit 13 can be constructed using a comparator powered by two power supplies, a saturated operational amplifier, or a zero-crossing detector, as long as the gradient vector can be calculated. That's all: Find the voltage x at the input terminal of circuit 13 that is used to map the current state vector of the signal to be recovered, and then use the sign function to find the L1 norm of the current state vector for each element x. i The partial derivatives are used to obtain the gradient vector. The gradient vector needs to be calculated once for each iteration of the current state vector x.

[0060] The second projection circuit 14 can be constructed using a memristor array, an operational amplifier, and a transconductance amplifier module, as long as the gradient projection can be obtained through calculation. That's all: The second projection circuit 14 calculates the gradient vector output by the conductive circuit 13. Calculate the gradient vector The gradient projection is obtained by multiplying the gradient projection by the projection matrix P. The gradient projection needs to be calculated once for each iteration of the current state vector x.

[0061] The first adder circuit 15 can be constructed using adders, as long as the orthogonal gradient components can be obtained through calculation. That's all: The first adder circuit 15 calculates the gradient vector output by the conductivity circuit 13. Gradient projection output of the second projection circuit 14 The first adder circuit 15 is used to calculate the negative of the sum of the two components, thus obtaining the orthogonal gradient components. Each iteration of the current state vector x requires calculating the orthogonal gradient components.

[0062] The second adder circuit 16 can be constructed using adders, as long as the gradient correction can be calculated. That's it. The second adder circuit 16 projects the current state -Px output by the first projection circuit 12 and the gradient quadrature component output by the first adder circuit 15. The gradient correction is obtained by calculating the negative of the sum of the two using the second adder circuit 16. The gradient correction needs to be calculated once for each iteration of the current state vector x.

[0063] The third adder circuit 17 can be constructed using adders, as long as the update direction g(x) can be obtained through calculation: The third adder circuit 17 uses the observed matching vector -q output by the right inverse circuit 11 and the gradient correction amount output by the second adder circuit 16. The third adder circuit 17 is used to calculate the negative of the sum of the two, thus obtaining the update direction g(x). The update direction g(x) needs to be calculated once for each iteration of the current state vector x.

[0064] The simplification of taking the partial value of an element is equivalent to not considering x at all. i The subgradient at which x = 0 may cause some convergence values ​​in the state equation to be unstable. In practical applications, the update direction g(x) generated in each iteration needs to be multiplied by the coefficient λ of the convergence step size. k The incremental vector Δx of the current state vector is obtained, and those skilled in the art can set the coefficient λ that controls the convergence step size according to their needs. k This ensures that the fluctuation value is controlled within an acceptable range. Each iteration of the current state vector x requires calculating the increment vector Δx until Δx converges. The resulting x is the recovered signal, which is the output of the L1 norm minimization problem calculation circuit 100.

[0065] The L1 norm minimization problem calculation circuit 100 described above calculates the gradient of the L1 norm minimization problem by taking the sign function, which avoids the need to directly calculate the complex expression of L1 norm and reduces the amount of computation for multiplication and summation; it simplifies the circuit implementation, only requires determining the positive or negative sign of the input, which reduces the consumption of logic resources; it only requires taking the sign of the elements, which reduces the computational complexity and greatly reduces the demand for computing resources.

[0066] Furthermore, due to their small size, low power consumption, and reconfigurability, memristors can be used to construct right-hand inverse circuits and projection circuits, resulting in a more compact circuit layout and reduced system size. Overall circuit power consumption can be reduced. Online circuit reconfiguration can be performed according to algorithm requirements, improving computational flexibility. Compared with digital computing circuits, they offer higher speed and lower power consumption.

[0067] In one embodiment, such as Figure 2 As shown, the right inverse circuit 11 includes a first memristor array 111, M operational amplifier modules 112, a second memristor array 113, and N transconductance amplifier modules 114. The circuit structures of the first memristor array 111 and the second memristor array 113 are the same.

[0068] The first memristor array 111 includes M memristor subarrays 1111, each memristor subarray 1111 including N memristors; the first terminals of each memristor in each memristor subarray 1111 are connected, and the second terminals of each memristor in the same row in each memristor subarray 1111 are connected; the conductance values ​​of each memristor in the first memristor array 111 and the second memristor array 113 are obtained by mapping according to the element values ​​of the observation matrix.

[0069] The input terminals of the M memristor subarrays 1111 of the first memristor array 111 are respectively used to connect the current mapped by the observation results. The input terminals of the M operational amplifier modules 112 are respectively connected to the output terminals of the M memristor subarrays 1111 of the first memristor array 111. The output terminals of the M operational amplifier modules 112 are respectively connected to the input terminals of the M memristor subarrays 1131 of the second memristor array 113. The input terminals of the N transconductance amplifier modules 114 are respectively connected to the output terminals of each memristor in the same row of the second memristor array 113. The output terminals of the N transconductance amplifier modules 114 are respectively connected to the input terminals of each memristor in the same row of the first memristor array 111. The output terminal of the first memristor array 111 is used to output the observation matching vector.

[0070] It is understood that since the circuit structures of the first memristor array 111 and the second memristor array 113 are the same, the second memristor array 113 includes M memristor subarrays 1131, and each memristor subarray 1131 includes N memristors; the first terminals of each memristor in each memristor subarray 1131 are connected, and the second terminals of each memristor in the same row in each memristor subarray 1131 are connected.

[0071] In addition, each of the N transconductance amplification modules 114 includes a transconductance amplifier and a feedback resistor. The positive input terminal of the transconductance amplifier is connected to the first terminal of the feedback resistor, and the output terminal of the transconductance amplifier is connected to the second terminal of the feedback resistor.

[0072] The input terminal of the right inverse circuit 11 is used to connect the current y mapped from the compressed sensing observation results. When the M operational amplifier modules 112 are operating in a deep negative feedback state, the voltage virtual short at the non-inverting input terminal is 0, and the current virtual open is 0. According to Kirchhoff's laws, we can obtain:

[0073] -RAA T v+y=0;

[0074] Where R is the resistance value of the feedback resistor, R is a constant, A is the observation matrix, and v is the op-amp output voltage value of the operational amplifier module 112. Therefore, the op-amp output voltage value can be calculated as follows:

[0075]

[0076] Then the voltage vector output by the right inverse circuit 11 is:

[0077]

[0078] Therefore, the voltage vector output by the right inverse circuit 11 is the observed matching vector -q.

[0079] Operational amplifier module 112 ensures that the virtual short voltage and virtual open current at the non-inverting input are zero, satisfying Kirchhoff's laws. The transconductance amplifier in transconductance amplifier module 114 provides a virtual ground for the first memristor array 111, amplifies the current output from the first memristor array 111, and converts it into a voltage signal input to the second memristor array 113, ensuring that the input voltage and output current of both memristor arrays satisfy I = U * G (G is an A). T The relationship between the corresponding conductance values ​​is used to realize the multiplication operation of the second memristor array 113. The value of the feedback resistor R can adjust the amplification factor. In this calculation circuit, all Rs are kept consistent, that is, the amplification factor is the same.

[0080] Compared with digital computing, the aforementioned right inverse circuit 11 has a high degree of computational parallelism, can complete matrix operations in nanoseconds, and has a fast response speed; the operation is based on changes in physical quantities, does not require repeated charging and discharging, and the power consumption can be several orders of magnitude lower than that of digital circuits; it can use the same integrated circuit technology as digital circuits to achieve large-scale integration, and the array size can be expanded to thousands of orders; the calculation is based on continuous changes in physical quantities, and the numerical accuracy is higher than that of digital computers; compared with digital computers, it is smaller in size and can be applied to fields with high space requirements; it has a certain tolerance to noise and the calculation is stable and reliable.

[0081] In one embodiment, such as Figure 3 As shown, the first projection circuit 12 includes a projection right inverse circuit 121 and a third memristor array 122; the projection right inverse circuit 121 has the same structure as the right inverse circuit 11, and the third memristor array 122 has the same circuit structure as the first memristor array 111.

[0082] The input terminal of the third memristor array 122 is used to connect the voltage of the current state vector mapping. The output terminals of the M memristor subarrays 1221 of the third memristor array 122 are respectively connected to the input terminals of the projection right inverse circuit 121. The output terminal of the projection right inverse circuit 121 is used to output the current state projection.

[0083] It is understood that since the projection right inverse circuit 121 has the same structure as the right inverse circuit 11, the projection right inverse circuit 121 includes a first memristor array 1211, M operational amplifier modules 1212, a second memristor array 1213, and N transconductance amplifier modules 1214. The circuit structures of the first memristor array 1211 and the second memristor array 1213 are the same. The first memristor array 1211 includes M memristor subarrays, and each memristor subarray includes N memristors; the first terminals of each memristor in each memristor subarray are connected, and the second terminals of each memristor in the same row in each memristor subarray are connected.

[0084] Since the circuit structures of the first memristor array 1211 and the second memristor array 1213 are identical, the second memristor array 1213 includes M memristor subarrays, each of which includes N memristors. The first terminals of each memristor in each memristor subarray are connected, and the second terminals of memristors in the same row within each memristor subarray are connected. The conductance values ​​of each memristor in the first memristor array 1211 and the second memristor array 1213 are obtained by mapping the element values ​​of the observation matrix.

[0085] The input terminals of the M operational amplifier modules 1212 are connected one-to-one with the output terminals of the M memristor subarrays of the first memristor array 1211. The output terminals of the M operational amplifier modules 1212 are connected one-to-one with the input terminals of the M memristor subarrays of the second memristor array 1213. The input terminals of the N transconductance amplifier modules 1214 are connected one-to-one with the output terminals of each memristor in the same row of the second memristor array 1213. The output terminals of the N transconductance amplifier modules 1214 are connected one-to-one with the input terminals of each memristor in the same row of the first memristor array 1211.

[0086] Since the third memristor array 122 has the same circuit structure as the first memristor array 111, the third memristor array 122 includes M memristor subarrays 1221, and each memristor subarray 1221 includes N memristors. The first terminals of each memristor in each memristor subarray 1221 are connected, and the second terminals of each memristor in the same row in each memristor subarray 1221 are connected. The conductance value of each memristor in the third memristor array 1221 is obtained by mapping the element values ​​of the observation matrix.

[0087] Projection matrix P = A T (AA T ) -1 A. It can be seen that the product of the projection matrix P and the current state vector x only needs to be multiplied by A on the left before the right inverse operation. TTherefore, since the voltage virtual short at the input current of the projection right inverse circuit 121 is 0, the output current of the third memristor array 122 can be directly used as the input current of the projection right inverse circuit 121. The input terminal of the third memristor array 122 is used to connect the voltage x mapped by the current state vector. Therefore, the output current of the third memristor array 122 is: y = Ax, and the output voltage vector of the projection right inverse circuit 121 is:

[0088]

[0089] That is, the right inverse circuit 121 outputs the current state projection -Px.

[0090] Compared with digital computing, the first projection circuit 12 has high computational parallelism, can complete matrix operations in nanoseconds, and has a fast response speed; the operation is based on changes in physical quantities, does not require repeated charging and discharging, and the power consumption can be several orders of magnitude lower than that of digital circuits; it can use the same integrated circuit technology as digital circuits to achieve large-scale integration, and the array size can be expanded to thousands of orders; the calculation is based on continuous changes in physical quantities, and the numerical accuracy is higher than that of digital computers; compared with digital computers, it is smaller in size and can be applied to fields with high space requirements; it has a certain tolerance to noise and the calculation is stable and reliable.

[0091] In one embodiment, such as Figure 4 As shown, the conductive circuit 13 includes N comparators powered by dual power supplies; the input terminals of the N comparators are respectively used to connect to the voltage mapped by the current state vector, and the output terminals of the N comparators are respectively used to output the gradient vector.

[0092] It is understandable that the formula for calculating the partial derivative of the L1 norm of the objective function is as follows:

[0093]

[0094] When x i When x ≠ 0, its partial derivative can be determined simply by taking the sign of the element; when x ≠ 0, its partial derivative can be determined by taking the sign of the element. i When x ≠ 0, the target L1 norm function is not differentiable at that point; secondly, the gradient is in the interval [-1, 1], and the calculation is relatively complex. To reduce circuit complexity, this application uses each element x... i Use a dual-supply comparator when the input element x i The output is VDD when the time is positive and -VDD when the time is negative. This simplified differentiation process is equivalent to not considering x. i The subgradient when ≠ 0 may cause some convergence values ​​in the state equation to be unstable. In practical applications, those skilled in the art can set the coefficient λ that controls the convergence step size according to requirements. kThis ensures that the fluctuation value is controlled within an acceptable range. Following the rules of mapping specific values ​​and current to voltage, setting VDD to the value of 1 after voltage mapping enables the sign-reversal circuit. In this circuit, with n elements, N parallel comparators are needed. The inputs of the N comparators are respectively connected to the voltage x mapped from the current state vector, and the outputs of the N comparators are respectively used to output the gradient vector.

[0095] The above-mentioned circuit 13 has a simple structure and is easy to integrate with other circuits. The number of comparators can be expanded according to the number of input elements. It has a fast calculation speed with a nanosecond-level response time. It is suitable for different input quantities and the corresponding VDD value can be flexibly set. It has low power consumption and does not require complex calculations but relies solely on comparison.

[0096] In one embodiment, such as Figure 5 As shown, the second projection circuit 14 has the same structure as the first projection circuit 12.

[0097] It can be understood that the second projection circuit 14 includes a projection right inverse circuit 141 and a third memristor array 142; the projection right inverse circuit 141 has the same structure as the right inverse circuit 11, and the third memristor array 142 has the same circuit structure as the first memristor array 111.

[0098] The input terminal of the third memristor array 142 is used to connect the gradient vector. The outputs of the M memristor subarrays 1421 of the third memristor array 142 are connected one-to-one with the inputs of the projection right inverse circuit 141. The output of the projection right inverse circuit 141 is used to output gradient projection.

[0099] The gradient vector is connected to the input terminal of the third memristor array 142. The current output by the third memristor array 142 is: The output voltage vector of the projection right inverse circuit 141 is:

[0100]

[0101] That is, the right inverse projection circuit 141 outputs gradient projection.

[0102] Compared with digital computing, the aforementioned second projection circuit 14 has high computational parallelism, can complete matrix operations in nanoseconds, and has a fast response speed; the operation is based on changes in physical quantities, does not require repeated charging and discharging, and its power consumption can be several orders of magnitude lower than that of digital circuits; it can use the same integrated circuit technology as digital circuits to achieve large-scale integration, and the array size can be expanded to thousands of orders; the calculation is based on continuous changes in physical quantities, and the numerical accuracy is higher than that of digital computers; compared with digital computers, it is smaller in size and can be applied to fields with high space requirements; it has a certain tolerance to noise and the calculation is stable and reliable.

[0103] In one embodiment, the first adder circuit 15 includes N independent first adders; the first input terminals of the N first adders are respectively used to input gradient vectors, the second input terminals of the N first adders are respectively used to input gradient projections, and the output terminals of the N first adders are respectively used to output orthogonal gradient components.

[0104] It is understandable that the first adder circuit 15 uses the gradient vector output by the calculating circuit 13. Gradient projection output of the second projection circuit 14 The first adder circuit 15 is used to calculate the negative of the sum of the two components, thus obtaining the orthogonal gradient components. Each first adder operates on a gradient vector element and a gradient projection element respectively to obtain the orthogonal gradient component of that element. Each first adder can be constructed by those skilled in the art based on common knowledge in the field. The input and output voltage relationship of each first adder is as follows:

[0105]

[0106] V o =-(V i1 +V i2 );

[0107] Among them, V i1 and V i2 There are two input voltages, Rs is the resistance, and V0 is the output voltage.

[0108] Therefore, by performing parallel operations on N first adders, the gradient vector of the input can be determined. and gradient projection Simultaneously calculate all orthogonal gradient components.

[0109]

[0110] The aforementioned first adder circuit 15 has a fast calculation speed, and multiple first adders can operate in parallel, which greatly improves the calculation speed; it can process more data per unit time and achieve higher computing throughput; each first adder works independently, with high resource utilization and avoids waiting and idling of a single first adder.

[0111] In one embodiment, the second adder circuit 16 includes N independent second adders; the first input terminals of the N second adders are respectively used to input the current state projection, the second input terminals of the N second adders are respectively used to input the gradient orthogonal components, and the output terminals of the N second adders are respectively used to output the gradient correction amount.

[0112] It can be understood that the second adder circuit 16 projects the current state -Px output by the first projection circuit 12 and the gradient orthogonal component output by the first adder circuit 15. The second adder circuit 16 is used to calculate the negative of the sum of the two, thereby obtaining the gradient correction amount. The calculation process of the second adder circuit 16 can be understood in the same way as the calculation process of the first adder circuit 15, and will not be repeated here.

[0113] The aforementioned second adder circuit 16 has a fast calculation speed, and multiple second adders can operate in parallel, which greatly improves the calculation speed; it can process more data per unit time and achieve higher computing throughput; each second adder works independently, with high resource utilization and avoids waiting and idling of a single second adder.

[0114] In one embodiment, the third adder circuit includes N independent third adders; the first input terminals of the N third adders are respectively used to input the observation matching vector, the second input terminals of the N third adders are respectively used to input the gradient correction amount, and the output terminals of the N third adders are respectively used to output the update direction.

[0115] It can be understood that the third adder circuit 17 is based on the observation matching vector -q output by the right inverse circuit 11 and the gradient correction amount output by the second adder circuit 16. The third adder circuit 17 is used to calculate the opposite of the sum of the two, thereby obtaining the update direction g(x). The calculation process of the third adder circuit 17 can be understood in the same way as the calculation process of the first adder circuit 15, and will not be repeated here.

[0116] The aforementioned third adder circuit 17 has a fast calculation speed, and multiple third adders can operate in parallel, which greatly improves the calculation speed; it can process more data per unit time and achieve higher computing throughput; each third adder works independently, with high resource utilization and avoids waiting and idling of a single third adder.

[0117] In some embodiments, to more intuitively and comprehensively illustrate the L1 norm minimization problem calculation circuit 100 described above, the following are application examples of the L1 norm minimization problem calculation circuit 100. It should be noted that the implementation examples given in this specification are merely illustrative and not the only limitation on specific implementation examples of the present invention. Those skilled in the art can use the above-described L1 norm minimization problem calculation circuit 100 based on the illustrative implementation examples provided by the present invention to reduce computational resource consumption and improve computational speed.

[0118] like Figure 6 As shown, the number of input / output ports for each module is exemplified by m=2 and n=3. The two current sources at the top represent the input after the compressed sensing observation vector y is mapped to current values; this input / output does not need to be changed during the iterative process. The three voltage sources at the bottom left represent the current state vector x. k The three elements are mapped to the input voltage value. At this time, the rightmost output voltage signal of the circuit is the update direction g(x). Multiplying it by the iteration step size yields the increment vector Δx. k Thus, the new current state vector x is calculated. k+1 This process is repeated until the increment vector converges. At this point, the value of the current state vector is the solution to the corresponding L1 norm minimization problem.

[0119] To further verify the beneficial effects of the L1 norm minimization problem computation circuit proposed in this invention, a 32*32 pixel minimization dataset (Modified National Institute of Standards and Technology dataset) handwritten digit dataset was used for testing. First, the handwritten digit images were compressed sensing by 40%, i.e., n = 1024, m = floor(0.4 * 1024) = 409, and matrix A was an m x n random matrix generated by MATLAB. After obtaining the compressed sensing output signal y, the compressed sensing reconstruction problem was solved using the designed circuit with Discrete Cosine Transform (DCT) as the sparse basis, according to the method described in this application. To compare the performance with the traditional Orthogonal Matching Pursuit (OMP) algorithm, the compressed signal was simultaneously recovered using the proposed method and the OMP algorithm, and the performance was compared. The Mean Squared Error (MSE), commonly used in the literature, was used as an indicator to measure the similarity between the recovered image x' and the original image x; the smaller the MSE, the closer it is to the original image.

[0120] We first selected handwritten digits 1, 2, and 7 for verification. The original DCT coefficients and their corresponding images for the handwritten digit 7, the DCT coefficients and their corresponding images recovered using the method proposed in this application, and the DCT coefficients and their corresponding images recovered using the OMP algorithm are shown below. Figures 7-9 As shown in the figure. The MSE comparison of the three images is shown in Table 1. In addition, the above recovery performance comparison experiment was repeated at a compression rate of 20%, and the comparison results are also given in Table 1.

[0121]

[0122] Table 1: Performance Comparison of MES between this application and the OMP algorithm

[0123] It is evident that the method proposed in this application is efficient and simple, and the MSE performance is improved compared to the OMP algorithm.

[0124] In one embodiment, the present invention provides an image sensing device, including the L1 norm minimization problem calculation circuit 100 provided in any of the above embodiments.

[0125] It is understood that the circuit structure in each embodiment of the image sensing device can be understood by referring to the corresponding circuit structure in each embodiment of the L1 norm minimization problem calculation circuit 100, and will not be repeated here or in the following text.

[0126] Specifically, the image sensing device may be, but is not limited to, a computational image compression device, an image noise reduction device, an image feature extraction device, an image recognition device, or an image restoration device. In addition to the L1 norm minimization problem calculation circuit 100, the aforementioned image sensing device may also include other necessary components not mentioned above. The specific components can be understood by referring to the existing structural components of various image sensing devices in the field.

[0127] The aforementioned image sensing device calculates the gradient for minimizing the L1 norm by using a sign function, avoiding the need to directly calculate the complex expression of the L1 norm and reducing the computational load of multiplication and summation. It simplifies the circuit implementation, requiring only the determination of the positive or negative sign of the input, thus reducing the consumption of logic resources. It only requires taking the sign of the elements, reducing computational complexity and significantly reducing the demand for computational resources.

[0128] Furthermore, due to their small size, low power consumption, and reconfigurability, memristors can be used to construct right-hand inverse circuits and projection circuits, resulting in a more compact circuit layout and reduced system size. Overall circuit power consumption can be reduced. Online circuit reconfiguration can be performed according to algorithm requirements, improving computational flexibility. Compared with digital computing circuits, they offer higher speed and lower power consumption.

[0129] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0130] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A computational circuit for the L1 norm minimization problem, characterized in that, It includes a right inverse circuit, a first projection circuit, a conductivity circuit, a second projection circuit, a first adder circuit, a second adder circuit, and a third adder circuit; The input terminal of the right inverse circuit is used to receive the current mapped by the compressed sensing observation result. The input terminals of the first projection circuit and the calculation circuit are respectively used to receive the voltage mapped by the current state vector of the signal to be recovered. The output terminal of the calculation circuit is connected to the input terminal of the second projection circuit. The input terminal of the first adder circuit is connected to the output terminals of the calculation circuit and the second projection circuit, respectively. The input terminal of the second adder circuit is connected to the output terminals of the first projection circuit and the first adder circuit, respectively. The input terminal of the third adder circuit is connected to the output terminals of the right inverse circuit and the second adder circuit, respectively. The output terminal of the third adder circuit is used to output the voltage corresponding to the update direction of the current state vector. The right inverse circuit is used to calculate the product of the right inverse of the observation matrix and the observation result to obtain the observation matching vector; the first projection circuit is used to calculate the product of the current state vector and the projection matrix to obtain the current state projection; the gradient circuit is used to calculate the partial derivative of the L1 norm of the current state vector with respect to each element according to the sign function to obtain the gradient vector. The second projection circuit is used to calculate the product of the gradient vector and the projection matrix to obtain the gradient projection; The first adder circuit is used to calculate the negative of the sum of the gradient vector and the gradient projection to obtain the orthogonal gradient component. The second adder circuit is used to calculate the negative of the sum of the current state projection and the orthogonal gradient component to obtain the gradient correction amount. The third adder circuit is used to calculate the negative of the sum of the observation matching vector and the gradient correction amount to obtain the update direction. The product of the update direction and the update step size is the increment vector of the current state vector. When the increment vector converges, the L1 norm minimization problem calculation circuit outputs a recovery signal.

2. The L1 norm minimization problem calculation circuit according to claim 1, characterized in that, The right inverse circuit includes a first memristor array, M operational amplifier modules, a second memristor array, and N transconductance amplifier modules. The circuit structures of the first memristor array and the second memristor array are the same. The first memristor array includes M memristor subarrays, each memristor subarray including N memristors; the first terminals of each memristor in each memristor subarray are connected, and the second terminals of each memristor in the same row in each memristor subarray are connected; the conductance value of each memristor in the first memristor array and the second memristor array is obtained by mapping according to the element values ​​of the observation matrix; The input terminals of the M memristor subarrays of the first memristor array are respectively used to connect to the current mapped by the observation result. The input terminals of the M operational amplifier modules are respectively connected to the output terminals of the M memristor subarrays of the first memristor array. The output terminals of the M operational amplifier modules are respectively connected to the input terminals of the M memristor subarrays of the second memristor array. The input terminals of the N transconductance amplifier modules are respectively connected to the output terminals of each memristor in the same row of the second memristor array. The output terminals of the N transconductance amplifier modules are respectively connected to the input terminals of each memristor in the same row of the first memristor array. The output terminal of the first memristor array is used to output the observation matching vector.

3. The L1 norm minimization problem calculation circuit according to claim 2, characterized in that, The first projection circuit includes a projection right inverse circuit and a third memristor array; the projection right inverse circuit has the same structure as the right inverse circuit, and the third memristor array has the same circuit structure as the first memristor array. The input terminal of the third memristor array is used to connect to the voltage mapped by the current state vector. The output terminals of the M memristor subarrays of the third memristor array are respectively connected to the input terminal of the projection right inverse circuit. The output terminal of the projection right inverse circuit is used to output the projection of the current state.

4. The L1 norm minimization problem calculation circuit according to claim 1, characterized in that, The circuit for determining conductivity includes N comparators powered by dual power supplies; The input terminals of the N comparators are respectively used to receive the voltage mapped by the current state vector, and the output terminals of the N comparators are respectively used to output the gradient vector.

5. The L1 norm minimization problem calculation circuit according to claim 3, characterized in that, The second projection circuit has the same structure as the first projection circuit.

6. The L1 norm minimization problem calculation circuit according to claim 1, characterized in that, The first adder circuit includes N independent first adders; The first input terminals of the N first adders are respectively used to input the gradient vector, the second input terminals of the N first adders are respectively used to input the gradient projection, and the output terminals of the N first adders are respectively used to output the orthogonal components of the gradient.

7. The L1 norm minimization problem calculation circuit according to claim 1, characterized in that, The second adder circuit includes N independent second adders; The first input terminals of the N second adders are respectively used to connect to the current state projection, the second input terminals of the N second adders are respectively used to connect to the gradient orthogonal components, and the output terminals of the N second adders are respectively used to output the gradient correction amount.

8. The L1 norm minimization problem calculation circuit according to claim 1, characterized in that, The third adder circuit includes N independent third adders; The first input terminals of the N third adders are respectively used to input the observation matching vector, the second input terminals of the N third adders are respectively used to input the gradient correction amount, and the output terminals of the N third adders are respectively used to output the update direction.

9. An image sensing device, characterized in that, Includes a computational circuit for the L1 norm minimization problem according to any one of claims 1-8.

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