Transistor and method of manufacturing the same, electronic device

Abstract

A transistor and its manufacturing method, and an electronic device thereof, the transistor comprising: an active post disposed on a substrate, the active post including a first contact terminal, a channel region, and a second contact terminal sequentially disposed along a direction away from the substrate, the first contact terminal being made of metal silicide; a bit line disposed between the substrate and the first contact terminal, the bit line being electrically connected to the first contact terminal; a drain electrode disposed on the side of the active post away from the substrate, the drain electrode being electrically connected to the second contact terminal; and a gate electrode disposed around the outside of the channel region, the gate electrode being insulated from the channel region.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of storage technology, specifically to a transistor and its manufacturing method, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM has the advantages of simpler structure, lower manufacturing cost, and higher capacity density. With the development of technology, the application of DRAM is becoming increasingly widespread.

[0003] Higher integration density is an important development direction for memory to meet consumer demand for excellent performance and low prices. For memory, integration density is a significant factor determining product price, thus increasing integration density is particularly desirable. For two-dimensional or planar memory devices, since their integration density is primarily determined by the area occupied by transistors, it is greatly influenced by the level of fine patterning technology.

[0004] In related technologies, the miniaturization of Dynamic Random Access Memory (DRAM) is approaching its physical limits. Traditional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are no longer suitable for advanced DRAMs due to their short-channel effects. Vertical transistors, with their excellent gate control capabilities, will replace traditional MOSFETs in next-generation DRAMs. However, vertical transistors are prone to floating body effects, forming parasitic transistors and generating leakage current, which degrades charge retention time. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] In a first aspect, embodiments of this disclosure provide a transistor, including:

[0007] An active post disposed on a substrate, the active post comprising a first contact end, a channel region and a second contact end sequentially disposed along a direction away from the substrate, wherein the material of the first contact end comprises metal silicide;

[0008] A bit line is disposed between the substrate and the first contact end, and the bit line is electrically connected to the first contact end;

[0009] A drain electrode is disposed on the side of the active post away from the substrate, and the drain electrode is electrically connected to the second contact terminal.

[0010] A gate electrode is disposed around the outside of the channel region, and the gate electrode is insulated from the channel region.

[0011] In an exemplary embodiment, the metal silicide includes at least one of titanium silicide, tantalum silicide, cobalt silicide, and nickel silicide.

[0012] In an exemplary embodiment, the bit line includes a second portion and a first portion sequentially stacked along a direction away from the substrate, the first portion being electrically connected to the first contact end, the first portion comprising a metal silicide, and the second portion being connected to the substrate.

[0013] In an exemplary embodiment, the orthographic projection of the first contact end onto the substrate is located in the orthographic projection of the bit line onto the substrate, and the sidewall of the first contact end and the sidewall of the bit line form a stepped shape.

[0014] In an exemplary embodiment, a first insulating layer is also included, which is disposed on the substrate and covers the sidewalls of the bit line.

[0015] In an exemplary embodiment, a second insulating layer is further included, which is disposed on the first insulating layer and covers the sidewall of the first contact end, and the gate electrode is disposed on the second insulating layer.

[0016] In an exemplary embodiment, a word line is also included, which is disposed on the side of the active pillar away from the substrate, and the word line is electrically connected to the gate electrode.

[0017] Secondly, embodiments of this disclosure also provide an electronic device, including the aforementioned transistor.

[0018] Thirdly, embodiments of this disclosure also provide a method for manufacturing a transistor, comprising:

[0019] Semiconductor pillars are formed on the substrate;

[0020] A channel region and a second contact terminal are formed on the semiconductor pillar, wherein the second contact terminal is located on the side of the channel region away from the substrate.

[0021] A first contact terminal and a bit line are formed on the substrate. The first contact terminal is located in the channel region near the substrate. The material of the first contact terminal includes metal silicide. The bit line is disposed between the substrate and the first contact terminal and is electrically connected to the first contact terminal.

[0022] A gate electrode is formed on the substrate, the gate electrode is disposed around the outside of the channel region, and the gate electrode is insulated from the channel region;

[0023] A drain electrode is formed on the side of the semiconductor pillar away from the substrate, and the drain electrode is electrically connected to the second contact terminal.

[0024] In an exemplary embodiment, forming the first contact end and bit line on the substrate includes:

[0025] A hard mask layer covering the channel region and the second contact end is formed on the semiconductor pillar;

[0026] The substrate is etched for the first time to form a first contact area on the substrate;

[0027] A second etching is performed on the substrate to form a second contact region on the substrate;

[0028] Metal is deposited on the first contact area and the second contact area, causing the first contact area to react with the metal to form the first contact end; at least a portion of the second contact area is caused to react with the metal, and the second contact area forms a bit line.

[0029] Alternatively, metal ions are injected into the first contact region and the second contact region, causing the first contact region to react with the metal to form the first contact end; at least a portion of the second contact region reacts with the metal, and the second contact region forms a bit line.

[0030] The transistor in this embodiment includes a metal silicide as the material of its first contact. This metal silicide can form a Schottky junction with the active pillar, resulting in a low hole diffusion barrier. This allows the transistor to release accumulated holes, thereby suppressing the floating body effect. Furthermore, by including a metal silicide as the material of the first contact, the transistor in this embodiment can reduce the resistance of the bit lines electrically connected to the first contact in the memory.

[0031] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0032] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0033] Figure 1 This is a schematic diagram of the transistor structure in an embodiment of this application. Figure 1 ;

[0034] Figure 2 This is a schematic diagram of the transistor with a source pillar in an embodiment of this application;

[0035] Figure 3 This is a schematic diagram of the transistor structure in an embodiment of this application. Figure 2 ;

[0036] Figure 4a This is a schematic diagram of the transistor after the second contact terminal and channel region are formed according to an embodiment of this application;

[0037] Figure 4b This is a schematic diagram of the transistor after the second hard mask layer has been formed according to an embodiment of this application;

[0038] Figure 4c This is a schematic diagram of the transistor after the first contact area has been formed according to an embodiment of this application;

[0039] Figure 4d This is a schematic diagram of the transistor after the second contact region has been formed according to an embodiment of this application;

[0040] Figure 4e This is a schematic diagram of the transistor after the first insulating layer has been formed, according to an embodiment of this application.

[0041] Figure 4f This is a schematic diagram showing the transistor after the first contact terminal and bit line are formed according to an embodiment of this application;

[0042] Figure 4g This is a schematic diagram of the transistor after the second insulating layer has been formed in an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0044] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0045] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0046] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0047] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0048] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (also called the drain terminal, drain region, or drain electrode) and the source electrode (also called the source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0049] In this specification, the first electrode mentioned below can be the drain electrode and the second electrode can be the source electrode, or both can be either the source electrode or the drain electrode. In practical applications, which electrode is the source and which is the drain depends on the direction of current flow; generally, current flows from the source to the drain. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0050] In this specification, "electrical connection" includes situations where components are connected together by elements that have some electrical function, such as physical connections or signal connections. There are no particular limitations on the term "elements that have some electrical function," as long as they can facilitate electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0051] In this specification, the terms "parallel" and "perpendicular" as used below refer to approximately parallel and approximately perpendicular lines within the tolerance range. "Parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes angles greater than -5° and less than 5°. Similarly, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes angles greater than 85° and less than 95°.

[0052] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0053] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0054] In related technologies, Dynamic Random Access Memory (DRAM) typically employs multiple transistors connected on the same plane using planar channels. For example, a 2T0C or 2T1C DRAM structure generally uses two planar channel transistors connected on the same plane, with no overlap in the direction perpendicular to the substrate. This results in a larger area occupied, which is not conducive to improving integration density. The planar channel refers to the channel of the planar transistor, as opposed to the vertical transistor.

[0055] This application provides a transistor, including:

[0056] An active post disposed on a substrate, the active post comprising a first contact end, a channel region and a second contact end sequentially disposed along a direction away from the substrate, wherein the material of the first contact end comprises metal silicide;

[0057] A bit line is disposed between the substrate and the first contact end, and the bit line is electrically connected to the first contact end;

[0058] A drain electrode is disposed on the side of the active post away from the substrate, and the drain electrode is electrically connected to the second contact terminal.

[0059] A gate electrode is disposed around the outside of the channel region, and the gate electrode is insulated from the channel region.

[0060] Figure 1 This is a schematic diagram of the transistor structure in an embodiment of this application. Figure 1 ; Figure 2 This is a schematic diagram of a transistor with a source pillar according to an embodiment of this application. In an exemplary embodiment, as shown... Figure 1 and Figure 2 As shown, the transistor in this embodiment includes an active pillar 20 and a gate electrode 30 disposed on a substrate 10.

[0061] The transistors in this application embodiment are vertical transistors. For example, the transistors in this application embodiment are VCAA (vertical channel all around) transistors. The transistors in this application embodiment can serve as read or write transistors in Dynamic Random Access Memory (DRAM), which can reduce the memory area and increase storage density.

[0062] In an exemplary embodiment, the substrate 10 may be made of a semiconductor material. For example, the substrate 10 may be made of single-crystal silicon.

[0063] In an exemplary embodiment, such as Figure 2 As shown, an active post 20 is disposed on the substrate 10 and is columnar in shape. The active post 20 can extend along a direction perpendicular to the substrate 10 (direction Z). The active post 20 includes a first contact end 21, a channel region 22, and a second contact end 23 sequentially disposed along a direction away from the substrate 10. The end of the active post 20 closest to the substrate 10 is the first contact end 21, and the end of the active post 20 away from the substrate 10 is the second contact end 23. The channel region 22 is located between the first contact end 21 and the second contact end 23 and is electrically connected to the first contact end 21 and the second contact end 23, respectively. The material of the first contact end 21 includes metal silicide.

[0064] In an exemplary embodiment, the metal silicide in the first contact terminal 21 can be made of a variety of materials. For example, the metal silicide may include at least one of titanium silicide, tantalum silicide, cobalt silicide, and nickel silicide.

[0065] In an exemplary embodiment, the first contact end 21 can take various shapes. For example, the first contact end is a columnar structure; or, the vertical cross-section of the first contact end is a shape that is larger at the top and smaller at the bottom.

[0066] In this embodiment of the transistor, the first contact 21 is made of metal silicide. The metal silicide can form a Schottky junction with the active pillar, resulting in a low hole diffusion barrier. This allows the release of holes accumulated in the transistor, thereby suppressing the floating body effect. Furthermore, by making the first contact 21 of the transistor made of metal silicide, the resistance of the bit lines electrically connected to the first contact in the memory can be reduced.

[0067] In an exemplary embodiment, the orthographic projection of the active pillar 20 onto the substrate 10 can take various shapes, such as regular or irregular shapes like circles, ellipses, rectangles, and polygons.

[0068] In an exemplary embodiment, the gate electrode 30 is disposed around the outside of the channel region 22, and the gate electrode 30 is insulated from the first contact end 21, the channel region 22 and the second contact end 23.

[0069] In an exemplary embodiment, the gate electrode 30 material may be polycrystalline silicon or a metal. The metal may include conductive metals such as tin and tungsten.

[0070] In an exemplary embodiment, the gate electrode 30 is disposed opposite to the channel region 22, and the gate electrode 30 does not cover the first contact end 21 and the second contact end 23, and does not contact the first contact end 21 and the second contact end 23. The gate electrode 30 may surround part or all of the channel region 22 to form a ring gate structure. For example, the gate electrode 30 may be ring-shaped, and the gate electrode 30 surrounds the perimeter of the channel region 22.

[0071] The ring-gate structure of the transistor in this application embodiment provides strong gate control, increases the channel area, and improves hold time. Furthermore, the ring-gate structure can reduce the memory area.

[0072] In an exemplary embodiment, such as Figure 1 As shown, the transistor in this embodiment further includes a gate insulating layer 70, which is disposed between the gate electrode 30 and the channel region 22, isolating the gate electrode 30 from the channel region 22. The gate insulating layer 70 can be made of a wide bandgap and high dielectric constant material, or a material suitable for fabricating extremely small devices, such as hafnium dioxide. The gate insulating layer 70 can be a single-layer dielectric material, such as an oxide or nitride; or, the gate insulating layer 70 can be a multilayer dielectric material, such as a combination of oxides and nitrides.

[0073] In an exemplary embodiment, such as Figure 1 and Figure 2 As shown, the transistor in this embodiment of the application further includes a bit line 60, which is disposed between the substrate 10 and the first contact terminal 21, and is electrically connected to the first contact terminal 21. The bit line 60 and the first contact terminal 21 overlap in their orthogonal projections onto the substrate 10.

[0074] In an exemplary embodiment, such as Figure 1 and Figure 2 As shown, bit line 60 includes a second portion 602 and a first portion 601 sequentially stacked along a direction away from the substrate. The first portion 601 is located on the side of the second portion 602 near the first contact end 21 and is electrically connected to the first contact end 21. The first portion 601 includes metal silicide. The second portion 602 is connected to the substrate 10. For example, the second portion 602 is integrally formed with the substrate 10.

[0075] In some embodiments, the bit line is a single-film structure, and the bit line includes metal silicide.

[0076] In an exemplary embodiment, such as Figure 1 and Figure 2As shown, the orthographic projection of the first contact end 21 onto the substrate 10 is located within the orthographic projection of the bit line 60 onto the substrate 10, and the area of ​​the orthographic projection of the first contact end 21 onto the substrate 10 is smaller than the area of ​​the orthographic projection of the bit line 60 onto the substrate 10, so that at least a portion of the sidewall of the first contact end 21 and at least a portion of the bit line 60 form a stepped shape.

[0077] The above-described structure of the first contact terminal 21 and bit line 60 of the transistor in the embodiments of this application can increase the connection area between the first contact terminal 21 and the bit line 60, thereby improving the stability of signal transmission.

[0078] In an exemplary embodiment, such as Figure 1 As shown, the transistor in this embodiment further includes a first insulating layer 40, which is disposed on the substrate 10 and covers the sidewalls of the bit line 60. The first insulating layer 40 may be a single-layer dielectric material, such as an oxide or a nitride, and the oxide may include silicon dioxide.

[0079] In an exemplary embodiment, such as Figure 1 As shown, the transistor in this embodiment further includes a second insulating layer 50, which is disposed on the first insulating layer 40 and covers the sidewall of the first contact terminal 21. A gate electrode 30 is disposed on the second insulating layer 50. The second insulating layer 50 can be a single-layer dielectric material, such as an oxide or nitride, and the oxide may include silicon dioxide.

[0080] Figure 3 This is a schematic diagram of the transistor structure in an embodiment of this application. Figure 2 In an exemplary embodiment, such as Figure 3 As shown, the transistor in this embodiment further includes a third insulating layer 80, which is disposed on the second insulating layer 50. The third insulating layer 80 covers the active pillar 20 and the gate electrode 30. The surface of the third insulating layer 80 away from the substrate 10 is higher than the surface of the active pillar 20 away from the substrate 10. The third insulating layer 80 may be a single-layer dielectric material, such as an oxide or a nitride, and the oxide may include silicon dioxide.

[0081] In an exemplary embodiment, such as Figure 3 As shown, the transistor in this embodiment further includes a drain electrode 90, which is disposed on the third insulating layer 80, located on the side of the active pillar 20 away from the substrate 10, and the drain electrode 90 overlaps with the orthographic projection of the active pillar 20 onto the substrate 10. A first via is provided in the third insulating layer 80, and the drain electrode 90 is electrically connected to the second contact terminal 23 of the active pillar 20 through the first via.

[0082] In an exemplary embodiment, such as Figure 3As shown, the transistor in this embodiment of the application further includes a word line 100, which is disposed on the third insulating layer 80 and located on the side of the active pillar 20 away from the substrate 10. The word line 100 overlaps with the orthographic projection of the gate electrode 30 onto the substrate 10. A second via is provided in the third insulating layer 80, and the word line 100 is electrically connected to the gate electrode 30 through the second via.

[0083] This application also provides a method for manufacturing a transistor, including:

[0084] Semiconductor pillars are formed on the substrate;

[0085] A channel region and a second contact terminal are formed on the semiconductor pillar, wherein the second contact terminal is located on the side of the channel region away from the substrate.

[0086] A first contact terminal and a bit line are formed on the substrate. The first contact terminal is located in the channel region near the substrate. The material of the first contact terminal includes metal silicide. The bit line is disposed between the substrate and the first contact terminal and is electrically connected to the first contact terminal.

[0087] A gate electrode is formed on the substrate, the gate electrode is disposed around the outside of the channel region, and the gate electrode is insulated from the channel region;

[0088] A drain electrode is formed on the side of the semiconductor pillar away from the substrate, and the drain electrode is electrically connected to the second contact terminal.

[0089] In an exemplary embodiment, forming the first contact end and bit line on the substrate includes:

[0090] A hard mask layer covering the channel region and the second contact end is formed on the semiconductor pillar;

[0091] The substrate is etched for the first time to form a first contact area on the substrate;

[0092] A second etching is performed on the substrate to form a second contact region on the substrate;

[0093] Metal is deposited on the first contact area and the second contact area, causing the first contact area to react with the metal to form the first contact end; at least a portion of the second contact area is caused to react with the metal, and the second contact area forms a bit line.

[0094] Alternatively, metal ions are injected into the first contact region and the second contact region, causing the first contact region to react with the metal to form the first contact end; at least a portion of the second contact region reacts with the metal, and the second contact region forms a bit line.

[0095] The following reference Figures 4a to 4gThe fabrication process of a transistor is illustrated by way of example.

[0096] The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0097] In an exemplary embodiment, the transistor fabrication process may include:

[0098] (1) Provide a substrate.

[0099] In an exemplary embodiment, the substrate can be any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, with the corresponding top semiconductor material being silicon, germanium, silicon germanium, or gallium arsenide. The semiconductor layer on the substrate is doped according to the device type to form a P-well (for nMOSFETs) or an n-well (for pMOSFETs). For example, the substrate is made of silicon.

[0100] (2) Formation of the second contact end and channel area.

[0101] In an exemplary embodiment, forming the second contact terminal and the channel region includes: depositing a first hard mask layer on the substrate 10, forming a semiconductor pillar on the substrate 10 through photolithography and etching processes; and then forming the second contact terminal 23 and the channel region 22 from the semiconductor pillar, wherein the second contact terminal 23 is located on the side of the channel region 22 away from the substrate 10, such as... Figure 4a As shown. The first hard mask layer can be made of inorganic materials, for example, silicon dioxide.

[0102] (3) Form a second hard mask layer.

[0103] In an exemplary embodiment, forming the second hard mask layer includes: depositing an inorganic material thin film on the substrate 10 on which the aforementioned pattern is formed; patterning the inorganic material thin film using a patterning process to form a second hard mask layer 1 covering the second contact terminal 23 and the channel region 22; the second hard mask layer 1 covering the entire outer wall of the second contact terminal 23 and the channel region 22; and forming a covered area 2 and an uncovered area 3 on the substrate 10. The covered area 2 of the substrate 10 refers to the area where the second hard mask layer 1, the second contact terminal 23, and the channel region 22 are located. The uncovered area 3 of the substrate 10 refers to the area outside the area where the second hard mask layer 1, the second contact terminal 23, and the channel region 22 are located, such as... Figure 4b As shown. The second hard mask layer 1 can be made of inorganic materials, for example, the second hard mask layer 1 can be made of silicon nitride.

[0104] (4) Formation of the first contact zone.

[0105] In an exemplary embodiment, forming the first contact area includes: performing a first etching on the uncovered area 3 of the substrate 10 on the substrate 10 where the aforementioned pattern is formed. Since the covered area 2 of the substrate 10 is covered by the second hard mask layer 1, the covered area 2 of the substrate 10 is not etched, thus partially exposing the covered area 2 of the substrate 10 to form the first contact area 4. One end of the first contact area 4 contacts the bottom of the channel region 22, and the other end of the first contact area 4 contacts the substrate 10. The first contact area 4 and the channel region 22 overlap in their orthographic projections on the substrate 10. For example, the orthographic projection of the first contact area 4 on the substrate 10 completely overlaps with the orthographic projection of the channel region 22 on the substrate 10. Figure 4c As shown.

[0106] (5) Formation of a second contact zone.

[0107] In an exemplary embodiment, forming the second contact area includes: performing a second etching on the substrate 10 on which the aforementioned pattern is formed, forming a second contact area 5 on the substrate 10. The second contact area 5 is located on the side of the first contact area 4 near the substrate 10. One end of the second contact area 5 contacts the bottom of the first contact area 4, and the other end of the first contact area 4 contacts the substrate 10. The orthographic projection of the first contact area 4 onto the substrate 10 is located in the orthographic projection of the second contact area 5 onto the substrate 10, such that the sidewalls of the first contact area 4 and the sidewalls of the second contact area 5 form a stepped shape, as shown below. Figure 4d As shown.

[0108] (6) Form the first insulating layer.

[0109] In an exemplary embodiment, forming the first insulating layer includes: depositing a first insulating film on the substrate 10 on which the aforementioned pattern is formed; patterning the first insulating film using a patterning process to form a first insulating layer 40, wherein the first insulating layer 40 covers the sidewalls of the second contact area 5, such as... Figure 4e As shown.

[0110] (7) Form the first contact end and bit line.

[0111] In an exemplary embodiment, forming the first contact end and the bit line includes: depositing a metal thin film on the substrate 10 on which the aforementioned pattern is formed, on the first contact region 4 and the second contact region 5; reacting all of the first contact region 4 with the metal thin film to form the first contact end 21; reacting a portion of the second contact region 5 with the metal thin film to silicide the portion of the second contact region 5 to form the bit line 60, wherein the silicided second contact region 5 forms a first portion 601 of the bit line 60, the first portion 601 comprising metal silicide; and the unsilicided second contact region 5 forming a second portion 602 of the bit line 60, such as... Figure 4f As shown. The thickness of the metal thin film can be from 10 nanometers to 30 nanometers. The metal thin film may include at least one of titanium, tantalum, cobalt, and nickel.

[0112] Alternatively, forming the first contact terminal includes: implanting metal ions into the first contact region 4 and the second contact region 5 on the substrate 10 where the aforementioned pattern is formed; reacting all of the first contact region 4 with the metal ions to form the first contact terminal 21; reacting a portion of the second contact region 5 with the metal ions to silicide the portion of the second contact region 5, forming a bit line 60; the silicided second contact region 5 forms a first portion 601 of the bit line 60, the first portion 601 comprising metal silicide; and the unsilicided second contact region 5 forms a second portion 602 of the bit line 60. For example, 1×10⁻⁶ electron volts can be used at a high temperature of 500°C to 800°C to form the first contact terminal 21. 20 ~1×10 21 cm -2 Metal ions are implanted, and then thermal annealing is performed within 60 seconds to form the first contact end 21 in the entire first contact region 4, and to silicide the portion of the second contact region 5 by reacting with the metal ions, thus forming the bit line 60 in the second contact region 5. Figure 4f As shown. The metal ions may include at least one of titanium ions, tantalum ions, cobalt ions, and nickel ions.

[0113] (8) Form a second insulating layer.

[0114] In an exemplary embodiment, forming the second insulating layer includes: removing the second hard mask layer 1 on the substrate 10 where the aforementioned pattern is formed; depositing a second insulating film on the first insulating layer 40; and patterning the second insulating film using a patterning process to form a second insulating layer 50 covering the sidewalls of the first contact end 21. Figure 4g As shown.

[0115] (9) Forming the gate electrode.

[0116] In an exemplary embodiment, forming the gate electrode includes: forming a gate insulating layer 70 on the substrate 10 on which the aforementioned pattern is formed, outside the channel region 22; then, depositing a conductive thin film on the second insulating layer 50, and patterning the conductive thin film using a patterning process, so that the conductive thin film forms a gate electrode 30 disposed on the second insulating layer 50, the gate electrode 30 being insulated from the channel region 22 through the gate insulating layer 70, such as... Figure 1 As shown.

[0117] The transistor manufacturing method of this application involves etching a first contact region and a second contact region on a substrate using a hard mask layer. The first contact region then reacts with a metal thin film or metal ions to form a first contact terminal 21 comprising a metal silicide. The metal silicide and the active pillar can form a Schottky junction, which has a low hole diffusion barrier, releasing accumulated holes in the transistor and thus suppressing the transistor's floating body effect. Furthermore, the first contact terminal 21 comprising the metal silicide can reduce the resistance of the bit lines electrically connected to the first contact terminal in the memory.

[0118] The transistor manufacturing method of this application has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0119] This application also provides an electronic device, including any of the transistors described above. This application does not impose any special limitations on the specific form of the described electronic device.

[0120] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0121] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A transistor, characterized in that, include: An active post disposed on a substrate, the active post comprising a first contact end, a channel region and a second contact end sequentially disposed along a direction away from the substrate, wherein the material of the first contact end comprises metal silicide; A bit line is disposed between the substrate and the first contact end, and the bit line is electrically connected to the first contact end; A drain electrode is disposed on the side of the active post away from the substrate, and the drain electrode is electrically connected to the second contact terminal. A gate electrode is disposed around the outside of the channel region, and the gate electrode is insulated from the channel region. The bit line includes a second part and a first part that are sequentially stacked along a direction away from the substrate. The first part is integrally connected to the first contact end. The first part and the first contact end use the same metal silicide and are prepared by the same silicide process. The second part is integrally connected to the substrate and uses the same material.

2. The transistor according to claim 1, characterized in that, The metal silicide includes at least one of titanium silicide, tantalum silicide, cobalt silicide, and nickel silicide.

3. The transistor according to claim 1, characterized in that, The first contact end is projected onto the substrate in the orthographic projection of the bit line onto the substrate, and the sidewall of the first contact end and the sidewall of the bit line form a stepped shape.

4. The transistor according to claim 1, characterized in that, It also includes a first insulating layer disposed on the substrate, the first insulating layer covering the sidewalls of the bit line.

5. The transistor according to claim 4, characterized in that, It also includes a second insulating layer disposed on the first insulating layer, the second insulating layer covering the sidewall of the first contact end, and the gate electrode disposed on the second insulating layer.

6. The transistor according to any one of claims 1 to 5, characterized in that, It also includes word lines, which are disposed on the side of the active pillar away from the substrate, and the word lines are electrically connected to the gate electrode.

7. An electronic device, characterized in that, Includes the transistor as described in any one of claims 1 to 6.

8. A method for manufacturing a transistor, characterized in that, include: Semiconductor pillars are formed on the substrate; A channel region and a second contact terminal are formed on the semiconductor pillar, wherein the second contact terminal is located on the side of the channel region away from the substrate. A first contact terminal and a bit line are formed on the substrate. The first contact terminal is located in the channel region near the substrate. The material of the first contact terminal includes metal silicide. The bit line is disposed between the substrate and the first contact terminal and is electrically connected to the first contact terminal. A gate electrode is formed on the substrate, the gate electrode is disposed around the outside of the channel region, and the gate electrode is insulated from the channel region; A drain electrode is formed on the side of the semiconductor pillar away from the substrate, and the drain electrode is electrically connected to the second contact terminal. The bit line includes a second part and a first part that are sequentially stacked along a direction away from the substrate. The first part is integrally connected to the first contact end and is made of the same material. The first part and the first contact end are prepared by the same siliconization process. The second part is integrally connected to the substrate and is made of the same material.

9. The method for manufacturing a transistor according to claim 8, characterized in that, Forming the first contact terminal and bit line on the substrate includes: A hard mask layer covering the channel region and the second contact end is formed on the semiconductor pillar; The substrate is etched for the first time to form a first contact area on the substrate; A second etching is performed on the substrate to form a second contact region on the substrate; Metal is deposited on the first contact area and the second contact area, causing the first contact area to react with the metal to form the first contact end; at least a portion of the second contact area reacts with the metal, and the second contact area forms a bit line; or, metal ions are implanted into the first contact area and the second contact area, causing the first contact area to react with the metal to form the first contact end; at least a portion of the second contact area reacts with the metal, and the second contact area forms a bit line.

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