Semiconductor structure, memory and method of operating the same

Abstract

The present disclosure provides a semiconductor structure, a memory and an operating method thereof. The semiconductor structure comprises: a substrate; a first gate structure and a second gate structure on a surface of the substrate; the second gate structure has a same thickness as the first gate structure and is smaller than a predetermined thickness; a first doped region and a second doped region in the substrate, and the first doped region and the second doped region are respectively located on two sides of the first gate structure; the first gate structure, the first doped region and the second doped region form a selection transistor; a projection of the second gate structure on the substrate at least partially overlaps the second doped region; the second gate structure and the second doped region form an anti-fuse bit structure; a breakdown state and a non-breakdown state of the anti-fuse bit structure are used to represent different storage data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor structure, a memory, and a method of operating thereof. Background Technology

[0002] With the continuous development of science and technology, semiconductor memory devices are becoming increasingly powerful while their feature sizes are shrinking. One-Time Programmable (OTP) memory is a type of non-volatile memory (NVM) that retains stored data even when power is lost. OTP memory can only be programmed once and cannot be electrically erased. It can be used in program code memory, serial configuration memory, and system-on-chip (SoC) applications, and plays a role in ID identification and memory recovery.

[0003] Currently, one-time programmable memories (IPMs) mainly adopt a structure similar to Dynamic Random Access Memory (DRAM), which includes a selection transistor and a breakdown capacitor (1T1C). Since the breakdown of the dielectric layer in the capacitor is irreversible, the stored data can be obtained by reading the breakdown state of the capacitor. However, IPMs face problems such as large storage cell area, low integration density, complex manufacturing process, and high manufacturing cost. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, as well as a memory and a method for operating the same.

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including: a substrate; a first gate structure and a second gate structure located on the surface of the substrate; the second gate structure having the same thickness as the first gate structure and a thickness less than a predetermined thickness; a first doped region and a second doped region located in the substrate, wherein the first doped region and the second doped region are respectively located on opposite sides of the first gate structure; the first gate structure, the first doped region, and the second doped region constitute a selection transistor; the orthogonal projection of the second gate structure onto the substrate at least partially overlaps with the second doped region; the second gate structure and the second doped region constitute an antifuse bit structure; and the breakdown state and non-breakdown state of the antifuse bit structure are used to represent different stored data.

[0006] In some embodiments, the first gate structure includes a first gate electrode and a first gate dielectric layer located below the first gate electrode; the second gate structure includes a second gate electrode and a second gate dielectric layer located below the second gate electrode; the first gate dielectric layer and the second gate dielectric layer have the same thickness, and the first gate dielectric layer and the second gate dielectric layer are predetermined thin gate oxide structures.

[0007] In some embodiments, the semiconductor structure further includes: a first metal line located above the first gate structure and the second gate structure; the first metal line is connected to the first doped region via a first connection structure.

[0008] In some embodiments, the semiconductor structure further includes: a second metal line located between the first gate structure and the first metal line; the second metal line is connected to the substrate via a second connection structure.

[0009] In some embodiments, the semiconductor structure further includes: an isolation structure located in the substrate between two adjacent antifuse site structures; wherein at least a portion of the second connection structure is located on the isolation structure.

[0010] In some embodiments, the semiconductor structure further includes: a third doped region located in the substrate on both sides of the isolation structure; the second connection structure is connected to the substrate through the third doped region.

[0011] In some embodiments, the semiconductor structure further includes: a word line located above the first gate structure; the word line connecting a plurality of first gate structures located in the word line extension direction; a third metal line located above the second gate structure, the third metal line extending in a direction parallel to the word line extension direction; the third metal line connecting a plurality of second gate structures located in the third metal line extension direction.

[0012] In some embodiments, two adjacent selection transistors are symmetrically arranged and share the same first doped region.

[0013] Secondly, embodiments of this disclosure provide a method for operating a memory, the memory including any of the semiconductor structures described in the above embodiments; the method includes: performing a write operation on the memory according to data to be written, the write operation including: breaking down a target antifuse bit structure in the antifuse bit structure of the memory, causing the target antifuse bit structure to switch from a non-breakdown state to a breakdown state; and maintaining the non-breakdown state of non-target antifuse bit structures; wherein, the non-target antifuse bit structure is an antifuse bit structure other than the target antifuse bit structure.

[0014] In some embodiments, the write operation further includes applying a first voltage to the substrate to maintain the non-breakdown state of the select transistor.

[0015] In some embodiments, the step of breaking down a target antifuse bit structure in the antifuse bit structure of the memory, causing the target antifuse bit structure to switch from a non-breakdown state to a breakdown state, includes: applying a second voltage to the first gate electrode of the select transistor connected to the target antifuse bit structure to turn on the select transistor; applying a third voltage to the first metal line connected to the select transistor; the difference between the third voltage and the second voltage being less than the breakdown voltage of the first gate dielectric layer; and applying a fourth voltage to the second gate electrode of the target antifuse bit structure to switch the target antifuse bit structure from a non-breakdown state to a breakdown state; wherein the voltage difference between the third voltage and the fourth voltage is greater than or equal to the breakdown voltage of the second gate dielectric layer.

[0016] In some embodiments, maintaining the non-breakdown state of the non-target antifuse bit structure includes: applying a second voltage to the first gate electrode of the select transistor connected to the non-target antifuse bit structure to turn on the select transistor; applying a first voltage to the first metal line connected to the select transistor; the difference between the first voltage and the second voltage is less than the breakdown voltage of the first gate dielectric layer; applying a fourth voltage to the second gate electrode of the non-target antifuse bit structure to maintain the non-breakdown state of the non-target antifuse bit structure; wherein the voltage difference between the first voltage and the fourth voltage is less than the breakdown voltage of the second gate dielectric layer.

[0017] In some embodiments, maintaining the non-breakdown state of the non-target antifuse bit structure includes: applying a cutoff voltage to the first gate electrode of the select transistor connected to the non-target antifuse bit structure to turn off the select transistor; applying a third voltage to the first metal line connected to the select transistor; the difference between the third voltage and the cutoff voltage is less than the breakdown voltage of the first gate dielectric layer; applying a first voltage to the second gate electrode of the non-target antifuse bit structure to maintain the non-breakdown state of the non-target antifuse bit structure; wherein the voltage difference between the third voltage and the first voltage is less than the breakdown voltage of the second gate dielectric layer.

[0018] In some embodiments, the method further includes: performing a read operation on the memory, the read operation including: grounding the substrate; applying a first read voltage to the first gate electrode of the select transistor connected to the antifuse bit structure to turn on the select transistor; applying a second read voltage to a first metal line connected to the select transistor; and detecting the current on the first metal line.

[0019] Thirdly, embodiments of this disclosure provide a memory, including: a memory array, the memory array including any of the semiconductor structures described in the above embodiments; and peripheral circuitry coupled to the memory array.

[0020] In the semiconductor structure provided in this embodiment, the first gate structure and the second gate structure have the same thickness and are less than a predetermined thickness; the orthogonal projection of the second gate structure onto the substrate at least partially overlaps with the second doped region. Thus, on the one hand, the first gate structure and the second gate structure can have thin gate oxide structures of the same thickness, resulting in a smaller channel width for the selection transistor, reducing the occupied area of ​​the semiconductor structure, and the thin gate oxide structures of both can be formed simultaneously, simplifying the manufacturing process; on the other hand, the overlap between the second gate structure and the second doped region reduces the horizontal length of the antifuse site structure, also reducing the occupied area of ​​the semiconductor structure and improving the integration density of the memory. Attached Figure Description

[0021] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0022] Figure 2 A schematic diagram of another semiconductor structure provided in an embodiment of this disclosure;

[0023] Figure 3 A schematic diagram of yet another semiconductor structure provided in this disclosure embodiment;

[0024] Figure 4 A schematic diagram of yet another semiconductor structure provided in this disclosure embodiment;

[0025] Figure 5 A schematic diagram of yet another semiconductor structure provided in this disclosure embodiment;

[0026] Figure 6 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0027] Figure 7 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0028] Figure 8 A schematic diagram of a storage array in a memory provided in an embodiment of this disclosure;

[0029] Figure 9 This is a flowchart illustrating the steps of an operation method for a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0030] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0031] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, some technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described in detail.

[0032] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0033] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit this disclosure. When used, the singular forms “a,” “an,” and “ / the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] To fully understand this disclosure, detailed steps and structures will be set forth in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0035] like Figure 1As shown, this disclosure provides a semiconductor structure 10, including: a substrate 100; a first gate structure 110 and a second gate structure 120 located on the surface of the substrate 100; the second gate structure 120 having the same thickness as the first gate structure 110 and less than a predetermined thickness; a first doped region 101 and a second doped region 102 located in the substrate 100, with the first doped region 101 and the second doped region 102 respectively located on opposite sides of the first gate structure 110; the first gate structure 110, the first doped region 101, and the second doped region 102 forming a selection transistor 130; the orthographic projection of the second gate structure 120 onto the substrate 100 at least partially overlapping the second doped region 102; the second gate structure 120 and the second doped region 102 forming an antifuse bit structure 140; the breakdown state and non-breakdown state of the antifuse bit structure 140 are used to represent different stored data.

[0036] It is worth noting that, in order to clearly show all the structures in the diagram, the dimensional proportions of the structures may not match the actual structures.

[0037] In this embodiment, the semiconductor structure 10 can be used for a one-time programmable memory. The substrate 100 can be made of elemental semiconductor materials, such as silicon (Si), germanium (Ge), or compound semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP). In some embodiments, the substrate 100 may also have well regions, such as P-wells and deep N-wells located below the P-wells. The P-wells can be used to form the channel of the selection transistor 130, while the deep N-wells can be used to isolate the P-wells and reduce noise interference to devices formed in the P-wells.

[0038] The semiconductor structure 10 may further include multiple first doped regions 101 and second doped regions 102 to serve as the source and drain of the selection transistor 130. The first doped regions 101 and second doped regions 102 are located in the substrate 100. The first doped regions 101 and second doped regions 102 may have the same doping type. The impurity ions doped in the P-type doped region may be trivalent elements, such as boron; while the impurity ions doped in the N-type doped region may be pentavalent elements, such as phosphorus or arsenic. In some embodiments, the first doped region 101 and second doped region 102 may be high-concentration N-type doped regions in a P-well, i.e., N+ type doped regions.

[0039] like Figure 1As shown, a first gate structure 110 and a second gate structure 120 are located on the surface of the substrate 100. The first gate structure 110 and the second gate structure 120 are located in the same plane and can have the same thickness. A first doped region 101 and a second doped region 102 are located on both sides of the first gate structure 110, and the first doped region 101, the second doped region 102, and the first gate structure 110 constitute a selection transistor 130. Furthermore, the projection of the second gate structure 120 onto the substrate 100 at least partially overlaps with the second doped region 102, and the second gate structure 120 and the second doped region 102 constitute an antifuse bit structure 140. The antifuse bit structure 140 can be a structure similar to a metal oxide semiconductor field effect transistor (MOSFET), wherein the breakdown state and non-breakdown state of the gate dielectric layer of the antifuse bit structure 140 are used to represent different stored data, i.e., "0" or "1". For example, the first gate structure 110 may include a first gate electrode and a first gate dielectric layer, with the first gate electrode located above the first gate dielectric layer. The first gate electrode can be connected to a word line (WL) via a contact structure. The second gate structure 120 may include a second gate electrode and a second gate dielectric layer, with the second gate electrode located above the second gate dielectric layer. The breakdown and non-breakdown states of the second gate dielectric layer are used to represent different stored data. The first and second gate electrodes include, but are not limited to, conductive materials such as metals and doped semiconductors. The first and second gate dielectric layers may be materials such as silicon oxide and hafnium oxide.

[0040] In some embodiments, a select transistor 130 and an antifuse bit structure 140 constitute a memory cell of a one-time programmable memory. The selection transistor 130 can be turned on and off by applying different voltages to the first gate electrode. In some embodiments, the first doped region 101 in the select transistor 130 is also connected to a first metal line, which can be a bit line. When the select transistor 130 is turned on, the voltage on the first metal line can be applied to the second doped region 102. Applying a suitable voltage to the second gate electrode at this time allows the voltage difference between the second gate electrode and the second doped region 102 to be greater than or equal to the breakdown voltage of the second gate dielectric layer, thereby causing the antifuse bit structure 140 to permanently break down, completing the one-time programming operation of the memory cell.

[0041] In some embodiments, the first gate dielectric layer in the first gate structure 110 is a thick gate oxide structure, with a thickness reaching 6 nm. A thick gate oxide structure allows the select transistor 130 to withstand a higher gate voltage, reducing the possibility of false breakdown. However, to ensure sufficient read current for the thick gate oxide select transistor 130, the diffusion width of the select transistor 130 should be large, i.e., a large channel width, where the channel width refers to the width of the channel in the direction of the source-drain connection. This results in a larger area occupied by the select transistor 130, leading to a lower integration density of the one-time programmable memory. Furthermore, the antifuse bit structure 140 uses a thin gate oxide structure as the second gate dielectric layer, resulting in a significant difference in thickness between the second and first gate dielectric layers. During manufacturing, a large distance is required between the first gate structure 110 and the second gate structure 120 to meet the requirements of the photolithography process for different gate oxide layer thicknesses, which also results in a larger area occupied by the semiconductor structure 10.

[0042] In this embodiment, the first gate dielectric layer and the second gate dielectric layer can be thin gate oxide structures with the same thickness, that is, the thicknesses of the first gate structure 110 and the second gate structure 120 can be the same and less than a predetermined thickness. For example, the thickness of the thin gate oxide structure here can be less than 3 nm. In this way, the thin gate oxide structure allows the selection transistor 130 to reduce the channel width while having sufficient read current, thereby reducing the occupied area of ​​the selection transistor 130 and improving the integration density of the memory; and since the first gate dielectric layer and the second gate dielectric layer have the same thickness, they can be formed simultaneously during the manufacturing process, simplifying the manufacturing process and shortening the distance between the first gate structure 110 and the second gate structure 120. Secondly, since the projection of the second gate structure 120 on the substrate 100 at least partially overlaps with the second doped region 102, it is not necessary to form an additional doped region next to the second doped region 102 as the lower electrode corresponding to the second gate electrode, simplifying the manufacturing process and further reducing the occupied area of ​​the semiconductor structure 10. In some embodiments, the voltage applied to the first doped region 101 and the first gate electrode can be adjusted so that the voltage difference between them is less than the breakdown voltage of the thin gate oxide structure, thereby reducing the possibility of false breakdown of the select transistor 130.

[0043] In some embodiments, such as Figure 2 As shown, the first gate structure 110 includes a first gate electrode 111 and a first gate dielectric layer 112 located below the first gate electrode 111; the second gate structure 120 includes a second gate electrode 121 and a second gate dielectric layer 122 located below the second gate electrode 121; the first gate dielectric layer 112 and the second gate dielectric layer 122 have the same thickness, and the first gate dielectric layer 112 and the second gate dielectric layer 122 are predetermined thin gate oxide structures.

[0044] In this embodiment, the first gate structure 110 may include a first gate electrode 111 and a first gate dielectric layer 112, with the first gate dielectric layer 112 located at least between the first gate electrode 111 and the substrate 100. The second gate structure 120 may include a second gate electrode 121 and a second gate dielectric layer 122, with the second gate dielectric layer 122 located at least between the second gate electrode 121 and the second doped region 102. Exemplarily, the first gate electrode 111 and the second gate electrode 121 may include, but are not limited to, conductive materials such as tungsten (W) or doped polysilicon; the first gate dielectric layer 112 and the second gate dielectric layer 122 may be materials such as silicon oxide or hafnium oxide. The first gate dielectric layer 112 and the second gate dielectric layer 122 have the same thickness and are both predetermined thin gate oxide structures. Here, the predetermined thin gate oxide structure may be a gate oxide layer with a thickness of less than 3 nm, where the thickness refers to the thickness in the direction perpendicular to the surface of the substrate 100. The thin gate oxide structure of the first gate dielectric layer 112 allows for a smaller channel width in the select transistor 130, thereby reducing the area occupied by the select transistor 130. Furthermore, the first gate dielectric layer 112 and the second gate dielectric layer 122 of the same thickness can be formed simultaneously to simplify the manufacturing process. Thus, when the voltage difference between the second gate electrode 121 and the second doped region 102 is greater than or equal to the breakdown voltage of the second gate dielectric layer 122, the second gate dielectric layer 122 is broken down, i.e., the antifuse bit structure 140 is permanently broken down, thereby completing the one-time programming operation of the memory cell.

[0045] In some embodiments, the first gate dielectric layer 112 and the second gate dielectric layer 122 can be a continuous thin gate oxide structure of the same layer. The portion of the thin gate oxide structure located between the first gate electrode 111 and the substrate 100 is the first gate dielectric layer 112, and the portion of the thin gate oxide structure located between the second gate electrode 121 and the second doped region 102 is the second gate dielectric layer 122.

[0046] In some embodiments, such as Figures 3 to 6 As shown, the first gate structure 110 can also be connected to the word line 113 through a contact structure, and the second gate structure 120 can be connected to the third metal line 123 through a contact structure. The extension direction of the word line 113 can be parallel to the extension direction of the third metal line 123.

[0047] In some embodiments, such as Figure 3 As shown, the semiconductor structure 10 further includes:

[0048] The first metal line 150 is located above the first gate structure 110 and the second gate structure 120; the first metal line 150 is connected to the first doped region 101 through the first connection structure 160.

[0049] In this embodiment, the first metal line 150 can be a bit line (BL) in the memory. When the select transistor 130 is turned on, the voltage on the first metal line 150 can be applied to the second doped region 102 of the antifuse bit structure 140 through the select transistor 130. At this time, applying a suitable voltage to the second gate electrode 121 makes the voltage difference between the second doped region 102 and the second gate electrode 121 greater than or equal to the breakdown voltage of the second gate dielectric layer 122, causing the antifuse bit structure 140 to permanently break down, thereby completing the one-time programming operation of the memory cell. The extension direction of the first metal line 150 can be perpendicular to the extension direction of the word line 113 in the memory, so that memory cells can be set at the intersection of the bit line and the word line 113 extension directions to form a memory cell array. In other embodiments, the extension direction of the first metal line 150 intersects with the extension direction of the word line 113, but is not perpendicular to it. The first metal line 150 is connected to the first doped region 101 through the first connection structure 160, wherein the first connection structure 160 can be a conductive material such as a metal or a doped semiconductor.

[0050] In some embodiments, such as Figure 3 As shown, the substrate 100 includes a first well 104 and a second well 105 with opposite doping types, the second well 105 being located below the first well 104; the first doped region 101 and the second doped region 102 are located in the first well 104; the first doped region 101 and the second doped region 102 have the same doping type as the second well 105.

[0051] In this embodiment, the substrate 100 further includes a second well 105 and a first well 104 located above the second well 105. The first well 104 is used to form the channel of the selection transistor 130. The first well 104 and the second well 105 have opposite doping types, so the second well 105 has the same doping type as the first doped region 101 and the second doped region 102, and the second well 105 can effectively isolate the first well 104. In some embodiments, the substrate 100 may further include a substrate 106 located below the second well 105, where the substrate 106 may have the same doping type as the first well 104. Exemplarily, the first well 104 is a P-well, the second well 105 is a deep N-well, the substrate 106 is a P-type doped semiconductor material, and the first doped region 101 and the second doped region 102 are N-type doped regions. Thus, an anti-biased PN junction is formed between the first well 104 and the second well 105, and between the second well 105 and the substrate 106, thereby reducing noise interference experienced by the device formed in the first well 104. In some embodiments, the second well 105 may surround the bottom and sides of the first well 104 to improve the isolation effect.

[0052] In some embodiments, such as Figure 4As shown, the semiconductor structure 10 further includes:

[0053] The second metal line 190 is located between the first gate structure 110 and the first metal line 150; the second metal line 190 is connected to the substrate 100 through the second connection structure 170.

[0054] In this embodiment, the second metal line 190 can apply a voltage to the substrate 100 through the second connection structure 170. The second metal line 190 is located above the first gate structure 110 and below the first metal line 150, thereby reducing the risk of short circuits between the second metal line 190 and the first gate structure 110 and the first metal line 150. The second connection structure 170 can be a conductive material such as metal or doped semiconductor. The second metal line 190 applies a voltage to the substrate 100, thereby ensuring that the PN junctions formed between the first doped region 101, the second doped region 102 in each selection transistor 130 and the substrate 100 are not reverse-biased, such as avalanche breakdown of the source and drain in a MOS transistor. In some embodiments, in the memory cell array of a one-time programmable memory, the second metal line 190 can be arranged in a matrix and connected to the substrates of multiple selection transistors 130 through multiple second connection structures 170, thereby simultaneously applying voltage to the substrates of multiple memory cells and ensuring that the PN junctions in the multiple selection transistors 130 are not reverse-biased.

[0055] In some embodiments, such as Figure 4 As shown, the semiconductor structure 10 further includes:

[0056] An isolation structure 180 is located in the substrate 100 between two adjacent antifuse site structures 140; wherein at least a portion of the second connection structure 170 is located on the isolation structure 180.

[0057] In this embodiment, the antifuse bit structures 140 of two adjacent memory cells that do not share the same first doped region 101 are close to each other. Therefore, by providing an isolation structure 180 between two adjacent antifuse bit structures 140, leakage problems between the active regions of the two adjacent memory cells that do not share the first doped region 101 can be prevented. The depth of the isolation structure 180 is greater than the depth of the first doped region 101 and the depth of the second doped region 102. For example, the isolation structure 180 can be a shallow trench isolation (STI), which has advantages such as low cost and good isolation effect. The material of the isolation structure 180 includes, but is not limited to, silicon oxide. At least a portion of the second connection structure 170 is located on the isolation structure 180, and the bottom width of the second connection structure 170 can be greater than the top width of the isolation structure 180, so that the bottom of the second connection structure 170 can contact the substrate 100, realizing an electrical connection between the second connection structure 170 and the substrate 100.

[0058] In some embodiments, such as Figure 4 As shown, the semiconductor structure 10 further includes:

[0059] The third doped region 103 is located in the substrate 100 on both sides of the isolation structure 180; the second connection structure 170 is connected to the substrate 100 through the third doped region 103.

[0060] In this embodiment, the substrates 100 on both sides of the isolation structure 180 further have a third doped region 103. The second connection structure 170 is connected to the substrate 100 through the third doped region 103, thereby applying a voltage to the substrate 100. The doping type of the third doped region 103 can be opposite to that of the first doped region 101 and the second doped region 102. The third doped region 103 is used to reduce the contact resistance between the second connection structure 170 and the substrate 100. For example, the third doped region 103 can be a P+ type doped region.

[0061] Understandable, Figure 4 The second connection structure 170 is relatively far from the first connection structure 160, meaning a first gate structure 110 and a second gate structure 120 are disposed between the second connection structure 170 and the first connection structure 160. This effectively reduces signal interference during memory operation. Furthermore, the second gate structures 120 located on both sides of the second connection structure 170 can play a self-aligning role when forming the third doped region 103, and these second gate structures 120 can still serve as part of a memory cell for storing data. In some embodiments, such as... Figure 5As shown, the second connection structure 170 can be positioned close to the first connection structure 160, meaning that only one first gate structure 110 is provided between the second connection structure 170 and the first connection structure 160, thereby saving the area occupied by the semiconductor structure 10; however, the first gate structure 110 provided here alone cannot form a memory cell, but only plays a self-alignment role when forming the third doped region 103. Figure 5 In the case shown, the second connection structure 170 and the first connection structure 160 can be staggered by a certain distance in the word line extension direction, thereby reducing signal interference.

[0062] In some embodiments, such as Figure 6 The diagram shows a partial top view of the semiconductor structure 10. The semiconductor structure 10 further includes: a word line 113 located above the first gate structure 110; the word line 113 connects to a plurality of first gate structures 110 located in the extension direction of the word line 113; a third metal line 123 located above the second gate structure 120, the extension direction of the third metal line 123 being parallel to the extension direction of the word line 113; the third metal line 123 connects to a plurality of second gate structures 120 located in the extension direction of the third metal line 123.

[0063] In this embodiment, a select transistor 130 and an antifuse bit structure 140 constitute a memory cell of a one-time programmable memory. A first gate structure 110 is connected to a word line 113 located above the first gate structure 110 via a contact structure. The word line 113 connects to the first gate structures 110 of multiple memory cells located in its extension direction. A second gate structure 120 is connected to a third metal line 123 located above the second gate structure 120 via a contact structure. The third metal line 123 connects to the second gate structures 120 of multiple memory cells located in its extension direction. The extension direction of the word line 113 is parallel to the extension direction of the third metal line 123. Thus, one word line 113 can control the conduction or cutoff of the select transistor 130 of multiple memory cells located in its extension direction, while one third metal line 123 can simultaneously apply voltage to the second gate structures 120 of multiple memory cells in its extension direction, simplifying memory operation. For example, word lines 113 and third metal lines 123 may be located in the same plane parallel to the surface of substrate 100, and word lines 113 and third metal lines 123 may be formed simultaneously to simplify the manufacturing process.

[0064] In some embodiments, such as Figures 3 to 5 As shown, the two adjacent selection transistors 130 are symmetrically arranged and share the same first doped region 101.

[0065] In this embodiment, any two adjacent selection transistors 130 are symmetrically arranged and share the same first doped region 101. Thus, in the one-time programmable memory, any two adjacent memory cells are symmetrically arranged and share a first doped region 101, reducing the area occupied by each memory cell. Furthermore, a bit line (first metal line 150) can be connected to two adjacent memory cells through a first connection structure 160 to simultaneously apply voltage to the first doped region 101 of both memory cells, improving the memory's operating efficiency.

[0066] like Figure 7 As shown, this disclosure also provides a memory 20, including: a memory array 21, the memory array 21 including the semiconductor structure 10 described in any of the above embodiments; and peripheral circuitry 22 coupled to the memory array 21.

[0067] In this embodiment, the memory 20 includes a memory array 21 and peripheral circuitry 22 coupled to the memory array 21. The memory array 21 includes a semiconductor structure 10 as described in any of the above embodiments. The peripheral circuitry 22 includes address circuitry for latching and decoding row / column address information, sensing circuitry for monitoring and judging the information stored in the antifuse cells, and control circuitry for switching operating modes. Thus, on the one hand, the first gate structure and the second gate structure can have thin gate oxide structures of the same thickness, resulting in a smaller channel width for the selection transistor, reducing the area occupied by the antifuse bit structure, and the thin gate oxide structures of both can be formed simultaneously, simplifying the manufacturing process; on the other hand, the overlap between the second gate structure and the second doped region reduces the horizontal length of the antifuse bit structure, also reducing the area of ​​the antifuse bit structure, and improving the integration density of the memory.

[0068] Figure 8 The diagram shows a memory array 21, in which a select transistor 240 and an antifuse bit structure 250 constitute a memory cell 210. Each word line 213 connects to the first gate electrode 211 of a plurality of memory cells 210 located in its extension direction; each third metal line 223 connects to the second gate electrode 221 of a plurality of memory cells 210 located in its extension direction. A first metal line 260 (bit line) connects two adjacent memory cells 210 that share a first doped region 201. The memory array 21 also includes a substrate 200 to which voltage can be applied, thereby simultaneously applying voltage to the channels of the select transistors 240 in the plurality of memory cells 210 to ensure that the PN junctions in the plurality of select transistors 240 are not reverse-biased.

[0069] like Figure 9As shown, this disclosure also provides a method for operating a memory, the memory including the semiconductor structure 10 described in any of the above embodiments; the method includes:

[0070] Step S10: Perform a write operation on the memory according to the data to be written. The write operation includes: breaking down a target antifuse bit structure in the antifuse bit structure of the memory, so that the target antifuse bit structure changes from a non-breakdown state to a breakdown state; and maintaining the non-breakdown state of the non-target antifuse bit structure; wherein, the non-target antifuse bit structure is an antifuse bit structure other than the target antifuse bit structure.

[0071] In this embodiment of the disclosure, reference is made to Figure 8 When performing a write operation on target memory cell 210a, based on the data to be written, the second gate dielectric layer of a target antifuse bit structure 250a in the memory array 21 is broken down, causing the target antifuse bit structure 250a to switch from a non-breakdown state to a breakdown state, while maintaining the non-breakdown state of non-target antifuse bit structures 250b and 250c. It can be understood that by applying different voltages to the second doped region and the second gate electrode, the voltage difference between them is greater than or equal to the breakdown voltage HV, thereby achieving breakdown of the antifuse bit structure; conversely, if the voltage difference is less than the breakdown voltage HV, the non-breakdown state of the antifuse bit structure can be maintained.

[0072] In some embodiments, the voltage applied to the first metal line and the word line can also be controlled so that the difference between the voltage on the first doped region and the voltage on the first gate electrode is less than the breakdown voltage HV of the first gate dielectric layer, thereby preventing the first gate dielectric layer with a thin gate oxide structure from being mistakenly broken down. It is understood that since the first gate dielectric layer and the second gate dielectric layer are thin gate oxide structures with the same thickness, their breakdown voltages are both HV. The following discussion uses the operating voltages shown in Table 1 and... Figure 8 The operation method of memory 20 is explained below. Non-target memory cell 210b and target memory cell 210a are connected to the same word line 213 and the same third metal line 223; non-target memory cell 210c and target memory cell 210a are connected to the same bit line, namely the first metal line 260.

[0073]

[0074] Table 1

[0075] In some embodiments, the write operation further includes:

[0076] A first voltage V1 is applied to the substrate 200 to maintain the non-breakdown state of the selection transistor.

[0077] In this embodiment, to prevent a large voltage (e.g., HV) applied through the first metal line 260 to the first doped region 201 and the second doped region 202 from causing reverse breakdown of the PN junction in the select transistor 240, a first voltage V1 can be applied to the substrate 200. The first voltage V1 can be HV / 2. It is understood that the first voltage V1 can be applied simultaneously to the substrates of the select transistors 240 in multiple memory cells 210 to simplify the operation of the memory 20.

[0078] In some embodiments, the process of breaking down a target antifuse bit structure 250a in the antifuse bit structure 250 of the memory, causing the target antifuse bit structure 250a to switch from a non-breakdown state to a breakdown state, includes:

[0079] A second voltage V2 is applied to the first gate electrode 211a of the select transistor 240a connected to the target antifuse site structure 250a to turn on the select transistor 240a; a third voltage V3 is applied to the first metal line 260 connected to the select transistor 240a; the difference between the third voltage V3 and the second voltage V2 is less than the breakdown voltage HV of the first gate dielectric layer;

[0080] A fourth voltage V4 is applied to the second gate electrode 221a of the target antifuse site structure 250a to switch the target antifuse site structure 250a from a non-breakdown state to a breakdown state; wherein the voltage difference between the third voltage V3 and the fourth voltage V4 is greater than or equal to the breakdown voltage HV of the second gate dielectric layer.

[0081] In this embodiment of the disclosure, data can be written by breaking down the target antifuse bit structure 250a in the target storage cell 210a. Specifically, as... Figure 8As shown, a second voltage V2 is applied to the first gate electrode 211a of the select transistor 240a connected to the target antifuse bit structure 250a, i.e., a second voltage V2 is applied to the word line 213, turning on the select transistor 240a. Optionally, the second voltage V2 here can be the breakdown voltage HV. Simultaneously, a third voltage V3 is applied to the first metal line 260 connected to the select transistor 240a, and a fourth voltage V4 is applied to the second gate electrode 221a of the target antifuse bit structure 250a, i.e., a fourth voltage V4 is applied to the third metal line 223. Thus, the third voltage V3 is applied from the turned-on select transistor 240a to the second doped region 202a of the target antifuse bit structure 250a. The voltage difference between the third voltage V3 and the fourth voltage V4 is greater than or equal to the breakdown voltage HV, causing the target antifuse bit structure 250a to switch from a non-breakdown state to a breakdown state. Optionally, the third voltage V3 here can be the breakdown voltage HV, while the fourth voltage V4 can be 0V. It is understandable that, since a second voltage V2 is applied to the first gate electrode 211a and a third voltage V3 is applied to the first doped region 201a, the voltage difference between the first gate electrode 211a and the first doped region 201a is 0V, which is less than the breakdown voltage HV of the first gate dielectric layer, thus ensuring that the first gate dielectric layer is not accidentally broken down.

[0082] In some embodiments, maintaining the non-breakdown state of the non-target antifuse site structure includes:

[0083] The second voltage V2 is applied to the first gate electrode 211b of the select transistor 240b connected to the non-target antifuse bit structure 250b to turn on the select transistor 240b; the first voltage V1 is applied to the first metal line 260b connected to the select transistor 240b; the difference between the first voltage V1 and the second voltage V2 is less than the breakdown voltage HV of the first gate dielectric layer;

[0084] A fourth voltage V4 is applied to the second gate electrode 221b of the non-target antifuse site structure 250b to keep the non-target antifuse site structure 250b in a non-breakdown state; wherein the voltage difference between the first voltage V1 and the fourth voltage V4 is less than the breakdown voltage HV of the second gate dielectric layer.

[0085] In this embodiment of the disclosure, when the target antifuse bit structure 250a in the target memory cell 210a is broken down, it is also necessary to maintain the non-breakdown state of the non-target antifuse bit structure 250b in the non-target memory cell 210b. Specifically, as Figure 8As shown, for a non-target memory cell 210b connected to the same word line 213 and the same third metal line 223 as the target memory cell 210a, since a second voltage V2 is applied to the first gate electrode 211b of the select transistor 240b connected to the non-target antifuse bit structure 250b, and the select transistor 240b is turned on, it is necessary to ensure that the voltage difference between the second doped region 202b and the second gate electrode 221b of the non-target antifuse bit structure 250b is less than the breakdown voltage HV. Therefore, a first voltage V1 is applied to the first metal line 260b connected to the select transistor 240b. Thus, the first voltage V1 is applied from the turned-on select transistor 240b to the second doped region 202b of the non-target antifuse bit structure 250b. The voltage difference between the fourth voltage V4 on the second gate electrode 221b and the first voltage V1 on the second doped region 202b is less than the breakdown voltage HV, so that the non-target antifuse bit structure 250b remains in a non-breakdown state. Optionally, the second voltage V2 can be the breakdown voltage HV, the first voltage V1 can be HV / 2, and the fourth voltage V4 can be 0V. It is understood that since the second voltage V2 is applied to the first gate electrode 211b and the first voltage V1 is applied to the first doped region 201b, the voltage difference between the first gate electrode 211b and the first doped region 201b is HV / 2, which is less than the breakdown voltage HV of the first gate dielectric layer, ensuring that the first gate dielectric layer is not accidentally broken down.

[0086] In some embodiments, maintaining the non-breakdown state of the non-target antifuse site structure includes:

[0087] A cutoff voltage Voff is applied to the first gate electrode 211c of the select transistor 240c connected to the non-target antifuse bit structure 250c to cut off the select transistor 240c; a third voltage V3 is applied to the first metal line 260 connected to the select transistor 240c; the difference between the third voltage V3 and the cutoff voltage Voff is less than the breakdown voltage HV of the first gate dielectric layer.

[0088] A first voltage V1 is applied to the second gate electrode 221c of the non-target antifuse site structure 250c to keep the non-target antifuse site structure 250c in a non-breakdown state; wherein the difference between the third voltage V3 and the first voltage V1 is less than the breakdown voltage HV of the second gate dielectric layer.

[0089] In this embodiment of the disclosure, when the target antifuse bit structure 250a in the target memory cell 210a is broken down, it is also necessary to maintain the non-breakdown state of the non-target antifuse bit structure 250c in the non-target memory cell 210c. Specifically, as Figure 8As shown, the non-target memory cell 210c and the target memory cell 210a are connected to the same first metal line 260, i.e., the bit line. Since a third voltage V3 is applied to the first metal line 260 connected to the non-target antifuse bit structure 250c, a cutoff voltage Voff can be applied to the first gate electrode 211c of the select transistor 240c connected to the non-target antifuse bit structure 250c, i.e., a cutoff voltage Voff is applied to the word line 213c, to cut off the select transistor 240c. At this time, the third voltage V3 cannot be transmitted to the second doped region 202c through the select transistor 240c. At the same time, a first voltage V1 can also be applied to the second gate electrode 221c of the non-target antifuse bit structure 250c, i.e., a first voltage V1 is applied to the third metal line 223c, and the difference between the third voltage V3 and the first voltage V1 is less than the breakdown voltage HV of the second gate dielectric layer, further ensuring that the non-target antifuse bit structure 250c is not broken down. Optionally, the cutoff voltage Voff can be HV / 2, the first voltage V1 can be HV / 2, and the third voltage V3 can be the breakdown voltage HV. It is understood that since a cutoff voltage Voff is applied to the first gate electrode 211c, and a third voltage V3 is applied to the first doped region 201c, the voltage difference between the first gate electrode 211c and the first doped region 201c is HV / 2, which is less than the breakdown voltage HV of the first gate dielectric layer, ensuring that the first gate dielectric layer is not accidentally broken down.

[0090] In some embodiments, the method further includes: performing a read operation on the memory, the read operation including: grounding the substrate 200; applying a first read voltage Vwlr to the first gate electrode 211 of the select transistor 240 connected to the antifuse bit structure 250 to turn on the select transistor 240; applying a second read voltage Vblr to the first metal line 260 connected to the select transistor 240; and detecting the current on the first metal line 260.

[0091]

[0092] Table 2

[0093] In this embodiment, the memory 20 can also be written and read according to the operating voltages shown in Table 2. Here, Vblr is the second read voltage Vblr for the first metal line 260, i.e., the bit line; Vwlr is the first read voltage Vwlr for the word line 213. When Vwlr is applied to the word line 213, i.e., the first gate electrode 211, the selection transistor 240 is turned on; at this time, the substrate 200 is grounded, i.e., the voltage on the substrate 200 is 0V, Vblr is applied to the first metal line 260, and 0V is applied to the third metal line 223, i.e., the second gate electrode 221; thus, by detecting the current on the first metal line 260, it can be determined whether the antifuse bit structure 250 is in a breakdown state or a non-breakdown state, thereby realizing the read operation.

[0094] In some embodiments, since the overlap between the second doped region and the antifuse electrode is small, the breakdown voltage required is small. Therefore, a smaller voltage can be applied to the substrate, word line structure, antifuse electrode, and first metal line in the memory, and the duration of the applied voltage is short, thereby saving energy.

[0095] It should be noted that the features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first gate structure and a second gate structure are located on the surface of the substrate; the second gate structure has the same thickness as the first gate structure but is less than a predetermined thickness. A first doped region and a second doped region are located in the substrate, and the first doped region and the second doped region are respectively located on both sides of the first gate structure; the first gate structure, the first doped region and the second doped region constitute a selection transistor; The orthogonal projection of the second gate structure onto the substrate at least partially overlaps with the second doped region; the second gate structure and the second doped region constitute an antifuse bit structure; the breakdown state and non-breakdown state of the antifuse bit structure are used to represent different stored data; A first metal line is located above the first gate structure and the second gate structure; the first metal line is connected to the first doped region through a first connection structure. The second metal line is located between the first gate structure and the first metal line; the second metal line is connected to the substrate through a second connection structure.

2. The semiconductor structure according to claim 1, characterized in that, The first gate structure includes a first gate electrode and a first gate dielectric layer located below the first gate electrode; the second gate structure includes a second gate electrode and a second gate dielectric layer located below the second gate electrode. The first gate dielectric layer and the second gate dielectric layer have the same thickness, and the first gate dielectric layer and the second gate dielectric layer are predetermined thin gate oxide structures.

3. The semiconductor structure according to claim 1, characterized in that, Also includes: An isolation structure is located in the substrate between two adjacent antifuse site structures; wherein at least a portion of the second connection structure is located on the isolation structure.

4. The semiconductor structure according to claim 3, characterized in that, Also includes: The third doped region is located in the substrate on both sides of the isolation structure; The second connection structure is connected to the substrate through the third doped region.

5. The semiconductor structure according to claim 1, characterized in that, Also includes: The word line is located above the first gate structure; The word line connects to a plurality of first gate structures located in the word line extension direction; A third metal line is located above the second gate structure, and the extension direction of the third metal line is parallel to the extension direction of the word line. The third metal line connects to a plurality of second gate structures located in the extension direction of the third metal line.

6. The semiconductor structure according to claim 1, characterized in that, The two adjacent selection transistors are symmetrically arranged and share the same first doped region.

7. A method for operating a memory, characterized in that, The memory comprises the semiconductor structure according to any one of claims 1 to 6; the method comprises: Based on the data to be written, a write operation is performed on the memory, the write operation including: The target antifuse bit structure in the antifuse bit structure of the memory is broken down, causing the target antifuse bit structure to switch from a non-breakdown state to a breakdown state; And maintain the non-breakdown state of the non-target antifuse position structure; wherein, the non-target antifuse position structure is an antifuse position structure other than the target antifuse position structure.

8. The method according to claim 7, characterized in that, The write operation also includes: A first voltage is applied to the substrate to maintain the non-breakdown state of the selection transistor.

9. The method according to claim 7, characterized in that, The process of breaking down a target antifuse bit structure in the antifuse bit structure of the memory, causing the target antifuse bit structure to switch from a non-breakdown state to a breakdown state, includes: A second voltage is applied to the first gate electrode of the select transistor connected to the target antifuse bit structure to turn on the select transistor; a third voltage is applied to the first metal line connected to the select transistor; the difference between the third voltage and the second voltage is less than the breakdown voltage of the first gate dielectric layer; A fourth voltage is applied to the second gate electrode of the target antifuse site structure to switch the target antifuse site structure from a non-breakdown state to a breakdown state; wherein the voltage difference between the third voltage and the fourth voltage is greater than or equal to the breakdown voltage of the second gate dielectric layer.

10. The method according to claim 7, characterized in that, Maintaining the non-breakdown state of the non-target antifuse site structure includes: A second voltage is applied to the first gate electrode of the select transistor connected to the non-target antifuse bit structure to turn on the select transistor; a first voltage is applied to the first metal line connected to the select transistor; the difference between the first voltage and the second voltage is less than the breakdown voltage of the first gate dielectric layer; A fourth voltage is applied to the second gate electrode of the non-target antifuse site structure to keep the non-target antifuse site structure in a non-breakdown state; wherein the voltage difference between the first voltage and the fourth voltage is less than the breakdown voltage of the second gate dielectric layer.

11. The method according to claim 7, characterized in that, Maintaining the non-breakdown state of the non-target antifuse site structure includes: A cutoff voltage is applied to the first gate electrode of the select transistor connected to the non-target antifuse bit structure to turn off the select transistor; a third voltage is applied to the first metal line connected to the select transistor; the difference between the third voltage and the cutoff voltage is less than the breakdown voltage of the first gate dielectric layer; A first voltage is applied to the second gate electrode of the non-target antifuse site structure to keep the non-target antifuse site structure in a non-breakdown state; wherein the voltage difference between the third voltage and the first voltage is less than the breakdown voltage of the second gate dielectric layer.

12. The method according to claim 7, characterized in that, Also includes: Perform a read operation on the memory, the read operation including: Ground the substrate; A first read voltage is applied to the first gate electrode of the select transistor connected to the antifuse bit structure to turn on the select transistor; A second read voltage is applied to the first metal line connected to the selection transistor; The current on the first metal wire is detected.

13. A memory, characterized in that, include: A memory array, wherein the memory array includes the semiconductor structure as described in any one of claims 1 to 6; Peripheral circuitry coupled to the storage array.

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