Three-dimensional vertical memristor and preparation method thereof

Abstract

The application provides a three-dimensional vertical memristor and a preparation method thereof. The three-dimensional vertical memristor comprises a substrate, insulating layers and word line layers which are alternately stacked on the substrate, the insulating layers comprise at least three layers, the word line layers comprise at least two layers, the ability of at least one word line layer to capture oxygen ions is greater than or equal to a first preset value, the ability of at least one word line layer to capture oxygen ions is less than the first preset value, a channel penetrates through the insulating layers and the word line layers, a storage layer, a selection layer and a bit line layer are located on the sidewall of the channel, the selection layer is located on the side of the storage layer away from the sidewall of the channel, and the bit line layer is located on the side of the selection layer away from the channel. By arranging the word line layers with different abilities to capture oxygen ions, the word line layers with strong ability to capture oxygen ions exhibit non-volatile characteristics, the word line layers with weak ability to capture oxygen ions exhibit dynamic characteristics, and a three-dimensional memristor array with different characteristics is realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a three-dimensional vertical memristor and its fabrication method. Background Technology

[0002] Humans can efficiently and flexibly perceive the external physical world through various senses such as sight, touch, hearing, smell, and taste. The neural networks in our brains gather and process the information collected by these senses, enabling us to explore, understand, and learn. Specifically, sensory neurons in the human multisensory neural network (such as gustatory neurons) convert physical stimuli into impulse signals, which are then transmitted to the cerebral cortex for further processing.

[0003] In recent years, with the development of wearable devices and the Internet of Things (IoT), the types and numbers of sensor nodes have increased dramatically, generating a large amount of sensor data that requires efficient, real-time processing. However, unlike efficient human sensing systems, traditional sensing systems suffer from high energy consumption and low efficiency in data acquisition and processing. Therefore, an increasing number of studies are attempting to emulate human perception of the world by creating hardware systems capable of efficiently processing various physical signals.

[0004] Inspired by biology, scientists have developed neuromorphic perception systems that promise to effectively process multi-sensory signals from the physical world. Realizing such systems requires combining sensors with artificial synapses and neurons. However, to date, we still lack hardware capable of efficiently sensing and pulse-coding multiple physical signals.

[0005] Among emerging devices, memristors, with their rich ion dynamics, are being used to mimic the functions of synapses and neurons. By combining memristors with sensors, researchers have demonstrated that such neuromorphic sensing systems can process sensory information, such as tactile, visual, and nociceptive information.

[0006] However, these artificial neurons can currently only process single physical signals. For example, convolutional neural networks (CNNs) using non-volatile memristors (NVMs) are widely used for static information recognition, such as image recognition and object detection, and can only be used to simulate the human eye. Delay feedback reservoirs (DFRs) using dynamic memristors can process time-related information, such as speech recognition, and can only be used to simulate the human ear.

[0007] Non-volatile memristors and dynamic memristors are discrete arrays, with one array possessing only non-volatile characteristics or only dynamic characteristics. To date, no research has been able to integrate non-volatile and dynamic memristors onto the same three-dimensional array, enabling devices in different layers to possess different characteristics.

[0008] Therefore, how to realize a three-dimensional memristor array with different characteristics to meet the high-density, miniaturization and multi-functional requirements of hardware systems brought about by the rapid development of the Internet of Things is a technical problem that needs to be solved in this field. Summary of the Invention

[0009] In view of this, a summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0010] The purpose of this application is to provide a three-dimensional vertical memristor and its fabrication method, which can realize a three-dimensional memristor array with different characteristics to meet the high-density, miniaturization and multi-functional requirements of hardware systems brought about by the rapid development of the Internet of Things.

[0011] To achieve the above objectives, this application provides the following technical solution:

[0012] In a first aspect, embodiments of this application provide a three-dimensional vertical memristor, comprising:

[0013] Substrate;

[0014] An insulating layer and a word line layer are alternately stacked on the substrate; the insulating layer comprises at least three layers; the word line layer comprises at least two layers; at least one word line layer has an oxygen ion capture capability greater than or equal to a first preset value; at least one word line layer has an oxygen ion capture capability less than the first preset value.

[0015] A channel penetrating the insulating layer and the word line layer;

[0016] A storage layer, a selection layer, and a bit line layer are located on the sidewall of the channel; the selection layer is located on the side of the storage layer away from the sidewall of the channel; the bit line layer is located on the side of the selection layer away from the sidewall of the channel.

[0017] In one possible implementation, the material of at least one word line layer includes TiN or Ru; the material of at least one word line layer includes W.

[0018] The ability of TiN or Ru to capture oxygen ions is less than the first preset value;

[0019] The ability of W to capture oxygen ions is greater than or equal to the first preset value.

[0020] In one possible implementation, the material of the word line layer includes TiN, Ru, W, TaN, Mo, Ta, Al, Ir, Pd, Pt, Cu, Ti, Co, Mo, Ni, Nb, or IrO2.

[0021] In one possible implementation, the material of the insulating layer includes SiN, SiO, SiON, SiO2, C-doped SiO2, P-doped SiO2, or F-doped SiO2.

[0022] In one possible implementation, the material of the storage layer includes HfO. x ,TaO x , HZO or ZrO x The material of the selection layer includes TiO2 or Al2O3; the material of the bit line layer includes TiN, W, Pt, Ru, TaN, Mo, Ta, Al, Au, Ir, Pd or Pt.

[0023] In one possible implementation, the thickness of one word line layer is [5nm, 10nm]; the thickness of one insulating layer is [10nm, 200nm]; the thickness of the memory layer is [2nm, 15nm]; and the thickness of the select layer is [5nm, 20nm].

[0024] Secondly, embodiments of this application provide a method for fabricating a three-dimensional vertical memristor, including:

[0025] Provide substrate;

[0026] Alternating layers of insulating layers and word line layers are formed on the substrate; the insulating layers comprise at least three layers; the word line layers comprise at least two layers; at least one word line layer has an oxygen ion capture capability greater than or equal to a first preset value; at least one word line layer has an oxygen ion capture capability less than the first preset value.

[0027] Etch the insulating layer and the word line layer to form a channel penetrating the insulating layer and the word line layer;

[0028] A storage layer, a selection layer, and a bit line layer are sequentially formed on the sidewall of the channel.

[0029] In one possible implementation, the word line layer is formed by chemical electroplating, magnetron sputtering, chemical vapor deposition, physical vapor deposition, pulsed laser, atomic layer deposition, or electron beam evaporation.

[0030] In one possible implementation, the etching includes ion beam etching, dry etching, or wet etching.

[0031] In one possible implementation, the insulating layer is formed by sputtering or chemical vapor deposition.

[0032] Compared with the prior art, the embodiments of this application have the following beneficial effects:

[0033] This application provides a three-dimensional vertical memristor and its fabrication method. The three-dimensional vertical memristor includes: a substrate; an insulating layer and a word line layer alternately stacked on the substrate; the insulating layer includes at least three layers; the word line layer includes at least two layers; at least one word line layer has an oxygen ion capture capability greater than or equal to a first preset value; at least one word line layer has an oxygen ion capture capability less than the first preset value; a channel penetrating the insulating layer and the word line layer; a storage layer, a select layer, and a bit line layer located on the sidewall of the channel; the select layer is located on the sidewall of the storage layer away from the channel; the bit line layer is located on the side of the select layer away from the channel. This application achieves a three-dimensional memristor array with different oxygen ion capture capabilities by setting word line layers with strong oxygen ion capture capabilities, exhibiting non-volatile characteristics, and word line layers with weak oxygen ion capture capabilities exhibiting dynamic characteristics. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent when taken in conjunction with the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0036] Figure 1 This illustration shows a cross-sectional structural diagram of a three-dimensional vertical memristor structure provided in an embodiment of this application;

[0037] Figure 2 A schematic diagram of a reservoir calculation provided in an embodiment of this application is shown;

[0038] Figure 3 A schematic diagram of a convolutional neural network provided in an embodiment of this application is shown;

[0039] Figure 4 A schematic diagram of an echo state network provided in an embodiment of this application is shown;

[0040] Figure 5This illustration shows a line scan diagram of the first word line layer to the oxide layer of a first-layer device according to an embodiment of this application.

[0041] Figure 6 This illustration shows a line scan diagram of the second word line layer to the oxide layer of a second-layer device according to an embodiment of this application.

[0042] Figure 7 This illustration shows a line scan diagram of the third word line layer to the oxide layer of a third-layer device according to an embodiment of this application;

[0043] Figure 8 This application provides a voltage-current curve diagram of a first-layer device according to an embodiment of the present application.

[0044] Figure 9 This paper shows a dynamic characteristic diagram of a first-layer device under a pulse according to an embodiment of this application;

[0045] Figure 10 This application provides a voltage-current curve diagram of a second-layer device according to an embodiment of the present application.

[0046] Figure 11 The diagram shows the dynamic characteristics of a second-layer device under pulse according to an embodiment of this application;

[0047] Figure 12 This application provides a voltage-current curve diagram of a third-layer device according to an embodiment of the present application.

[0048] Figure 13 This paper illustrates a diagram showing the retention characteristics of multiple states of a second-layer device according to an embodiment of this application.

[0049] Figure 14 A flowchart illustrating a method for fabricating a three-dimensional vertical memristor according to an embodiment of this application is shown. Detailed Implementation

[0050] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0051] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0052] As described in the background section, the applicant's research has found that humans can efficiently and flexibly perceive the external physical world through different senses such as sight, touch, hearing, smell, and taste. The neural networks in our brains gather and process the information collected by these senses, enabling us to explore, understand, and learn. Specifically, sensory neurons in the human multi-sensory neural network (such as gustatory sensory neurons) convert physical stimuli into pulse signals, which are then transmitted to the cerebral cortex for further processing.

[0053] In recent years, with the development of wearable devices and the Internet of Things (IoT), the types and numbers of sensor nodes have increased dramatically, generating a large amount of sensor data that requires efficient, real-time processing. However, unlike efficient human sensing systems, traditional sensing systems suffer from high energy consumption and low efficiency in data acquisition and processing. Therefore, an increasing number of studies are attempting to emulate human perception of the world by creating hardware systems capable of efficiently processing various physical signals.

[0054] Inspired by biology, scientists have developed neuromorphic perception systems that promise to effectively process multi-sensory signals from the physical world. Realizing such systems requires combining sensors with artificial synapses and neurons. However, to date, we still lack hardware capable of efficiently sensing and pulse-coding multiple physical signals.

[0055] Among emerging devices, memristors, with their rich ion dynamics, are being used to mimic the functions of synapses and neurons. By combining memristors with sensors, researchers have demonstrated that such neuromorphic sensing systems can process sensory information, such as tactile, visual, and nociceptive information.

[0056] However, these artificial neurons can currently only process single physical signals. For example, convolutional neural networks (CNNs) using non-volatile memristors (NVMs) are widely used for static information recognition, such as image recognition and object detection, and can only be used to simulate the human eye. Delay feedback reservoirs (DFRs) using dynamic memristors can process time-related information, such as speech recognition, and can only be used to simulate the human ear.

[0057] Non-volatile memristors and dynamic memristors are discrete arrays, with one array possessing only non-volatile characteristics or only dynamic characteristics. To date, no research has been able to integrate non-volatile and dynamic memristors onto the same three-dimensional array, enabling devices in different layers to possess different characteristics.

[0058] Therefore, how to realize a three-dimensional memristor array with different characteristics to meet the high-density, miniaturization and multi-functional requirements of hardware systems brought about by the rapid development of the Internet of Things is a technical problem that needs to be solved in this field.

[0059] To address the above technical problems, this application provides a three-dimensional vertical memristor and its fabrication method. The three-dimensional vertical memristor includes: a substrate; alternating layers of insulating and word lines on the substrate; at least three insulating layers; at least two word lines; at least one word line layer has an oxygen ion capture capability greater than or equal to a first preset value; at least one word line layer has an oxygen ion capture capability less than the first preset value; a channel penetrating the insulating and word lines; a storage layer, a select layer, and a bit line layer located on the sidewall of the channel; the select layer is located on the sidewall of the storage layer away from the channel; the bit line layer is located on the side of the select layer away from the channel. This application achieves a three-dimensional memristor array with different oxygen ion capture capabilities by setting word lines with strong oxygen ion capture capabilities, exhibiting non-volatile characteristics, and word lines with weak oxygen ion capture capabilities exhibiting dynamic characteristics.

[0060] Exemplary devices

[0061] See Figure 1 The diagram shown is a cross-sectional view of a three-dimensional vertical memristor structure provided in an embodiment of this application, including:

[0062] Substrate 1; insulating layer 2 and word line layer 3 (WL) alternately stacked on substrate 1; insulating layer 2 includes at least three layers; word line layer 3 includes at least two layers; that is, insulating layer 2 is provided on both sides of each word line layer 3, at least one word line layer 3 has an oxygen ion capture capability greater than or equal to a first preset value; at least one word line layer 3 has an oxygen ion capture capability less than the first preset value.

[0063] Channel 4 runs through insulating layer 2 and word line layer 3; storage layer 5, select layer 6 and bit line layer 7 (BL) are located on the sidewall of channel 4; select layer 6 is located on the sidewall of storage layer 5 away from channel 4; bit line layer 7 is located on the sidewall of select layer 6 away from channel 4.

[0064] Specifically, the substrate 1 provided in this embodiment may include a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). In this embodiment, substrate 1 is a bulk silicon substrate.

[0065] Optionally, the material of the insulating layer 2 provided in this application embodiment may include SiN, SiO, SiON, SiO2, C-doped SiO2, P-doped SiO2, or F-doped SiO2. Optionally, the material of the word line layer 3 provided in this application embodiment may include TiN, Ru, W, TaN, Mo, Ta, Al, Ir, Pd, Pt, Cu, Ti, Co, Mo, Ni, Nb, or IrO2.

[0066] In this embodiment, since the ability of at least one word line layer 3 to capture oxygen ions is greater than or equal to a first preset value, oxygen ions can be captured more effectively, making the device exhibit non-volatile characteristics. Simultaneously, since the ability of at least one word line layer 3 to capture oxygen ions is less than the first preset value, oxygen ions spontaneously diffuse and relax, making the device exhibit volatile characteristics, i.e., dynamic characteristics.

[0067] It should be noted that the embodiments of this application do not specifically limit the size of the first preset value, which can be set by those skilled in the art according to the actual situation.

[0068] Therefore, embodiments of this application can employ layered devices exhibiting dynamic characteristics to simulate the cell body of neurons, mimicking the firing behavior of neurons, and construct neuromorphic computing systems based on dynamic memristors, such as Spiking Neural Networks (SNNs) and Reservoir Computing (RCs) (not limited to SNNs and RCs), for processing speech signals, performing time series prediction, etc. See also Figure 2 The diagram shown is a schematic diagram of a reservoir calculation provided in an embodiment of this application, in which the reservoir calculation is performed through input and output.

[0069] Furthermore, embodiments of this application can utilize layered devices exhibiting non-volatile characteristics to construct neuromorphic computing networks based on non-volatile memristors, such as Convolutional Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and Echo State Networks (ESNs), for processing static information, such as image recognition. See also... Figure 3 The diagram shown is a schematic representation of a convolutional neural network provided in an embodiment of this application. See also... Figure 4 The diagram shown is a schematic of an echo state network provided in an embodiment of this application, including an input layer, a dynamic memory, and an output layer. The input layer can input a fixed weight and output a training weight to the output layer.

[0070] Optionally, the material of the storage layer 5 provided in this application embodiment may include HfO. x ,TaO x , HZO or ZrO x The material of the selection layer 6 may include TiO2 or Al2O3; the material of the bit line layer 7 may include TiN, W, Pt, Ru, TaN, Mo, Ta, Al, Au, Ir, Pd or Pt.

[0071] In this embodiment, the height of the Schottky barrier can be adjusted by controlling the ion concentration of the storage layer 5, the selection layer 6 can be used to suppress interlayer leakage, and the bit line layer 7 serves as a conductive connection for the device.

[0072] Optionally, the thickness of the word line layer 3 provided in this embodiment can be [5nm, 10nm]; the thickness of the insulating layer 2 can be [10nm, 200nm]; the thickness of the storage layer 5 can be [2nm, 15nm]; and the thickness of the select layer 6 can be [5nm, 20nm].

[0073] In one possible implementation, see Figure 1 As shown, the material of at least one word line layer 3 in this application embodiment may include TiN or Ru; the material of at least one word line layer 3 may include W; the ability of TiN or Ru to capture oxygen ions is less than a first preset value; the ability of W to capture oxygen ions is greater than or equal to the first preset value.

[0074] For details, see Figure 1As shown, word line layer 3 may include a first word line layer 31, a second word line layer 32 and a third word line layer 33. The material of the first word line layer 31 may be TiN, the material of the second word line layer 32 may be Ru, and the material of the third word line layer 33 may be W.

[0075] The electron affinity of an element reflects how easily its atoms gain electrons; the higher the electron affinity, the more difficult it is to gain electrons. The electron affinity of Ti is 8.4 kJ / mol, that of W is 79 kJ / mol, and that of Ru is 101 kJ / mol.

[0076] The work function refers to the minimum energy required to move an electron from the interior of a solid to its surface. The work function of Ti is 4.33 eV, that of W is 4.55 eV, and that of Ru is 4.71 eV.

[0077] Ti has the lowest electron affinity and the lowest work function, so it oxidizes naturally in air at room temperature. Using TiN as the first word line layer material in the first layer of the device forms the thickest oxide layer (Ti). x O y N z (7.4nm), followed by the oxide layer formed by the third layer device using W as the third word line material (WO). x (5.2nm), the thinnest layer is the oxide layer formed by the second device layer using Ru as the second word line material (RuO). x :1nm).

[0078] See Figure 5 The diagram shown is a line scan schematic of the first word line layer 31 to the oxide layer of a first-layer device provided in an embodiment of this application. See also... Figure 6 The diagram shown is a line scan schematic of the second word line layer 32 to the oxide layer of a second-layer device provided in an embodiment of this application. See also... Figure 7 The diagram shown is a line scan schematic of the third word line layer 33 to the oxide layer of a third-layer device provided in an embodiment of this application.

[0079] Figure 5-7 The image provides an energy dispersive spectrometer (EDS) line, where the horizontal axis represents position and the vertical axis represents intensity, showing the relationship between each layer of the device and HfO. x In comparison, it can be seen that 7.4nm TiON oxygen-rich (O-rich TiON) exhibits volatile characteristics, while 1nm RuO... xUltra-thin RuOx exhibits volatile characteristics; 5.2nm WO3... x Hypoxia exhibits non-volatile characteristics.

[0080] Specifically, Ti with sufficient oxygen content x O y N z (Layer 1) and excessively thin RuO x (The second layer) can only introduce shallow-level defects. Therefore, after the voltage is removed, oxygen ions spontaneously diffuse and relax, resulting in volatile characteristics in devices with the first and second layers. Meanwhile, WO3 in an oxygen-deficient state... x It can better capture oxygen ions and exhibits non-volatile properties.

[0081] See Figure 8 The figure shown is a voltage-current curve of a first-layer device provided in an embodiment of this application. See also... Figure 9 The diagram shown is a dynamic characteristic diagram of a first-layer device under pulse according to an embodiment of this application.

[0082] See Figure 8 As shown, the horizontal axis represents voltage (Voltage (V)) and the vertical axis represents current (A) . The devices in the first layer are subjected to three consecutive positive voltage scans (1... st sweep, 2 nd sweep and 3 rd sweep), such as Figure 8 As shown, the device exhibits "memory loss"; the gradual change in conductance can be observed more intuitively under pulsed conditions.

[0083] See Figure 9 As shown, the horizontal axis represents time (Time (µs)) and the vertical axis represents read current (nA). When a 2V pulse is applied, the device's conductance gradually increases. After the 2V programming voltage is removed, at a read voltage of 0.5V, the device's conductance cannot be maintained and gradually decreases back to its initial state. This is due to the Ti in the first layer of the device. x O y N z When in an "oxygen-rich" state, its ability to capture oxygen ions is relatively weak. This gradual change in conductivity can be expressed by the formula... The fitting is performed, where τ1st = 1.66us, which means that the characteristic time constant of the relaxation characteristics of the first layer device is 1.66us.

[0084] Similarly, see Figure 10 The figure shown is a voltage-current curve of a second-layer device provided in an embodiment of this application. See also... Figure 11The diagram shown is a dynamic characteristic diagram of a second-layer device under pulse according to an embodiment of this application.

[0085] Three consecutive positive voltage scans are applied to the devices in the second layer, such as... Figure 10 As shown, compared to the first-layer device 9, the second-layer device exhibits a more significant "memory loss," which is due to the RuO oxide layer of the second-layer device. x (1nm) compared to the first layer Ti x O y N z The second layer is 7.4 nm thinner, allowing oxygen ions to diffuse more easily. Therefore, the time constant of the relaxation characteristics of the second layer device (0.93 μs) is smaller than that of the first layer. Figure 11 As shown.

[0086] See Figure 12 The figure shown is a voltage-current curve of a third-layer device provided in an embodiment of this application. See also... Figure 13 The diagram shown illustrates the retention characteristics of multiple states of a second-layer device according to an embodiment of this application.

[0087] The voltage-current curves of the third-layer device under DC scanning conditions are as follows: Figure 12 As shown, due to the WO of the 3rd layer x The third layer device is in an "oxygen-deficient" state, exhibiting a strong ability to capture oxygen ions. Therefore, it displays non-volatile characteristics, possesses multiple states, and has good retention properties, as shown in the figure. Figure 13 As shown.

[0088] Therefore, the different properties (volatile or non-volatile characteristics) exhibited by each layer are related to the electron affinity, work function, thickness of the oxide layer formed by natural oxidation, and oxygen content of each word line layer material. Furthermore, the operating voltages of devices in each layer are also different. Therefore, all of the above factors should be considered comprehensively, and a suitable word line material should be selected based on the actual application requirements. This application does not impose specific limitations on the embodiments herein; the specific material selection can be made by those skilled in the art based on the actual situation.

[0089] This application provides a three-dimensional vertical memristor, comprising: a substrate; an insulating layer and a word line layer alternately stacked on the substrate; the insulating layer comprising at least three layers; the word line layer comprising at least two layers; at least one word line layer having an oxygen ion capture capability greater than or equal to a first preset value; at least one word line layer having an oxygen ion capture capability less than the first preset value; a channel penetrating the insulating layer and the word line layer; a storage layer, a select layer, and a bit line layer located on the sidewall of the channel; the select layer being located on the sidewall of the storage layer away from the channel; and the bit line layer being located on the side of the select layer away from the channel. This application achieves a three-dimensional memristor array with different oxygen ion capture capabilities by setting word line layers with strong oxygen ion capture capabilities, exhibiting non-volatile characteristics, and word line layers with weak oxygen ion capture capabilities exhibiting dynamic characteristics.

[0090] Exemplary methods

[0091] See Figure 14 The diagram shown is a flowchart of a method for fabricating a three-dimensional vertical memristor according to an embodiment of this application, including:

[0092] S101: Provides a substrate.

[0093] S102: An alternating layer of insulating layer and word line layer is formed on the substrate; the insulating layer comprises at least three layers; the word line layer comprises at least two layers; the ability of at least one word line layer to capture oxygen ions is greater than or equal to a first preset value; the ability of at least one word line layer to capture oxygen ions is less than the first preset value.

[0094] S103: Etch the insulating layer and the word line layer to form a channel penetrating the insulating layer and the word line layer.

[0095] S104: A storage layer, a selection layer, and a bit line layer are sequentially formed on the sidewall of the channel.

[0096] In one possible implementation, the word line layer is formed by chemical electroplating, magnetron sputtering, chemical vapor deposition, physical vapor deposition, pulsed laser, atomic layer deposition, or electron beam evaporation.

[0097] In one possible implementation, the etching includes ion beam etching, dry etching, or wet etching.

[0098] Specifically, taking SiO2 as the insulating layer as an example, this application embodiment can use positive adhesive, negative adhesive, or metal as a mask, and use ion beam etching, dry etching, or wet etching to etch down to the bottom SiO2 layer in one step. In this embodiment:

[0099] The insulating layer SiO2 (30nm) was etched using dry etching conditions: octafluoropropane 20 sccm, sulfur hexafluoride 2 sccm, power 50W / 500W, time 9s; the metal W (20nm) was etched using dry etching conditions: argon 10 sccm, sulfur hexafluoride 10 sccm, power 20W / 300W, time 15s; the metal Ru (20nm) was etched using ion beam etching for 1 min 30s with an ion energy of 500 eV; the TiN (20nm) was etched using dry etching conditions: octafluoropropane 20 sccm, sulfur hexafluoride 2 sccm, power 50W / 500W, time 12s; the etching reached the bottom SiO2 layer, forming trenches to separate the planar electrodes.

[0100] In one possible implementation, the insulating layer is formed by sputtering or chemical vapor deposition. In another possible implementation, various storage layers are grown using methods such as atomic layer deposition, magnetron sputtering, or ion beam sputtering. In one possible implementation, a self-aligned selection layer is grown using methods such as atomic layer deposition of metal or oxygen plasma. In one possible implementation, the deposited bit line layer can be prepared using any of the following methods: electron beam evaporation, magnetron sputtering, ion beam sputtering, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and electroplating.

[0101] This application provides a method for fabricating a three-dimensional vertical memristor. The three-dimensional vertical memristor formed by this method includes: a substrate; an insulating layer and a word line layer alternately stacked on the substrate; the insulating layer includes at least three layers; the word line layer includes at least two layers; at least one word line layer has an oxygen ion capture capability greater than or equal to a first preset value; at least one word line layer has an oxygen ion capture capability less than the first preset value; a channel penetrating the insulating layer and the word line layer; a storage layer, a select layer, and a bit line layer located on the sidewall of the channel; the select layer is located on the sidewall of the storage layer away from the channel; the bit line layer is located on the side of the select layer away from the channel. This application achieves a three-dimensional memristor array with different oxygen ion capture capabilities by setting word line layers with strong oxygen ion capture capabilities, exhibiting non-volatile characteristics, and word line layers with weak oxygen ion capture capabilities exhibiting dynamic characteristics.

[0102] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the method embodiments are basically similar to the device embodiments, so they are described more simply; relevant parts can be referred to the descriptions of the method embodiments.

[0103] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A three-dimensional vertical memristor, characterized in that, include: Substrate; An insulating layer and a word line layer are alternately stacked on the substrate; the insulating layer comprises at least three layers; the word line layer comprises at least two layers; at least one of the word line layers has an oxygen ion capture capability greater than or equal to a first preset value; The ability of at least one of the word line layers to capture oxygen ions is less than a first preset value; A channel penetrating the insulating layer and the word line layer; A storage layer, a selection layer, and a bit line layer are located on the sidewall of the channel; the selection layer is located on the side of the storage layer away from the sidewall of the channel; the bit line layer is located on the side of the selection layer away from the sidewall of the channel.

2. The three-dimensional vertical memristor according to claim 1, characterized in that, The material of at least one of the word line layers includes TiN or Ru; the material of at least one of the word line layers includes W; The ability of TiN or Ru to capture oxygen ions is less than the first preset value; The ability of W to capture oxygen ions is greater than or equal to the first preset value.

3. The three-dimensional vertical memristor according to claim 1, characterized in that, The material of the word line layer includes TiN, Ru, W, TaN, Mo, Ta, Al, Ir, Pd, Pt, Cu, Ti, Co, Mo, Ni, Nb, or IrO2.

4. The three-dimensional vertical memristor according to claim 1, characterized in that, The insulating layer is made of materials including SiN, SiO, SiON, SiO2, C-doped SiO2, P-doped SiO2, or F-doped SiO2.

5. The three-dimensional vertical memristor according to claim 1, characterized in that, The material of the storage layer includes HfO. x ,TaO x , HZO or ZrO x The material of the selection layer includes TiO2 or Al2O3; the material of the bit line layer includes TiN, W, Pt, Ru, TaN, Mo, Ta, Al, Au, Ir, Pd or Pt.

6. The three-dimensional vertical memristor according to claim 1, characterized in that, The thickness of the word line layer is [5nm, 10nm]; the thickness of the insulating layer is [10nm, 200nm]; the thickness of the memory layer is [2nm, 15nm]; and the thickness of the select layer is [5nm, 20nm].

7. A method for fabricating a three-dimensional vertical memristor, characterized in that, include: Provide substrate; Alternating layers of insulating layers and word line layers are formed on the substrate; The insulating layer comprises at least three layers; the word line layer comprises at least two layers; the ability of at least one word line layer to capture oxygen ions is greater than or equal to a first preset value; The ability of at least one of the word line layers to capture oxygen ions is less than a first preset value; Etch the insulating layer and the word line layer to form a channel penetrating the insulating layer and the word line layer; A storage layer, a selection layer, and a bit line layer are sequentially formed on the sidewall of the channel.

8. The preparation method according to claim 7, characterized in that, The word line layer is formed by chemical electroplating, magnetron sputtering, chemical vapor deposition, physical vapor deposition, pulsed laser, atomic layer deposition, or electron beam evaporation.

9. The preparation method according to claim 7, characterized in that, The etching includes ion beam etching, dry etching, or wet etching.

10. The preparation method according to claim 7, characterized in that, The insulating layer is formed by sputtering or chemical vapor deposition.

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