Probe card system, method of manufacturing probe card system, method of using probe card system

Abstract

A probe card system is provided. The probe card system includes: a test assembly; a probe body configured to couple with the test assembly; a first interconnect structure on a first side of the probe body; and a probe layer structure on the first interconnect structure on the first side of the probe body, the probe layer structure being configured to bond with a wafer under test (WUT). The probe layer structure includes: a sacrificial layer connected to the first interconnect structure; a bonding layer connected to the sacrificial layer; and a plurality of probe tips, each connected to and electrically coupled to the first interconnect structure via a corresponding conductive pattern exposed from the bonding layer. The sacrificial layer allows removal of the bonding layer and the plurality of probe tips via an etching operation. A method of manufacturing the probe card system is also provided.

Description

[0001] Priority claims and cross-references

[0002] This application asserts the rights of U.S. Provisional Application No. 63 / 390,684, filed July 20, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to a probe card system, a method for manufacturing a probe card system, and a method for using a probe card system, and more specifically, the probe card system includes interconnect structures associated with an interposer for ultra-fine pitch, ultra-high I / O, full-wafer probing with high probe tip and bump / pad alignment accuracy. Background Technology

[0004] For high-end applications such as high-performance computing (HPC), data centers, artificial intelligence (AI), and smart handheld devices, the miniaturization cost of System-on-Chip (SoC) ICs (integrated circuits) is increasing exponentially. Associated development costs have also grown from $217 million for 7nm to $590 million for 3nm. The industry is increasing complexity and cost due to its growing reliance on complex advanced System-in-Packages (SiPs) to package advanced ICs. The advanced SiPs described in this article include... Figure 1A The 2.5D IC shown in the article Figure 1B The fan-out SiP shown in the article Figure 1C The embedded SiP shown in the article Figure 1D The silicon photonics and Figure 1E The 3D ICs based on chip-to-wafer (C2W) assembly shown in the article and Figure 1F The example shown is a wafer-to-wafer (W2W) assembly. Advanced SiP can also include chiplets within the SiP to enable the use of chiplets and Figures 1A to 1F One or more of the advanced SiP technologies described herein target yield, cost, time to market, and performance to enable high-end SoC partitioning. All advanced SiPs involve the integration of multiple chips, and some SiPs (e.g., 2.5D and 3D ICs) can contain wafer-level components with tiny through-silicon vias (TSVs) with a diameter of about 5 μm and a depth of about 30 μm, which is equal to the thickness of the silicon substrate, in thin active ICs (e.g., high-bandwidth memory (HBM) dynamic random access memory (DRAM) chips and fine L (linewidth) / S (line spacing) redistribution layers (RDLs) with L / S ratios of 2 μm / 2 μm and below).

[0005] exist Figure 1AIn the 2.5D IC structure 90, a laminated substrate 901 supports a silicon interposer 902 via multiple solder connectors 903. The silicon interposer 902, commonly used in 2.5D IC packaging and containing through-silicon vias (TSVs) 904, can be used as a bridge between the laminated substrate 901 and the IC block covering the 3D IC (e.g., HBM DRAM stack). Figure 1A The platform provides fine L / S / pitch capability between the memory structure 905 and the processor IC 907. Various electronic components, including memory devices (e.g., memory structure 905), logic ICs (e.g., processor IC 907), MEMS (microelectromechanical systems) devices, and passive devices, can be mounted on the top side (i.e., the chip side) of the silicon interposer 902, which is manufactured using a wafer-level process. These electronic components can be arranged in 2D IC, 2.5D IC, or 3D IC packages. For example, Figure 1A The memory structure 905 can be an HBM DRAM stack, comprising multiple DRAM dies 905a vertically stacked above a substrate (or control) die 905b via copper pillar microbumps or a copper hybrid bonding layer. If necessary, at least one electronic component mounted on the silicon interposer can be embedded within the interposer. For example... Figure 1A As shown, the laminated substrate 901, which uses microbumps or solder bumps to bond the silicon interposer 902, can be bonded to the printed circuit board (PCB) (not shown in the figure) via multiple ball grid array (BGA) solder balls 906 under the laminated substrate 901.

[0006] exist Figure 1B In this configuration, a fan-out package structure 91 can be employed, wherein electrical connections on chips 913a and 913b fan out from the active surfaces of the chips to allow external I / O 903a to be placed beyond the chip boundaries. The fan-out package structure 91, comprising one or more semiconductor chips (e.g., chips 913a and 913b), allows individual chips to be connected to the fan-out wiring layer 911 and coupled to solder bumps 903a, or, depending on the application, alternatively, to use microbump coupling. Figure 1B As depicted, a fan-out package structure 91, produced by a wafer-level fan-out process, is bonded to a substrate 901, which may be a laminated substrate, an interlayer, or a fan-out package structure, and is subsequently bonded to a next-level substrate using solder bumps or solder balls 906.

[0007] exist Figure 1CIn this embodiment, the embedded SiP 92 includes one or more devices 923 embedded in a laminated substrate 901. The one or more devices 923 may be embedded silicon interconnects (which may be passive or active devices), active devices, or embedded passive devices, such as capacitors or inductors. Furthermore, depending on the application, the laminated substrate 901 in which the devices 923 are embedded may be further bonded to another laminated substrate or PCB 908 via solder balls 906 or microbumps.

[0008] exist Figure 1D In this process, the silicon photonic structure 93 includes a CMOS die 916, a waveguide structure 918, a modulator 919 embedded in the waveguide structure 918, a photodetector 920, and an optical fiber 921 coupling optical signals to or from the waveguide structure 918. A laser diode 917, the waveguide structure 918, and components coupled to the waveguide structure are integrated over a silicon interposer 914 having a TSV. The silicon interposer 914, fabricated using a wafer-level process, is configured to be mounted on the substrate via multiple solder bumps 903 (or microbumps, as needed) or a hybrid bonding structure for external interconnection.

[0009] exist Figure 1E In the C2W structure 94, a first carrier 940, a first die 941, and a second die 942 are included. The first die 941 and the second die 942 are positioned above the first carrier 940 using various suitable bonding techniques including microbump-based flip-chip assembly and copper hybrid bonding. The first carrier 940 may be an active or passive device including an interposer with vias 943, and the first carrier 940 serves as a platform for interconnecting the first and second dies with a substrate (not shown) on which the C2W structure is mounted.

[0010] exist Figure 1F In this configuration, the W2W structure 95 includes a first carrier 951, a second carrier 952, and an interconnect layer 953 electrically coupling the first carrier 951 and the second carrier 952. The interconnect layer 953 includes flip-chip bonding, polyimide (PI) to PI bonding, or an oxide-to-oxide copper hybrid bonding, or other suitable bonding structures. For example, vias 954 may be formed in the first carrier 951 to mount a substrate (not shown) of the W2W structure thereon using solder bumps or balls 955, establishing an electrical connection between the first carrier 951 and the second carrier 952.

[0011] The current competition lies in more advanced packaging technologies, including advanced ICs and advanced wafer-level packaging components. For years, the industry at the forefront of this technology has used flip-chip based on copper pillar solder microbumps to assemble advanced multi-chip SiPs, including 2.5D ICs, 3D ICs, fan-out, embedded SiPs, and silicon photonics. Furthermore, this technology can also be used for chiplet assembly within SiPs to build complex systems. Figures 1A to 1FThe advanced SiP described in the document. Currently, the most advanced flip chips in mainstream production incorporate microbumps with a 40μm pitch, a bump size equivalent to a 25μm bump, and a 15μm spacing between adjacent bumps. Looking ahead, efforts are underway to shrink microbumps to 20μm or even potentially 10μm pitch for high-end, high-pin-count applications including HPC, data centers, and AI. At a 20μm pitch, the bump or pad size is less than 10μm. Alongside flip chip miniaturization, there is a growing trend towards copper hybrid bonding for applications requiring 10μm and below pitch, and limited production of pitches below 10μm has proven successful.

[0012] Advanced SiP packaging (whether flip-chip based or hybrid) faces numerous IC, IC assembly, and testing challenges when manufacturing packaged components (especially wafer-level components, including advanced ICs, contact pads, and interposers for high-end applications such as HPC, data centers, and AI) involves ultra-fine pitch and ultra-high I / O or pin counts. A significant and sometimes overlooked challenge for advanced SiP is the ability to obtain and test known-good chips (KGD; and equivalently, known-good wafer-level package components, such as interposers and fan-out packages) in wafer form (involving large, thin, high-power, high-cost advanced digital ICs for high-end applications). The challenges of advanced SiP designs involving 2.5D and 3D chip stacks of multiple high-end dies are escalating, where the unintentional use of defective, high-cost dies (or wafer-level package components) can lead to catastrophic consequences for yield, cost, time-to-market, and even reliability. For example, the most advanced SiP chiplets currently under development can contain more than 40 chiplets (and various wafer-level package components), thus ensuring that KGD's capabilities are a key factor in developing economically viable production plans that cover advanced ICs and advanced wafer-level package components.

[0013] In advanced SiP fabrication, 300mm wafers typically need to be thinned to unprecedented thicknesses. For example, for HBMDRAM, chemical mechanical polishing (CMP) can reduce the wafer from 775μm to 30μm, which can induce new defects due to thermal and thermomechanical stress rather than intentionally. 2.5D ICs can achieve this through the presence of TSVs and RDLs on both the top (chip side) and bottom (BGA ball side) of the silicon interposer (see...). Figure 1A This is achieved through the silicon interposer 902 in the wafer. Similarly, TSV and RDL (or an extension of the BEOL layer in the back-end wafer process) can also be created in a 300mm wafer-based HBM DRAM die to prepare it for 3D stacking (see [link to HBM DRAM die]). Figure 1AThe DRAM die 905a and memory structure 905 are examples of this. New defects associated with, for example, adhesive / barrier layers, liner layers, copper-plated via filling, alignment, etc., can also be found in these ultra-thin, ultra-high I / O wafers with TSVs and RDLs. SiPs contain multiple dies, and their yield risk is driven by the lowest yield IC (or package assembly). Sometimes, expensive, high-yield memories in a memory stack can need to be scrapped due to defects that are not detected on other devices in the stack. Complicating matters further, high-end and automotive applications often require high-temperature and / or low-temperature testing (e.g., from -55°C to 150°C) to eliminate edge defects in the device.

[0014] Therefore, it is necessary to develop advanced wafer testing capabilities and solutions to test KGD of advanced IC nodes and advanced SiP involving wafer-level processes in order to minimize scrap assemblies, increase product profits, and enable the industry to boldly explore the unknown areas involving increasingly active dies and wafer-level packaged components with ultra-fine pitch and ultra-high I / O interconnects. The main products of advanced IC and advanced SiP are proposed for high-end applications such as HPC, data centers and AI.

[0015] Especially for high-end applications, the testing costs for advanced ICs and advanced SiPs are increasing as pitch decreases, pad / probe counts increase, and parallelism increases. This means that complex advanced ICs and complex advanced SiPs, which include advanced ICs and advanced wafer-level packaged components, require high yields, and the billions of dollars in revenue that these products can generate over their lifecycle make the investment in each design economically viable. Summary of the Invention

[0016] One aspect of this disclosure is to provide a probe card system for whole-wafer testing, comprising: a test assembly; a probe body configured to be electrically coupled to the test assembly; a first interconnect structure on a first side of the probe body; and a probe layer structure on the first interconnect structure on the first side of the probe body, the probe layer structure being configured to bond with a wafer under test (WUT). The probe layer structure includes: a sacrificial layer connected to the first interconnect structure; a bonding layer connected to the sacrificial layer; and a plurality of probe tips, each connected to and electrically coupled to the first interconnect structure via a corresponding conductive pattern exposed from the bonding layer. The sacrificial layer allows the bonding layer and the plurality of probe tips to be removed via an etching operation.

[0017] Another aspect of this disclosure is a method for manufacturing a probe card system, wherein the method includes the following operations: receiving a carrier wafer having a first surface to be shielded; forming a cavity in the carrier wafer from the shielded first surface; forming a probe tip by filling the cavity with a conductive material; receiving an interposer layer, wherein the interposer layer includes a probe body and a first interconnect structure on a first side of the probe body; bonding the first surface of the carrier wafer and the first interconnect structure of the interposer layer; and releasing the probe tip from the carrier wafer by an etching operation.

[0018] Another aspect of this disclosure is a method of using a probe card system, wherein the method includes the following operations: receiving an interposer layer, wherein the interposer layer includes: a probe body; a first interconnect structure on a first side of the probe body; and a probe layer structure on the first side of the probe body, the probe layer structure being configured to bond with a wafer under test (WUT). The probe layer structure includes: a first sacrificial layer connected to the first interconnect structure; a bonding layer connected to a compliant layer deposited on the sacrificial layer; and a plurality of probe tips, each connected to a corresponding conductive pattern exposed from the bonding layer and electrically connected to the first interconnect structure. Next, a bonding layer is formed on at least one of the bonding layer of the interposer layer or a contact terminal layer of the WUT. The bonding layer bonds the interposer layer and the WUT at a first temperature and does not necessarily form an electrical connection between the probe tips and the contact terminals of the contact terminal layer. Next, an electrical connection is formed between the probe tips and the contact terminals at a second temperature, wherein the second temperature is greater than the first temperature. Attached Figure Description

[0019] The aspects of this disclosure are best understood from the following detailed description, which is taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various structures are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily increased or decreased.

[0020] Figures 1A to 1F Explain various advanced system-in-packages (SIPs).

[0021] Figure 2 Explain the typical IC testing process.

[0022] Figure 3A This describes a typical wafer test station that operates under mechanical drive.

[0023] Figure 3B illustrate Figure 3A The enlarged cross-sectional view of the test head, probe card system, and the chip under test in the chip testing station.

[0024] Figure 4AA cross-sectional view illustrating a full-wafer probe card system according to some embodiments of the present disclosure.

[0025] Figure 4B Description of some embodiments according to this disclosure Figure 4A An enlarged cross-sectional view of the interposer layer in a full-chip probe card system.

[0026] Figure 5A A cross-sectional view illustrating a full-wafer probe card system according to some embodiments of the present disclosure.

[0027] Figure 5B Description of some embodiments according to this disclosure Figure 5A A top-view cross-sectional view of the horizontal plane of the fluid channel in the all-wafer probe card system.

[0028] Figure 6A A cross-sectional view illustrating a full-wafer probe card system according to some embodiments of the present disclosure.

[0029] Figure 6B Description of some embodiments according to this disclosure Figure 6A A top-view cross-sectional view of the horizontal plane of the fluid channel in the all-wafer probe card system.

[0030] Figure 7A A cross-sectional view illustrating a probe layer structure according to some embodiments of the present disclosure.

[0031] Figure 7B Description of some embodiments according to this disclosure Figure 7A An enlarged cross-sectional view of the probe layer structure.

[0032] Figure 8A A cross-sectional view illustrating a probe layer structure according to some embodiments of the present disclosure.

[0033] Figure 8B Description of some embodiments according to this disclosure Figure 8A An enlarged cross-sectional view of the probe layer structure.

[0034] Figure 9A A cross-sectional view illustrating a probe layer structure according to some embodiments of the present disclosure.

[0035] Figure 9B Description of some embodiments according to this disclosure Figure 9A An enlarged cross-sectional view of the probe layer structure.

[0036] Figures 10A to 10G This describes the operation for forming a plurality of probe tips on an intermediary layer according to some embodiments of the present disclosure.

[0037] Figures 11A to 11GThis describes the operation for forming a plurality of probe tips on an intermediary layer according to some embodiments of the present disclosure.

[0038] Figures 12A to 12E The description relates to the operation of using a release / adhesive layer to bond a probe card system to a WUT containing microbumps, according to some embodiments of this disclosure.

[0039] Figures 13A to 13B The description relates to the operation of bonding a probe card system to a WUT containing a metal pad using a release / adhesive layer according to some embodiments of the present disclosure.

[0040] Figures 14A to 14B The simplified direct-linking process flow is described according to some embodiments of this disclosure.

[0041] Figures 15A to 15B The description relates to operations of using direct bonding to join a probe card system with a WUT containing microbumps, according to some embodiments of this disclosure.

[0042] Figure 16A and Figure 16B The following describes structures and methods for adjusting direct bonding forces according to some embodiments of the present disclosure.

[0043] Figures 17A to 17B The description relates to operations of bonding a probe card system to a WUT containing a metal pad using direct bonding, according to some embodiments of this disclosure.

[0044] Figures 18A to 18B The description relates to operations of bonding a probe card system to a WUT containing a metal pad using direct bonding, according to some embodiments of this disclosure.

[0045] Figure 19 This document provides an overview of advanced wafer BEOL and advanced packaging technologies according to some embodiments of the present disclosure.

[0046] In the following detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the disclosed embodiments. However, it should be understood that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and apparatuses are schematically illustrated for the purpose of simplifying the drawings. Detailed Implementation

[0047] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0048] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” and similar terms may be used herein to describe the relationship between one element or feature and another element or feature(s), as illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or other directions), and thus the spatial relative descriptive terms used herein may also be interpreted.

[0049] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or sections, which should not be limited by these terms. These terms may be used only to distinguish elements, components, regions, layers, or sections from one another. Unless the context clearly indicates otherwise, the terms such as “first,” “second,” and “third” as used herein do not imply a sequence or order.

[0050] While chipmakers are striving to develop a range of Design for Testability (DFT) techniques (such as boundary scan, built-in self-test (BIST), and redundancy and repair), the industry needs a new type of probe card for another breakthrough. This new probe card would allow for the use of wafer test stations capable of handling 100,000 or more contacts on the wafer to provide sufficient test coverage for wafers with ultra-fine pitch microbumps or metal pads (such as active IC wafers or wafer-level packaged components) with pad pitches of 20 μm, 10 μm, or even less. For example, DFT with an envelope can help reduce the number of I / O (input / output) pads that need to be contacted and probed during wafer testing. Regarding probe cards, both microelectromechanical systems (MEMS) and thin-film-based technologies are being explored for pitches of 40 μm and below. The MEMS approach is led by FormFactor, which is developing MEMS-based fine-pitch probe cards targeting pitches of 40 μm and below. On the other hand, IMEC and Cascade Microtech have been working on the early stages of developing rocker beam interposer (RBI) probe card technology with a pitch of 35μm. Pitches below 40μm have posed a significant challenge to the manufacturing of probe card components and the nanotechnology and MEMS (microelectromechanical systems) processes required to produce precision probes, carriers, and substrate structures to meet accuracy requirements.

[0051] There is a significant gap between what the probe industry can offer and what is needed for advanced ICs and advanced SiPs in KGD with current pitches below 40μm and in the near future pitches below 10μm or even below 6μm. The single most significant obstacle to implementing complex advanced SiPs is the availability of affordable KGD, involving advanced ICs on 300mm wafers and 300mm wafer-level packaged components, such as interposers at different stages of wafer-level processing (while still in wafer form).

[0052] This disclosure provides a method, process, and structure for a probe card system to achieve ultra-fine pitch, ultra-high I / O, multi-temperature whole-wafer, and wafer-level probing of microbumps or metal pads with a pitch of 40 μm or less using a probe card system based on a reusable interposer layer. The coefficient of thermal expansion (CTE) of the interposer layer probe card is closely matched with the coefficient of thermal expansion of silicon (approximately 3 ppm / ℃) for high accuracy of probe tip and bump / pad alignment.

[0053] Figure 2This describes a typical IC testing process. After IC manufacturing, devices typically undergo standard parameter and functional testing during wafer testing (or wafer sorting), followed by the assembly of fully functional devices into packages for pre-burn-in package testing, burn-in testing, and final testing. Burn-in testing stresses the packaged IC by applying high operating temperatures and voltages to accelerate failure mechanisms that lead to early field failures. Advanced SiPs require KGDs containing fully functional and highly reliable but expensive dies. Although the following description focuses on wafer-level testing with full wafer contact, this disclosure can also be applied to wafer-level burn-in, allowing for cost savings by identifying defects at an early stage (before IC packaging). With the increasing complexity of advanced ICs and advanced SiPs, both wafer-level testing and wafer-level burn-in can utilize DFT methods to reduce yield / reliability risks, time-to-market, and testing costs. When wafer-level testing or wafer-level burn-in is involved, a probe card system for full wafer contact can be used to access selected groups of I / O pads on the IC on the wafer, which are then electrically connected to a probe station as part of the wafer testing system.

[0054] A wafer testing system is a system that provides special test modes (such as electrical signals) to wafer-level devices to test for functional defects. For example... Figure 3A As shown, the wafer testing system 80 includes a test unit 801, a measurement and stage movement section 802, and a wafer handling section 803. The test unit 801 is connected to the measurement and stage movement section 802 via a data network connection, for example, cable 804. Through cable 804 and test head 805, the test unit 801 provides special test modes to test wafers or devices mounted on the stage movement section 802. The test head 805, carrying a probe card or a probe subsystem with precisely shaped probe tips, is mechanically driven to position the probe tips and lower them onto the I / O pads of the device under test (or wafer under test) to establish an electrical connection, and the connection is routed to the test subsystem using the circuitry on the probe card.

[0055] Figure 3B illustrate Figure 3A The image shows an enlarged cross-sectional view of the test head, probe card system, and the wafer under test at the wafer testing station. (Reference) Figure 3BThe performance board 806 and tester interface 807 are connected to the probe card system 10. The probe card system probes and tests a wafer 809 or any device in wafer form, wherein the wafer is vacuum-mounted on a wafer chuck 808. Typically, the wafer chuck 808 can be mounted on a precision XY stage that provides accurate movement. When the device (or more) on the wafer 809 is powered on, the wafer test system 80 uses the results and software to determine whether the IC passes the test. Each probe card can measure multiple dies in a single drop. The wafer-level probe card system disclosed herein uses a single drop to contact all pads on the wafer to avoid damage to the precision, ultra-fine pitch structure caused by multiple drops. Wafer testing can then be performed.

[0056] Each wafer test landing of the probe card to the I / O pad requires good electrical contact between the probe tip of the probe card system and the I / O pad. To date, by... Figure 3A and Figure 3B The mechanical actuation of the test head 805 shown is the only way to establish physical contact between the probe tip and the I / O pad, enabling the electrical connection for transmitting power and signals to the device under test. As the number of I / Os in advanced ICs (and advanced wafer-level packaged components) increases exponentially with increasingly fine pitches and as microbumps or metal pads become smaller (e.g., less than 10 μm in size), continuing to rely solely on macroscopic mechanical actuation to ensure increasingly smaller microprobe tips contact increasingly smaller bumps or pads with increasingly higher numbers while ensuring uniform, consistent, non-over-contact, and non-damaging contact with the probed microprobe tips and pads becomes a challenging task. Traditional probe cards based on (e.g.) cantilever / epoxy resin and blades (involving a higher coefficient of thermal expansion than silicon) are unsuitable for ultra-fine pitch and ultra-high I / O applications due to limitations in the number of probe tips / pins, probe tip number and density, pressure uniformity, and planarity.

[0057] This disclosure discloses the use of full-wafer-size probe cards, which allow for probing of an IC across the entire wafer in a single drop, minimizing damage to multiple large, thin dies (or wafer-level package assemblies) on the wafer, unlike the multiple drops required by conventional probe cards. This disclosure also discloses a probe card-WUT bonding method, distinct from conventional mechanically driven methods, that utilizes adhesive bonding or direct bonding forces to contact probe tips on a full-wafer-size interposer with the I / O pads of the IC on the WUT. Compared to mechanical driving, adhesive or direct bonding across the entire wafer provides more uniform and consistent contact forces involving tiny probes and pads compared to mechanical driving, and is more easily scalable to finer pitches for further development. Furthermore, the probe card-WUT bonding method described in this disclosure can simultaneously contact die pins / pads and locations across the entire wafer and perform defined testing and burn-in stress through die block partitioning or other methods.

[0058] refer to Figure 4A In some embodiments of this disclosure, the probe card system 100 includes an intermediary layer 1100 and a test machine assembly 1200 configured to be coupled to the intermediary layer 1100. The test machine assembly 1200 includes components for routing connections to a test machine interface 1201 and a test system. Figure 4A The circuit system (not shown in the image).

[0059] Figure 4B Description of some embodiments according to this disclosure Figure 4A An enlarged cross-sectional view of the interposer layer 1100 in the all-chip probe card system. The interposer layer 1100 includes a probe body 1101, a first interconnect structure 1102A on a first side 1101A of the probe body 1101, and a second interconnect structure 1102B on a second side 1101B of the probe body 1101. In some embodiments, the first and second interconnect structures 1102A and 1102B can be used as an RDL with built-in redundancy to, for example, allow different probe layer structures 1103 and different types of probe tips to be built on the RDL to probe different ICs using the same common interposer platform. The first interconnect structure 1102A and the second interconnect structure 1102B are electrically connected through a plurality of vias 1106 penetrating the probe body 1101. Depending on the material of the probe body 1101, the vias 1106 can be TSV or through-glass vias (TGV). Intermediate layer 1100 further includes probe layer structure 1103 attached to first interconnect structure 1102A on a first side 1101A of probe body 1101. Probe layer structure 1103 is configured to bond with wafer under test (WUT).

[0060] Interposer 1100 may be based on silicon, glass, diamond, or a silicon-diamond composite wafer. Mechanical actuation may be used in conjunction with the adhesive or direct bonding methods described herein, as needed. Interposer 1100 may be made of a suitable probe body material having a coefficient of thermal expansion (CTE) closely matching that of the WUT (e.g., a silicon wafer or a wafer based on other materials). CTE is a desirable property for improved probe tip-pad alignment compared to PCBs or thin-film-based probe cards. Depending on their chemical composition, glass interposer substrates may have a CTE in the XY plane ranging from 3 to 10 ppm / °C, while silicon has a CTE of approximately 3 ppm / °C, diamond has a CTE of approximately 1 ppm / °C, and PCBs have a CTE of 17 to 18 ppm / °C, with larger values ​​in the thickness direction. Recent demonstrations in the synthetic diamond industry of growing larger, higher-quality electronic-grade diamond films (typically via microwave plasma chemical vapor deposition (MPCVD)) offer an excellent opportunity to produce novel interposers for wafer-level testing and burn-in aging of diamond (both polycrystalline diamond (PCD) and single-crystal diamond (SCD)) and diamond-silicon and other types of diamond-based composite wafers. These interposers can leverage the extreme properties of diamond, such as its excellent thermal conductivity (approximately 20 to 24 W / cm K) (five times that of copper), its exceptionally high breakdown electric field (approximately 20 MV / cm), and its extremely low coefficient of thermal expansion (approximately 1 ppm / °C at room temperature). It should be noted that at temperatures above approximately 100 K, diamond exhibits the highest thermal conductivity of all known materials, exceeding that of copper by more than five times.

[0061] Still referencing Figure 4B The probe layer structure 1103 on the interposer layer 1100 may use copper for electrical wiring and connections, and may employ polymer dielectric materials (e.g., polyimide) or inorganic dielectric materials (e.g., silicon dioxide (SiO2)) commonly used in back-to-the-edge (BEOL) and advanced SiP-related wafer-level processing. Additionally, the interposer layer 1100 may contain solder bumps 1104 at the second side 1101B of the probe body 1101, such as... Figure 4A As shown, the test signal returns to the test assembly 1200 via the second interconnection structure 1102B.

[0062] Even though the examples provided for demonstration are based on an interposer with electrical wiring and TSVs (which is a synonym for a non-silicon interposer), the processes and structures disclosed in this disclosure can be extended to glass interposers, diamond interposers, and interposers containing optical wiring / waveguides, optical TSVs, and single-mode fiber arrays / coupled for probes involving optical interconnects. While the (electrical) vias 1106 can transfer power and signals from the PCB assembly and interposer 1100, the optical vias in interposer 1100 can provide ultra-high bandwidth communication. In addition to electrical and optical vias, interposer 1100 may also contain fluid channels to allow coolant to pass through interposer 1100 to enhance thermal management during wafer testing or burn-in aging processes, such as... Figure 5A , Figure 5B , Figure 6A and Figure 6B The example is shown in the text.

[0063] refer to Figure 5A In some embodiments of this disclosure, the probe card system 200 includes one or more optical components selected from at least one of a probe body 2101, a first interconnect structure 1102A, a second interconnect structure 1102B, or a probe layer structure 1103. Figure 5A In this configuration, two optical adapters 2013 may be located on both sides of the interposer layer 2100 and connected to the optical waveguides 2016 connecting both sides of the interposer layer 2100. In some embodiments, the optical waveguides 2016 pass through the first interconnect structure 1102A, the probe body 2101, and the second interconnect structure 1102B.

[0064] By integrating optical components in the interposer layer 2100, the optical signal 700, propagating via the circuit layer 810 of the WUT 809, is redirected by the reflector 2015 to enter the optical waveguide 2016 and reach the test assembly 1200. Other optical components (not shown here) can be used, including (but not limited to) single-mode or multimode fiber arrays or couplers, optical transceivers, photoelectric converters, etc. The optical signal 700 can be transmitted back and forth from the WUT 809 to the test assembly 1200 to complete optical probing or testing. This configuration enables ultra-high bandwidth communication through this probe card system, which incorporates an interposer layer containing optical structures to cooperate with optical interconnects for probing.

[0065] Still referencing Figure 5AThe interposer 2100 may include one or more fluid channels 2014 in the probe body 2101 and the second interconnection structure 1102B, which consist of, for example, two vertical segments 2014A and a horizontal segment 2014B connecting the two vertical segments 2014A. The fluid channels 2014 are coupled to a coolant inlet 2017 and a coolant outlet 2018, each located on one side of the interposer 2100. This arrangement facilitates thermal management during testing or burn-in aging processes by allowing coolant or liquid 701 of a selected temperature to flow through the fluid channels 2014 in the probe card system 200 and through heat exchangers outside the probe card system 200.

[0066] Figure 5B Description of some embodiments according to this disclosure Figure 5A The horizontal section 2014B of the fluid channel 2014 in the all-chip probe card system is a top view of the cross-section. (See attached image.) Figure 5B As shown, the horizontal section 2014B of the fluid channel 2014 is located in an area not used for providing power and transmitting signals, and is isolated from the through-hole 1106 used for providing power and transmitting signals. In other words, the electrical components in the interlayer 2100 are isolated from the liquid 701 passing through the interlayer 2100 to prevent the coolant 701 from directly contacting the through-hole 1106.

[0067] Alternatively, in other embodiments, the method for preventing coolant 701 from contacting (electrical) via 1106 can be modified to enhance thermal management, such as... Figure 6A and 6B As shown in the image. Figure 5A , 5B The same numbers in 6A and 6B refer to the same or equivalent structures, and for the sake of simplicity, they will not be repeated here. Figure 6A In the probe card system 300 shown, the interposer 3100 may include one or more fluid channels 3014 in the probe body 3101 and the second interconnect structure 1102B, which consists of, for example, two vertical segments 3014A and a horizontal segment 3014B connecting the two vertical segments 3014A. Multiple (electrically) vias 1106 are laterally surrounded by an insulating layer 3011, through which liquid 701 flows in close proximity.

[0068] Figure 6B Description of some embodiments of this disclosure Figure 6A The horizontal segment 3014B of the fluid channel 3014 in the all-chip probe card system is a top view in cross-section. An additional insulating layer 3011 surrounding the (electrical) vias 1106 allows these vias 1106 to be located within and isolated from the fluid channel 3014 in the horizontal segment 3014B. This is because the space occupied by the vertical segment 3014A and the horizontal segment 3014B of the fluid channel 3014 is larger than... Figure 5BThe fluid channel 2014 contains the space of the vertical section 2014A and the horizontal section 2014B, so the thickness of the horizontal section 2014B can be thinner than that of the horizontal section 2014B to achieve a similar cooling effect to the probe card system. As described below, the temperature of the probe layer structure can be controlled by the cooling structure described herein to achieve a sufficiently low temperature to avoid permanent bonding during the direct bonding process of the probe card and the WUT.

[0069] Figures 7A to 9B Three different examples of the probe layer structure 1103 in some embodiments of this disclosure are illustrated. The probe layer structure 1103 described herein includes at least a sacrificial layer and a bonding layer. For whole-wafer probing, the sacrificial layer in the probe layer structure 1103 can be peeled off after multiple uses, and a new probe layer structure 1103 can be generated, allowing the interposer to be reused. The bonding layer at the top of the probe layer structure 1103 may be based on a dielectric (e.g., silicon dioxide (SiO2)) or a polymer (e.g., fully cured polyimide (PI)), both of which are commonly used in back-to-the-end wafer (BEOL) and advanced SiP processes. In some embodiments, an optional compliant layer in the probe layer structure helps maintain the integrity of the probe structure below the probe tip.

[0070] Figure 4B , 7A The same numbers in 7B refer to the same or equivalent structures, and for the sake of brevity, they will not be repeated here. Figure 7B Description of some embodiments according to this disclosure Figure 7A An enlarged cross-sectional view of the probe layer structure. Figure 7B In this configuration, the sacrificial layer 401 is connected to the first interconnect structure 1102A, a bonding layer 405 is stacked on top of the sacrificial layer 401, and a plurality of probe tips 407 are each connected to and electrically coupled to a corresponding conductive pattern 409 exposed from the bonding layer 405 and to the first interconnect structure 1102A. In embodiments where an optional compliant layer 403 is included in the probe layer structure 1103, such as... Figure 7B As described, the compliant layer 403 is disposed between the sacrificial layer 401 and the bonding layer 405 and may be composed of an elastomer. In some embodiments, a first portion 4031 of the compliant layer 403 is located between the sacrificial layer 401 and the bonding layer 405, and a second portion 4032 of the compliant layer 403 is located between the sacrificial layer 401 and the corresponding conductive pattern 409 of the probe layer structure 1103.

[0071] Bonding layer 405 serves as a layer for bonding with the WUT, for example, through direct bonding of PI to PI or oxide to oxide, or through adhesive bonding via a release / adhesive layer, so that the probe card system can be used interchangeably with WUTs involving adhesive and direct bonding. Bonding layer 405 typically comprises a polymer (e.g., fully cured PI, which is common in advanced packaging and IC passivation) and an inorganic layer such as SiO2 (which is also commonly used in advanced packaging and IC passivation).

[0072] The sacrificial layer 401 can be made of a combination of metallic and non-metallic materials. Possible metallic options include nickel (Ni), chromium (Cr), titanium (Ti), copper (Cu), manganese (Mn), iron (Fe), cobalt (Co), tungsten (W), molybdenum (Mo), and tantalum (Ta), while non-metallic options can consist of oxides, phosphates, and chromates of these metals. Some preferred mixtures contain chromium and chromium oxide, and nickel and nickel oxide. In some embodiments, the sacrificial layer 401 can be made of an etchable metal, an etchable non-metal, or a combination thereof. Additionally, various sacrificial layers 401 commonly used in MEMS processing can be considered, such as metallic materials (e.g., Cu, aluminum (Al), Ti, and Cr) and non-metallic materials (e.g., silicon dioxide, polycrystalline silicon, and polymers such as polymethyl methacrylate (PMMA), polyimide, and photoresist (including photosensitive polyimide)). Notably, the sacrificial layer 401 can be relatively thin, with a measured thickness of less than 0.3 μm. In some embodiments, chromium oxide (Cr2O3) as the sacrificial layer 401 possesses several desirable properties. For example, it can be sputtered to deposit stress-controlled films with a thickness of several hundred nanometers. Furthermore, chromium oxide exhibits strong adhesion to both dielectrics and metal surfaces, demonstrates resistance to various acids and alkalis, undergoes rapid etching in standard chromium etchants, and exhibits minimal reactivity with common materials even at high temperatures. Various methods exist for forming the sacrificial layer 401, including vapor deposition, sputtering, electroplating, and dip-plating.

[0073] In some embodiments, Figure 7B The probe layer structure 1103 includes a bonding layer 405 and a plurality of vias 4051 in an optional compliant layer 403. These vias 4051 expose the sacrificial layer 401 beneath the bonding layer 405 and the optional compliant layer 403 to an etchant to facilitate the removal of the sacrificial layer 401.

[0074] Depending on the shape and structure of the probe tip and the contact forces applied during wafer-level probing, the compliant layer 403 can be incorporated into the probe layer structure immediately adjacent to the probe tip. This helps minimize the thermomechanical effects on the probe card and WUT, while also extending the lifetime of the probe card system. If the compliant layer 403 is used, it can be constructed using an elastomer such as polydimethylsiloxane (PDMS), which can be spin-coated, cured, and patterned onto the interposer. Polymers such as polyimide and PDMS can be microfabricated using photolithography or laser technology. By optimizing the pulse duration, repetition rate, and the number of emission times using ultrashort laser pulses, microvias with a diameter of less than 10 μm can be produced with minimal thermal damage using polyimide (PI) when the pulse duration is less than 140 femtoseconds. In some embodiments, a suitable short-pulse laser source can be a mode-locked oscillator operating at a wavelength of 800 nm and a regenerative amplifier equipped with Ti:sapphire (e.g., the Mira900 / RegA900 from Coherent).

[0075] Figure 7A , 7B The same numbers in 8A, 8B, 9A, and 9B refer to the same or equivalent structures, and for the sake of simplicity, they will not be repeated here. Except for the outline of the probe tip, Figure 8A Intermediate layer 1110 and Figure 9A Intermediate layer 1120 and Figure 7A The intermediate layers are essentially the same. Typically, the probe tip is designed to deflect and scrub the micro-bumps or metal pads after contact. As illustrated in the figure, Figure 7B The probe tip 407 is a vertical needle-shaped tip, while Figure 8B The probe tip 507 is a dendrite tip comprising, for example, a plurality of dendrites of electroplated palladium dendrites, wherein the hard palladium dendrites can penetrate softer microbumps or solder bumps at room temperature or low temperature to establish electrical connections during whole-wafer testing, and can subsequently be separated or disconnected from the microbumps or solder bumps. Figure 9B The probe tip 607 is a microcantilever tip or a spring-loaded probe tip that deflects upon landing and provides gentle scrubbing at microbumps or metal pads. In addition to vertical needle tips, dendrite tips, and microcantilever tips, the probe tip may also be pyramidal or a combination of these shapes. In some embodiments, the minimum spacing between a plurality of probe tips 407, 507, or 607 is less than 40 μm to cover an area of ​​probe layer structure 1103 equivalent to the area of ​​the WUT.

[0076] To achieve high-yield wafer testing, the formation of copper oxide on the copper pads (which is not an issue for probe pads with solder bumps) is a concern when designing suitable probe tips (and for pre-test wafer cleaning as needed). Therefore, in some embodiments, non-oxidized probe metallurgy can be used. This helps to scrub away the oxide layer on the copper pads and prevents probe adhesion. By using non-oxidized probe metallurgy, the contact between the probe and the pad remains stable and any unwanted adhesion is avoided. In some embodiments, suitable probe geometry and tip shape may be employed. The probe geometry and tip shape should allow for proper scrubbing action while achieving optimal over-travel. In some embodiments, the cleaning protocol may be optimized to remove any oxides, contaminants, or residues that could impede proper electrical contact.

[0077] In some embodiments, various types of probe tips can be combined with each other within a single intermediary layer. For example... Figures 7A to 9B As described, the conductive metal of the probe tip can be made using materials such as Cu, W, Ni-Co, Ni-boron (B), Ni / Ni-W, or other conductive materials commonly used in the industry. These metal probe tips, in various forms, can be accompanied by surface coatings (e.g., PdCo) to improve performance.

[0078] For high-frequency RF applications, advanced probe card designs should consider impedance control of the supply and transmission lines. Additionally, these designs should address probe inductance and incorporate short probe tips to meet the specific requirements of such applications.

[0079] Figures 7A to 9B The embodiments depicted are not drawn to scale. The sacrificial layer 401 may have a thickness of several hundred nanometers, while the bonding layer 405 may be less than 1 μm thick. The compliant layer 403 may also be thin and positioned immediately adjacent to and below the probe tips 407, 507, and 607, if desired. Furthermore, implementing an elastomer to form the compliant layer 403 allows for the application of higher contact forces to break down the oxide layers on the IC pads and probe tips, while minimizing damage to the underlying structures.

[0080] Figures 10A to 10G This describes a method for forming multiple probe tips on an intermediate layer. (Reference) Figure 10A The device can receive a carrier wafer 7011 having a first surface 7011A to be masked. The carrier wafer 7011 may be a silicon wafer. In some embodiments, a masking film 7012 deposited over the first surface 7011A of the carrier wafer 7011 may comprise SiO2, Si3N4, or the like, which may then be patterned for a desired opening. Figure 10B As shown, a cavity 7013 can be formed in the carrier wafer 7011 from an opening in the masking film 7012. The cavity 7013 can be a tip cavity formed via a silicon etching operation. Next, refer to... Figure 10C A seed layer 7014 can be sputtered onto the inner wall of the cavity 7013 and the masking film 7012 on the carrier wafer 7011. Subsequently, a photoresist 7015 is formed and patterned over the seed layer 7014 to form a beam cavity 7016 over the tip cavity 7013 through appropriate photolithography. Figure 10D As shown, the probe tip 7018 can be formed by electroplating the tip cavity 7013 and the beam cavity 7016 with a suitable conductive material (e.g., copper (Cu)).

[0081] like Figure 10E As described, a photoresist stripping operation can be performed to remove the photoresist, followed by an etching process to remove a portion of the seed layer 7014 exposed from the probe tip 7018. Figures 10A to 10E The example in the text uses only a single cavity 7013 to illustrate the operation for forming probe tips. In fact, multiple cavities 7013 can be generated in the carrier wafer 7011 in a single operation to allow for the simultaneous formation of many probe tips.

[0082] like Figure 10F As shown, the carrier wafer 7011 supporting the probe tip 7018 can be directly bonded to the first interconnect structure 1102A at the first side 7101A of the probe body 7101. Alternatively, the carrier wafer 7011 can be attached to the first side 7019A of the interposer 7019 using a suitable bonding material. (See reference...) Figure 10G The carrier wafer is moved via a silicon etching operation, and other exposed layers after silicon etching can be removed by a suitable etching operation. The silicon etching operation may include selective etching of bulk silicon. For example, hydrofluoric acid solution or other bulk silicon etching techniques may be used to selectively remove silicon above the probe tip. Subsequently, one or more solder bumps 7020 may be formed on the second side 7019B of the interposer, wherein the probe tip side of the interposer uses a release layer (e.g., a release layer commonly used in fan-out processes) to bond to a temporary glass carrier for external connection.

[0083] Return to reference Figure 7B , 8B 9B, prior to the operation of bonding the carrier wafer 7011 to the interposer 7019, a two- or three-layer stack of probe layer structures of the interposer 7019 is formed over the first interconnect structure 1102A, such that the probe tip 7018 can be integrated with the two- or three-layer probe layer stack to complete the probe layer structure described herein. In some embodiments, the formation of the two- or three-layer stack includes operations such that a sacrificial layer 401 is formed in conjunction with the first interconnect structure 1102A, a bonding layer 405 is formed over the sacrificial layer 401 (two-layer stack), and optionally, a compliant layer 403 is formed between the sacrificial layer 401 and the bonding layer 405 (three-layer stack).

[0084] Figures 11A to 11G Examples of forming microcantilever tips are shown. Figures 10A to 10G The same numbers in 11A to 11G refer to the same or equivalent structures, and for the sake of brevity, they will not be repeated here. Except Figure 11C In addition to the operations in the middle, Figures 11A to 11G The operation in is similar to Figures 10A to 10G In the process, an additional sacrificial layer 7021 can be deposited above the masking film 7012 prior to the deposition of the seed layer 7014. This sacrificial layer 7021 can facilitate copper plating and promote separation of the carrier wafer 7011 from the probe tip. The photoresist 7015 above the seed layer 7014 can be patterned by appropriate photolithography operations to create a beam cavity 7016 above the tip cavity 7013. Figure 11D In this process, the tip cavity 7013 and the beam cavity 7016 are filled with a conductive material, such as Cu, by performing an electroplating operation to form the probe tip 7018. This is achieved through repeated... Figure 11C and Figure 11D The photolithography and electroplating operations can further construct a flange 7018A above the probe tip 7018 and form a cantilever tip or microcantilever tip with flange 7018A to be bonded to the first interconnect structure 1102A on the first side 7101A of the probe body 7101.

[0085] refer to Figure 11F A carrier wafer 7011 carrying a probe tip 7018 with a flange 7018A can be bonded to a first interconnect structure 1102A at a first side 7101A of the probe body 7101. In other words, the carrier wafer 7011 can be bonded to a first side 7019A of the interposer 7019 using a suitable bonding material to form an electrical connection between the probe tip 7018 with the flange 7018A and the electrical wiring in the first interconnect structure 1102A. (Reference) Figure 11G The carrier wafer is removed via a silicon etching operation, and other exposed layers after silicon etching can be removed with a suitable etchant. The silicon etching operation may include selective etching of bulk silicon. For example, hydrofluoric acid (HF) solution or other bulk silicon etching techniques can be used to selectively remove silicon above the probe tip. An additional sacrificial layer 7021 formed before the seed layer 7014 further facilitates separation of the carrier wafer 7011 from the probe tip 7018. One or more solder bumps 7020 are formed on the second side of the interposer layer 7019B to achieve external connections, as... Figure 10G The situation.

[0086] Return to reference Figure 7B , 8B9B, prior to the operation of bonding the carrier wafer 7011 to the interposer 7019, a two- or three-layer probe layer stack of the interposer 7019 is formed over the first interconnect structure 1102A, such that the probe tip 7018 having a flange 7018A can be integrated with the two- or three-layer stack to complete the probe layer structure described herein. In some embodiments, the formation of the two- or three-layer stack includes operations such that a sacrificial layer 401 is formed in conjunction with the first interconnect structure 1102A, a bonding layer 405 is stacked over the sacrificial layer 401 (two-layer stack), and optionally, a compliant layer 403 is formed between the sacrificial layer 401 and the bonding layer 405 (three-layer stack).

[0087] A wide range of probes can be fabricated using MEMS or thin-film processes, including vertical probes, microcantilever probes, torsion probes, and various other types. When designing probe tips for a specific application, several key parameters need to be considered. These include pad type, pad configuration, die size, pad size (passivation openings and spacing), pad material, force requirements, scrubbing depth, frequency / bandwidth, pad density (probes per square millimeter), effective area (size of the probe array), and temperature sensitivity. Advanced probe cards must support high-speed testing, thermal cycling testing, and handle pitches smaller than 20 μm.

[0088] This disclosure discloses two methods for achieving the required probe card contact force: adhesive bonding force and direct bonding force, i.e., chemical force, which can be combined with conventional mechanical actuation as needed. After depositing and patterning a release / adhesive layer (commonly used in advanced SiP processes, such as fan-out processes) on a 2- or 3-layer stacked probe layer structure with a glass interposer, the glass interposer probe card can be bonded to the probed wafer via the release / adhesive layer, achieving probe-pad electrical contact at low temperature. After wafer testing or burn-in, the interposer / wafer assembly can be irradiated with a laser to release the release / adhesive layer from the glass interposer and separate the wafer from the interposer probe card. In this case, adhesive force is used for interposer / wafer bonding and separation. Another way to apply contact force is through direct bonding, which is tailored to limit heating to apply a sufficiently strong self-aligning force to achieve electrical contact, while being weak enough to allow the bonding surface and interposer to separate from the wafer after full wafer testing. In some embodiments, when the WUT uses SiO2 as the top layer of the copper hybrid bonding, the bonding layer on the interposer can be accordingly based on SiO2. Correspondingly, when the wafer is incorporated into a fully cured PI layer as a top passivation or bonding layer for copper hybrid bonding, an interposer can be deposited on top of the PI layer. By adapting the surface and bonding conditions and characteristics of SiO2 or PI, a self-aligned bonding force derived from direct bonding can be achieved, strong enough to cause the interposer probe card to drop onto and test the IC wafer, but weak enough to release the interposer probe card from the IC wafer. Both PI-to-PI bonding and oxide-to-oxide bonding, as well as self-alignment, are assisted by water. After plasma activation on the surfaces of the interposer and wafer, water is applied to the surface to form hydrophilic assembly regions. Self-assembly of the hydrophilic regions on the interposer and wafer surfaces can occur at low temperatures (e.g., room temperature). During direct temporary bonding, especially in the case of PI-to-PI bonding, external pressure can be applied to promote probe tip drop.

[0089] According to some embodiments of this disclosure Figures 12A to 12E The description pertains to the operation of bonding the probe card system to the WUT containing microbumps using a release / adhesive layer, and Figures 13A to 13B The instructions pertain to the operation of bonding the probe card system to the WUT containing the metal pad using a release / adhesive layer.

[0090] refer to Figure 12A The bonding layer 7322 may be formed on side 7319A of the interposer layer 7319 opposite to side 7319B having solder bumps 7320. The bonding layer 7322 (e.g., a release / adhesive layer as described herein) is deposited and patterned on bonding layer 405, which is the uppermost layer in a two-layer or three-layer stack of the probe layer structure 1103, as previously described. Figure 7B , 8BAs described in 9B, the bonding layer 7322 is formed to expose the probe tip 7318 with a suitable gap on the side 7319A of the intermediate layer 7319.

[0091] refer to Figure 12B Intermediate layer 7319 is bonded to WUT 7324 to have microbumps as contact terminals 7323 or I / O, without first forming an electrical connection between probe tip 7318 and I / O of WUT 7324 at a first temperature (e.g., about room temperature). In some embodiments, WUT 7324 includes substrate 7325, device layer 7326 above substrate 7325, BEOL structure 7327 above device layer 7326, and contact terminals 7323 above BEOL structure 7327. In some embodiments, contact terminal 7323 includes bump under metallization (UBM) 7330 contacting contact pad 7328 of BEOL structure 7327, passivation layer 7329 above BEOL structure 7327 and laterally surrounding UBM 7330, and solder-containing structure (e.g., microbumps) above UBM 7330. In some embodiments, contact terminal 7323 includes copper pillars 7331 on UBM 7330, a barrier layer 7332 on copper pillars 7331, and solder-containing structures (e.g., microbumps) 7333 on barrier layer 7332. An electrical connection between probe tip 7318 and contact terminal 7323 is then established at a second temperature above a first temperature. The second temperature is used to provide limited heating (e.g., below 250°C) to cure the release / adhesive layer and seal the gap between probe tip 7318 and contact terminal 7323. Because the CTE of the release / adhesive layer made of polymeric material is greater than the CTE of a probe tip or contact pad made of metal, appropriate bonding pressure should be applied to seal the gap between probe tip 7318 and contact terminal 7323. For optimal bonding of interlayer 7319 and WUT 7324, the process can be performed in a vacuum atmosphere. A vacuum atmosphere helps eliminate or minimize voids at the bonding interface and removes any residual volatiles present in the release / adhesive layer.

[0092] In some embodiments, a bonding layer 7322 may be formed on the WUT 7324, exposing the contact terminals 7323, rather than depositing the bonding layer on the bonding layer of the interposer 7319 prior to bonding. However, in other embodiments, the bonding layer 7322 may be formed on both the interposer 7319 and the WUT 7324 prior to bonding. The bonding layer 7322 may be a release / adhesive layer in the form of two separate layers (a release layer and an adhesive layer) or a two-in-one layer. The bonding layer 7322 deposited by spin coating can have a very thin thickness, such as 0.5 μm or less, after undergoing pre-baking and post-baking processes. Similarly, the adhesive layer can also be very thin, with a thickness in the micrometer range or even thinner. Commercially available two-in-one films can be as thin as 10 μm.

[0093] When the release / adhesive layer is used as a bonding layer 7322 (see...) Figure 12B When releasing / adhesive layers are used, they can be composed of PI-based or silicon-based materials. They can be thermoplastic or thermosetting and can be patterned using photolithography or laser technology. Post-baking or curing the release / adhesive layer at a second temperature below 250°C induces compressive force to ensure close contact between the probe tip 7318 and the contact terminal 7323 in the WUT 7324. Furthermore, if a laser is used to release the interposer and wafer from the release / adhesive layer, a laser-transparent interposer, such as a glass or diamond interposer 7319, is required. This allows the laser to penetrate and reach the release / adhesive layer. Additionally, if necessary, mechanical actuation or other isostatic pressing methods can be used to apply uniform pressure from the test head to the interposer / wafer assembly.

[0094] refer to Figures 12C to 12E After bonding the interposer 7319 and WUT 7324, the solder bump 7320 on side 7319B (which is immediately adjacent to the second interconnect structure 1102B) can be mounted on the test assembly 1200, as follows. Figure 12D As shown in the diagram. In this operation, the interposer 7319 of the probe card system and the tester assembly 1200 are electrically connected via temporary connection terminals on the tester assembly 1200, involving multiple Pd dendrite connectors 7334 and solder bumps 7320 on the second interconnect structure 1102B of the interposer 7319. Testing or burn-in of the WUT 7324 can be performed after this temporary connection. After performing the testing or burn-in process, the interposer 7319 can be separated from the tester assembly 1200, for example, by applying tensile stress to the temporary connection at a low temperature, such as room temperature, without causing solder reflow on the solder bumps 7320, as shown in the diagram. Figure 12E As shown in the figure. When the bonding layer 7322 is a release / adhesive layer, the intermediate layer 7319 and WUT 7324 may be further separated by, for example, by: (1) irradiating the bonding layer 7322 with a laser or macroscopically irradiating the intermediate layer 7319, which is at least partially transparent to the wavelength band of the laser; and / or (2) immersing the bonding layer 7322 in a polymer expansion agent or release liquid.

[0095] Figure 13A and 13B The method of using the probe card system described herein is similar to Figures 12A to 12E The method described in [the document] is only in [the context of] Figure 13A In the middle, the metal pad 7340 replaces the previous one. Figure 12B The contact terminal 7323 shown (e.g., containing solder material) is used in WUT 7344. Figure 13A and 13BIn this configuration, a metal pad 7340 is laterally surrounded by a bonding layer 7343, which may be part of an RDL or back-to-the-edge wafer (BEOL) structure, with its top surface higher than the top surface of the metal pad 7340. A metal barrier layer 7341 may be disposed between the bonding layer 7343 and the contact pad 7328 or the BEOL structure. In some embodiments, the metal pad 7340 comprises copper. An interposer layer 7319 is bonded to a WUT 7344 having the metal pad 7340 as I / O, without first forming an electrical connection between the probe tip 7318 and the I / O of the WUT 7344 at a first temperature (e.g., about room temperature). Subsequently, an electrical connection between the probe tip 7318 and the metal pad 7340 is established at a second temperature above the first temperature. The second temperature is used to provide limited heating (e.g., below 250°C) to close the gap between the probe tip 7318 and the metal pad 7340.

[0096] although Figure 13A and Figure 13B Although not explicitly stated, a similar temporary connection between the intermediary layer 7319 and the test assembly 1200 can be used to perform testing or burn-in aging processes on the WUT 7344, similar to... Figures 12C to 12E As described in the description. After performing a test or burn-in process, the interposer 7319 can be separated from the test assembly 1200, for example, by applying tensile stress to the temporary connection at a low temperature without causing solder reflow at the solder bump 7320. When the bonding layer 7322 is a release / adhesive layer, the interposer 7319 and WUT 7344 can be further separated by, for example, by: (1) irradiating the bonding layer 7322 with a laser or macroscopically irradiating the interposer 7319, which is at least partially transparent to the wavelength band of the laser; and / or (2) immersing the bonding layer 7322 in a polymer expansion agent or release liquid.

[0097] In addition to utilizing adhesive force, such as Figures 12A to 13B As described, customization of the process and surface conditions can also be used to facilitate high-quality, self-aligned wafer testing. For example, PI-to-PI bonding or oxide-to-oxide bonding can be used to generate sufficiently strong adhesion to establish contact between the probe tip and the microbumps or metal pads, but also sufficiently weak to allow easy separation of the interposer or probe card system from the IC wafer after testing or burn-in operations. This approach is not limited to using laser-transparent thermally expanded matching glass or diamond interposers for release / adhesive layer removal, but can be applied to a variety of interposers including silicon, diamond, and silicon-diamond interposers.

[0098] Figure 14A and 14BThe demonstration simplifies the direct bonding process flow, where direct bonding begins, for example, at a first low temperature of room temperature to prevent the establishment of a strong dielectric-to-dielectric bond between the WUT and the probe tip. Figure 14A As shown in the diagram. It is then heated to a higher second temperature, low enough to prevent permanent bonding between the dielectrics, but high enough to seal the gap between the probe tip and the pad being probed (external pressure is applied as needed), as... Figure 14B As shown in the illustration. In this demonstration, the probe layer structure 1103 on the interposer 7419 has a first bonding layer 7401 configured to bond with a second bonding layer 7402 on the BEOL structure 7427 (or a portion of 7427) above the wafer 7425. The probe tip 7418 can contact the pad 7423 by using a second low temperature (and, if necessary, external pressure). In some specific examples, the second temperature for oxide-to-oxide and PI-to-PI direct bonding should be below 250°C.

[0099] Figures 15A to 15B The description relates to operations of directly bonding a probe card system to a WUT containing microbumps, according to some embodiments of this disclosure. References Figure 15A and 15B When using PI-to-PI bonding or oxide-to-oxide bonding based on PI or oxide bonding layers on interposer 7519 and WUT 7524, a sacrificial layer 7534 and a bonding layer 7535 are formed on WUT 7524 prior to bonding. Bonding layer 7535 may be based on SiO2 or PI, similar to the material used for bonding layer 405 in forming probe layer structure 1103, as previously described. Figure 7B As discussed in [the document]. Typically, the materials of bonding layer 7535 and bonding layer 405 are essentially the same to facilitate direct bonding. Figure 15A In this process, a sacrificial layer 7534 is formed on the WUT as needed to facilitate separation between the bonding layer 7535 and the WUT 7524 after wafer testing or burn-in aging process, and the bonding layer may contain etchant inlet holes to facilitate the removal of the sacrificial layer.

[0100] In cases where the height of the microbumps on WUT 7524, the height and shape of the probe tip, and the surface BEOL structure (or RDL layer) prevent direct contact bonding between WUT 7524 and the interposer 7519, a sacrificial layer 7534 and a bonding layer 7535 are formed only on WUT 7524 before wafer testing. The sacrificial layer 7534 formed on WUT 7524 may be the same as or different from the sacrificial layer 401 in a 2-layer or 3-layer stack for probe layer structure 1103, as previously... Figure 7B , 8BAs described in 9B. The sacrificial layer 401 in the probe layer structure 1103 can be removed with the same or different etchant as the etchant used to remove the sacrificial layer 7534 formed on the WUT 7524. The sacrificial layer 7534 of the WUT 7524 can be released in a manner similar to that used to remove the sacrificial layer 401 of the probe layer structure 1103 without damaging the underlying structure.

[0101] exist Figure 15B In this process, interposers 7519 and WUT 7524 are bonded together without forming a permanent dielectric-to-dielectric bond between them. The bond can be separated in two ways: (1) PI-to-PI bonding; and (2) oxide-to-oxide bonding.

[0102] To achieve full-wafer bonding involving PI-to-PI bonding, activating the polyimide surface via oxygen plasma activation is crucial. This process generates low-density hydrophilic groups on the polyimide surface, which enhance the adsorption of water molecules introduced during the deionized water wetting process. The adsorbed water molecules then generate high-density -OH groups (-hydroxyl groups), which promote room-temperature pre-bonding.

[0103] Following polyimide surface activation and wetting, self-aligned PI-to-PI hybrid bonding can occur for a short duration at relatively low temperatures (e.g., room temperature) below 250°C, particularly when permanent bonding is not desired. Plasma processing and wetting / hydration processes are required to achieve satisfactory interposer-WUT bonding and temporary bonding. Several parameters can be manipulated to achieve appropriate bonding or contact force at the probe tip-pad contact while ensuring easy separation of the interposer from the wafer; these include plasma activation time, water introduction volume, bonding temperature, and bonding time.

[0104] In the embodiments, when using PI-to-PI bonding, particularly based on pyromellitic dianhydride (PMDA) and 4,4'-diaminodiphenyl ether (4,4'-ODA), the shear strength can be tuned by adjusting various parameters, such as the volume of water introduced, the bonding time, and the oxygen (O2) plasma activation time. This allows for shear strengths ranging from 3.3 MPa to 35.3 MPa, a tenfold increase. A shear strength of approximately 3 MPa or lower indicates easily separable unbonded wafers.

[0105] Furthermore, for direct bonding, there is a shear strength window between 3.3 MPa and 35.3 MPa, which provides a sufficiently strong force for the probe tip to contact the pad while still allowing the interlayer to be separated from the wafer by means of, for example, immersion in a heated polyimide swelling agent (e.g., N-methyl-2-pyrrolidone (NMP)).

[0106] Typically, direct oxide-to-oxide bonding follows this sequence of steps: (a) forming dangling bonds and bonds between hydroxyl groups and water molecules through plasma activation using gases such as O2 (oxygen), N2 (nitrogen), or Ar (argon); (b) removing defects by cleaning and scrubbing with deionized water; (c) bonding the wafer (or wafer and wafer-sized interlayer) to the oxide bonding layer using van der Waals hydrogen bonds between two to three monolayers of water molecules and polar hydroxyl groups (-OH) found on natural and thermal SiO2 at room temperature and atmospheric pressure; and (d) forming H2O molecules and silanol groups (Si-OH-(H2O)) on the top and bottom wafer surfaces. x (e) Van der Waals bonds between (-HO-Si; silanol group = Si-OH) and annealing to remove water molecules at the interface and form covalent bonds. This annealing process is typically performed at temperatures below 400°C for several hours, especially when the goal is permanent bonding to prevent intermetallic layer melting and implanted dopant diffusion. Exposure to temperatures below 250°C for a shorter period is required here to ensure sufficient contact force and easier separation of the interlayer from the WUT. In oxide-on-oxide bonding, adjusting various factors (e.g., oxide type, deposition technique, process conditions (e.g., plasma gas, plasma power), surface roughness associated with chemical mechanical polishing (CMP), surface cleanliness, single-layer to multi-layer water molecules from deionization cleaning, bonding conditions (e.g., temperature and speed), and annealing conditions (e.g., annealing temperature, annealing time, and number of annealing steps)) can also result in shear strength adjustments of more than 30 times between the interlayer (i.e., with SiO2-based bonding layers) and the wafer (i.e., with SiO2-based bonding layers), ranging from 3 MPa to 100 MPa.

[0107] To prevent void formation caused by water droplet formation at the wafer edge (Joule-Thomson expansion effect) during direct bonding, it is necessary to control parameters such as plasma conditions, surface roughness, cleanliness, wafer warpage / flatness, and bonding conditions.

[0108] although Figure 15A and Figure 15B Not specified in the text, but can be used Figures 12C to 12E The temporary connection described herein is used to perform a test or burn-in process on the WUT7524. After the test or burn-in process, the interposer 7519 and the test assembly 1200 (not shown) can be separated, for example, by applying tensile stress to the temporary connection without causing solder reflow on the solder bump 7320, and removing the interposer 7519 from the test assembly 1200. When the bonding layer 7535 is a direct bonding layer (e.g., a PI or oxide layer), the interposer 7519 and the WUT 7524 can be further separated, for example, by applying tensile stress to the bonding layer 7535.

[0109] Figure 16A and Figure 16B The following describes some embodiments according to this disclosure, as well as those described herein (but not limited to). Figure 15A , Figure 15B , Figure 17A , Figure 17B , Figure 18A and Figure 18B The described direct bonding examples are associated with structures and methods for adjusting the direct bonding force. Oxide-to-oxide bonding can be performed on a platform or chuck with a flat central region and a lower outer ring region. Figure 16A This demonstrates the design of a wafer chuck 760 that facilitates the escape of water molecules. The wafer chuck 760 has a flat central region 7601 and a lower outer ring region 7602 to disrupt van der Waals forces at the outer ring region (operations (c) and (d) above)), with the edge portion of the mounted wafer biased toward the outer ring region 7602. This bias creates an edge gap that allows water molecules to escape at the wafer edge. The ring region approach can be extended to cover multiple regions (not shown) to disrupt van der Waals forces in more than one region (and away from regions containing microbumps or metal pads), and allows for fine-tuning of both oxide-to-oxide bonding and PI-to-PI bonding processes used for wafer testing.

[0110] Another method to adjust the bonding strength and facilitate easy separation of the interposer from the wafer requires that the patch of the hydrophobic region 7702 on the WUT 770 be moved away from the probe pad (possibly close to the center of the WUT 770) before plasma activation and water immersion or wetting. Figure 16B As shown in the figure. Taking silicon (or silicon oxide, since bare silicon is typically covered with at least a few angstroms of natural oxide) as an example, a hydrophobic region 7702 can be created on the silicon or oxide surface after RCA (Radio Corporation of America) cleaning by an operation involving immersion in approximately 1% hydrofluoric acid without any subsequent deionized water rinsing. RCA cleaning is a set of standard wafer cleaning steps performed prior to high-temperature wafer processing. It involves the following processes in the RCA cleaning sequence: (1) removal of organic contaminants by organic and particulate cleaning; and (2) removal of a thin oxide layer by oxide stripping and removal of ionic contaminants by ionic cleaning.

[0111] Keeping all other conditions constant, the bonding strength of both PI-PI and oxide-oxide bonding can be adjusted by modifying plasma activation and water immersion conditions and processes. Typically, surfaces treated with both water and plasma exhibit significantly higher shear strength compared to surfaces treated with only plasma (i.e., producing the lowest shear strength) or only water (i.e., producing the second lowest shear strength), while keeping other conditions constant.

[0112] For oxide-to-oxide hybrid bonding, achieving high module flatness and ensuring surface cleanliness are crucial for preventing electrical interconnect failures. This is particularly important due to the high hardness and poor deformability of silica. In contrast, PI-to-PI bonding offers advantages in terms of surface roughness tolerances and module flatness. This is attributed to the lower modulus and more compliant properties of polyimide, which allows for more flexible bonding.

[0113] Figures 17A to 17B This description relates to the operation of bonding a probe card system to a WUT having a metal pad using direct bonding, according to some embodiments of this disclosure. Except in WUT 7744 (see...) Figure 17A Metal pad 7740 was used instead of the previous one. Figure 15A In addition to the contact terminal 7523 shown (e.g., containing solder material), Figure 17A and 17B The method of using the probe card system described herein is similar to Figures 15A to 15B The method described in [the document / article]. Figure 17A and 17B In this design, the metal pad 7740 is laterally surrounded by a bonding layer 7722, which may be part of an RDL or wafer BEOL structure. An interposer 7719 is bonded to the WUT 7744, which contains the metal pad 7740 as I / O, without the need to form a permanent bond between the bonding layer of the interposer and the top or between the bonding layers of the WUT 7744 at a first temperature (e.g., approximately room temperature). Subsequently, an electrical connection is established between the probe tip 7718 and the metal pad 7740 at a second temperature greater than the first temperature. The second temperature provides limited heating (e.g., below 250°C) to close the gap between the probe tip 7718 and the metal pad 7740.

[0114] although Figure 17A and Figure 17B It is not stated in the text, but it is similar to Figures 12C to 12E As described, the testing or burn-in process for WUT 7524 can be performed after this temporary connection. After performing the testing or burn-in process, the interposer 7719 and the test assembly 1200 (not shown) can be separated, for example, by applying tensile stress to the temporary connection without causing solder reflow at the solder bump 7320. When the bonding layer or joint layer 7722 is a direct bonding layer (e.g., PI or oxide layer), the interposer 7719 and WUT 7744 can be further separated by, for example, applying tensile stress to the bonding layer 7722.

[0115] Figures 18A to 18B The description relates to operations of bonding a probe card system to a WUT containing a metal pad using direct bonding, according to some embodiments of this disclosure. Figure 18A and 18BThis paper presents an alternative method when using a probe card system and a direct combination of WUTs, where the separation of the probe card system's intermediary layer 7819 from the WUT 7844 is challenged. This method is similar to... Figure 17A and 17B The difference between the embodiments described herein and those described is that the former incorporates an additional bonding layer 7837 and an additional sacrificial layer 7836 on the WUT 7844. The bonding layer 7837 of the WUT 7844 serves as a direct bonding layer to bond with bonding layers in a 2-layer or 3-layer probe layer stack of the interposer layer 7819. In terms of etch selectivity, the sacrificial layer 7836 may contain a different material than the sacrificial layer 401 on the 2-layer or 3-layer stack of the interposer layer 7819, as previously described. Figure 7B As described in [the document]. After wafer testing or burn-in process is completed, the sacrificial layer 7836 can be etched to facilitate separation between the WUT 7844 and the interposer 7819. When the bonding layer or bonding layer 7837 is a direct bonding layer (e.g., PI or oxide layer), the interposer 7819 and the WUT 7844 can be further separated by, for example, selectively applying an etch solution relative to the sacrificial layer 7836.

[0116] After the probe tip wears down due to frequent use, the sacrificial layer 401 on the interposer can be removed in a separate etching operation. Figure 18A and 18B The disclosed embodiments involve enhancing the probe layer structure 1103 by etching a sacrificial layer 401 on a 2-layer or 3-layer stack of the interposer layer 7819, as previously described. Figure 7A and 7B The description in (which also applies to) Figure 18A and 18B (Intermediate layer 7819 in the middle). In high-volume and high-end applications, especially for large, thin, and high-value dies, the parallel processing of probe layer deposition and sacrificial layer release can be an effective method for achieving wafer-level testing and even wafer-level burn-in for KGD. The disclosed full-wafer contactor or probe card system can be used to facilitate this process to achieve efficient and comprehensive wafer-level testing.

[0117] Figure 19 This document provides an overview of advanced wafer-on-a-chip (BEOL) and advanced packaging technologies according to some embodiments of this disclosure. Currently, direct bonding or copper hybrid bonding achieves remarkable accuracy at the approximately 500 nanometer level, while flip chips based on microbumps achieve accuracy of 3 μm. By utilizing adhesive and direct bonding force-induced actuation (derived from advanced packaging and copper hybrid bonding), the methods, structures, and processes disclosed herein can be extended to finer pitches, far exceeding the pitches desired by traditional "macro" mechanical actuation, as flip chips and copper hybrid bonding continue to evolve and miniaturize.

[0118] Probe tip technologies (such as variants of nanotechnology and nano-MEMS technology) can also achieve ultra-fine pitches, as in the case of wafer BEOLs and interposers. The contact forces imparted or provided by wafer-level release / adhesive layers and wafer-level direct bonding can be implemented in the production of ultra-fine pitches (junction / interconnect pitches below 2μm / 2μm L / S and below 10 / 6μm) and ultra-high I / O, and will also be miniaturized with wafer BEOLs and advanced SiP technologies based on flip-chip microbumps and copper hybrid bonding.

[0119] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other operations and structures to implement the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A probe card system, comprising: Test machine assembly; The probe body is configured to couple with the test assembly; A first interconnection structure is located on a first side of the probe body; and A probe layer structure is provided on the first interconnect structure on the first side of the probe body, the probe layer structure being configured to engage with the wafer under test (WUT). The probe layer structure includes: A sacrificial layer, which is connected to the first interconnect structure; A bonding layer, which is connected to the sacrificial layer; and Multiple probe tips, each connected to and electrically coupled to a corresponding conductive pattern exposed from the bonding layer, are attached to the first interconnect structure. The sacrificial layer allows the bonding layer and the plurality of probe tips to be removed via an etching operation.

2. The probe card system of claim 1, further comprising a second interconnect structure on a second side of the probe body opposite the first side, wherein the second interconnect structure includes at least one solder connector configured to engage with the test assembly of the probe card system.

3. The probe card system according to claim 1, wherein the probe layer structure further comprises: A compliant layer comprising an elastomer, wherein a first portion of the compliant layer is between the sacrificial layer and the bonding layer, and a second portion of the compliant layer is between the sacrificial layer and the corresponding conductive pattern of the probe layer structure.

4. The probe card system of claim 3, wherein the sacrificial layer comprises an etchable metal, an etchable non-metal, or a combination thereof.

5. The probe card system of claim 1, further comprising a plurality of vias exposing the sacrificial layer in the bonding layer to facilitate sacrificial layer removal.

6. The probe card system according to claim 2, wherein the probe body is made of the same material as the WUT, glass, or diamond, or a material having a thermal expansion coefficient that matches or is close to that of the WUT, and one or more through holes in the probe body are electrically connected to the first interconnect structure and the second interconnect structure.

7. The probe card system of claim 6, further comprising one or more fluid channels between the through-holes in the probe body to facilitate thermal management during testing by allowing liquid to flow through the fluid channels in the probe card system and a heat exchanger outside the probe card system.

8. The probe card system according to claim 2, further comprising one or more optical components selected from at least one of the probe body, the first interconnect structure, the second interconnect structure, or the probe layer structure.

9. The probe card system of claim 1, wherein the plurality of probe tips include vertical tips, dendritic tips, microcantilever tips, pyramid tips, or combinations thereof.

10. The probe card system of claim 9, wherein the minimum spacing between the plurality of probe tips is less than 40 μm, and wherein the area of ​​the probe layer structure is comparable to the area of ​​the WUT.

11. A method for manufacturing a probe card system, wherein the method comprises: Receive a carrier wafer with a first surface to be shielded; A cavity is formed in the carrier wafer from the shielded first surface; The probe tip is formed by filling the cavity with a conductive material; Receiving an intermediary layer, wherein the intermediary layer includes: The probe body; and A first interconnection structure is located on a first side of the probe body; The first interconnect structure combining the first surface of the carrier wafer and the first interconnect structure of the interposer layer; and The probe tip is released from the carrier wafer by an etching operation. Prior to bonding the carrier wafer and the interposer, a probe layer structure is formed above the first interconnect structure of the interposer, comprising: A first sacrificial layer is formed to be connected to the first interconnect structure; and A bonding layer is formed that is connected to the first sacrificial layer.

12. The method of claim 11, wherein forming the probe tip by filling the cavity with the conductive material comprises: A second sacrificial layer is formed in the cavity; After the second sacrificial layer is formed, a seed layer is formed in the cavity; and An electroplating operation is performed to fill the cavity.

13. A method of using a probe card system, wherein the method comprises: Receiving an intermediary layer, wherein the intermediary layer includes: Probe body; A first interconnection structure is located on a first side of the probe body; and A probe layer structure is located on the first side of the probe body, and the probe layer structure is configured to engage with the wafer under test (WUT). The probe layer structure includes: A first sacrificial layer is connected to the first interconnect structure; A bonding layer, which is connected to the first sacrificial layer; and Multiple probe tips, each connected to a corresponding conductive pattern exposed from the bonding layer and electrically connected to the first interconnect structure, A bonding layer is formed on at least one of the bonding layer of the intermediate layer or the contact terminal layer of the WUT; The bonding layer bonds the intermediate layer and the WUT at a first temperature without requiring an electrical connection between the probe tip and the contact terminals of the contact terminal layer; and An electrical connection is formed between the probe tip and the contact terminal at a second temperature. The second temperature is greater than the first temperature.

14. The method of claim 13, wherein the formation of the bonding layer comprises forming a laser-release adhesive layer or forming an organic or inorganic direct bonding layer.

15. The method of claim 14, wherein the formation of the organic or inorganic direct-bonding layer comprises: A second sacrificial layer is formed on the contact terminal layer; and A polyimide layer or an oxide layer is formed above the second sacrificial layer. The first sacrificial layer may be removed with the same or different etchant used to remove the second sacrificial layer.

16. The method of claim 13, wherein the intermediary layer further comprises a second interconnect structure on a second side of the probe body, and the method further comprises: The test assembly of the interposer layer and the probe card system is joined via temporary connection terminals on the test assembly and solder bumps on the second interconnect structure; and This separates the interlayer from the test assembly without causing solder backflow on the solder bumps.

17. The method of claim 14, further comprising: The interlayer is separated from the WUT by at least one of the following: (1) irradiating the interlayer, which is at least partially transparent to the wavelength band of the laser, with a laser; (2) immersing the bonding layer in a polymer swelling agent or a release liquid; or (3) applying tensile stress to the bonding layer.

18. The method of claim 13, further comprising removing the probe layer structure from the intermediary layer via a stripping operation using an etchant that removes the first sacrificial layer.

19. The method of claim 13, wherein joining the intermediary layer with the WUT comprises: Hydroxyl groups on the bonding layer are increased by performing plasma activation on the bonding layer, wetting the bonding layer with water, or a combination thereof.

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