Memory device and data operation method thereof

Abstract

A memory device and a data operation method thereof are disclosed. The memory device includes a memory array, a data terminal module, an input / output module, and a peripheral interface module. The input / output module includes a write pipeline that serial-parallel converts serial write data received from the data terminal module into first parallel write data in a 1:m1 manner based on a write clock signal during a data write operation. The peripheral interface module includes a deserializer circuit that serial-parallel converts the first parallel write data received from the input / output module via a data write bus into second parallel write data in a 1:m2 manner based on the write clock signal during the data write operation to be written to the memory array, where m1×m2=n.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory technology, and in particular to a memory device and a method for manipulating data thereon. Background Technology

[0002] With the rapid development of semiconductor processing technology, the number of prefetch bits and input / output (IOs) in memory devices has increased significantly. For example, in LPDDR4 (Low Power Double Data Rate SDRAM), a type of Dynamic Random Access Memory (DRAM) with fast data access speed and large capacity, if the prefetch bit is 16, the total number of access bits for 16 IOs reaches 256 bits.

[0003] Figure 1 The diagram shows an example of a data path global graph for an existing memory device. Figure 1 As shown, the memory device 1 includes a memory array for storing data, a peripheral interface module for performing read and write operations on the memory array, a data input / output module with write and read pipelines, multiple data terminals (e.g., 16 data I / Os), and instruction terminals (instruction I / Os) for inputting read / write instructions, read / write addresses, etc. In a data write operation, 16 bits of serial write data are provided from each data terminal, and this serial write data is stored in an input register. The serial-to-parallel conversion is performed in a 1:16 ratio via the write pipeline to obtain a total of 256 bits of parallel write data. This 256 bits of parallel write data is transmitted along the data write bus to the peripheral interface module for loading into the memory array. In a data read operation, 256 bits of parallel read data are obtained from the memory array via the peripheral interface module. This 256 bits of parallel read data is transmitted along the data read bus to the read pipeline, where it undergoes a 16:1 parallel-to-serial conversion to obtain 16 bits of serial read data. This serial read data is then transmitted to an output register and provided to each data terminal. The memory device can perform these operations based on the timing of various clock signals generated by the clock terminal (such as write clock signal Dclk1, read clock signal Dclk2, and instruction clock signal).

[0004] With the significant increase in the prefetch bits and I / O bits of memory devices, there are numerous data write buses and data read buses between the data I / O modules and the peripheral interface modules. For example, Figure 1 The data bits transmitted on the data write bus and data read bus reach 256 bits. This results in the data write bus and data read bus occupying a large number of metal traces, increasing the chip size of the memory device. Summary of the Invention

[0005] This disclosure was made to solve the aforementioned problems in the prior art, and its purpose is to provide a memory device and a data operation method thereof that can reduce the number of data buses, thereby reducing the number of metal traces and shrinking the die size.

[0006] According to an exemplary embodiment of the present disclosure, a memory device is provided, comprising: a data terminal module including a plurality of data terminals, each data terminal being used to input n bits of serial write data or output n bits of serial read data; an input / output module for transmitting data input from the data terminal module to the memory array, or outputting data read from the memory array to the data terminal module; and a peripheral interface module disposed between the memory array and the input / output module, for performing read and write operations on the memory array, via a data write bus and... Data is transmitted between the data read bus and the input / output module. The input / output module includes a write pipeline that, during a data write operation, converts serial write data received from the data terminal module into first parallel write data in a 1:m1 ratio based on a write clock signal. The peripheral interface module includes a deserializer circuit that, during a data write operation, converts the first parallel write data received from the input / output module via the data write bus into second parallel write data in a 1:m2 ratio based on a write clock signal for writing to the memory array, where m1×m2=n.

[0007] Furthermore, the peripheral interface module also includes a serializer circuit, which, during a data read operation, converts parallel read data read from the memory array into first serial read data in a parallel-to-serial ratio of m2:1 based on a read clock signal. The input / output module also includes a read pipeline, which, during a data read operation, converts the first serial read data received from the peripheral interface module via the data read bus into second serial read data in a parallel-to-serial ratio of m1:1 based on a read clock signal, for output to the data terminal module.

[0008] Furthermore, each data terminal is used to input 16-bit serial write data, the write pipeline performs serial-to-parallel conversion in a 1:8 ratio, and the deserializer circuit performs serial-to-parallel conversion in a 1:2 ratio.

[0009] Furthermore, each data terminal is used to output 16-bit serial read data, the serializer circuit performs parallel-to-serial conversion in a 2:1 ratio, and the read pipeline performs parallel-to-serial conversion in an 8:1 ratio.

[0010] Furthermore, the data write bus is also multiplexed as the data read bus.

[0011] Furthermore, the memory device is a DRAM device.

[0012] According to another exemplary embodiment of this disclosure, a data operation method for a memory device is provided. The memory device includes: a memory array including a plurality of memory cells arranged in an array; a data terminal module including a plurality of data terminals, each data terminal being used to input n bits of serial write data or output n bits of serial read data; an input / output module for transmitting data input from the data terminal module to the memory array or outputting data read from the memory array to the data terminal module; and a peripheral interface module disposed between the memory array and the input / output module for performing read and write operations on the memory array. The operation involves transmitting data between the input / output module and the data write bus and data read bus. The data operation method includes the following steps: During a data write operation, using the write pipeline in the input / output module, serial write data received from the data terminal module is converted into first parallel write data in a 1:m1 ratio using a write clock signal; during a data write operation, using the deserializer circuit in the peripheral interface module, the first parallel write data received from the input / output module via the data write bus is converted into second parallel write data in a 1:m2 ratio using a write clock signal; and the second parallel write data is written to the memory array, where m1×m2=n.

[0013] Furthermore, the data operation method also includes the following steps: during the data read operation, using the serializer circuit in the peripheral interface module, the parallel read data read from the memory array is converted into first serial read data in a parallel-to-serial ratio of m2:1 based on the read clock signal; during the data read operation, using the read pipeline in the input / output module, the first serial read data received from the peripheral interface module via the data read bus is converted into second serial read data in a parallel-to-serial ratio of m1:1 based on the read clock signal; and the second serial read data is output to the data terminal module.

[0014] According to the memory device and data operation method disclosed herein, the number of data buses can be reduced, thereby reducing the number of metal traces and shrinking the chip size of the memory device. Attached Figure Description

[0015] This disclosure can be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A global graph of the data path for an example of an existing memory device;

[0017] Figure 2 This is a structural block diagram of a memory device according to an embodiment of the present disclosure;

[0018] Figure 3 This is a global data path diagram of a memory device according to an embodiment of the present disclosure;

[0019] Figure 4 This is a signal timing diagram of a data write operation based on a 1:2 deserializer according to one embodiment of the present disclosure;

[0020] Figure 5 This is a signal timing diagram of a data read operation based on a 2:1 serializer according to one embodiment of the present disclosure;

[0021] Figure 6 A flowchart illustrating the data write operation in a data operation method for a memory device according to an embodiment of the present disclosure; and

[0022] Figure 7 This is a flowchart of a data read operation in a data operation method of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0023] The following describes specific embodiments of this disclosure. It should be noted that, in order to maintain brevity, this specification cannot provide a detailed description of all features of the actual embodiments. It should be understood that, in the actual implementation of any embodiment, just as in any engineering or design project, various specific decisions are often made to achieve the developer's specific goals and to meet system-related or business-related constraints, and this can change from one embodiment to another. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content of this disclosure, changes in design, manufacturing, or production based on the technical content disclosed herein are merely conventional technical means and should not be construed as insufficient content of this disclosure.

[0024] Unless otherwise defined, the technical or scientific terms used in the claims and description shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this patent application description and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0025] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0026] Unless otherwise specified, all embodiments and preferred embodiments mentioned herein can be combined to form new technical solutions. Similarly, unless otherwise specified, all technical features and preferred features mentioned herein can be combined to form new technical solutions.

[0027] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0028] The embodiments of this disclosure will now be described with reference to the accompanying drawings. It should be understood that the embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0029] Figure 2This is a structural block diagram of a memory device 100 according to an embodiment of the present disclosure. The memory device 100 may be, for example, a DRAM device integrated on a single semiconductor chip. Of course, the type of memory device 100 is not limited to this, and may also be other types of memory devices such as Synchronous Dynamic Random Access Memory (SDRAM), Ferroelectric Transistor Random Access Memory (FeTRAM), Ferroelectric Random Access Memory (FeRAM), Magnetic Random Access Memory (MRAM), Spin-Torque (STT)-MRAM, Conductive Bridged RAM (CBRAM), Resistive Random Access Memory (RRAM), Oxide-based RRAM (OxRAM), etc.

[0030] like Figure 2 As shown, the memory device 100 includes a data terminal module 101, an input / output module 102, a memory array 103, and a peripheral interface module 104.

[0031] The data terminal module 101 includes multiple data terminals, each of which is used to input n bits of serial write data or output n bits of serial read data. During a data write operation, data written from an external source can be provided to the data terminal module 101, while during a data read operation, data read from the memory array 103 can be provided to the data terminal module 101.

[0032] The input / output module 102 transmits data input from the data terminal module to the memory array 103, or outputs data read from the memory array 103 to the data terminal module 101.

[0033] The memory array 103 includes a plurality of memory cells arranged in an array. Each memory cell is located at the intersection of a word line (row) and a bit line (column). During an access operation, one or more rows and columns can be activated, and data can be read from or written to the memory cell at the intersection of the activated row and column.

[0034] The peripheral interface module 104 is located between the memory array 103 and the input / output module 102. It is used to perform read and write operations on the memory array 103 and to transmit data between the input / output module 102 and the data write bus 105 and the data read bus 106.

[0035] In this embodiment, the input / output module 102 includes a write pipeline 1021. During a data write operation, the write pipeline 1021 converts the serial write data received from the data terminal module 101 into first parallel write data DIN in a 1:m1 manner based on the write clock signal Dclk1.

[0036] The peripheral interface module 104 includes a deserializer circuit 1041. During a data write operation, the deserializer circuit 1041 converts the first parallel write data DIN received from the input / output module 102 via the data write bus 105 into second parallel write data (e.g., in a 1:m2 serial-to-parallel manner) based on the write clock signal Dclk1. Figure 2 The second parallel write data is written to the memory array 103.

[0037] The relationship between n, m1, and m2 satisfies: m1 × m2 = n. n, m1, and m2 can all be powers of 2.

[0038] In addition, the peripheral interface module 104 may include a serializer circuit 1042. During a data read operation, the serializer circuit 1042 reads parallel data (e.g., data from the memory array 103) based on the read clock signal Dclk2. Figure 2 The DR and DF in the data are converted from parallel to serial in an m2:1 ratio to the first serial read data DOUT.

[0039] The input / output module 102 may include a read pipeline 1022. During a data read operation, the read pipeline 1022 converts the first serial read data DOUT received from the peripheral interface module via the data read bus 106 into second serial read data in a parallel-to-serial ratio of m1:1 based on the read clock signal Dclk2, and outputs it to the data terminal module 101.

[0040] Figure 3 A global diagram of the data path of a memory device according to an embodiment of the present disclosure is shown. In this example, n is 16, and the write pipeline 1021 performs serial-to-parallel conversion in a 1:8 ratio. The deserializer circuit 1041 employs a 1:2 deserializer to perform serial-to-parallel conversion in a 1:2 ratio.

[0041] Therefore, the number of data write buses 105, which serve as data buses, can be reduced by half, for example, by reducing the number of global metal tracks of the data write bus 105 from... Figure 1 The number of 256 shown has been reduced to Figure 3 The 128 shown.

[0042] in addition, Figure 3 In the serializer circuit 1042, a 2:1 serializer is used to perform parallel-to-serial conversion in a 2:1 manner, while the read pipeline 1022 performs parallel-to-serial conversion in an 8:1 manner.

[0043] Therefore, similarly, the number of data read buses 106 that serve as data buses can be reduced by half, for example, by reducing the number of global metal lines of the data read bus 106 from... Figure 1 The number of 256 shown has been reduced to Figure 3 The 128 shown.

[0044] Figure 4 This is a signal timing diagram of a data write operation based on a 1:2 deserializer according to one embodiment of the present disclosure.

[0045] Figure 4 The code provides a write clock signal Dclk1, which is a periodic signal that switches between high and low logic levels according to a regular timing. The first parallel write data DIN is 2-bit serial data. A 1:2 deserializer deserializes the write data DIN into parallel write data DR and DF.

[0046] Of course, the deserializer circuit 104 is not limited to a 1:2 deserializer; it can also use, for example, a 1:4 deserializer, a 1:8 deserializer, a 1:16 deserializer, etc.

[0047] Figure 5 This is a signal timing diagram of a data read operation based on a 2:1 serializer according to one embodiment of the present disclosure.

[0048] Figure 5 The system provides a read clock signal Dclk2, which is a periodic signal that switches between high and low logic levels according to a regular timing. A 2:1 serializer serializes the parallel read data DR and DF into 2-bit serial read data DOUT.

[0049] Similarly, the serializer circuit 104 is not limited to a 2:1 serializer; for example, a 4:1 serializer, an 8:1 serializer, a 16:1 serializer, etc., can also be used.

[0050] In addition, the memory device 100 includes instruction and address terminals (not shown) from which write instructions and addresses are provided, specifying which memory cells data should be written. Furthermore, the write clock signal Dclk1 and the read clock signal Dclk2 can be set, for example, based on an internal system clock signal.

[0051] The memory device 100 may also include a driver interface (MIO DRV, not shown) for signal enhancement disposed in the peripheral interface module 104.

[0052] According to the memory device disclosed herein, the number of data buses can be reduced, thereby reducing the number of metal traces and shrinking the chip size of the memory device.

[0053] Furthermore, in other exemplary embodiments of this disclosure, since data writing and data reading are not performed simultaneously, the data write bus 105 can be configured to be multiplexed as a data read bus 106 in the memory device 100 described above.

[0054] Therefore, by multiplexing the data write bus as a data read bus at the same time, the number of data buses can be further reduced, thereby further reducing the number of metal traces and shrinking the chip size of the memory device.

[0055] According to another exemplary embodiment of the present disclosure, a data operation method for a memory device is provided. Figure 6 This is a flowchart illustrating a data write operation in a data operation method for a memory device according to an embodiment of the present disclosure. Figure 6 As shown, the data manipulation method includes the following steps.

[0056] Step S201: During the data write operation, the serial write data received from the data terminal module is converted into first parallel write data in a 1:m1 manner using the write pipeline in the input / output module based on the write clock signal.

[0057] Step S202: During the data write operation, the deserializer circuit in the peripheral interface module is used to convert the first parallel write data received from the input / output module via the data write bus into the second parallel write data in a 1:m2 manner based on the write clock signal.

[0058] Step S203: Write the second parallel write data to the memory array. To write data, rows and / or columns of the memory array can be activated based on addresses indicating which rows and / or columns to activate. For example, signals can be used to activate one or more selected bit lines of the memory array, and parallel write data can be loaded along those activated bit lines.

[0059] Figure 7 This is a flowchart of a data read operation in a data operation method of a memory device according to an embodiment of the present disclosure.

[0060] Step S204: During the data read operation, using the serializer circuit in the peripheral interface module, the parallel read data read from the memory array is converted into first serial read data in an m2:1 parallel-to-serial ratio based on the read clock signal. The parallel read data can be read based on the received read clock signal, read instruction, and read address. For example, the bit lines of the memory array can be activated based on the timing of the read clock signal, and the read address can be used to determine which bit lines to activate. The parallel read data can then be read along the activated bit lines.

[0061] Step S205: During the data read operation, the first serial read data received from the peripheral interface module via the data read bus is converted into second serial read data in a parallel-to-serial manner in an m1:1 ratio using the read pipeline in the input / output module based on the read clock signal.

[0062] Step S206: Output the second serial read data to the data terminal module.

[0063] in, Figure 6 and Figure 7 There are no restrictions on the order of data write and data read operations; they can be adjusted according to the actual read requirements of the memory device.

[0064] According to the data operation method of the memory device disclosed herein, the number of data buses can be reduced, thereby reducing the number of metal traces and shrinking the chip size of the memory device.

[0065] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular situations or materials to the teachings of the various embodiments of this disclosure without departing from the scope of this disclosure. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of this disclosure, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A memory device, characterized in that, include: A memory array comprising multiple memory cells arranged in an array; The data terminal module includes multiple data terminals, each of which is used to input n bits of serial write data or output n bits of serial read data. An input / output module that transmits data input from the data terminal module to the memory array, or outputs data read from the memory array to the data terminal module; and A peripheral interface module, located between the memory array and the input / output module, is used to perform read and write operations on the memory array and to transmit data with the input / output module via a data write bus and a data read bus. The input / output module includes a write pipeline that, during a data write operation, converts the serial write data received from the data terminal module into first parallel write data in a 1:m1 manner based on a write clock signal. The peripheral interface module includes a deserializer circuit. During a data write operation, this deserializer circuit, based on a write clock signal, converts the first parallel write data received from the input / output module via the data write bus into second parallel write data in a 1:m2 ratio (serial to parallel) for writing to the memory array. Where m1×m2=n.

2. The memory device as claimed in claim 1, characterized in that, The peripheral interface module also includes a serializer circuit, which, during data read operations, converts the parallel read data read from the memory array into first serial read data in an m2:1 ratio based on the read clock signal. The input / output module also includes a read pipeline, which, during data read operations, converts the first serial read data received from the peripheral interface module via the data read bus into second serial read data in a parallel-to-serial ratio of m1:1 based on the read clock signal, and outputs it to the data terminal module.

3. The memory device as claimed in claim 1, characterized in that, Each data terminal is used to input 16 bits of serial write data. The write pipeline performs serial-to-parallel conversion in a 1:8 ratio. The deserializer circuit performs serial-to-parallel conversion in a 1:2 ratio.

4. The memory device as claimed in claim 2, characterized in that, Each data terminal is used to output 16-bit serial read data. The serializer circuit performs parallel-to-serial conversion in a 2:1 ratio. The read pipeline performs parallel-to-serial conversion in an 8:1 ratio.

5. The memory device as claimed in claim 2, characterized in that, The data write bus is also multiplexed as the data read bus.

6. The memory device as claimed in claim 1, characterized in that, The memory device is a DRAM device.

7. A method for data operation of a memory device, the memory device comprising: A memory array comprising multiple memory cells arranged in an array; The data terminal module includes multiple data terminals, each of which is used to input n bits of serial write data or output n bits of serial read data. An input / output module that transmits data input from the data terminal module to the memory array, or outputs data read from the memory array to the data terminal module; and A peripheral interface module, located between the memory array and the input / output module, is used to perform read and write operations on the memory array and to transmit data with the input / output module via a data write bus and a data read bus. The data manipulation method is characterized by including the following steps: During the data write operation, the write pipeline in the input / output module is used to convert the serial write data received from the data terminal module into first parallel write data in a 1:m1 manner based on the write clock signal. During the data write operation, the deserializer circuit in the peripheral interface module is used to convert the first parallel write data received from the input / output module via the data write bus into second parallel write data in a 1:m2 ratio based on the write clock signal; and The second parallel write data is written to the memory array. Where m1×m2=n.

8. The data operation method of the memory device as described in claim 7, characterized in that, It also includes the following steps: During the data read operation, the serializer circuit in the peripheral interface module is used to convert the parallel read data read from the memory array into first serial read data in an m2:1 ratio based on the read clock signal. During the data read operation, the first serial read data received from the peripheral interface module via the data read bus is converted into second serial read data in a parallel-to-serial manner in an m1:1 ratio using the read pipeline in the input / output module based on the read clock signal. and The second serial read data is output to the data terminal module.

9. The data operation method of the memory device as described in claim 7, characterized in that, Each data terminal is used to input 16 bits of serial write data. The write pipeline performs serial-to-parallel conversion in a 1:8 ratio. The deserializer circuit performs serial-to-parallel conversion in a 1:2 ratio.

10. The data operation method of the memory device as described in claim 8, characterized in that, Each data terminal is used to output 16-bit serial read data. The serializer circuit performs parallel-to-serial conversion in a 2:1 ratio. The read pipeline performs parallel-to-serial conversion in an 8:1 ratio.

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