A DMA system supporting simultaneous requests of multiple peripherals and a method for implementing the same

Abstract

The application discloses a DMA system supporting simultaneous requests of multiple peripherals and an implementation method thereof, wherein the DMA system specifically comprises: a memory access module, which is used for channel arbitration and channel transmission; a channel matching module, which is used for receiving a request of a peripheral, setting a request enable of a corresponding channel and setting a clock control signal of a corresponding peripheral bus; the channel matching module is also used for receiving a first response signal fed back by the memory access module and converting the first response signal into a second response signal whose width can be sampled by the target peripheral; and a response signal from different channels of the memory access module is correctly mapped to different peripherals, so that the target peripheral clears the request signal after receiving the second response signal. The DMA system of the application can support simultaneous requests of multiple peripherals with different working frequencies and generate correct response signals.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and more specifically, to a DMA system that supports simultaneous requests from multiple peripherals and its implementation method. Background Technology

[0002] In general-purpose MCU (microcontroller unit) chips that support AMBA (Advanced Microcontroller Bus Architecture), multiple peripherals with different operating frequencies are connected to meet various application requirements. To reduce the burden on the central processing unit (CPU), these peripherals can support DMA (Direct Memory Access) transfers. In this case, the DMA needs to support multiple channels to satisfy the requests of multiple peripherals. Simultaneously, the DMA also needs to support situations where the peripheral's operating frequency differs from the DMA's operating frequency, and allow the peripheral to request transfers from any DMA channel.

[0003] In the above situation, two problems may occur: first, when the peripheral and DMA operate at different frequencies, the peripheral cannot correctly sample the response signal given by the DMA; second, the response signal transmitted on one channel may be incorrectly output to the peripheral on another channel.

[0004] In existing technologies, the DMA channel requested by peripherals is fixed, so the timing of the requests that DMA needs to process is known. However, this DMA processing method has poor reusability and flexibility. When multiple peripherals request DMA transfer at the same time, the response signal is prone to being accidentally cleared to zero. Summary of the Invention

[0005] To address the technical problem that the DMA cannot correctly generate response signals when multiple peripherals with different operating frequencies simultaneously request multi-channel DMA transfers, this application provides a DMA system and its implementation method that supports simultaneous requests from multiple peripherals. The DMA architecture proposed in this application can support simultaneous requests from multiple peripherals with different operating frequencies and generate correct response signals.

[0006] Specifically, the technical solution of this application is as follows:

[0007] In a first aspect, this application discloses a DMA system supporting simultaneous requests from multiple peripherals, characterized in that the DMA system connects to several peripherals; the DMA system specifically includes:

[0008] The channel matching module is used to receive request signals from peripherals, and is also used to set the request enable of the corresponding channel and the clock control signal of the corresponding peripheral bus according to the channel data of the channel corresponding to the request signal.

[0009] The memory access module is used to receive the channel data. When multiple peripherals request data simultaneously, the memory access module is also used to determine the processing order of the corresponding channels based on the channel data, and to transmit data to the target channels in sequence.

[0010] After the current transmission is completed, the memory access module is also used to generate a first response signal for the target channel;

[0011] The channel matching module is further configured to receive the first response signal and obtain the configuration information of the target channel and the operating frequency of the bus where the target peripheral is located; the channel matching module is further configured to convert the first response signal into a second response signal whose width can be sampled by the target peripheral; so that the target peripheral clears the request signal after receiving the second response signal.

[0012] In some implementations, the channel matching module includes the following sub-modules:

[0013] The request submodule is used to receive request signals from peripherals, and is also used to set the request enable of the corresponding channel and the clock control signal of the corresponding peripheral bus according to the channel data of the channel corresponding to the request signal.

[0014] The widening submodule is used to receive the first response signal and obtain the configuration information of the target channel and the operating frequency of the bus where the target peripheral is located;

[0015] The widening submodule is further configured to convert the first response signal into a second response signal whose width can be sampled by the target peripheral.

[0016] In some implementations, the memory access module includes the following sub-modules:

[0017] A gating submodule is used to receive the channel data;

[0018] The gating submodule is also used to determine the processing order of the corresponding channels based on the channel data when multiple peripherals make simultaneous requests.

[0019] The transmission submodule is used to sequentially transmit data to the target channel.

[0020] The response submodule is used to generate the first response signal for the channel after the current transmission is completed.

[0021] In some implementations, the channel data includes one or more of the following: channel number, channel bandwidth, channel rate, channel distance, and channel environment.

[0022] In some implementations, the DMA system is also connected to a central processing unit and a channel mapping control register;

[0023] The central processing unit is used to configure the channel data of the target channel and the operating frequency of the bus where the target peripheral is located;

[0024] The channel mapping control register is used to configure the mapping relationship between peripherals and channels.

[0025] Secondly, this application also discloses a DMA implementation method that supports simultaneous requests from multiple peripherals, comprising the following steps:

[0026] Receive a request signal from a peripheral device, and based on the channel data of the channel corresponding to the request signal, set the request enable of the corresponding channel and the clock control signal of the corresponding peripheral bus.

[0027] When multiple peripherals make simultaneous requests, the processing order of the corresponding channels is determined based on the channel data, and data is transmitted to the target channels in sequence.

[0028] Upon completion of the current transmission, a first response signal for the target channel is generated; the configuration information of the target channel and the operating frequency of the bus where the target peripheral is located are obtained;

[0029] The first response signal is converted into a second response signal with a width that can be sampled by the target peripheral device; so that the target peripheral device clears the request signal after receiving the second response signal.

[0030] In some implementations, the step of receiving a request signal from a peripheral device is further included before the following steps:

[0031] The central processing unit configures the channel data of the target channel and the operating frequency of the bus where the target peripheral is located;

[0032] The mapping relationship between peripherals and channels is configured through the channel mapping control register.

[0033] In some embodiments, converting the first response signal into a second response signal with a width that can be sampled by the target peripheral includes the following sub-steps:

[0034] The signal broadening size is determined based on the operating frequency of the bus where the target peripheral is located;

[0035] The first response signal is broadened to obtain the second response signal.

[0036] In some implementations, the channel data includes one or more of the following: channel number, channel bandwidth, channel rate, channel distance, and channel environment.

[0037] In some implementations, the channel data is a channel number;

[0038] The process of determining the processing order of corresponding channels based on the channel data specifically includes processing the channels in ascending order of channel number.

[0039] Compared with the prior art, this application has at least one of the following beneficial effects:

[0040] 1. In the event of multiple peripherals making simultaneous requests, this application determines the processing order of the corresponding channels based on the channel data and sequentially transmits data to the target channels. After the transmission is completed, a response signal with a width that can be sampled by the target peripheral is generated and fed back to the corresponding peripheral. In this application, the DMA system ensures that only the selected channel generates a response signal by obtaining which bus the request on each channel originates from. By obtaining which bus the request on each channel originates from, the timing of generating the response signal for that channel ensures that the peripheral on that bus can correctly sample it.

[0041] 2. Before executing the method of this application, the channel data of the target channel and the operating frequency of the bus where the target peripheral is located are configured by the central processing unit. The operating frequency of each peripheral can be flexibly configured. It can also respond normally when multiple peripherals with different operating frequencies make simultaneous requests.

[0042] 3. Configure the mapping relationship between peripherals and channels through the channel mapping control register. Each peripheral can be flexibly configured to be mapped to a specified DMA channel through the register. Attached Figure Description

[0043] The preferred embodiments will now be described in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this application.

[0044] Figure 1 This application provides a structural block diagram of a DMA system embodiment.

[0045] Figure 2 A structural block diagram of another DMA system embodiment provided in this application;

[0046] Figure 3 A structural block diagram of another DMA system embodiment provided in this application;

[0047] Figure 4 A flowchart illustrating the steps of a DMA implementation method supporting simultaneous requests from multiple peripherals provided in this application;

[0048] Figure 5 A flowchart illustrating the steps of another DMA implementation method supporting simultaneous requests from multiple peripherals provided in this application;

[0049] Figure 6This is a schematic diagram of timing operations in the embodiments of this application. Detailed Implementation

[0050] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0051] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or sets.

[0052] To keep the drawings concise, each figure only schematically shows the parts relevant to the invention, and these do not represent the actual structure of the product. Furthermore, to facilitate understanding, in some figures, only one of components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0053] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0054] In this document, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0055] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0056] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the specific implementation methods of this application will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort.

[0057] In general-purpose MCU (microcontroller unit) chip products that support AMBA (Advanced Microcontroller Bus Architecture), in order to meet a variety of applications as much as possible, multiple peripherals with different operating frequencies will be connected. In order to reduce the burden on the central processing unit, these peripherals can support DMA (Direct Memory Access) transfer.

[0058] In this scenario, the DMA needs to support multiple channels to satisfy the requests of multiple peripherals. At the same time, the DMA also needs to support situations where the operating frequency of the peripherals is different from the operating frequency of the DMA, and support the ability for peripherals to request transmission from any DMA channel.

[0059] DMA (Direct Memory Access) transfers data from one address space to another, providing high-speed data transfer between peripherals and memory, or between memory devices. While the CPU initiates the transfer, the transfer itself is implemented and completed by the DMA controller. DMA transfers do not require direct CPU control or interrupt handling (saving and restoring the context). By establishing a direct data transfer channel between RAM and I / O devices through hardware, DMA efficiency is significantly improved.

[0060] In the above situation, two problems may occur: first, when the peripheral and DMA operate at different frequencies, the peripheral cannot correctly sample the response signal given by the DMA; second, the response signal transmitted on one channel may be incorrectly output to a peripheral on another channel. Based on this, this application provides an embodiment of a DMA system supporting simultaneous requests from multiple peripherals, as shown in the appendix to the specification. Figure 1 As shown, it includes:

[0061] The channel matching module is used to receive request signals from peripherals, and also to set the request enable of the corresponding channel and the clock control signal of the corresponding peripheral bus according to the channel data of the channel corresponding to the request signal.

[0062] The memory access module is used to receive the channel data. When multiple peripherals make simultaneous requests, the memory access module is also used to determine the processing order of the corresponding channels based on the channel data, and to transmit data to the target channels in sequence.

[0063] After the current transmission is completed, the memory access module is also used to generate a first response signal for the target channel.

[0064] The channel matching module is further configured to receive the first response signal and acquire the configuration information of the target channel and the operating frequency of the bus where the target peripheral is located. The channel matching module is also configured to convert the first response signal into a second response signal with a width that can be sampled by the target peripheral, so that the target peripheral clears the request signal after receiving the second response signal.

[0065] In this embodiment, the DMA system is also connected to a central processing unit and a channel mapping control register.

[0066] The central processing unit is used to configure the channel data of the target channel and the operating frequency of the bus where the target peripheral is located.

[0067] The channel mapping control register is used to configure the mapping relationship between peripherals and channels.

[0068] For more detailed control logic, please refer to the instruction manual. Figure 2 The DMA system of this application mainly comprises two modules: a channel matching module (CHMAP) and a memory access module (DMA). The DMA module performs channel arbitration and channel transfer. The CHMAP module is responsible for mapping peripheral requests to different channels of the DMA module and generating the operating frequency of the peripheral mapped to each DMA channel. Simultaneously, the CHMAP module is also responsible for correctly mapping response signals from different channels of the DMA module to different peripherals.

[0069] To support the mapping of each peripheral's request to each DMA channel, configuration registers are defined, such as... Figure 2 The CHMAP_REG(x=1,2,3) signal, the number of channel mapping control registers depends on the number of channels supported by the DMA, and the bit width of the channel mapping control register depends on the number of supported peripherals.

[0070] Based on the DMA channel mapped to the peripheral and the bus from which the peripheral originates (AHB, APB1, or APB2), and the relationship between that bus and the memory access module's operating frequency (represented by the signals AHB_CLKEN, APB1_CLKEN, and APB2_CLKEN), the channel matching module generates peripheral clock frequency control signals and channel request signals for each DMA channel. Furthermore, the number of peripheral clock frequency signals and channel request signals for each channel depends on the chip's bus system. Figure 2As shown, if the chip has AHB bus, APB1 bus, and APB2 bus, the corresponding peripheral frequency control signals generated are CHx_AHB_CLKEN, CHx_APB1_CLKEN, and CHx_APB2_CLKEN (x = 1, 2, 3). The corresponding DMA channel request signals generated are CHx_AHB_REQ, CHx_APB1_REQ, and CHx_APB2_REQ.

[0071] The memory access module generates response signals based on the channel. Figure 2 The CHx_ACK (x = 1, 2, 3) signal is based on which bus the peripheral on this channel originates from, and the timing may vary. The CHMAP signal generates a response signal for the corresponding peripheral based on which peripheral requested the channel. This response signal clears the request signal.

[0072] This application provides another embodiment of a DMA system that supports simultaneous requests from multiple peripherals, as shown in the appendix to the specification. Figure 3 As shown, based on the above DMA system embodiment, the DMA system supporting simultaneous requests from multiple peripherals includes: a channel matching module CHMAP and a memory access module DMA.

[0073] The channel matching module CHMAP includes the following sub-modules:

[0074] The request submodule REQMUX is used to receive request signals from peripherals and to set the request enable of the corresponding channel and the clock control signal of the corresponding peripheral bus according to the channel data of the channel corresponding to the request signal.

[0075] The SLAVE_ACKGEN submodule is used to receive the first response signal sent by the memory access module and obtain the configuration information of the target channel and the operating frequency of the bus where the target peripheral is located.

[0076] The SLAVE_ACKGEN submodule is also used to convert the first response signal into a second response signal whose width can be sampled by the target peripheral.

[0077] The memory access module DMA includes the following sub-modules:

[0078] The REQSEL gating submodule is used to receive the channel data.

[0079] The REQSEL gating submodule is also used to determine the processing order of the corresponding channels based on the channel data when multiple peripherals make simultaneous requests.

[0080] The TRANS_CTRL submodule is used to transmit data sequentially to the target channel.

[0081] The ACKGEN submodule is used to generate the first response signal for the channel after the current transmission is completed.

[0082] In one embodiment of this example, the channel data is a channel number.

[0083] The gating submodule is specifically used to process channels in ascending order of channel number.

[0084] For details, please refer to Figure 3 Taking the connection of three peripherals (AHB_SLV / APB1_SLV / APB2_SLV) as an example, the CPU configures the operating frequency of the bus (AHB / APB1 / APB2) where one or more peripherals are located, as well as the channel number mapped to the DMA for each peripheral.

[0085] After the CHMAP module waits for the peripheral request signal to be set, the REQMUX submodule sets the request enable for the channel corresponding to the bus (AHB / APB1 / APB2) according to its mapped channel number and the bus it is on, and generates the clock control signal for the channel corresponding to the bus (AHB / APB1 / APB2).

[0086] The DMA module transmits data for this channel. When multiple channels request data, the REQSEL submodule selects one channel to transmit based on the configured channel number (the channel with the smaller number is transmitted first).

[0087] Once the current transfer is complete, the ACKGEN submodule of the DMA module generates a response signal for that channel.

[0088] The SLAVE ACKGEN submodule of the CHMAP module converts the single-cycle response signal of a certain channel output by the DMA module into a response signal with a width that can be sampled by the peripheral of the corresponding channel, based on the channel configuration of the peripheral and the operating frequency of the bus on which the peripheral is located.

[0089] When the peripheral device receives the response signal, it clears its DMA transfer request signal.

[0090] In another embodiment of this invention, the channel data includes one or more of the following: channel number, channel bandwidth, channel rate, channel distance, and channel environment. Specifically, other channel characteristics can be provided to determine the transmission order, which is set according to the actual situation.

[0091] Based on the same technical concept, this application also discloses an embodiment of a DMA implementation method supporting simultaneous requests from multiple peripherals. This DMA implementation method can be applied to any of the aforementioned DMA systems supporting simultaneous requests from multiple peripherals. (See attached specification.) Figure 4 This includes the following steps:

[0092] S100: Receives a request signal from a peripheral device, and sets the request enable signal for the corresponding channel and the clock control signal for the corresponding peripheral bus according to the channel data of the channel corresponding to the request signal.

[0093] S200: When multiple peripherals make simultaneous requests, the processing order of the corresponding channels is determined according to the channel data, and data is transmitted to the target channels in sequence.

[0094] S300, after the current transmission is completed, a first response signal for the target channel is generated. The configuration information of the target channel and the operating frequency of the bus containing the target peripheral are obtained.

[0095] S400, the first response signal is converted into a second response signal with a width that can be sampled by the target peripheral. This is so that after the target peripheral receives the second response signal, it clears the request signal.

[0096] In this embodiment, step S400, which converts the first response signal into a second response signal whose width can be sampled by the target peripheral device, includes the following sub-steps:

[0097] S410, determine the signal broadening size based on the operating frequency of the bus where the target peripheral is located.

[0098] S420, the first response signal is broadened to obtain the second response signal.

[0099] In another embodiment of this example, before step S100: receiving a request signal from a peripheral device, the following step is further included:

[0100] The central processing unit configures the channel data of the target channel and the operating frequency of the bus where the target peripheral is located.

[0101] The mapping relationship between peripherals and channels is configured through the channel mapping control register.

[0102] In one embodiment of this example, the following assumption is made:

[0103] DMA supports three channels, with channel 1 having the highest priority, followed by channel 2, and then channel 3 having the lowest priority. AHB_SLV is configured for channel 1, APB1_SLV for channel 2, and APB2_SLV for channel 3.

[0104] Specifically, the CLKEN signal for that channel is generated based on the channel mapping control register CHxMAP_REG.

[0105] like Figure 3As shown, assuming the operating frequency of peripherals connected to the AHB bus is the same as the operating frequency of the DMA, the frequency division control signal for peripherals connected to the APB1 bus based on the DMA operating frequency is APB1_CLKEN, and the frequency division control signal for peripherals connected to the APB2 bus based on the DMA operating frequency is APB2_CLKEN. Peripherals on the AHB bus are mapped to DMA channel 1, peripherals on the APB1 bus are mapped to DMA channel 2, and peripherals on the APB2 bus are mapped to DMA channel 3. Then:

[0106] CH1_AHB_CLKEN=AHB_CLKEN, CH1_APB1_CLKEN=0, CH1_APB2_CLKEN=0.

[0107] CH2_AHB_CLKEN=0, CH2_APB1_CLKEN=APB1_CLKEN, CH2_APB2_CLKEN=0.

[0108] CH3_AHB_CLKEN=0, CH3_APB1_CLKEN=0, CH3_APB2_CLKEN=APB2_CLKEN.

[0109] Even better, based on the channel mapping control register CHxMAP_REG, different bus (AHB, APB1, APB2) corresponding peripheral transmission request signals are generated for each DMA channel:

[0110] Taking AHB_SLV as channel 1, APB1_SLV as channel 2, and APB2_SLV as channel 3 as an example, the values ​​of CHx_AHB_REQ, CHx_APB1_REQ, and CHx_APB2_REQ (x = 1, 2, 3) are as follows:

[0111] CH1_AHB_REQ=1, CH1_APB1_REQ=0, CH1_APB2_REQ=0.

[0112] CH2_AHB_REQ=0, CH2_APB1_REQ=1, CH2_APB2_REQ=0.

[0113] CH3_AHB_REQ=0, CH3_APB1_REQ=0, CH3_APB2_REQ=1.

[0114] Even better, after the DMA transfer is completed, an acknowledgment signal (CHx_ACK) is generated for each channel. This signal generates a corresponding peripheral's acknowledgment signal based on the peripheral subject requested by the channel.

[0115] Taking AHB_SLV as channel 1, APB1_SLV as channel 2, and APB2_SLV as channel 3 as an example:

[0116] When CH1_ACK=1, AHB_SLV_ACK=1, APB1_SLV_ACK=0, APB2_SLV_ACK=0;

[0117] When CH2_ACK=1, AHB_SLV_ACK=0, APB1_SLV_ACK=1, APB2_SLV_ACK=0;

[0118] When CH3_ACK=1, AHB_SLV_ACK=0, APB1_SLV_ACK=0, APB2_SLV_ACK=1;

[0119] Another embodiment of a DMA implementation method supporting simultaneous requests from multiple peripherals, as described in the appendix to this application, is as follows. Figure 5 As shown, it includes the following steps:

[0120] Step 1: The CPU configures the channel number of a peripheral device mapped to the DMA, and the operating frequency of the bus where the peripheral device is located.

[0121] Step 2: After the CHMAP module waits for the peripheral request signal to be set, it sets the request signal corresponding to the bus and the clock control signal corresponding to the bus for that channel according to the channel number it is mapped to.

[0122] Step 3: The DMA module transmits the channel data. When multiple channels request data, one channel is selected for transmission based on priority.

[0123] Step 4: After the current transfer is completed, the DMA module generates a response signal for the channel.

[0124] Step 5: The CHMAP module converts the channel response signal output by the DMA module into the response of the corresponding channel based on the channel configuration of the peripheral.

[0125] Step 6: The peripheral device receives the response signal and clears its DMA transfer request signal.

[0126] For details, please refer to Figure 3 Taking the connection of three peripherals (AHB_SLV / APB1_SLV / APB2_SLV) as an example, the CPU configures the operating frequency of the bus (AHB / APB1 / APB2) where one or more peripherals are located, as well as the channel number mapped to the DMA for each peripheral.

[0127] After the CHMAP module waits for the peripheral request signal to be set, the REQMUX submodule sets the request enable for the channel corresponding to the bus (AHB / APB1 / APB2) according to its mapped channel number and the bus it is on, and generates the clock control signal for the channel corresponding to the bus (AHB / APB1 / APB2).

[0128] The DMA module transmits data for this channel. When multiple channels request data, the REQSEL submodule selects one channel to transmit based on the configured channel number (the channel with the smaller number is transmitted first).

[0129] Once the current transfer is complete, the ACKGEN submodule of the DMA module generates a response signal for that channel.

[0130] The SLAVE_ACKGEN submodule of the CHMAP module converts the single-cycle response signal of a certain channel output by the DMA module into a response signal with a width that can be sampled by the peripheral of the corresponding channel, based on the channel configuration of the peripheral and the operating frequency of the bus on which the peripheral is located.

[0131] When the peripheral device receives the response signal, it clears its DMA transfer request signal.

[0132] More preferably, the timing operation of this application is as shown in the appendix to the specification. Figure 6 As shown, the signal is described as follows:

[0133] 1) HCLK: DMA and AHB bus peripheral clock.

[0134] 2) APB1_CLKEN: APB1 bus peripheral clock division control signal, which is 4 times the AHB bus clock HCLK.

[0135] 3) APB2_CLKEN: APB2 bus peripheral clock division control signal, which is 8 times the AHB bus clock HCLK.

[0136] 4) AHB_SLV_REQ: AHB bus peripheral request DMA transfer signal.

[0137] 5) APB1_SLV_REQ: APB1 bus peripheral request DMA transfer signal.

[0138] 6) APB2_SLV_REQ: APB2 bus peripheral request DMA transfer signal.

[0139] 7) CH1_AHB_REQ: The DMA channel 1 transmission request signal generated by the channel matching module indicates that the signal originates from the AHB bus peripheral.

[0140] 8) CH1_APB1_REQ: The DMA channel 1 transmission request signal generated by the channel matching module indicates that the signal originates from the APB1 bus peripheral.

[0141] 9) CH1_APB2_REQ: The DMA channel 1 transmission request signal generated by the channel matching module indicates that the signal originates from the APB2 bus peripheral.

[0142] 10) CH2_APB1_REQ: This is a transfer request signal for DMA channel 2 generated by the channel matching module, indicating that the signal originates from the APB1 bus peripheral. Corresponding signals are CH2_AHB_REQ and CH2_APB2_REQ. Under assumed conditions, these two signals are 0 and are not reflected in the waveform.

[0143] 11) CH3_APB2_REQ: This is a transmission request signal for DMA channel 3 generated by the channel matching module, indicating that the signal originates from the APB2 bus peripheral. Corresponding signals are CH3_AHB_REQ and CH3_APB1_REQ, which, under assumed conditions, are 0 and are not reflected in the waveform.

[0144] 12) DMA_FSM: DMA state machine. The ACTIVE_STATE waveform actually contains multiple states, which are irrelevant to the description, so they are merged into one state.

[0145] 13) CH1_ACK: A signal generated based on the END state of DMA_FSM indicating that the transmission of channel 1 is complete. Assuming that channel 1 is an AHB bus peripheral transmission, this response signal only needs to be maintained for one HCLK width.

[0146] 14) CH2_ACK: A signal generated based on the END state of DMA_FSM indicating that the transmission of channel 2 is complete. Assuming that channel 2 is an APB1 bus peripheral transmission, this response signal is maintained until the APB1_CLKEN signal is high.

[0147] 15) CH3_ACK: A signal generated based on the END state of DMA_FSM indicating that the transmission of channel 3 is complete. Assuming that channel 3 is an APB2 bus peripheral transmission, this response signal is maintained until the APB2_CLKEN signal is high.

[0148] 16) AHB_SLV_ACK: AHB bus peripheral response signal, used to clear AHB_SLV_REQ. Based on the assumption that the AHB bus peripheral is mapped to DMA channel 1, its timing is consistent with CH1_ACK.

[0149] 17) APB1_SLV_ACK: APB1 bus peripheral response signal, used to clear APB1_SLV_REQ. Based on the assumption that the APB1 bus peripheral is mapped to DMA channel 2, its timing is consistent with CH2_ACK.

[0150] 18) APB2_SLV_ACK: APB2 bus peripheral response signal used to clear APB2_SLV_REQ. Based on the assumption that the APB2 bus peripheral is mapped to DMA channel 3, its timing is consistent with CH3_ACK.

[0151] The DMA system and its implementation method that support simultaneous requests from multiple peripherals in this application have the same technical concept, and the technical details of the embodiments of the two are applicable to each other. To reduce repetition, they will not be repeated here.

[0152] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of program modules is merely an example. In practical applications, the above functions can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program units or modules to complete all or part of the functions described above. The program modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software program unit. Furthermore, the specific names of the program modules are only for easy differentiation and are not intended to limit the scope of protection of this application.

[0153] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0154] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0155] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interface; the indirect coupling or communication connection of apparatus or units may be electrical, mechanical, or other forms.

[0156] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0157] Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0158] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0159] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A DMA system supporting simultaneous requests from multiple peripherals, characterized in that, The DMA system connects to several peripherals; the DMA system specifically includes: The channel matching module is used to receive request signals from peripherals, and is also used to set the request enable of the corresponding channel and the clock control signal of the corresponding peripheral bus according to the channel data of the channel corresponding to the request signal. The memory access module is used to receive the channel data. When multiple peripherals request data simultaneously, the memory access module is also used to determine the processing order of the corresponding channels based on the channel data, and to transmit data to the target channels in sequence. After the current transmission is completed, the memory access module is also used to generate a first response signal for the target channel; The channel matching module is further configured to receive the first response signal and obtain the configuration information of the target channel and the operating frequency of the bus where the target peripheral is located; the channel matching module is further configured to convert the first response signal into a second response signal with a width that can be sampled by the target peripheral; so that the target peripheral clears the request signal after receiving the second response signal; The channel matching module includes the following sub-modules: The request submodule is used to receive request signals from peripherals, and is also used to set the request enable of the corresponding channel and the clock control signal of the corresponding peripheral bus according to the channel data of the channel corresponding to the request signal. The widening submodule is used to receive the first response signal and obtain the configuration information of the target channel and the operating frequency of the bus where the target peripheral is located; The widening submodule is also used to convert the first response signal into a second response signal whose width can be sampled by the target peripheral device; The memory access module includes the following sub-modules: A gating submodule is used to receive the channel data; The gating submodule is also used to determine the processing order of the corresponding channels based on the channel data when multiple peripherals make simultaneous requests. The transmission submodule is used to sequentially transmit data to the target channel. The response submodule is used to generate the first response signal for the channel after the current transmission is completed; The DMA system is also connected to a central processing unit and a channel mapping control register; The central processing unit is used to configure the channel data of the target channel and the operating frequency of the bus where the target peripheral is located; The channel mapping control register is used to configure the mapping relationship between peripherals and channels.

2. The DMA system supporting simultaneous requests from multiple peripherals as described in claim 1, characterized in that: The channel data includes one or more of the following: channel number, channel bandwidth, channel rate, channel distance, and channel environment.

3. A DMA implementation method supporting simultaneous requests from multiple peripherals, characterized in that, Includes the following steps: Receive a request signal from a peripheral device, and based on the channel data of the channel corresponding to the request signal, set the request enable of the corresponding channel and the clock control signal of the corresponding peripheral bus. When multiple peripherals make simultaneous requests, the processing order of the corresponding channels is determined based on the channel data, and data is transmitted to the target channels in sequence. Upon completion of the current transmission, a first response signal for the target channel is generated; Obtain the configuration information of the target channel and the operating frequency of the bus where the target peripheral is located; The first response signal is converted into a second response signal whose width can be sampled by the target peripheral device; So that after the target peripheral receives the second response signal, it clears the request signal; The procedure includes the following steps before receiving the request signal from the peripheral device: The central processing unit configures the channel data of the target channel and the operating frequency of the bus where the target peripheral is located; The mapping relationship between peripherals and channels is configured through the channel mapping control register; The process of converting the first response signal into a second response signal with a width that can be sampled by the target peripheral device includes the following sub-steps: The signal broadening size is determined based on the operating frequency of the bus where the target peripheral is located; The first response signal is broadened to obtain the second response signal.

4. The DMA implementation method supporting simultaneous requests from multiple peripherals as described in claim 3, characterized in that, The channel data includes one or more of the following: channel number, channel bandwidth, channel rate, channel distance, and channel environment.

5. A DMA implementation method supporting simultaneous requests from multiple peripherals as described in claim 4, characterized in that, The channel data is the channel number; The process of determining the processing order of corresponding channels based on the channel data specifically includes processing the channels in ascending order of channel number.

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