PUF and TRNG integrated output method, circuit and FPGA

Abstract

The application discloses a PUF and TRNG integrated output method, a circuit and an FPGA, wherein a plurality of excitation data are input to an arbitrator PUF for excitation to obtain excitation-response data; screening is performed to obtain a first excitation data set; the arbitrator PUF is configured; PUF modeling is performed on a 62-stage PUF and a 32-stage PUF respectively, then delay difference selection is performed, the arbitrator PUF is configured through a second excitation data set; finally, an exclusive or processing is performed through the arbitrator PUF to obtain a TRNG value, and a 64-stage output PUF value is obtained through the arbitrator PUF. The application realizes true integration of the PUF and the TRNG, reduces the area and resource overhead, has a simple structure, and can realize simultaneous output of the PUF and the TRNG, in addition, is good in universality and applicable to all delay type PUFs.

Description

Technical Field

[0001] This invention relates to the field of information security, and in particular to an integrated PUF and TRNG output method, circuit, and FPGA. Background Technology

[0002] The security of IoT devices is critical to the IoT ecosystem. Successful compromise of IoT devices by attackers can cause serious damage. PUF (Programmatically PureFunctional) is a lightweight cryptographic primitive ideal for verifying IoT devices operating within power and area constraints. An electronic PUF within the device hardware generates an output bit sequence as a response to the input. The PUF's response to a given challenge should demonstrate uniqueness and reliability. A True Random Number Generator (TRNG) is another cryptographic primitive required by cryptographic protocols to generate keys, random numbers, initialization vectors, etc. TRNG utilizes random variations introduced by physical noise sources to generate an unpredictable output bit sequence that changes each time it is generated.

[0003] In recent years, integrated PUF and TRNG solutions have developed rapidly. These structures are mostly based on the integrated design of memory cells and ring oscillators. The shortcomings of existing integrated PUF and TRNG solutions are: in the existing technology, the circuits of PUF and TRNG are mostly designed separately and then assembled together, which consumes a lot of area and has a complex structure. They are not truly integrated designs, and they cannot output PUF values ​​and TRNG values ​​at the same time. Therefore, their functions are not fully integrated, and they are only for a fixed structure and do not have universality. Summary of the Invention

[0004] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes an integrated PUF and TRNG output method, circuit, and FPGA, which can solve the problems of complex structure, high resource consumption, inability to simultaneously output PUF and TRNG values, and poor versatility of existing integrated PUF and TRNG solutions.

[0005] A method for integrated PUF and TRNG output according to a first aspect embodiment of the present invention includes the following steps: Multiple stimulus data are input into the arbitrator PUF for stimulus, and the response value of the 64-level arbitrator PUF is obtained. The stimulus-response data is obtained based on the stimulus data and the response value. The stimulus-response data is filtered to obtain the first stimulus dataset, and the first stimulus-response data in the first stimulus dataset satisfies the stability, uniqueness and uniformity of PUF; Configure the arbitrator PUF using the first stimulus dataset to obtain the response values ​​of the 62-level arbitrator PUF and the 32-level arbitrator PUF; The response values ​​of the 62-level arbitrator PUF and the 32-level arbitrator PUF were modeled using the logistic regression algorithm. Then, the delay difference was selected to obtain the stimulus-response data that is closest to the delay difference of the 62-level and 32-level arbitrator PUF, thus obtaining the second stimulus dataset. Configure the arbitrator PUF using the second incentive dataset; The TRNG value is obtained by XORing with the arbiter PUF, and the PUF value of the 64-level output is obtained by the arbiter PUF.

[0006] The integrated PUF and TRNG output method according to the first aspect of the present invention has at least the following beneficial effects: In this embodiment of the invention, multiple stimulus data are first input into the Arbitrator PUF for stimulation to obtain the response values ​​of a 64-level arbitrator PUF. Stimulus-response data is then obtained based on the stimulus data and response values. Next, the stimulus-response data is filtered to obtain a first stimulus dataset, where the first stimulus-response data satisfies the stability, uniqueness, and uniformity of the PUF. The arbitrator PUF is configured using the first stimulus dataset to obtain the response values ​​of a 62-level and a 32-level arbitrator PUF. PUF modeling is then performed on the response values ​​of the 62-level and 32-level arbitrator PUFs using a logistic regression algorithm. Delay difference selection is then performed to obtain the stimulus-response data closest to the delay difference of the 62-level and 32-level arbitrator PUFs, resulting in a second stimulus dataset. The arbitrator PUF is then configured using the second stimulus dataset. Finally, the TRNG value is obtained by XORing the arbitrator PUF, and the PUF value output by the 64-level arbitrator PUF is obtained. This invention achieves true integration of PUF and TRNG, reducing area and resource overhead, with a simple structure, and can achieve simultaneous output of PUF and TRNG. In addition, it has good versatility and is applicable to all types of delay PUF.

[0007] According to some embodiments of the present invention, in the step of inputting the excitation data to the arbitrator PUF for excitation, more than 5,000 64-bit excitation data are input to the arbitrator PUF for excitation.

[0008] According to some embodiments of the present invention, in the step of filtering the stimulus-response data to obtain the first stimulus dataset, all first stimulus-response data with uniformity approaching 50%, uniqueness approaching 50%, and stability approaching 100% are filtered as the first stimulus dataset.

[0009] According to some embodiments of the present invention, the specific steps for obtaining the TRNG value through XOR processing via the arbiter PUF are as follows: Obtain the response values ​​of the 2-power-level arbitrator PUF and the 62-level arbitrator PUF through the arbitrator PUF; The TRNG value is obtained by XORing the response values ​​of the 2-power-level arbitrator PUF and the 62-level arbitrator PUF.

[0010] According to a second aspect of the present invention, an FPGA-based integrated PUF and TRNG circuit includes: The arbitrator PUF module is used to output a corresponding response value based on the input excitation data. A control module, connected to the arbitrator PUF module, is used to control the output of the TRNG value and the PUF value; The VIO module is connected to the arbitrator PUF module and the control module respectively to realize data output and data input; A data processing unit, which is connected to the VIO module.

[0011] The FPGA-based integrated PUF and TRNG circuit according to the second aspect of the present invention has at least the following beneficial effects: In this embodiment of the invention, multiple stimulus data are first input into the Arbitrator PUF for stimulation to obtain the response values ​​of a 64-level arbitrator PUF. Stimulus-response data is then obtained based on the stimulus data and response values. Next, the stimulus-response data is filtered to obtain a first stimulus dataset, where the first stimulus-response data satisfies the stability, uniqueness, and uniformity of the PUF. The arbitrator PUF is configured using the first stimulus dataset to obtain the response values ​​of a 62-level and a 32-level arbitrator PUF. PUF modeling is then performed on the response values ​​of the 62-level and 32-level arbitrator PUFs using a logistic regression algorithm. Delay difference selection is then performed to obtain the stimulus-response data closest to the delay difference of the 62-level and 32-level arbitrator PUFs, resulting in a second stimulus dataset. The arbitrator PUF is then configured using the second stimulus dataset. Finally, the TRNG value is obtained by XORing the arbitrator PUF, and the PUF value output by the 64-level arbitrator PUF is obtained. This invention achieves true integration of PUF and TRNG, reducing area and resource overhead, with a simple structure, and can achieve simultaneous output of PUF and TRNG. In addition, it has good versatility and is applicable to all types of delay PUF.

[0012] According to some embodiments of the present invention, the control module includes a puf_fsm module and a trng_fsm module. The puf_fsm module is used to control the PUF value output of the arbitrator PUF module, and the trng_fsm module is used to control the start and stop of the arbitrator PUF module and XOR the PUF value of a specified level to obtain a random value.

[0013] According to some embodiments of the present invention, the arbiter PUF module includes a trigger module, a chain_group module, a compensation module, and an arbiter module connected in sequence. The trigger module is used to control pulse transmission, the chain_group module is used to implement the circuit for arbitrating the PUF, the compensation module is used to compensate for delay difference, and the arbiter module is used to determine the speed of the two lines.

[0014] According to some embodiments of the present invention, an ILA module is also included, which is used to monitor signals between the arbitrator PUF module, the control module, and the VIO module.

[0015] According to a third aspect of the present invention, the FPGA includes the above-described integrated circuit of FPGA-based PUF and TRNG.

[0016] The FPGA according to the third aspect embodiment of the present invention has at least the following beneficial effects: In this embodiment of the invention, multiple stimulus data are first input into the Arbitrator PUF for stimulation to obtain the response values ​​of a 64-level arbitrator PUF. Stimulus-response data is then obtained based on the stimulus data and response values. Next, the stimulus-response data is filtered to obtain a first stimulus dataset, where the first stimulus-response data satisfies the stability, uniqueness, and uniformity of the PUF. The arbitrator PUF is configured using the first stimulus dataset to obtain the response values ​​of a 62-level and a 32-level arbitrator PUF. PUF modeling is then performed on the response values ​​of the 62-level and 32-level arbitrator PUFs using a logistic regression algorithm. Delay difference selection is then performed to obtain the stimulus-response data closest to the delay difference of the 62-level and 32-level arbitrator PUFs, resulting in a second stimulus dataset. The arbitrator PUF is then configured using the second stimulus dataset. Finally, the TRNG value is obtained by XORing the arbitrator PUF, and the PUF value output by the 64-level arbitrator PUF is obtained. This invention achieves true integration of PUF and TRNG, reducing area and resource overhead, with a simple structure, and can achieve simultaneous output of PUF and TRNG. In addition, it has good versatility and is applicable to all types of delay PUF.

[0017] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 This is a flowchart of the integrated PUF and TRNG output method in an embodiment of the present invention; Figure 2 This is a circuit schematic diagram of the FPGA-based integrated PUF and TRNG circuit in an embodiment of the present invention; Figure 3 This is a schematic diagram of the control module in an embodiment of the present invention; Figure 4 This is a state diagram of the puf_fsm module in an embodiment of the present invention; Figure 5 This is a state diagram of the trng_fsm module in an embodiment of the present invention; Figure 6 This is a schematic diagram of the arbitrator PUF module in an embodiment of the present invention; Figure 7 This is the core circuit diagram of the arbitrator PUF module in an embodiment of the present invention. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the drawings and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0021] In the description of this invention, "multiple" refers to two or more. The use of "first" and "second" is for distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features or their sequential relationship.

[0022] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0023] First, let's analyze some of the terms used in this application: PUF: A hardware security technique that leverages inherent device variations to produce a unique, non-cloning device response to a given input; TRNG: A function or device based on an unpredictable physical phenomenon (called an entropy source) used to generate nondeterministic data to provide seeds for secure algorithms. Arbitrator PUF: The arbitrator PUF is a module used to output PUF values. Its principle is as follows: Assume there are two perfectly symmetrical paths A and B, with identical path lengths and materials. If a pulse level is simultaneously applied to the left side of both ends of A and B, they will both reach the arbitrator C after a certain time. The arbitrator C then arbitrates the arrival order of A and B. Ideally, because the two paths are perfectly symmetrical and use the same material, their delays are exactly the same, and A and B will arrive simultaneously. However, in actual implementation, slight deviations in the manufacturing process can prevent the delays of paths A and B from being completely identical. Therefore, the arrival times at the arbitrator C are not consistent, and the output of the arbitrator C will also differ. Since these slight deviations in the manufacturing process are completely random, the path delays of A and B are also completely random, ultimately making the output of the arbitrator C unpredictable.

[0024] Reference Figure 1 As shown, an integrated PUF and TRNG output method includes the following steps: S100. Input multiple challenge data into the arbitrator PUF for stimulation, obtain the response value of the 64-level arbitrator PUF, and obtain challenge-response data based on the challenge data and response value. It should be noted that the excitation data in step S100 refers to the control selection of parallel lines or cross lines. The excitation data is input into the arbitrator PUF for excitation, and the corresponding response value is obtained. The excitation-response data, also known as the CRP pair, is obtained by statistically analyzing the input excitation data and the corresponding response value obtained by the arbitrator PUF.

[0025] It should be noted that, after repeated experiments, 4,000 64-bit stimulus data are usually required to complete PUF modeling. Using more than 5,000 stimulus data can make the modeling more accurate. In this embodiment, 10,000 64-bit stimulus inputs are used to the arbiter PUF to improve the accuracy of the modeling.

[0026] S200. Filter the stimulus-response data to obtain the first stimulus dataset. The first stimulus-response data in the first stimulus dataset satisfies the stability, uniqueness and uniformity of PUF. It should be noted that in step S200, satisfying the stability, uniqueness, and uniformity of PUF refers to the first stimulus-response data with uniformity approaching 50%, uniqueness approaching 50%, and stability approaching 100%.

[0027] The following describes the calculation methods for the stability, uniqueness, and uniformity of PUF: The stability of a PUF (Programmatic Activated Function) refers to the difference in its output response when external factors change, given that the same PUF entity is continuously input with the same challenge. Ideally, the stability of a PUF entity tends to be 100%. The formula for calculating the stability of a PUF is as follows:

[0028] Where m represents the number of measurements, HD(R) g , R t ) represents the on-chip Hamming distance of the arbitrator PUF, m is the number of the same challenge (input), and n is the bit width of the arbitrator PUF's output response.

[0029] The uniqueness of a PUF refers to the difference in responses produced by multiple PUF entities that are structurally identical but independent. Ideally, the uniqueness value tends to be 50%. The formula for calculating the uniqueness of a PUF is as follows:

[0030] Where k is the number of arbitrator PUFs participating in the test, HD(R) i , R j) The inter-chip Hamming distance of the arbitrator PUF. The uniformity of a PUF (Physical Response Function) refers to the probability of 1 and 0 appearing in all responses generated by the same PUF entity. Ideally, the uniformity of a PUF tends to be 50%. The formula for calculating the uniformity of a PUF is as follows:

[0031] Where, r i,j This is the value of the j-th bit of the i-th response.

[0032] It should be understood that the screening of stimulus-response data in step S200 refers to screening all first stimulus-response data with uniformity close to 50%, uniqueness close to 50%, and stability close to 100%.

[0033] S300. Configure the arbitrator PUF through the first stimulus dataset to obtain the response values ​​of the 62-level arbitrator PUF and the 32-level arbitrator PUF. S400: The response values ​​of the 62-level arbitrator PUF and the 32-level arbitrator PUF are modeled using the logistic regression algorithm. Then, the delay difference is selected to obtain the stimulus-response data that is closest to the delay difference of the 62-level and 32-level arbitrator PUF, thus obtaining the second stimulus dataset. It should be noted that the logistic regression algorithm refers to using a logistic function to map the result of linear regression from (-∞, ∞) to (0, 1); where the linear regression function is: , in, It is a constant. It is a vector.

[0034] Therefore, the logistic regression function can be obtained as follows:

[0035] Where e is a mathematical constant.

[0036] It should be noted that the PUF modeling formula is as follows: , , ; , , ; When t = -1, the response = 0; when t = 1, the response = 1.

[0037] Where C represents the excitation data, C = b1...bk, where b1...bk are the excitation values ​​for the corresponding levels. For example, b1 = 1 —> the excitation data for the first level of the arbitrator PUF is 1; For latency difference, w represents the latency of each stage of the APUF. For functions in C, When b=0 This represents the parallel time of the i-th level PUF, when b=1. Let T represent the cross-line time of the i-th level PUF, where T is a vector.

[0038] It should be noted that in step S400, the delay difference selection to obtain the stimulus-response data that is closest to the delay difference of the 62-level and 32-level arbitrator PUF means selecting stimulus-response data that is close to both the delay difference of the 62-level and the delay difference of the 32-level arbitrator, that is, stimulus-response data with a delay difference close to 0.

[0039] S500, Configure the arbitrator PUF through the second incentive dataset; It should be noted that after configuring the arbitrator PUF through the second incentive dataset, the response value of each level of the arbitrator PUF can be obtained.

[0040] S600: The TRNG value is obtained by XORing through the arbiter PUF, and the PUF value of the 64-level output is obtained through the arbiter PUF.

[0041] It should be noted that the specific steps for obtaining the TRNG value through XOR processing using the arbiter PUF are as follows: S601. Obtain the response values ​​of the power-of-2 arbitrator PUF and the 62-level arbitrator PUF through the arbitrator PUF. S602. The TRNG value is obtained by XORing the response value of the 2-power-level arbitrator PUF and the response value of the 62-level arbitrator PUF.

[0042] It should be understood that the response value of the arbitrator PUF with powers of 2 refers to the response value of 2^n (n=1,2,3,4,5,6) levels of the arbitrator PUF. Because the randomness of each level is different, the use of powers of 2 in this invention can increase the randomness. In addition to using powers of 2, other methods can be used to XOR the response value, such as XORing all levels, or XORing powers of 3 with 62 levels and 32 levels, etc.

[0043] It should be noted that the PUF value obtained through the arbitrator PUF is the response value of the 64-level arbitrator PUF.

[0044] refer to Figure 2 The diagram shows an integrated PUF and TRNG circuit based on FPGA that applies the above-mentioned method according to the present invention. It includes: an arbitrator PUF module, a control module, a VIO module, and a data processing unit. The arbitrator PUF module, control module, and VIO (virtual input output) module are hardware, while the data processing unit is software. It performs PUF modeling and delay difference selection functions. The data processing unit can be a host computer or other data processing chip running related functional software.

[0045] Specifically, the arbitrator PUF module is used to output the corresponding response value based on the input stimulus data; the control module is connected to the arbitrator PUF module to control the output of TRNG and PUF values; the VIO module is connected to both the arbitrator PUF module and the control module to realize data output and data input; the data processing unit is connected to the VIO module, and the data processing unit transmits signals to the PUF module and the control module through the VIO module to send and receive stimulus data and response values.

[0046] For details, please refer to Figure 3 As shown, in this embodiment of the invention, the control module includes a puf_fsm module and a trng_fsm module, which are two state machines. (Refer to...) Figure 4 As shown, the puf_fsm module is used to control the PUF value output of the arbitrator's PUF module. In this invention, the puf_fsm module controls the PUF module to output a PUF value every five times. The output value is only output when the number of 1s in the five output values ​​is greater than or equal to 4 and less than or equal to 1, thus ensuring the stability of the PUF value. (Reference) Figure 5 As shown, the trng_fsm module is used to control the startup and shutdown of the arbiter PUF module and to XOR the PUF value of the specified level to obtain a random value. It should be understood that in this embodiment, the specified level refers to the power of 2 level and the 62 level.

[0047] refer to Figure 6 As shown, the arbitrator PUF module includes a trigger module, a chain_group module, a compensation module, and an arbiter module connected in sequence. The trigger module is used to control pulse transmission. In this embodiment, the trigger module controls the pulse to be transmitted once every 10 cycles. Since a PUF value is output five times in this embodiment, and each output of a PUF value requires 2 cycles, the pulse is set to be transmitted once every 10 cycles. The chain_group module is the specific circuit for implementing the arbitration PUF. The compensation module is used to compensate for the delay difference. The arbiter module is used to determine the speed of the two lines.

[0048] It's important to note that since FPGAs don't have two perfectly symmetrical lines, a compensation module is needed to compensate for the delay difference, resulting in two nearly identical lines. The arbitration PUF module uses the imperfection of the two lines to determine speed, a consequence of the manufacturing process. These imperfectly symmetrical lines refer to lines that were originally perfectly symmetrical after board installation, but due to process limitations, they experience delays, leading to asymmetry. Therefore, the compensation module is needed to compensate for this delay difference. The specific implementation steps are as follows: first, two perfectly symmetrical lines are constructed in the code, compensated for by the compensation module; then, after board installation, the process results in two lines with a delay difference. This delay difference is random, thus enabling the PUF's decision.

[0049] It should be noted that the reference is... Figure 7 As shown, the arbitrator PUF module in this invention has an asynchronous clear D flip-flop with FDCE (Flip-Flop with Clock Enable and Asynchronous Reset) function. FDCE is set in the chain_group module. Compared with FDRE, it changes the synchronous reset to an asynchronous reset. When the synchronous reset interface is high, it directly triggers the register reset (sets it to 0); when the synchronous clock interface is low and the enable interface is high, the rising edge of the clock triggers the register to load the data from the data interface.

[0050] It should be noted that the arbitrator PUF module in the hardware circuit of this invention can be replaced by other delay-type PUFs, which has wide adaptability.

[0051] It should be noted that, Figure 7 The pulse signal is sent by the trigger module, and its PUF value is [value missing]. Figure 6 The arbiter_out signal, TRN is Figure 6 The atbiter_out_i signal, i.e., the TRNG value.

[0052] refer to Figure 2 As shown, it also includes an ILA module, which is used to monitor the signals between the arbitrator PUF module, the control module, and the VIO module. Its purpose is to observe the waveform and data input and output.

[0053] The present invention also relates to an FPGA, including the FPGA-based integrated circuit of PUF and TRNG described in the above embodiments.

[0054] In summary, this invention obtains random numbers by modeling and configuring stimuli through PUF and increases randomness through feedback. By selecting stimuli that satisfy both PUF and TRNG, it achieves true integration of PUF and TRNG, reducing area and resource overhead, simplifying the structure, and enabling simultaneous output of PUF and TRNG. Furthermore, it has good versatility and is applicable to PUFs of all delay types.

[0055] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for integrated output of PUF and TRNG, characterized in that, Includes the following steps: Multiple stimulus data are input into the arbitrator PUF for stimulus, and the response value of the 64-level arbitrator PUF is obtained. The stimulus-response data is obtained based on the stimulus data and the response value. The stimulus-response data is filtered to obtain the first stimulus dataset, and the first stimulus-response data in the first stimulus dataset satisfies the stability, uniqueness and uniformity of PUF; Configure the arbitrator PUF using the first stimulus dataset to obtain the response values ​​of the 62-level arbitrator PUF and the 32-level arbitrator PUF; The response values ​​of the 62-level arbitrator PUF and the 32-level arbitrator PUF were modeled using the logistic regression algorithm. Then, the delay difference was selected to obtain the stimulus-response data that is closest to the delay difference of the 62-level and 32-level arbitrator PUF, thus obtaining the second stimulus dataset. Configure the arbitrator PUF using the second incentive dataset; The TRNG value is obtained by XORing with the arbiter PUF, and the PUF value with 64 levels of output is obtained by the arbiter PUF. The specific steps for obtaining the TRNG value through XOR processing using the arbiter PUF are as follows: Obtain the response values ​​of the 2-power-level arbitrator PUF and the 62-level arbitrator PUF through the arbitrator PUF; The TRNG value is obtained by XORing the response values ​​of the 2-power-level arbitrator PUF and the 62-level arbitrator PUF.

2. The integrated PUF and TRNG output method according to claim 1, characterized in that, In the step of inputting multiple stimulus data into the arbitrator PUF for stimulus, more than 5,000 64-bit stimulus data are input into the arbitrator PUF for stimulus.

3. The integrated PUF and TRNG output method according to claim 1, characterized in that, In the step of filtering the stimulus-response data to obtain the first stimulus dataset, all first stimulus-response data with uniformity approaching 50%, uniqueness approaching 50%, and stability approaching 100% are selected as the first stimulus dataset.

4. An integrated FPGA-based PUF and TRNG circuit applying the method of any one of claims 1 to 3, characterized in that, include: The arbitrator PUF module is used to output a corresponding response value based on the input excitation data. A control module, connected to the arbitrator PUF module, is used to control the output of the TRNG value and the PUF value; The VIO module is connected to the arbitrator PUF module and the control module respectively to realize data output and data input; A data processing unit, which is connected to the VIO module.

5. The FPGA-based integrated PUF and TRNG circuit according to claim 4, characterized in that, The control module includes a puf_fsm module and a trng_fsm module. The puf_fsm module is used to control the PUF value output of the arbiter PUF module, and the trng_fsm module is used to control the start and stop of the arbiter PUF module and XOR the PUF value of a specified level to obtain a random value.

6. The FPGA-based integrated PUF and TRNG circuit according to claim 4, characterized in that, The arbiter PUF module includes a trigger module, a chain_group module, a compensation module, and an arbiter module connected in sequence. The trigger module is used to control pulse transmission, the chain_group module is used to implement the circuit for arbitrating the PUF, the compensation module is used to compensate for delay differences, and the arbiter module is used to determine the speed of the two lines.

7. The FPGA-based integrated PUF and TRNG circuit according to claim 4, characterized in that, It also includes an ILA module, which is used to monitor the signals between the arbitrator PUF module, the control module, and the VIO module.

8. An FPGA, characterized in that, Includes the FPGA-based integrated PUF and TRNG circuit as described in any one of claims 4 to 7.

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