Chip grid division method and device, electronic equipment and storage medium

Abstract

The application provides a chip grid division method and device, electronic equipment and storage medium, relates to the technical field of chip simulation, and comprises the following steps: determining the chip heat dissipation type of a target chip, the chip heat dissipation type comprising any one of a natural heat dissipation type, an air cooling heat dissipation type and a water cooling heat dissipation type; calculating the power density of the target chip based on the chip heat dissipation type, wherein the power density comprises a surface power density corresponding to the natural heat dissipation type and the air cooling heat dissipation type, and a volume power density corresponding to the water cooling heat dissipation type; determining a target grid encryption level corresponding to the power density; and performing grid division processing on the target chip based on the target grid encryption level. The application can perform chip grid division according to different chip power densities, and can take into account simulation accuracy and calculation time.

Description

Technical Field

[0001] This application relates to the field of chip simulation technology, and in particular to a chip meshing method, apparatus, electronic device and storage medium. Background Technology

[0002] Currently, chip thermal simulation typically relies on industrial software, such as Icepak and Flotherm. With thermal simulation software, users can reduce design costs, increase first-pass yield, improve electronic product performance, enhance product reliability, and shorten time-to-market. Appropriate mesh size can achieve accurate thermal simulation results while balancing computation time. When meshing, it's necessary to set the base mesh size and encryption level for the chip. A smaller base mesh size and a higher encryption level result in a smaller mesh size and more accurate simulation results, but this also increases computation time. Therefore, it's not advisable to simply reduce the mesh size indiscriminately.

[0003] In typical thermal simulations, the same base mesh size and encryption level are set for all chips. This can lead to some chips having insufficient mesh size, causing simulation deviations, or some chips having excessively small mesh size, increasing computation time. Consequently, it becomes impossible to balance simulation accuracy and computation time. Summary of the Invention

[0004] This application provides a chip meshing method, apparatus, electronic device, and storage medium, which can perform chip meshing according to different chip power densities, and can balance simulation accuracy and computation time.

[0005] Firstly, a chip meshing method is provided, including:

[0006] Determine the heat dissipation type of the target chip, which can be any one of natural heat dissipation, air cooling, or water cooling.

[0007] The power density of the target chip is calculated based on the chip heat dissipation type, where the power density includes the surface power density corresponding to natural heat dissipation type and air cooling type, and the volumetric power density corresponding to water cooling type.

[0008] Determine the target mesh density level;

[0009] The target chip is divided into grids based on the target grid encryption level.

[0010] Secondly, a chip grid division device is provided, comprising:

[0011] The first determining module is used to determine the heat dissipation type of the target chip, which includes any one of natural heat dissipation, air cooling, and water cooling.

[0012] The calculation module is used to calculate the power density of the target chip based on the chip heat dissipation type, wherein the power density includes the surface power density corresponding to the natural heat dissipation type and the air cooling type, and the volumetric power density corresponding to the water cooling type.

[0013] The second determining module is used to determine the target grid encryption level corresponding to the power density;

[0014] The processing module is used to perform mesh partitioning on the target chip based on the target mesh encryption level.

[0015] Thirdly, an electronic device is provided, comprising: a processor and a memory for storing a computer program, the processor for calling and running the computer program stored in the memory, and performing the methods as described in the first aspect or its various implementations.

[0016] Fourthly, a computer-readable storage medium is provided for storing a computer program that causes a computer to perform the methods described in the first aspect or its various implementations.

[0017] The technical solution provided in this application allows for the first determination of the heat dissipation type of the target chip, followed by the calculation of the power density of the target chip based on the heat dissipation type, and the determination of the target mesh refinement level corresponding to the power density. Finally, the target chip is meshed based on the target mesh refinement level. The technical solution in this disclosure allows for differentiated chip meshing based on different surface or volumetric power densities of the target chip. During the chip meshing process, both simulation accuracy and computation time can be considered to ensure the effectiveness of the chip meshing.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Other features and advantages of this application will be described in detail in the subsequent detailed description section. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 An application scenario diagram provided for an embodiment of this application;

[0021] Figure 2 A schematic flowchart illustrating a chip mesh partitioning method provided in an embodiment of this application;

[0022] Figure 3 A flowchart illustrating a chip meshing method according to another embodiment of this application;

[0023] Figure 4 This is a schematic diagram illustrating an example of mesh division under a natural heat dissipation type, provided in an embodiment of this application.

[0024] Figure 5 A schematic diagram illustrating an example of mesh division levels under different chip surface power densities provided in this application embodiment;

[0025] Figure 6 A schematic diagram illustrating the principle of chip mesh partitioning provided in this application embodiment;

[0026] Figure 7 This is a schematic diagram of a chip grid division device provided in an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of a chip grid division device provided in an embodiment of this application;

[0028] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0031] Currently, chip thermal simulation typically relies on industrial software, such as Icepak and Flotherm. With thermal simulation software, users can reduce design costs, increase first-pass yield, improve electronic product performance, enhance product reliability, and shorten time-to-market. Appropriate mesh size can achieve accurate thermal simulation results while balancing computation time. When meshing, it's necessary to set the base mesh size and encryption level for the chip. A smaller base mesh size and a higher encryption level result in a smaller mesh size and more accurate simulation results, but this also increases computation time. Therefore, it's not advisable to simply reduce the mesh size indiscriminately.

[0032] In typical thermal simulations, the same base mesh size and encryption level are set for all chips. This can lead to some chips having insufficient mesh size, causing simulation deviations, or some chips having excessively small mesh size, resulting in increased computation time.

[0033] To address the aforementioned technical problems, the inventive concept of this application is that electronic devices can differentiate chip grid partitioning based on different chip power densities, thereby balancing simulation accuracy and computation time in chip grid partitioning.

[0034] It should be understood that the technical solution of this application can be applied to the following scenarios, but is not limited to:

[0035] In some possible ways, Figure 1 An application scenario diagram provided for an embodiment of this application, such as... Figure 1 As shown, this application scenario may include electronic device 110 and network device 120. Electronic device 110 can establish a connection with network device 120 through a wired network or a wireless network.

[0036] For example, electronic device 110 may be a desktop computer, laptop computer, tablet computer, etc., but is not limited thereto. Network device 120 may be a terminal device or a server, but is not limited thereto. In one embodiment of this application, electronic device 110 may send a request message to network device 120, which may be used to request the chip heat dissipation type of the target chip. Further, electronic device 110 may receive a response message sent by network device 120, which includes the chip heat dissipation type of the target chip.

[0037] also, Figure 1 An electronic device 110 and a network device 120 are provided as examples, but other numbers of electronic devices and network devices may be included in practice, and this application does not limit this.

[0038] In other possible implementations, the technical solution of this application may also be executed by the aforementioned electronic device 110, or by the aforementioned network device 120, and this application does not impose any restrictions on this.

[0039] After introducing the application scenarios of the embodiments of this application, the technical solution of this application will be described in detail below:

[0040] Figure 2 This is a flowchart illustrating a chip mesh partitioning method provided in an embodiment of this application. This method can be performed by, for example... Figure 1 The electronic device 110 shown performs, but is not limited to, its functions. For example... Figure 2 As shown, the method may include the following steps:

[0041] Step 210: Determine the heat dissipation type of the target chip. The heat dissipation type can be any one of natural heat dissipation, air cooling, or water cooling.

[0042] In this context, the target chip is the chip to be meshed. Unlike typical thermal simulations that apply the same basic mesh size and mesh refinement level to all chips, this embodiment allows for differentiated meshing based on different chip heat dissipation types. For target chips with natural or air-cooled heat dissipation, meshing can be performed based on surface power density; for target chips with water-cooled heat dissipation, meshing can be performed based on volumetric power density.

[0043] In the embodiments of this disclosure, after determining the target chip to be meshed, the chip heat dissipation type of the target chip can be determined first, so that meshing can be performed differently based on different chip heat dissipation types.

[0044] Step 220: Calculate the power density of the target chip based on the chip heat dissipation type, wherein the power density includes the surface power density corresponding to the natural heat dissipation type and the air cooling type, and the volumetric power density corresponding to the water cooling type.

[0045] In one possible implementation of this disclosure, when the heat dissipation type of the target chip is determined to be either natural heat dissipation or air cooling, the heat dissipation capacity of the chip is related to the surface area of ​​the chip, and the surface power density of the target chip can be calculated. In another possible implementation, when the heat dissipation type of the target chip is determined to be water cooling, the heat dissipation capacity of the chip is related to the volume of the chip, and the volumetric power density of the target chip can be calculated.

[0046] Step 230: Determine the target grid densification level corresponding to the power density.

[0047] In one possible implementation of this disclosure, when calculating the surface power density corresponding to the natural heat dissipation type and the air-cooled heat dissipation type, the target mesh density level corresponding to the surface power density can be further determined; in another possible implementation, when calculating the volumetric power density corresponding to the water-cooled heat dissipation type, the target mesh density level corresponding to the volumetric power density can be further determined.

[0048] Step 240: Perform mesh division processing on the target chip based on the target mesh encryption level.

[0049] Among them, the target mesh refinement level is the optimal mesh refinement level that achieves a certain accuracy requirement for simulation while having a relatively short computation time, under the corresponding chip heat dissipation type of the target chip.

[0050] In the embodiments of this disclosure, after determining the target mesh encryption level corresponding to the target chip, the target chip can be meshed based on the target mesh encryption level. Since the target mesh encryption level is the optimal mesh encryption level determined based on the surface power density or volume power density of the target chip, which can achieve a certain accuracy requirement and has a relatively short calculation time, simulation accuracy and calculation time can be taken into account during the meshing process.

[0051] In summary, according to the chip meshing method provided in this application, the heat dissipation type of the target chip can be determined first, then the power density of the target chip can be calculated based on the heat dissipation type, and the target mesh density level corresponding to the power density can be determined; finally, the target chip is meshed based on the target mesh density level. The technical solution in this disclosure can perform differentiated chip meshing according to different surface power densities or volumetric power densities of the target chip. During the chip meshing process, simulation accuracy and computation time can be balanced to ensure the effectiveness of the chip meshing.

[0052] based on Figure 2 The embodiments shown are refinements and extensions of the above embodiments. To fully illustrate the specific implementation process of the method in this embodiment, this embodiment provides the following: Figure 3 The specific method is shown. Figure 3 based on Figure 2 The illustrated embodiment further defines step 230. Figure 2 In the illustrated embodiment, step 230 includes steps 330 to 350. As shown in Figure 3, the method includes the following steps:

[0053] Step 310: Determine the heat dissipation type of the target chip. The heat dissipation type can be any one of natural heat dissipation, air cooling, or water cooling.

[0054] For the specific implementation process of the embodiments disclosed herein, please refer to the relevant description in step 210 of the embodiment, which will not be repeated here.

[0055] Step 320: Calculate the power density of the target chip based on the chip heat dissipation type, wherein the power density includes the surface power density corresponding to the natural heat dissipation type and the air cooling type, and the volumetric power density corresponding to the water cooling type.

[0056] In one possible implementation of this disclosure, when the target chip's heat dissipation type is natural heat dissipation or air cooling, the surface power density of the target chip can be calculated. Assuming the target chip's power is P, and the chip dimensions (chip length, chip width, and chip height) are x, y, and z, respectively, for a target chip with natural heat dissipation or air cooling, since the chip's heat dissipation capacity is related to its surface area, the surface power density of each target chip is calculated as P / (2xy+2yz+2xz), in W / mm². Accordingly, the implementation steps may include: obtaining the target chip's power and chip dimensions, including chip length, chip width, and chip height; calculating the target chip's surface area based on the chip dimensions; and determining the ratio of chip power to chip surface area as the target chip's surface power density.

[0057] In one possible implementation of this disclosure, when the target chip's heat dissipation type is water-cooled, the volumetric power density of the target chip can be calculated. Assuming the target chip's power is P, and its dimensions (chip length, chip width, and chip height) are x, y, and z, for a water-cooled target chip, since the chip's heat dissipation capacity is related to its volume, the volumetric power density of each target chip is calculated as P / xyz, in W / mm³. Accordingly, the implementation steps may include: obtaining the target chip's power and dimensions, including chip length, chip width, and chip height; calculating the target chip's volume based on the chip dimensions; and determining the ratio of chip power to chip volume as the target chip's volumetric power density.

[0058] In specific application scenarios, after calculating the surface power density or volume power density of the target chip, the target mesh encryption level corresponding to the surface power density or volume power density can be determined by executing steps 330 to 350 of the embodiment.

[0059] Step 330: Set the basic grid size and initial grid encryption level n of the target chip, and perform grid encryption processing on the target chip based on the initial grid encryption level n to obtain the first temperature value of the target chip.

[0060] In this embodiment of the present disclosure, since the target chip is relatively thin, the basic mesh size can be set to 2mm, and the initial mesh refinement level can be set to n levels. The mesh size will be divided with reference to the 2mm / 2n size. Further thermal simulation calculations are performed to obtain the chip temperature corresponding to the n-level mesh refinement, i.e., the first temperature value T of the target chip. n .

[0061] Step 340: Keeping the basic grid size unchanged, perform grid encryption processing on the target chip based on the grid encryption level n+1 to obtain the second temperature value of the target chip.

[0062] In this embodiment of the disclosure, the basic dimensions can be kept constant, and the temperature of each chip under n+1 level mesh encryption can be obtained by increasing the mesh encryption level, i.e., the second temperature value T of the target chip. n+1 .

[0063] Step 350: Calculate the first temperature difference between the first temperature value and the second temperature value, and determine the target mesh refinement level that corresponds to the power density and meets the simulation accuracy requirements based on the first temperature difference.

[0064] In this embodiment of the disclosure, when determining the target mesh density level that corresponds to the power density and meets the simulation accuracy requirements based on the first temperature difference value, the temperature difference |T between chips with mesh density levels n and n+1 can be compared. n+1 -T n |, if |T n+1 -T n If |n < the first preset threshold, it means that the n-level mesh refinement level meets the simulation accuracy requirements under the surface / volume power density of the chip. Then, the above mesh division can be further used for thermal simulation, and the results compared with the thermal test results. If |simulated thermal case temperature - tested thermal case temperature| ≤ the second preset threshold, it proves that the thermal simulation accuracy has been verified under this mesh division. The initial mesh refinement level n can be determined as the target mesh refinement level. If |simulated thermal case temperature - tested thermal case temperature| > the second preset threshold, it proves that the thermal simulation accuracy has not been verified. In this case, there are two modification methods: further optimize the mesh division and reduce the basic size; modify the simulation boundary conditions. Conversely, if |T n+1 -T n If the value is greater than or equal to the first preset threshold, it indicates that the n-level mesh refinement level cannot meet the requirements. The initial mesh refinement level needs to be redefined, and the verification of refinement and simulation accuracy needs to be repeated. The first and second preset thresholds can be set numerically according to the actual application scenario; the smaller the value, the higher the required simulation accuracy. For example, the first preset threshold can be set to 1℃, and the second preset threshold can be set to 3℃.

[0065] Accordingly, when determining the target mesh encryption level corresponding to the power density and meeting the simulation accuracy requirements based on the first temperature difference value, the implementation steps may include: determining whether the first temperature difference value is less than a first preset threshold; if the first temperature difference value is less than the first preset threshold, then performing thermal simulation processing on the target chip based on the initial mesh encryption level n, comparing the obtained thermal simulation case temperature with the thermal test case temperature, and if the second temperature difference value between the thermal simulation case temperature and the thermal test case temperature is less than a second preset threshold, then determining the initial mesh encryption level n as the target mesh encryption level; if the first temperature difference value is greater than or equal to the first preset threshold, then updating the initial mesh encryption level n to mesh encryption level n+1, and recalculating the first temperature difference value based on the updated initial mesh encryption level n and the corresponding updated mesh encryption level n+1.

[0066] For example, if the base mesh size of the target chip is set to 2mm and the initial mesh encryption level n is 3, and the first temperature difference value |T4-T3| between the n-level and n+1-level chips is less than a first preset threshold and the second temperature difference value is less than a second preset threshold when the initial mesh encryption level n is 3, then the target mesh encryption level corresponding to the target chip can be determined to be 3. If the first temperature difference value is greater than or equal to the first preset threshold when the initial mesh encryption level n is 3, then the initial mesh encryption level n can be updated to 4, and the corresponding updated mesh encryption level n+1 is 5. Further, based on the updated initial mesh encryption level n and the corresponding updated mesh encryption level n+1, the first temperature difference value |T5-T4| is recalculated, and the above simulation accuracy is verified based on the recalculated first temperature difference value. When the verification is passed, the target mesh encryption level corresponding to the target chip is determined to be 4. Conversely, if the first temperature difference value is greater than or equal to the first preset threshold when the initial mesh density level n is 4, the initial mesh density level n and the corresponding mesh density level n+1 can be updated, and the above simulation accuracy can be verified based on the updated initial mesh density level n and mesh density level n+1... until it is determined that the simulation accuracy verification requirements are met, and the final updated initial mesh density level n is determined as the target mesh density level.

[0067] Correspondingly, if the second temperature difference between the thermal simulation case temperature and the thermal test case temperature is greater than or equal to the second preset threshold, the implementation steps may further include: updating the grid base size of the target chip, and recalculating the first temperature difference value based on the updated grid base size and the initial grid refinement level n; or, modifying the simulation boundary conditions corresponding to the thermal simulation processing.

[0068] As a preferred approach, after determining the target mesh encryption level corresponding to the power density, the implementation steps may further include: rounding down the power density to obtain the target power density of the target chip; and outputting the target mesh encryption level as the mesh encryption level under the target power density.

[0069] For example, for a target chip with natural heat dissipation, an example of a mesh generation method is given. Figure 4 As shown, the surface power density of the target chip can be rounded down. The target grid density level is determined by comparing the temperature difference between the initial grid density level n and the corresponding grid density level n+1 with a preset threshold. For example... Figure 5 As shown, the grid division level (i.e., the target grid refinement level) corresponding to the power density of each surface after rounding down can be obtained.

[0070] Step 360: Perform mesh division processing on the target chip based on the target mesh encryption level.

[0071] For the specific implementation process of the embodiments disclosed herein, please refer to the relevant description in step 240 of the embodiment, which will not be repeated here.

[0072] For ease of understanding, this is combined with Figure 6 The technical solution in this disclosure is described in full as follows: After determining the target chip to be meshed, the chip heat dissipation type of the target chip can be determined first. When the chip heat dissipation type of the target chip is determined to be natural heat dissipation or air cooling, the surface power density of the target chip can be calculated; when the chip heat dissipation type of the target chip is determined to be water cooling, the volumetric power density of the target chip can be calculated. After calculating the surface power density or volumetric power density of the target chip, the basic mesh size and initial mesh refinement level n of the target chip can be set. Based on the initial mesh refinement level n, the mesh of the target chip is refined to obtain the first temperature value T of the target chip. n Keeping the basic dimensions unchanged, by increasing the mesh encryption level, the temperature of each chip under n+1 level mesh encryption is obtained, which is the second temperature value T of the target chip. n+1 Compare the temperature difference |T between chips with mesh encryption levels n and n+1. n+1 -T n |, if |T n+1 -T n If |<1℃, it indicates that the n-level mesh refinement level meets the simulation accuracy requirements at the surface / volume power density of the chip. Further thermal simulation can be performed using the above mesh division, and the results compared with thermal test results. If |simulated thermal case temperature - tested thermal case temperature| ≤ 3℃, it proves that the thermal simulation accuracy has been verified under this mesh division. The initial mesh refinement level n can be determined as the target mesh refinement level. If |simulated thermal case temperature - tested thermal case temperature| > 3℃, it proves that the thermal simulation accuracy has not been verified. In this case, there are two modification methods: further optimize the mesh division and reduce the basic size; modify the simulation boundary conditions. Conversely, if |T n+1 -Tn If the temperature is ≥1℃, it indicates that the n-level mesh encryption level cannot meet the requirements. The initial mesh encryption level needs to be redefined, and the encryption and simulation accuracy verification needs to be repeated.

[0073] In summary, the technical solution in this application first determines the heat dissipation type of the target chip, then calculates the power density of the target chip based on the heat dissipation type, and determines the target mesh refinement level corresponding to the power density; finally, it performs meshing processing on the target chip based on the target mesh refinement level. The technical solution in this disclosure can perform differentiated chip meshing according to different surface power densities or volumetric power densities of the target chip. During the chip meshing process, simulation accuracy and computation time can be balanced to ensure the effectiveness of the chip meshing.

[0074] Based on the above Figure 2 , Figure 3 A detailed description of the provided chip meshing method, such as Figure 7 As shown, Figure 7 This is a block diagram illustrating a chip grid partitioning device according to an exemplary embodiment. Figure 7 As shown, the device includes:

[0075] The first determining module 41 can be used to determine the heat dissipation type of the target chip, which includes any one of natural heat dissipation, air cooling, and water cooling.

[0076] The calculation module 42 can be used to calculate the power density of the target chip based on the chip heat dissipation type, wherein the power density includes the surface power density corresponding to the natural heat dissipation type and the air cooling type, and the volumetric power density corresponding to the water cooling type.

[0077] The second determining module 43 can be used to determine the target grid densification level corresponding to the power density;

[0078] The processing module 44 can be used to perform mesh division processing on the target chip based on the target mesh encryption level.

[0079] In some embodiments of this application, when the heat dissipation type of the target chip is natural heat dissipation or air cooling, the calculation module 42 can be used to obtain the chip power and chip size of the target chip, the chip size including chip length, chip width and chip height; calculate the chip surface area of ​​the target chip based on the chip size; and determine the ratio of chip power to chip surface area as the surface power density of the target chip.

[0080] In some embodiments of this application, when the heat dissipation type of the target chip is water cooling, the calculation module 42 can be used to obtain the chip power and chip size of the target chip, the chip size including chip length, chip width and chip height; calculate the chip volume of the target chip based on the chip size; and determine the ratio of chip power to chip volume as the volumetric power density of the target chip.

[0081] In some embodiments of this application, the second determining module 43 can be used to set the basic grid size and initial grid encryption level n of the target chip; perform grid encryption processing on the target chip based on the initial grid encryption level n to obtain a first temperature value of the target chip; keep the basic grid size unchanged, perform grid encryption processing on the target chip based on grid encryption level n+1 to obtain a second temperature value of the target chip; calculate a first temperature difference between the first temperature value and the second temperature value, and determine the target grid encryption level corresponding to the power density and meeting the simulation accuracy requirements based on the first temperature difference.

[0082] In some embodiments of this application, the second determining module 43 can be used to determine whether the first temperature difference value is less than the first preset threshold. If the first temperature difference value is less than the first preset threshold, the target chip is subjected to thermal simulation processing based on the initial grid encryption level n, and the obtained thermal simulation shell temperature is compared with the thermal test shell temperature. If the second temperature difference value between the thermal simulation shell temperature and the thermal test shell temperature is less than the second preset threshold, the initial grid encryption level n is determined as the target grid encryption level. If the first temperature difference value is greater than or equal to the first preset threshold, the initial grid encryption level n is updated to the grid encryption level n+1, and the first temperature difference value is recalculated based on the updated initial grid encryption level n and the corresponding updated grid encryption level n+1.

[0083] In some embodiments of this application, such as Figure 8 As shown, the device also includes: an update module 45 and a modification module 46; if the second temperature difference between the thermal simulation shell temperature and the thermal test shell temperature is greater than or equal to the second preset threshold, the update module 45 can be used to update the grid base size of the target chip, and recalculate the first temperature difference value based on the updated grid base size and the initial grid refinement level n; or, the modification module 46 can be used to modify the simulation boundary conditions corresponding to the thermal simulation processing.

[0084] In some embodiments of this application, such as Figure 8 As shown, the device also includes: an output module 47;

[0085] The output module 47 can be used to round down the power density to obtain the target power density of the target chip; and output the target mesh encryption level as the mesh encryption level under the target power density.

[0086] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0087] In the embodiments of this application, the heat dissipation type of the target chip is first determined, then the power density of the target chip is calculated based on the heat dissipation type, and the target mesh density level corresponding to the power density is determined; finally, the target chip is meshed based on the target mesh density level. The technical solution in this disclosure can perform differentiated chip meshing according to different surface power densities or volumetric power densities of the target chip. During the chip meshing process, simulation accuracy and computation time can be balanced to ensure the effectiveness of the chip meshing.

[0088] The chip grid partitioning apparatus of this invention has been described above from the perspective of functional modules in conjunction with the accompanying drawings. It should be understood that this functional module can be implemented in hardware, in software instructions, or in a combination of hardware and software modules. Specifically, each step of the chip grid partitioning method embodiment of this invention can be completed by integrated logic circuits in the processor's hardware and / or by software instructions. The steps of the chip grid partitioning method claimed in this invention can be directly manifested as execution by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. Optionally, the software module can be located in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the chip grid partitioning method embodiment described above.

[0089] Figure 9 This is a schematic block diagram of an electronic device 700 according to an embodiment of the present invention.

[0090] like Figure 9 As shown, the electronic device 700 may include:

[0091] The system includes a memory 710 and a processor 720. The memory 710 stores computer programs and transfers the program code to the processor 720. In other words, the processor 720 can retrieve and run the computer program from the memory 710 to implement the methods described in the embodiments of the present invention.

[0092] For example, the processor 720 can be used to execute the above-described method embodiments according to instructions in the computer program.

[0093] In some embodiments of the present invention, the processor 720 may include, but is not limited to:

[0094] General-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0095] In some embodiments of the present invention, the memory 710 includes, but is not limited to:

[0096] Volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0097] In some embodiments of the present invention, the computer program may be divided into one or more modules, which are stored in the memory 710 and executed by the processor 720 to perform the method provided by the present invention. The one or more modules may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the controller.

[0098] like Figure 9 As shown, the electronic device 700 may further include:

[0099] Transceiver 730, which can be connected to processor 720 or memory 710.

[0100] The processor 720 can control the transceiver 730 to communicate with other devices; specifically, it can send data to or receive data sent by other devices. The transceiver 730 may include a transmitter and a receiver. The transceiver 730 may further include antennas, and the number of antennas may be one or more.

[0101] It should be understood that the various components in the electronic device are connected through a bus system, which includes a data bus, a power bus, a control bus, and a status signal bus.

[0102] The present invention also provides a computer storage medium having a computer program stored thereon, which, when executed by a computer, enables the computer to perform the methods of the above-described method embodiments. Alternatively, one embodiment of the present invention also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the methods of the above-described method embodiments.

[0103] When implemented using software, it can be implemented entirely or partially as a computer program product. This computer program product includes one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., Digital Video Disc (DVD)), or a semiconductor medium (e.g., Solid State Disk (SSD)).

[0104] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments claimed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0105] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0106] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. For example, the functional modules in the various embodiments of this application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0107] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip mesh generation method, characterized in that, include: Determine the heat dissipation type of the target chip, which includes any one of natural heat dissipation, air cooling, and water cooling. The power density of the target chip is calculated based on the chip heat dissipation type, wherein the power density includes the surface power density corresponding to the natural heat dissipation type and the air cooling type, and the volumetric power density corresponding to the water cooling type. Determine the target grid encryption level corresponding to the power density; The target chip is divided into grids based on the target grid encryption level. The step of determining the target grid encryption level corresponding to the power density includes: Set the base grid size and initial grid encryption level n of the target chip; Based on the initial grid encryption level n, the target chip is subjected to grid encryption processing to obtain the first temperature value of the target chip; Keeping the basic size of the grid unchanged, the target chip is subjected to grid encryption processing based on the grid encryption level n+1 to obtain the second temperature value of the target chip; Calculate the first temperature difference between the first temperature value and the second temperature value, and determine the target mesh refinement level that corresponds to the power density and meets the simulation accuracy requirements based on the first temperature difference.

2. The method according to claim 1, characterized in that, When the heat dissipation type of the target chip is the natural heat dissipation type or the air cooling type, the calculation of the power density of the target chip based on the heat dissipation type includes: Obtain the chip power and chip size of the target chip, wherein the chip size includes chip length, chip width and chip height; Calculate the surface area of ​​the target chip based on the chip size; The ratio of the chip power to the chip surface area is determined as the surface power density of the target chip.

3. The method according to claim 1, characterized in that, When the heat dissipation type of the target chip is the water cooling type, the calculation of the power density of the target chip based on the heat dissipation type includes: Obtain the chip power and chip size of the target chip, wherein the chip size includes chip length, chip width and chip height; Calculate the chip volume of the target chip based on the chip dimensions; The ratio of the chip power to the chip volume is determined as the volumetric power density of the target chip.

4. The method according to claim 1, characterized in that, determining the target mesh refinement level corresponding to the power density and meeting the simulation accuracy requirements based on the first temperature difference value includes: Determine whether the first temperature difference value is less than the first preset threshold; If the first temperature difference is less than the first preset threshold, then the target chip is subjected to thermal simulation based on the initial grid encryption level n, and the obtained thermal simulation case temperature is compared with the thermal test case temperature. If the second temperature difference between the thermal simulation case temperature and the thermal test case temperature is less than the second preset threshold, then the initial grid encryption level n is determined as the target grid encryption level. If the first temperature difference value is greater than or equal to the first preset threshold, the initial grid encryption level n is updated to the grid encryption level n+1, and the first temperature difference value is recalculated based on the updated initial grid encryption level n and the corresponding updated grid encryption level n+1.

5. The method according to claim 4, characterized in that, If the second temperature difference between the thermal simulation shell temperature and the thermal test shell temperature is greater than or equal to a second preset threshold, the method further includes: Update the grid base size of the target chip, and recalculate the first temperature difference value based on the updated grid base size and the initial grid refinement level n; or, Modify the simulation boundary conditions corresponding to the thermal simulation process.

6. The method according to any one of claims 1 to 5, characterized in that, After determining the target grid encryption level corresponding to the power density, the method further includes: The power density is rounded down to obtain the target power density of the target chip. The target mesh encryption level is output as the mesh encryption level under the target power density.

7. A chip grid division device, characterized in that, include: The first determining module is used to determine the heat dissipation type of the target chip, wherein the heat dissipation type includes any one of natural heat dissipation, air cooling, and water cooling. A calculation module is used to calculate the power density of the target chip based on the chip heat dissipation type, wherein the power density includes the surface power density corresponding to the natural heat dissipation type and the air cooling type, and the volumetric power density corresponding to the water cooling type. The second determining module is used to determine the target grid encryption level corresponding to the power density; The processing module is used to perform grid division processing on the target chip based on the target grid encryption level; The second determining module is used to set the basic grid size and initial grid encryption level n of the target chip; perform grid encryption processing on the target chip based on the initial grid encryption level n to obtain a first temperature value of the target chip; keep the basic grid size unchanged, perform grid encryption processing on the target chip based on grid encryption level n+1 to obtain a second temperature value of the target chip; calculate a first temperature difference between the first temperature value and the second temperature value, and determine a target grid encryption level that corresponds to the power density and meets the simulation accuracy requirements based on the first temperature difference.

8. An electronic device, characterized in that, include: A processor and a memory, the memory being used to store a computer program, the processor being used to invoke and run the computer program stored in the memory to perform the method of any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, Used to store a computer program that causes a computer to perform the method as described in any one of claims 1-6.

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