Methods, systems, equipment, and media for TSV array circuit model and parameter sensitivity analysis.

Abstract

This invention provides a method, system, device, and medium for TSV array circuit modeling and parameter sensitivity analysis, including the following steps: obtaining a physical model and process parameters containing signal TSVs and ground TSVs, and constructing an array model; based on the array model, process parameters, and parallel double-circular rod coupling model under high-frequency transmission conditions, constructing an RLGC model corresponding to the physical model, and calculating the calculation formulas for circuit parameters in the RLGC model; evaluating the accuracy of the constructed equivalent RLGC circuit model from the perspective of S-parameters for different size cases, and correcting the calculation formulas for circuit parameters in the constructed equivalent RLGC model if inaccurate, until an accurate equivalent RLGC circuit model is obtained; analyzing the influence of different physical parameters on transmission characteristics, and comparing the sensitivity of different physical parameters through S-parameters; the construction of the RLGC circuit in this application can effectively solve the problem of low efficiency of electromagnetic simulation software, and can quickly model while ensuring accuracy.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to methods, systems, equipment, and media for TSV array circuit model and parameter sensitivity analysis. Background Technology

[0002] As signal transmission rates continue to increase, packaging structures are increasingly moving towards miniaturization and low noise. However, as these structures approach their physical limits, they face more and more challenges, such as noise, power consumption, and cost. The emergence of 3D integration technology provides a new way to solve these problems. Essentially, it interconnects multiple layers of chips in the vertical direction, resulting in smaller chip areas, shorter interconnects, higher transmission bandwidth, and cost savings. Through Silicon Vias (TSVs), as a key component in 3D integrated interconnect structures, play a crucial role in signal transmission between chips. Therefore, analyzing the transmission characteristics of TSVs is essential.

[0003] When studying the electrical characteristics of TSV-based 3D integrated circuits, such as TSV transmission characteristics and noise crosstalk, electromagnetic simulation software is mostly used. However, when the TSV structure is complex, the simulation efficiency is low. While existing analysis methods based on RLGC equivalent circuits have solved the problem of low efficiency of electromagnetic simulation software, the analysis process is complex. At the same time, during the modeling process, different parameters have different effects on transmission characteristics and crosstalk. Therefore, it is necessary to analyze the sensitivity of different TSV parameters. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a method, system, equipment, and medium for TSV array circuit model and parameter sensitivity analysis, which simplifies the analysis process and improves simulation efficiency while ensuring accuracy.

[0005] This invention is achieved through the following technical solution:

[0006] The method for TSV array circuit model and parameter sensitivity analysis includes the following steps:

[0007] Obtain the physical model and process parameters including signal TSV and ground TSV, and build the array model;

[0008] Based on the array model, process parameters, and parallel double-circular rod coupling model under high-frequency transmission conditions, the RLGC model corresponding to the physical model is constructed, and the calculation formulas for the circuit parameters in the RLGC model are calculated.

[0009] For different size cases, the accuracy of the constructed equivalent RLGC circuit model is evaluated from the perspective of S-parameters. If it is inaccurate, the calculation formula of the circuit parameters in the constructed equivalent RLGC model is corrected until an accurate equivalent RLGC circuit model is obtained.

[0010] The effects of different physical parameters on transmission characteristics are analyzed, and the sensitivity of different physical parameters is compared using S-parameters.

[0011] Furthermore, the array model is a 3×3 array model.

[0012] Furthermore, the process parameters of the physical model include the height, diameter, spacing, and oxide layer thickness of the signal TSV and ground TSV.

[0013] Furthermore, a coupling capacitor array arrangement model and array coupling circuit units are constructed, and an equivalent RLGC circuit model is constructed. The circuit parameters of each part of the equivalent RLGC circuit model include the self-impedance and inductance values ​​of the signal TSV and ground TSV, the impedance and conductance formed by the coupling between the signal TSV and ground TSV and the silicon substrate, and the impedance and capacitance of the oxide layer.

[0014] The resistance of TSV is:

[0015]

[0016] Among them, R tSV R is the resistance of TSV. TSV,dc R is the DC resistance of TSV. TSV,ac The AC resistance of TSV;

[0017]

[0018]

[0019] Among them, h TSV For the TSV height, d TSV For the diameter of the TSV, ρ TSV Let σ be the resistivity of the TSV, δ be the skin depth of the TSV at high frequencies, and σ be the resistivity of the TSV. TSV f is the TSV conductivity, and f is the TSV operating frequency;

[0020] The inductance of TSV is:

[0021] The oxide layer capacitance is:

[0022] Where μ0 is the free permeability, μ r p is the relative permeability of TSV. TSVLet ε0 be the spacing between TSVs, ε0 be the vacuum permittivity, and ε0 be the free space permittivity. ox Let t be the dielectric constant of the oxide layer. ox The oxide layer thickness is 1 μm.

[0023] Furthermore, the accuracy of the equivalent RLGC circuit model is evaluated using the insertion loss S obtained from electromagnetic field simulation of the three-dimensional structure of the TSV array. 21 and remote crosstalk S 41 As a standard, the insertion loss S obtained from the simulation of the equivalent circuit model is... 21 and remote crosstalk S 41 The parameters are compared to evaluate the accuracy of the circuit model, and the silicon substrate capacitance is parametrically fitted.

[0024] Furthermore, the silicon substrate capacitance between the intermediate TSV and the edge TSV is denoted as C. Si1 The silicon substrate capacitance between the edge TSVs is denoted as C. Si2 The silicon substrate capacitance between indirectly adjacent TSVs is denoted as C. Si3 The calculation process is as follows:

[0025]

[0026] Among them, C Si For silicon substrate capacitors, ε Si α is the relative permittivity of silicon, and α is a coefficient related to the TSV spacing.

[0027] Furthermore, the fitting process is as follows:

[0028] d TSV =10um,h TSV =100um:α=2.5×10 3 ×p TSV +0.55;

[0029] d TSV =20um,h TSV =150um:α=2.5×10 3 ×p TSV +0.4;

[0030]

[0031] d TSV =20um,h TSV =200um:α=0.5;

[0032] The conductivity of the silicon substrate is:

[0033] Among them, G Si For the conductivity of the silicon substrate, σ Sih represents the conductivity of the silicon substrate. TSV For the TSV height, d TSV For the diameter of the TSV, ρ TSV Let δ be the resistivity of TSV, and δ be the skin depth of TSV at high frequency.

[0034] TSV array circuit model and parameter sensitivity analysis system, including:

[0035] The module is used to obtain the physical model and process parameters, including the signal TSV and ground TSV, and to build the array model.

[0036] The calculation module is used to build the RLGC model corresponding to the physical model based on the array model, process parameters and parallel double circular rod coupling model under high frequency transmission conditions, and to calculate the calculation formula of the circuit parameters in the RLGC model.

[0037] The correction module is used to evaluate the accuracy of the constructed equivalent RLGC circuit model from the perspective of S-parameters for different size conditions. If it is inaccurate, it corrects the calculation formula of the circuit parameters in the constructed equivalent RLGC model until an accurate equivalent RLGC circuit model is obtained.

[0038] The output module is used to analyze the impact of different physical parameters on transmission characteristics and compare the sensitivity of different physical parameters through S-parameters.

[0039] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a method for analyzing the sensitivity of a TSV array circuit model and its parameters.

[0040] A computer-readable storage medium storing a computer program, wherein when executed by a processor, the computer program implements the steps of a method for analyzing the sensitivity of parameters of a TSV array circuit model.

[0041] Compared with the prior art, the present invention has the following beneficial technical effects:

[0042] This invention provides a method, system, device, and medium for TSV array circuit model and parameter sensitivity analysis, including the following steps: obtaining a physical model and process parameters containing signal TSVs and ground TSVs, and constructing an array model; based on the array model, process parameters, and parallel double-circular rod coupling model under high-frequency transmission conditions, constructing an RLGC model corresponding to the physical model, and calculating the calculation formulas for circuit parameters in the RLGC model; evaluating the accuracy of the constructed equivalent RLGC circuit model from the perspective of S-parameters for different size cases, and correcting the calculation formulas for circuit parameters in the constructed equivalent RLGC model if inaccurate, until an accurate result is obtained. The present application provides an accurate equivalent RLGC circuit model; analyzes the impact of different physical parameters on transmission characteristics, and compares the sensitivity of different physical parameters through S-parameters; the RLGC circuit model constructed in this application can effectively solve the problem of low efficiency of electromagnetic simulation software. Compared with the prior art, the RLGC circuit model obtained in this application has the advantages of being fast, convenient, and accurate, which can help designers quickly build models while ensuring accuracy, and easily understand the transmission characteristics of TSV arrays and crosstalk between TSVs in the model; at the same time, designers can also design TSV arrays by combining the sensitivity relationship of TSV diameter, height, and spacing with actual needs. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the array model of the present invention;

[0044] Figure 2 This is a schematic diagram of the coupling capacitor array arrangement of the present invention;

[0045] Figure 3 This is a structural diagram of the coupling circuit unit between TSVs;

[0046] Figure 4(a) is the top-level diagram of the array equivalent RLGC circuit, (b) is the circuit diagram of the sub-circuit TSV1comp, (c) is the circuit diagram of the sub-circuit TSV2comp, and (d) is the circuit diagram of the sub-circuit TSV3comp.

[0047] Figure 5 This is a comparison chart of insertion loss fitting results for a 10µm diameter and 100µm height example.

[0048] Figure 6 This is a comparison chart of the crosstalk fitting results for a far end with a diameter of 10µm and a height of 100µm in the example.

[0049] Figure 7 This is a comparison chart of insertion loss fitting results for a diameter of 30µm and a height of 200µm in the example.

[0050] Figure 8This is a comparison chart of the crosstalk fitting results for a 30µm diameter and 200µm height in the example.

[0051] Figure 9 The simulation comparison graphs show the insertion loss at different spacings in the embodiments.

[0052] Figure 10 The simulation comparison graphs show the insertion loss at different heights in the embodiments.

[0053] Figure 11 The following is a simulation comparison of insertion loss for different diameters in the embodiments. Detailed Implementation

[0054] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0055] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0057] This invention provides a TSV array circuit model and a method for parameter sensitivity analysis, comprising the following steps:

[0058] Obtain the physical model and process parameters including signal TSV and ground TSV, and build the array model;

[0059] Based on the array model, process parameters, and parallel double-circular rod coupling model under high-frequency transmission conditions, the RLGC model corresponding to the physical model is constructed, and the calculation formulas for the circuit parameters in the RLGC model are calculated.

[0060] For different size cases, the accuracy of the constructed equivalent RLGC circuit model is evaluated from the perspective of S-parameters. If it is inaccurate, the calculation formula of the circuit parameters in the constructed equivalent RLGC model is corrected until an accurate equivalent RLGC circuit model is obtained.

[0061] The effects of different physical parameters on transmission characteristics are analyzed, and the sensitivity of different physical parameters is compared using S-parameters.

[0062] Preferably, the array model is a 3×3 array model, because in a TSV array, a TSV will be affected by crosstalk from the surrounding TSVs.

[0063] Preferably, the process parameters of the physical model include the height, diameter, spacing, and oxide layer thickness of the signal TSV and ground TSV.

[0064] Preferably, a coupling capacitor array arrangement model and array coupling circuit units are constructed to build an equivalent RLGC circuit model. The circuit parameters of each part of the equivalent RLGC circuit model include the self-impedance and inductance values ​​of the signal TSV and ground TSV, the impedance and conductance formed by the coupling between the signal TSV and ground TSV and the silicon substrate, and the impedance and capacitance of the oxide layer.

[0065] The resistance of TSV is:

[0066]

[0067] Among them, R TSV R is the resistance of TSV. TSV,dc R is the DC resistance of TSV. TSV,ac The AC resistance of TSV;

[0068]

[0069]

[0070] Among them, h TSV For the TSV height, d TSV For the diameter of the TSV, ρ TSV Let σ be the resistivity of the TSV, δ be the skin depth of the TSV at high frequencies, and σ be the resistivity of the TSV. TSV denoted as TSV conductivity, and f as TSV operating frequency.

[0071] The inductance of TSV is:

[0072] The oxide layer capacitance is:

[0073] Where μ0 is the free permeability, μ rp is the relative permeability of TSV. TSV Let ε0 be the spacing between TSVs, ε0 be the vacuum permittivity, and ε0 be the free space permittivity. ox Let t be the dielectric constant of the oxide layer. ox The oxide layer thickness is 1 μm.

[0074] Preferably, the accuracy of the equivalent RLGC circuit model is evaluated by assessing the insertion loss S. 21 and remote crosstalk S 41 The accuracy of the circuit model is evaluated by comparing parameters, and the silicon substrate capacitance is parametrically fitted; the silicon substrate capacitance between the middle TSV and the edge TSV is denoted as C. Si1 The silicon substrate capacitance between the edge TSVs is denoted as C. Si2 The silicon substrate capacitance between indirectly adjacent TSVs is denoted as C. Si3 The calculation process is as follows:

[0075]

[0076] Among them, C Si For silicon substrate capacitors, ε Si Let be the relative permittivity of silicon, and α be a coefficient related to the TSV spacing; the fitting process is as follows:

[0077] d TSV =10um,h TSV =100um:α=2.5×10 3 ×p TSV +0.55;

[0078] d TSV =20um,h TSV =150um:α=2.5×10 3 ×p TSV +0.4;

[0079]

[0080] d TSV =20um,h TSV =200um:α=0.5;

[0081] The conductivity of the silicon substrate is:

[0082] Among them, G Si For the conductivity of the silicon substrate, σ Si h represents the conductivity of the silicon substrate. TSV For the TSV height, d TSV For the diameter of the TSV, ρ TSV Let δ be the resistivity of TSV, and δ be the skin depth of TSV at high frequency.

[0083] This invention provides a TSV array circuit model and parameter sensitivity analysis system, including:

[0084] The module is used to obtain the physical model and process parameters, including the signal TSV and ground TSV, and to build the array model.

[0085] The calculation module is used to build the RLGC model corresponding to the physical model based on the array model, process parameters and parallel double circular rod coupling model under high frequency transmission conditions, and to calculate the calculation formula of the circuit parameters in the RLGC model.

[0086] The correction module is used to evaluate the accuracy of the constructed equivalent RLGC circuit model from the perspective of S-parameters for different size conditions. If it is inaccurate, it corrects the calculation formula of the circuit parameters in the constructed equivalent RLGC model until an accurate equivalent RLGC circuit model is obtained.

[0087] The output module is used to analyze the impact of different physical parameters on transmission characteristics and compare the sensitivity of different physical parameters through S-parameters.

[0088] The present invention provides an embodiment as follows:

[0089] A 3×3 array model was selected for study, and a system was built as follows: Figure 1 The model diagram shown.

[0090] according to Figure 1 The TSV model was built as follows Figure 2 The diagram shows the arrangement of the coupling capacitor array, where P is the power supply TSV, G is the ground TSV, C1 is the coupling capacitor between the middle TSV and the edge TSV, C2 is the coupling capacitor between the edge TSVs, and C3 is the coupling capacitor between indirectly adjacent TSVs.

[0091] Based on the skin effect in high-frequency signal transmission, the impedance calculation formula for TSV can be obtained as follows:

[0092] in,

[0093] R TSV R is the resistance of TSV. TSV,dc R is the DC resistance of TSV. TSV,ac The AC resistance of TSV.

[0094]

[0095]

[0096] Among them, h TSV For the TSV height, d TSV For the diameter of the TSV, ρTSV Let σ be the resistivity of the TSV, δ be the skin depth of the TSV at high frequencies, and σ be the resistivity of the TSV. TSV f is the TSV conductivity, and f is the TSV operating frequency;

[0097] Based on the coupling relationship of the parallel double circular rods, the coupling circuit unit between TSVs is obtained as follows: Figure 3 As shown, where:

[0098] The formula for calculating TSV inductance is:

[0099] The formula for calculating oxide layer capacitance is:

[0100] The formula for calculating the capacitance of a silicon substrate is:

[0101] The formula for calculating the conductivity of a silicon substrate is:

[0102] Where μ0 is the free permeability, μ r p is the relative permeability of TSV. TSV Let ε0 be the spacing between TSVs, ε0 be the vacuum permittivity, and ε0 be the free space permittivity. ox Let t be the dielectric constant of the oxide layer. ox The oxide layer thickness is 1 μm, α is a coefficient related to the TSV spacing, and ε Si Let σ be the relative permittivity of silicon. Si The conductivity of the silicon substrate.

[0103] Combination Figure 2 and Figure 3 Based on the above circuit parameter calculation formulas, the RLGC circuit diagram shown in Figure 4 is constructed. Due to the complexity of the equivalent circuit diagram, this application divides Figure 4 into a top-level diagram (Figure 4(a)) and circuit diagrams of sub-circuits TSV1comp (Figure 4(b), TSV2comp (Figure 4(c), and TSV3comp (Figure 4(d)).

[0104] The accuracy of the constructed equivalent RLGC circuit model is evaluated, and if inaccurate, the RLGC circuit model is corrected until an accurate equivalent RLGC model is obtained. This is mainly accomplished by modifying the calculation formula for the silicon substrate, where the silicon substrate capacitance between the middle TSV and the edge TSV is denoted as C. Si1 The silicon substrate capacitance between the edge TSVs is denoted as C. Si2 The silicon substrate capacitance between indirectly adjacent TSVs is denoted as C. Si3 ,

[0105] The calculation formulas are as follows:

[0106] Where α is a coefficient related to the TSV spacing, and its fitting formula is as follows:

[0107] d TSV =10um,h TSV =100um:α=2.5×10 3 ×p TSV +0.55;

[0108] d TSV =20um,h TSV =150um:α=2.5×10 3 ×p TSV +0.4;

[0109]

[0110] d TSV =20um,h TSV =200um:α=0.5;

[0111] Furthermore, in the above method, in the step of evaluating the accuracy of the equivalent RLGC model, the insertion loss S is used. 21 and remote crosstalk S 41 The accuracy of the constructed equivalent RLGC circuit model is evaluated, and the comparison results are as follows: Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown.

[0112] When the TSV array structure is complex, the electromagnetic simulation software has a low speed. Building an RLGC circuit can effectively solve the problem of low simulation efficiency of electromagnetic simulation software.

[0113] Increasing the spacing between TSVs reduces crosstalk between them, leading to more signal transmitted to the end of the TSV, thus increasing insertion loss S. 21 The insertion loss S increases. However, as the TSV spacing increases, the insertion loss S cannot be increased indefinitely. 21 The insertion loss S is increased by increasing the TSV spacing. 21 The effect is no longer obvious, as shown in the comparison results. Figure 9 As shown.

[0114] As the height of the TSV increases, the coupling length between TSVs also increases, leading to an increase in parasitic resistance. This results in a reduction in the signal reaching the TSV ends, increasing the insertion loss S. 21 Decrease, comparison results are as follows Figure 10 As shown.

[0115] As the diameter of the TSV increases, the distance between the power supply TSV (P) and the ground TSV (G) decreases, thereby increasing the insertion loss S. 21 However, in a 3×3 array, as the spacing between the power supply TSV(P) and the ground TSV(G) decreases, the spacing between the power supply TSV(P) and the power supply TSV(G) also decreases, leading to increased silicon substrate loss and decreased insertion loss. Since the increased loss between P and P has a greater impact on transmission performance than the decreased loss between P and P, the insertion loss S decreases as the TSV diameter increases. 21 The results of the reduction are compared as follows: Figure 11 As shown.

[0116] Compare Figure 9 , Figure 10 and Figure 11 The results show that the change in diameter has the greatest impact on transmission performance, while increasing the height of the TSV will increase the insertion loss S. 21 The insertion loss S is reduced, but the impact is less than that of the diameter. Increasing the spacing will increase the insertion loss S within a certain range. 21 However, the insertion loss S cannot be increased by increasing the spacing indefinitely. 21 Based on the degree of influence of TSV diameter, height, and spacing on transmission performance, the sensitivity can be ranked from highest to lowest as follows: diameter, height, spacing.

[0117] In summary, the TSV array circuit model and parameter sensitivity analysis method proposed in this invention simplifies the analysis process and improves simulation efficiency while ensuring accuracy. It also analyzes and compares the sensitivity of different design parameters, providing a reference for practical design.

[0118] In another embodiment of the present invention, a computer device is provided, comprising a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions from the computer storage medium to achieve a corresponding method flow or corresponding function. The processor described in this embodiment of the present invention can be used for the operation of methods for TSV array circuit model and parameter sensitivity analysis.

[0119] In another embodiment of the present invention, a storage medium is provided, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and extended storage media supported by the computer device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by a processor. These instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be high-speed RAM or non-volatile memory, such as at least one disk storage device. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the methods for TSV array circuit model and parameter sensitivity analysis in the above embodiments.

[0120] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0121] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0122] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0123] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for TSV array circuit modeling and parameter sensitivity analysis, characterized in that, Includes the following steps: Obtain the physical model and process parameters including the signal TSV and the ground TSV, and build the array model; the array model is a 3×3 array model; Based on the array model, process parameters, and parallel double-circular rod coupling model under high-frequency transmission conditions, the RLGC model corresponding to the physical model is constructed, and the calculation formulas for the circuit parameters in the RLGC model are calculated. Among them, the coupling capacitor array arrangement model and array coupling circuit unit are constructed, and the equivalent RLGC circuit model is constructed. The circuit parameters of each part of the equivalent RLGC circuit model include the self-impedance and inductance values ​​of the signal TSV and ground TSV, the impedance and conductance formed by the coupling between the signal TSV and ground TSV and the silicon substrate, and the impedance and capacitance of the oxide layer. For different size cases, the accuracy of the constructed equivalent RLGC circuit model is evaluated from the perspective of S-parameters. If inaccurate, the calculation formulas for the circuit parameters in the constructed equivalent RLGC model are corrected until an accurate equivalent RLGC circuit model is obtained. The accuracy of the equivalent RLGC circuit model is evaluated using the insertion loss obtained from electromagnetic field simulation of a three-dimensional TSV array structure. and remote crosstalk As a standard, the insertion loss obtained from the simulation of the equivalent circuit model is used. and remote crosstalk The parameters are compared to evaluate the accuracy of the circuit model, and the silicon substrate capacitance is parametrically fitted. The silicon substrate capacitance between the middle TSV and the edge TSV is denoted as . The silicon substrate capacitance between edge TSVs is denoted as The silicon substrate capacitance between indirectly adjacent TSVs is denoted as The calculation process is as follows: in, Silicon substrate capacitor, Here is the relative permittivity of silicon. A coefficient related to the TSV spacing; The fitting process is as follows: : ； : ； ； : ； The conductivity of the silicon substrate is: in, For the conductivity of silicon substrate, For the conductivity of silicon substrate, Skin depth under TSV high-frequency signals; The effects of different physical parameters on transmission characteristics are analyzed, and the sensitivity of different physical parameters is compared using S-parameters.

2. The TSV array circuit model and parameter sensitivity analysis method according to claim 1, characterized in that, The process parameters of the physical model include the height, diameter, spacing, and oxide layer thickness of the signal TSV and ground TSV.

3. The TSV array circuit model and parameter sensitivity analysis method according to claim 1, characterized in that, The resistance of TSV is: ； in, The resistor is for TSV. The DC resistance of the TSV is [value missing]. The AC resistance of TSV; ； ； in, Skin depth under TSV high-frequency signals, f is the TSV conductivity, and f is the TSV operating frequency; The inductance of TSV is: ; The oxide layer capacitance is: ; in, The permeability of free space, Let TSV be the relative permeability. The spacing of TSVs The vacuum permittivity, The dielectric constant of the oxide layer is... The oxide layer thickness is 1 μm.

4. A TSV array circuit model and parameter sensitivity analysis system, characterized in that, The method for sensitivity analysis of the TSV array circuit model and parameters according to any one of claims 1-3 includes: The module is used to obtain the physical model and process parameters, including the signal TSV and ground TSV, and to build the array model. The calculation module is used to build the RLGC model corresponding to the physical model based on the array model, process parameters and parallel double circular rod coupling model under high frequency transmission conditions, and to calculate the calculation formula of the circuit parameters in the RLGC model. The correction module is used to evaluate the accuracy of the constructed equivalent RLGC circuit model from the perspective of S-parameters for different size conditions. If it is inaccurate, it corrects the calculation formula of the circuit parameters in the constructed equivalent RLGC model until an accurate equivalent RLGC circuit model is obtained. The output module is used to analyze the impact of different physical parameters on transmission characteristics and compare the sensitivity of different physical parameters through S-parameters.

5. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method for analyzing the TSV array circuit model and parameters as described in any one of claims 1-3.

6. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for analyzing the TSV array circuit model and parameters as described in any one of claims 1-3.

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