Failure chip screening method, device and system, readable storage medium and terminal

Abstract

A kind of failure chip screening method and device and system, readable storage medium, terminal, the method comprises: obtaining one or more register test programs, each register test program contains the running program of at least one functional module of chip to be tested;According to the preset order, each register test program is run, write operation is carried out to the register of corresponding functional module, and the test result after the functional module is run is output;If the test result of any one functional module is inconsistent with the theoretical output data, then determine that the chip is failure chip;Wherein, the functional module includes memory, and the preset theoretical input data and theoretical output data of the memory are respectively preset memory write data and memory read data.The present application can efficiently determine chip failure in a wide range.

Description

Technical Field

[0001] This invention relates to the field of chip testing, and more particularly to a method, apparatus and system for screening failed chips, a readable storage medium, and a terminal. Background Technology

[0002] During the chip manufacturing process, a small number of defective chips may occur due to process or design issues. If these defective chips cannot be effectively screened out and reach the customer, it will increase the difficulty of solving the problem and increase the cost later.

[0003] Existing methods for screening failed chips typically utilize the electrical characteristics of the chip. For example, based on preset electrical parameters, chips with suitable electrical performance are obtained, and failed chips are screened out. However, such screening methods are time-consuming, costly, and have a limited scope of verification.

[0004] There is an urgent need for a method to screen for failed chips that can efficiently determine chip failure status over a wide range. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method, apparatus and system for screening failed chips, a readable storage medium and a terminal, which can improve testing efficiency and thus achieve efficient determination of chip failure status in a wider range.

[0006] To address the aforementioned technical problems, this invention provides a method for screening failed chips, comprising: acquiring one or more register test programs, each register test program containing an execution program for at least one functional module of the chip under test; running each register test program in a preset order, performing write operations to the registers of the corresponding functional module, and outputting the test results after the functional module has run, wherein each functional module has preset theoretical input data and theoretical output data, as well as register write information determined based on the theoretical input data; if the test result of any functional module is inconsistent with the theoretical output data, the chip is determined to be a failed chip; wherein the functional module includes a memory physical interface (PHY), and the preset theoretical input data and theoretical output data of the memory PHY are preset memory write data and memory read data, respectively.

[0007] Optionally, the memory is DDR, the memory PHY is DDR PHY, and the registers of the DDR PHY include registers of the DDR impedance control calibration ZQC controller and DDR data control registers for controlling data storage; the write operation to the registers of the corresponding functional module includes: enabling the registers of the DDR PHY to power on; configuring the CPU voltage register to a preset voltage; configuring the DDR type mode; and writing to the registers of the DDR ZQC controller for resistance calibration based on the register write information of the DDR PHY and the DDR type mode; wherein, if the calibration value obtained after resistance calibration is inconsistent with the preset resistance calibration threshold, the chip is determined to be a failed chip.

[0008] Optionally, the functional module further includes a GPU; the write operation to the register of the corresponding functional module includes: enabling the register of the GPU; writing write information to the register of the GPU and running the GPU, so that the GPU performs GPU computing and drawing based on the write information to the register of the GPU; wherein, the preset theoretical output data of the GPU is the graph data of the preset GPU computing and drawing program, and if the graph data obtained after GPU computing and drawing is inconsistent with the graph data of the preset GPU computing and drawing program, the chip is determined to be a faulty chip.

[0009] Optionally, the functional module further includes a CPU, whose registers include a CPU configuration voltage register, a CPU frequency register, and a CPU data register for data storage. The register write information determined based on the CPU's theoretical input data includes multiple sets of information. The write operation to the registers of the corresponding functional module includes: enabling the CPU's registers; writing the CPU's register write information group by group and running the CPU, satisfying one or more of the following: the configuration voltage of the CPU configuration voltage register running earlier is less than or equal to the configuration voltage of the CPU configuration voltage register running later; the frequency of the CPU frequency register running earlier is less than or equal to the frequency of the CPU frequency register running later; the read / write frequency of the CPU data register running earlier at the same configuration voltage and frequency is less than or equal to the read / write frequency of the CPU data register running later. If the CPU's read data after running is inconsistent with the CPU's theoretical output data, then the chip is determined to be a failed chip.

[0010] Optionally, the number of CPUs is multiple; writing the register write information of the CPUs group by group and running the CPUs further includes: traversing the register write information of each CPU and running each CPU separately to test the registers of each CPU separately; combining the register write information of each CPU and running each CPU simultaneously to test the registers of the combined CPUs.

[0011] Optionally, the functional module further includes HUK; the write operation to the register of the corresponding functional module includes: enabling the HUK register; writing write information to the HUK register and running the HUK, so that the HUK performs encryption processing based on the HUK register write information; wherein, the preset theoretical output data of the HUK is the processed data of the preset HUK encryption processing program, and if the processed data obtained after HUK encryption processing is inconsistent with the processed data of the preset HUK encryption processing program, the chip is determined to be a faulty chip.

[0012] Optionally, the memory, GPU, CPU, and HUK have different register test programs; wherein the test order of each register test program is predetermined, and if the test result of any functional module is inconsistent with the theoretical output data, the subsequent test is stopped.

[0013] Optionally, the failed chip screening method is run on a hardware device without an operating system.

[0014] To address the aforementioned technical problems, this invention provides a failed chip screening device, comprising: a program acquisition module for acquiring one or more register test programs, each register test program containing an execution program for at least one functional module of the chip under test; a register writing module for running each register test program in a preset order, performing write operations to the registers of the corresponding functional modules, and outputting the test results after the functional modules have run, wherein each functional module has preset theoretical input data and theoretical output data, as well as register write information determined based on the theoretical input data; and a judgment module for determining that the chip is a failed chip when the test result of any functional module is inconsistent with the theoretical output data; wherein the functional module includes a memory physical interface (PHY), and the preset theoretical input data and theoretical output data of the memory PHY are preset memory write data and memory read data, respectively.

[0015] To address the aforementioned technical problems, embodiments of the present invention provide a readable storage medium storing a computer program thereon, wherein the computer program, when run by a processor, executes the steps of the aforementioned failed chip screening method.

[0016] To address the aforementioned technical problems, this invention provides a terminal, including a memory and a processor. The memory stores a computer program that can run on the processor, and when the processor runs the computer program, it executes the steps of the aforementioned failed chip screening method.

[0017] To address the aforementioned technical problems, this invention provides a failed chip screening system, comprising: a test board, the test board including the aforementioned terminal and a chip base, the chip base being used to support the chip to be tested; a USB module, used to carry a computer program capable of running on the processor of the terminal, and to download the computer program to the terminal, and to send an enable power-on signal received from a host computer to the terminal, and to send failed chip information output by the terminal to the host computer.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0019] In this embodiment of the invention, each register test program includes an execution program for at least one functional module of the chip under test. Each register test program runs in a preset order, performs write operations to the registers of the corresponding functional module, and outputs the test results after the functional module has run. Furthermore, each functional module includes memory, allowing for testing of the registers of each functional module, particularly the registers of the memory PHY, thereby effectively determining register failure status. Further, since registers have a wide range of applications and are numerous, by setting the test results of any functional module to be inconsistent with the theoretical output data, the chip is determined to be a failed chip, which helps improve testing efficiency and thus achieves efficient determination of chip failure status over a wider range.

[0020] Furthermore, the memory is DDR, the memory PHY is DDR PHY, and the registers of the DDR PHY include registers for the DDR impedance control calibration ZQC controller and DDR data control registers for controlling data storage. Therefore, before performing write / read tests on the DDR data control registers for controlling data storage, resistance calibration can be performed by configuring the DDR type mode and writing to the DDR ZQC controller registers. Resistance calibration can be used to pre-screen the DDR PHY. Since resistance calibration is a crucial prerequisite step for DDR control, adding a comparison step between the calibration value obtained after resistance calibration and a preset resistance calibration threshold not only provides a basis for subsequent DDR operation but also allows for the detection of DDR ZQC controller register failures in the initial testing steps, thus identifying chip failures. This helps save testing time and improve testing efficiency.

[0021] Furthermore, the functional module also includes a GPU. By writing information into the GPU's registers and running the GPU, the GPU performs GPU computation and drawing based on the information written into the GPU's registers. If the graph data obtained after GPU computation and drawing is inconsistent with the graph data of the preset GPU computation and drawing program, the chip is determined to be a faulty chip. Thus, by testing the GPU's registers, the failure status of the GPU registers can be effectively determined. Since GPUs are used for image and graphics-related operations, there are many application scenarios, which helps to further expand the scope of implementation for determining chip failure.

[0022] Furthermore, the functional module also includes a CPU. The CPU's registers include a CPU configuration voltage register, a CPU frequency register, and a register for data storage. The register write information determined based on the CPU's theoretical input data contains multiple sets of information. Thus, by writing the CPU's register write information set by set and running the CPU, the read and write frequency of the CPU's data registers can be gradually increased under the same configuration voltage and frequency to achieve large-volume, frequent data read and write, and to realize the test curve of changing from low voltage and low frequency to high voltage and high frequency. In this way, the failure status of the CPU's registers can be detected by gradually increasing the CPU load, which is beneficial to improving the detection accuracy of the CPU's registers.

[0023] Furthermore, the number of CPUs is multiple; the registers of each CPU are traversed and written information is written, and each CPU is run separately to test the registers of each CPU individually; the registers of each CPU are combined and each CPU is run simultaneously to test the registers of the combined CPU, so that the registers of each CPU can be tested individually and in combination, thereby further improving the detection accuracy of CPU registers in the case of multiple CPUs.

[0024] Furthermore, the functional module also includes HUK, writes information to the register of the HUK and runs the HUK so that the HUK performs encryption processing based on the information written to the register of the HUK; then, if the processed data obtained after HUK encryption is inconsistent with the processed data of the preset HUK encryption processing program, the chip is determined to be a faulty chip. Thus, by testing the register of the HUK, the failure status of the HUK register can be effectively determined. Since the HUK is used for internal encryption in security scenarios, the scope of determining chip failure can be further expanded while testing the registers of important functional modules.

[0025] Furthermore, the memory, GPU, CPU, and HUK have different register test programs; the test order of each register test program is predetermined, and if the test result of any functional module is inconsistent with the theoretical output data, the subsequent test is stopped. This allows for immediate cessation of subsequent tests if any register failure is detected, effectively improving test efficiency.

[0026] Furthermore, the failure chip screening method is run on hardware devices without an operating system, which can avoid the situation where software faults (bugs) in the operating system environment lead to misjudgments of chip failure, effectively enhancing the targeting of screening and improving screening accuracy. Attached Figure Description

[0027] Figure 1 This is a flowchart of a method for screening failed chips according to an embodiment of the present invention;

[0028] Figure 2 yes Figure 1 A flowchart of a specific implementation of step S12;

[0029] Figure 3 yes Figure 1 A flowchart of another specific implementation of step S12;

[0030] Figure 4 This is a comparative diagram of CPU operating parameters at various stages in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the structure of a failed chip screening device according to an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of the structure of a failed chip screening system according to an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of a terminal outputting an executable file in an embodiment of the present invention. Detailed Implementation

[0034] Existing methods for screening failed chips typically utilize the electrical characteristics of the chip. For example, based on preset electrical parameters, chips with suitable electrical performance are obtained, and failed chips are screened out. However, such screening methods are time-consuming, costly, and have a limited scope of verification.

[0035] Research has revealed that in existing technologies, the electrical characteristics of a chip (current, voltage, etc.) are used to verify whether the chip is effective or not by inputting physical signals and observing the output signal waveform. This screening method can only verify a certain electrical path, is time-consuming and costly, and has a relatively small verification range.

[0036] Further research revealed that registers are extremely important in chips, with numerous applications and functional modules. Data reading and writing are required in multiple functional modules. In addition, registers are technically challenging to manufacture, and register failures can better indicate the failure status of other functional modules of the chip. In other words, compared with other detection objects with lower technical difficulty, the difference between the register failure rate and the actual chip failure rate is smaller. This is beneficial for initial screening of chips based on the validity or failure of registers, or for directly using the registration screening results as the chip failure screening results.

[0037] In this embodiment of the invention, each register test program includes an execution program for at least one functional module of the chip under test. Each register test program runs in a preset order, performs write operations to the registers of the corresponding functional module, and outputs the test results after the functional module has run. Furthermore, the functional module includes memory, allowing testing of the registers of each functional module, especially the memory registers, thereby effectively determining the failure status of the registers. Further, since registers have a wide range of applications and are numerous, by setting the test results of any functional module to be inconsistent with the theoretical output data, the chip is determined to be a failed chip, which helps improve testing efficiency and thus achieves efficient determination of chip failure status over a wider range.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 1 , Figure 1 This is a flowchart of a failed chip screening method according to an embodiment of the present invention. The failed chip screening method may include steps S11 to S13:

[0040] Step S11: Obtain one or more register test programs, each register test program containing the running program of at least one functional module of the chip under test;

[0041] Step S12: Run each register test program in a preset order, write to the registers of the corresponding functional modules, and output the test results after the functional modules have run. Each functional module has preset theoretical input data and theoretical output data, as well as register write information determined based on the theoretical input data.

[0042] Step S13: If the test result of any functional module is inconsistent with the theoretical output data, then the chip is determined to be a failed chip.

[0043] The functional module includes a memory physical interface (PHY), and the preset theoretical input data and theoretical output data of the memory PHY are preset memory write data and memory read data, respectively.

[0044] In the specific implementation of step S11, one or more register test programs can test the registers of multiple functional modules respectively. The function of the register is to store binary code, and it can be composed of flip-flops with storage function. One flip-flop can store 1 bit of binary code. Therefore, a register that stores n bits of binary code needs to be composed of n flip-flops.

[0045] Because registers are extremely important in chips, they have many applications and belong to many functional modules. Data reading and writing are required in multiple functional modules. Compared with the existing technology of testing chips by utilizing their electrical characteristics, this method can increase the testing range of failed chips.

[0046] A chip can contain many internal functional modules, such as a graphics processing unit (GPU), a central processing unit (CPU), a hardware unique key (HUK), and a memory physical interface (PHY).

[0047] The physical memory interface (PHY), also known as the memory port physical layer, is where the memory, as a storage chip, is typically connected externally (e.g., plugged in) and then controlled by the PHY. Specifically, the test target can be the memory PHY inside the chip, which drives the external memory (such as DDR chips). Read and write operations are initiated by the CPU, executed by the memory PHY, and ultimately implemented on the external memory.

[0048] Furthermore, memory can include main memory (RAM). As a crucial component of terminal devices, RAM, also known as internal memory or main memory, is used to temporarily store data processed by the CPU, as well as data exchanged with external storage devices such as hard drives. All programs in a terminal device run in RAM, and the performance of RAM directly impacts the overall performance of the terminal device; RAM operation determines the overall speed of the computer. Even further, RAM can include Double Data Rate Synchronous Dynamic Random Access Memory (DDR), flash memory, and other similar formats.

[0049] Among them, DDR uses advanced synchronization circuits, which enable the main steps of sending and outputting specified addresses and data to be executed independently while maintaining complete synchronization with the CPU. It is widely used, and the memory PHY is DDR PHY.

[0050] Flash memory can be seen as an upgrade to electrically erasable programmable read-only memory, which can be repeatedly erased and written using electrical principles. In this case, the memory PHY is the flash memory PHY.

[0051] Specifically, each chip screening module code can contain a register test program (also known as a chip screening interface function) designed based on the usage of chip register functions. This register test program can cover the design path and key design points of the chip's internal functional modules, thereby achieving the purpose of screening for failed chips. Each functional module can set error codes within its code. If a functional module fails (FAIL), it can return an error code; otherwise, it will not return an error code. Based on the returned error codes, the chip can be determined to be a failed chip.

[0052] In the specific implementation of step S12, each register test program is run in a preset order, writes to the registers of the corresponding functional modules, and outputs the test results after the functional modules have run.

[0053] Furthermore, the preset order can be set according to the importance of each functional module. For example, the memory, as an important component for storing programs and data, and the GPU, which is used for image and graphics-related computing, can be placed in a higher testing position.

[0054] The preset order can also be set according to the number of registers contained in each functional module. For example, memory is used to store programs and data, which depends more on the quality of registers, and registers account for a higher proportion of the number of registers in memory, so they can be placed in the test position earlier.

[0055] In practice, by writing to the registers of the corresponding functional module and outputting the test results after the functional module runs, the test code of the module interface function of the corresponding functional module can be executed, the module registers can be configured, the test logic can be executed, and the test results can be returned.

[0056] Furthermore, the failed chip screening method can be run on a hardware device without an operating system.

[0057] Specifically, an operating system (OS) is a set of interconnected system software programs that manage and control computer operation, the use and operation of hardware and software resources, and the provision of public services to organize user interaction. It is the most basic and important foundational system software. Over the decades, operating systems have evolved from simple control loops to more complex distributed operating systems. Coupled with the diversification of user needs, operating systems have become both complex and massive software systems.

[0058] In this embodiment of the invention, the failed chip screening method is run on a hardware device without an operating system, which can avoid the situation where software faults (bugs) in the operating system environment lead to misjudgments of chip failure, effectively enhancing the targeting of screening and improving screening accuracy.

[0059] Furthermore, the memory can be DDR, and the registers of the DDR PHY include registers for the DDR impedance control calibration (ZQC) controller and DDR data control registers for controlling data storage.

[0060] The DDR PHY has preset theoretical input data and theoretical output data. The theoretical output data is obtained by running the DDR PHY based on the preset theoretical input data. For example, the theoretical input data can be control instructions written to the register of the DDR ZQC controller. After the DDR ZQC controller performs resistance calibration, it should have a preset calibration result (i.e., a preset calibration value) as the theoretical output data. Alternatively, the theoretical input data can also be data written to the DDR data control register. The theoretical output data, as the data read from the DDR data control register, should be consistent with the data written to the DDR data control register.

[0061] Reference Figure 2 , Figure 2 yes Figure 1 A flowchart illustrating a specific implementation of step S12. The step of writing to the register of the corresponding functional module may include steps S21 to S24.

[0062] Step S21: Enable the registers of the DDR PHY when it is powered on;

[0063] Step S22: Configure the CPU voltage register to the preset voltage;

[0064] Step S23: Configure DDR type mode;

[0065] Step S24: Based on the register write information of the DDR PHY and the DDR type mode, write the resistor calibration information into the register of the DDR ZQC controller.

[0066] In step S21, the DDR PHY register can be enabled by first configuring the DDR PHY enable register and then configuring the DDR PHY power-on register.

[0067] It should be noted that other appropriate steps can also be used to enable the registers of the DDR PHY to power on.

[0068] In step S22, the CPU voltage register is configured to a preset voltage.

[0069] After being configured to a preset voltage, it can also be fixed at that voltage point.

[0070] In step S23, the DDR type mode is configured.

[0071] The DDR type can include DDR2 to DDR4, and can also include other appropriate DDR types.

[0072] In step S24, based on the register write information of the DDR PHY and the DDR type mode, resistor calibration is performed by writing to the register of the DDRZQC controller.

[0073] It should be noted that, before step S24, a reference voltage register used by ZQC can be added to further meet the accuracy requirements of resistor calibration.

[0074] Furthermore, Figure 1 The step S13 shown, which is to determine that the chip is a failed chip if the test result of any functional module is inconsistent with the theoretical output data, may include: if the calibration value obtained after resistance calibration is inconsistent with the preset resistance calibration threshold, then the chip is determined to be a failed chip.

[0075] It should be noted that the failure status of the DDR ZQC controller registers can be determined first, and then the failure status of the DDR data control registers can be determined.

[0076] Specifically, after performing resistor calibration in step S24, and comparing the calibration value with a preset resistor calibration threshold to determine the failure status, the process may further include: writing write information to the DDR data control register, and then reading the DDR data control register to obtain read data.

[0077] If the read data is inconsistent with the information written to the DDR data control register, it is determined that there is a faulty register in the DDR data control register, and thus the chip is determined to be a faulty chip.

[0078] In this embodiment of the invention, the memory is DDR, and the register of the DDR PHY includes a register of the DDR impedance control calibration ZQC controller and a DDR data control register for controlling data storage. Therefore, before performing write and read tests on the DDR data control register for controlling data storage, resistance calibration can be performed by configuring the DDR type mode and writing to the register of the DDR ZQC controller. Resistance calibration can be used to pre-screen the DDR PHY. Since the resistance calibration step is an important prerequisite step for implementing DDR control, adding a comparison step between the calibration value obtained after resistance calibration and the preset resistance calibration threshold not only provides a basis for subsequent DDR operation but also allows for the detection of DDR ZQC controller register failures in the initial test steps, thus identifying chip failures. This helps save test time and improve test efficiency.

[0079] Furthermore, the functional module may also include a GPU; the step of writing to the register of the corresponding functional module may include: enabling the register of the GPU; writing the register write information of the GPU and running the GPU, so that the GPU performs GPU computing and drawing based on the register write information of the GPU; wherein, the preset theoretical output data of the GPU is the graph data of the preset GPU computing and drawing program, and if the graph data obtained after GPU computing and drawing is inconsistent with the graph data of the preset GPU computing and drawing program, the chip is determined to be a faulty chip.

[0080] One approach is to first configure the GPU enable register, and then configure the GPU power-on register to enable the GPU's registers. Alternatively, other appropriate steps can be used to enable the GPU's registers.

[0081] Specifically, by enabling GPU operation, the GPU is allowed to process the preset input data by default, perform GPU calculations and drawing, and obtain the drawing result data. This result data is then compared with the preset correct result value in the code. The interface function will return either correct or incorrect, and the registers of the GPU module inside the chip can be filtered.

[0082] In this embodiment of the invention, the functional module further includes a GPU. By writing information into the GPU's registers and running the GPU, the GPU performs GPU computation and drawing based on the information written into the GPU's registers. If the graph data obtained after GPU computation and drawing is inconsistent with the graph data of the preset GPU computation and drawing program, the chip is determined to be a faulty chip. Thus, by testing the GPU's registers, the failure status of the GPU registers can be effectively determined. Since GPUs are used for image and graphics-related operations, there are many application scenarios, which helps to further expand the scope of implementation for determining chip failure.

[0083] Furthermore, the functional module may also include a CPU, whose registers include a CPU configuration voltage register, a CPU frequency register, and a CPU data register for data storage. The register write information determined based on the CPU's theoretical input data includes multiple sets of information.

[0084] The CPU configuration voltage register can be used to adjust the CPU configuration voltage to achieve low-voltage and high-voltage read / write; the CPU frequency register can be used to adjust the CPU frequency to achieve low-frequency and high-frequency read / write.

[0085] The CPU has preset theoretical input data and theoretical output data. The theoretical output data is obtained after running the CPU based on the preset theoretical input data. For example, the theoretical input data can be data written to the CPU data register, and the theoretical output data is output after the CPU runs.

[0086] Reference Figure 3 , Figure 3 yes Figure 1 A flowchart of another specific implementation of step S12. The step of writing to the register of the corresponding functional module may include steps S31 to S32.

[0087] Step S31: Enable the registers of the powered-on CPU;

[0088] Step S32: Write the register write information of the CPU group by group and run the CPU. The configuration voltage of the configuration voltage register of the CPU that runs first is less than or equal to the configuration voltage of the configuration voltage register of the CPU that runs later. The frequency of the frequency register of the CPU that runs first is less than or equal to the frequency of the frequency register of the CPU that runs later. The read and write frequency of the data register of the CPU that runs first under the same configuration voltage and the same frequency is less than or equal to the read and write frequency of the data register of the CPU that runs later.

[0089] In step S31, the CPU enable register can be configured first, and then the CPU power-on register can be configured to enable the CPU registers. Alternatively, other appropriate steps can be used to enable the CPU registers.

[0090] In step S32, the CPU configuration voltage register and CPU frequency register can be configured first to provide an initial power supply voltage and an initial frequency. Then, the CPU's operating environment can be changed by writing the new power supply voltage and frequency.

[0091] Reference Figure 4 , Figure 4 This is a comparative diagram of CPU operating parameters at various stages in an embodiment of the present invention.

[0092] exist Figure 4 The following example illustrates the three operating phases: the first operating phase can have the configuration voltage V1 of the CPU configuration voltage register, the frequency F1 of the CPU frequency register, and the read / write frequency Q1 of the CPU data register; the second operating phase can have the configuration voltage V2 of the CPU configuration voltage register, the frequency F2 of the CPU frequency register, and the read / write frequency Q2 of the CPU data register; the third operating phase can have the configuration voltage V3 of the CPU configuration voltage register, the frequency F3 of the CPU frequency register, and the read / write frequency Q3 of the CPU data register; and similarly, the parameters for the fourth operating phase, the fifth operating phase, and so on can be obtained.

[0093] Among them, the configuration voltage is used to adjust the CPU power supply voltage, and the frequency is used to adjust the CPU frequency (such as the clock frequency when the CPU is working).

[0094] Specifically, the operating parameters of adjacent operating phases can be the same or different.

[0095] In practice, the configuration voltage of the CPU configuration voltage register used in the first part of the operation phase can be lower than the configuration voltage of the CPU configuration voltage register used in the second part of the operation phase.

[0096] Specifically, it can be V1 < V2 < V3, or it can be V1 = V2 < V3, or it can be V1 < V2 = V3. Specifically, the variable voltage and variable frequency strategy is based on the rules of dynamic voltage and frequency scaling (DVFS), and the CPU cannot be in a low voltage and high frequency state at any time.

[0097] Specifically, when the configuration voltage changes, the later configuration voltage can be increased compared to the earlier configuration voltage, thereby achieving a transition from a low-voltage to a high-voltage operating environment.

[0098] In practice, the frequency of the CPU frequency register used in the first part of the operation can be lower than the frequency of the CPU frequency register used in the second part of the operation.

[0099] Specifically, it can be F1 < F2 < F3, or it can be F1 = F2 < F3, or it can be F1 < F2 = F3.

[0100] Specifically, when the frequency changes, the value of the later frequency can be increased compared to the earlier frequency, thereby achieving a transition from a low-frequency to a high-frequency operating environment.

[0101] In practice, the frequency of reading and writing CPU data registers in the earlier part of the operation phase can be less than the frequency of reading and writing CPU data registers in the later part of the operation phase.

[0102] Specifically, it can be Q1 < Q2 < Q3, or it can be Q1 = Q2 < Q3, or it can be Q1 < Q2 = Q3.

[0103] Specifically, when the read / write frequency changes, the subsequent read / write frequency can increase by a thousand times (i.e., by three orders of magnitude) to a hundred thousand times (i.e., by five orders of magnitude) of the previous read / write frequency, thereby enabling the transition from a low data load to a high data load working environment.

[0104] Furthermore, under the same configuration voltage and frequency, the read / write frequency of the data register of the CPU that runs earlier is less than or equal to the read / write frequency of the data register of the CPU that runs later.

[0105] In one specific embodiment of the present invention, F1 = F2 < F3 = F4, V1 = V2 < V3 = V4, Q1 < Q2, Q3 < Q4 can be used to achieve the principle of small to large under low frequency and low voltage, and small to large under high frequency and high voltage.

[0106] There are no restrictions on the size relationship between Q1 and Q3, and Q2 and Q4. It is also possible for Q1 = Q3 and Q2 = Q4.

[0107] In another specific embodiment of the present invention, F1 = F2 < F3 = F4, V1 = V2 < V3 = V4, Q1 < Q2 < Q3 < Q4, so that low-frequency and low-voltage operation can be performed first, followed by high-frequency and high-voltage operation, and the read and write frequency can be continuously increased.

[0108] In another specific embodiment of the present invention, F1 = F2 < F3 = F4, V1 = V2 < V3 = V4, Q1 < Q2 = Q3 < Q4, thus allowing for initial low-frequency, low-voltage operation followed by high-frequency, high-voltage operation, with a non-continuous increase in read / write frequency. In this embodiment, by writing information to the CPU registers group by group and running the CPU, the read / write frequency of the CPU data registers can be gradually increased under the same configuration voltage and frequency to achieve large-volume, frequent data read / write, and to realize a test curve from low-voltage, low-frequency to high-voltage, high-frequency changes. This allows for the detection of CPU register failures while gradually increasing the CPU load, which is beneficial for improving the accuracy of CPU register detection.

[0109] Furthermore, Figure 1 The step S13 shown, which is the step of determining that the chip is a failed chip if the test result of any functional module is inconsistent with the theoretical output data, may include: if the CPU read data after running is inconsistent with the theoretical output data of the CPU, then the chip is determined to be a failed chip.

[0110] In one specific embodiment of the present invention, the failure chip screening method is run in a hardware device without an operating system. By setting it to be without an operating system, in addition to avoiding software failures in the operating system environment from being mistakenly identified as chip failures, the accuracy of CPU register failure judgment can be further improved.

[0111] Specifically, as operating systems have evolved into complex distributed operating systems, coupled with the diversification of user needs, they have become both complex and massive software systems. When a CPU register failure occurs, it is difficult to determine whether it is caused by increased CPU load or by the high pressure on the CPU under the operating system environment. Therefore, running the CPU in an environment without an operating system can reduce the pressure on the CPU, thus making it possible to identify whether it is caused by increased CPU load. This improves the accuracy of the numerical results obtained from batch experiments on the CPU and allows for a more accurate assessment of the CPU register failure.

[0112] Furthermore, the number of CPUs is multiple; writing the register write information of the CPUs group by group and running the CPUs further includes: traversing the register write information of each CPU and running each CPU separately to test the registers of each CPU separately; combining the register write information of each CPU and running each CPU simultaneously to test the registers of the combined CPUs.

[0113] Specifically, the CPU can be enabled to run at a preset frequency and voltage point, and then the CPU load can be increased, such as by reading and writing large amounts of data frequently. Finally, the consistency between the read and written data can be checked. Then, the CPU frequency and voltage point can be changed again, and the CPU load can be increased to confirm the consistency between read and write. This process can be repeated, traversing and combining various CPUs for testing. Finally, the interface function will return a correct or incorrect result, thereby achieving the purpose of screening the CPU modules inside the chip.

[0114] In this embodiment of the invention, there are multiple CPUs; the registers of each CPU are traversed and written information is written, and each CPU is run separately to test the registers of each CPU separately; the registers of each CPU are combined and each CPU is run simultaneously to test the combined registers of each CPU, so that the registers of each CPU can be tested individually and in combination, thereby further improving the detection accuracy of CPU registers in the case of multiple CPUs.

[0115] Furthermore, the functional module may also include HUK.

[0116] HUK can be used to represent a hardware-unique key, which is unique to the hardware.

[0117] The step of writing to the register of the corresponding functional module may include: enabling the HUK register; writing the HUK register write information and running the HUK so that the HUK performs encryption processing based on the HUK register write information; wherein, the preset theoretical output data of the HUK is the processed data of the preset HUK encryption processing program, and if the processed data obtained after HUK encryption processing is inconsistent with the processed data of the preset HUK encryption processing program, the chip is determined to be a faulty chip.

[0118] One approach is to first configure the HUK enable register, then configure the HUK power-on register to enable the HUK registers. Alternatively, other appropriate steps can be used to enable the HUK registers.

[0119] Specifically, by configuring the HUK control access register, the HUK area is read, and the read value is compared with the preset correct result value in the code. The interface function will return correct or incorrect, which can filter the registers of the HUK module inside the chip.

[0120] In this embodiment of the invention, the functional module further includes a HUK, which writes register information to the HUK and runs the HUK so that the HUK performs encryption processing based on the register information. If the processed data obtained after HUK encryption is inconsistent with the processed data of the preset HUK encryption program, the chip is determined to be a faulty chip. Thus, by testing the HUK register, the failure status of the HUK register can be effectively determined. Since the HUK is used for internal encryption in security scenarios, the scope of chip failure determination can be further expanded while testing the registers of important functional modules.

[0121] Continue to refer to Figure 1 In the specific implementation of step S13, if the test result of any functional module is inconsistent with the theoretical output data, the chip is determined to be a failed chip.

[0122] In this embodiment of the invention, each register test program includes an execution program for at least one functional module of the chip under test. Each register test program runs in a preset order, performs write operations to the registers of the corresponding functional module, and outputs the test results after the functional module has run. Furthermore, the functional module includes memory, allowing testing of the registers of each functional module, especially the memory registers, thereby effectively determining the failure status of the registers. Further, since registers have a wide range of applications and are numerous, by setting the test results of any functional module to be inconsistent with the theoretical output data, the chip is determined to be a failed chip, which helps improve testing efficiency and thus achieves efficient determination of chip failure status over a wider range.

[0123] It should be noted that when a functional module has multiple types of registers, the test results can be output and judged one by one. For example, the registers of the DDR ZQC controller mentioned above can be judged before the DDR data control register.

[0124] If any type of register is determined to be faulty after testing, the testing of subsequent types of registers can be stopped. This allows for immediate cessation of subsequent tests if any register is found to be faulty, effectively improving testing efficiency.

[0125] Furthermore, the memory PHY, GPU, CPU, and HUK have different register test programs; the test order of each register test program is predetermined, and if the test result of any functional module is inconsistent with the theoretical output data, the subsequent test is stopped.

[0126] As mentioned earlier, the preset order can be set according to the importance of each functional module, or according to the number of registers contained in each functional module. By pre-determining the test order, if no failure is found, the functional modules in that test order can be tested sequentially by default, effectively improving testing efficiency.

[0127] In this embodiment of the invention, if the test result of any functional module is inconsistent with the theoretical output data, the subsequent test is stopped. This allows the subsequent test to be stopped immediately if any register failure is found during testing, thus effectively improving test efficiency.

[0128] Reference Figure 5 , Figure 5 This is a schematic diagram of a faulty chip screening device according to an embodiment of the present invention. The faulty chip screening device may include:

[0129] The program acquisition module 51 is used to acquire one or more register test programs, each register test program containing the running program of at least one functional module of the chip under test;

[0130] The register writing module 52 is used to run each register test program in a preset order, perform write operations to the registers of the corresponding functional modules, and output the test results after the functional modules are run. Each functional module has preset theoretical input data and theoretical output data, as well as register writing information determined based on the theoretical input data.

[0131] The judgment module 53 is used to determine that the chip is a failed chip when the test result of any functional module is inconsistent with the theoretical output data;

[0132] The functional module includes a memory PHY, whose preset theoretical input data and theoretical output data are preset memory write data and memory read data, respectively.

[0133] In practice, Figure 5 The failure chip screening device shown may correspond to a chip with data processing function in a terminal; or to a terminal including a chip or chip module with data processing function, or to a terminal.

[0134] For more information on the working principle, working method, and beneficial effects of the failed chip screening device in this application embodiment, please refer to the above section. Figures 1 to 4 The description of the failed chip screening method shown is not repeated here.

[0135] This application also provides a readable storage medium, such as a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, the above-described failed chip screening method is executed. The storage medium may include ROM, RAM, a disk, or an optical disk, etc. The storage medium may also include non-volatile memory or non-transitory memory, etc.

[0136] This application embodiment also provides a terminal, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor runs the computer program, it executes the preceding text and... Figures 1 to 4 The steps of the failed chip screening method are shown.

[0137] It should be understood that in the embodiments of this application, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0138] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0139] Reference Figure 6 , Figure 6 This is a schematic diagram of a failed chip screening system according to an embodiment of the present invention. The failed chip screening system may include a test board 61 and a USB module 62.

[0140] The test board 61 may include a terminal 611 and a chip base 612, wherein the chip base 612 is used to support the chip to be tested.

[0141] USB module 62 is used to carry a computer program that can run on the processor of the terminal, download the computer program to the terminal 611, send the enable power-on signal received from the host computer 63 to the terminal 611, and send the failed chip information output by the terminal 63 to the host computer 611.

[0142] It should be noted that the host computer 63 can also feed back the chip screening test code to the chip clamping device 64, which can automatically replace the chip to be tested on the test board 61.

[0143] Figure 7 This is a schematic diagram of a terminal outputting an executable file in an embodiment of the present invention.

[0144] The chip architecture file contains the arm\arm64\riscv\x86 startup configuration file, which is responsible for initializing the chip screening configuration according to different CPU architectures, and realizing the code execution environment without an operating system.

[0145] The chip architecture file consists of a startup file;

[0146] The chip platform file contains the chip screening program for each chip project (such as the register test program in the embodiment of this invention). By calling module interface functions in the chip screening program, the purpose of screening a specific module (such as the functional module in the embodiment of this invention) within a chip can be achieved for a given chip platform. For example:

[0147] In the A chip platform file, the interface function of the xx\yy\zz\ss module is called. The final compiled A platform screen chip executable file will contain the screen chip interface function of the xx\yy\zz\ss module.

[0148] The chip module layer contains many internal modules of the chip, such as the GPU, CPU, HUK, and memory (e.g., DDR) mentioned above. Each chip screening module's code contains screening interface functions designed based on the chip's register functionality. These interface functions cover the design path and key design points of the chip's internal modules, thereby achieving the chip screening purpose. Each module has an error code set in its code; if a module fails, it will return an error code; otherwise, it will not return an error code.

[0149] CMake files and GCC compilation rules are used throughout the entire small code platform. Compilation commands generate executable files for the specific chip platform in a fixed output (out) directory. The small code platform can be used to represent the operating system-less runtime environment mentioned above.

[0150] The purpose of these rules and generated files is to compile module files, select the modules to be screened, and ultimately generate an executable file containing a multi-module screening program.

[0151] In one specific implementation, combined with Figure 6 The system shown may include the following steps:

[0152] (1) Call the chip module screening module in the chip screening program of a certain screening platform;

[0153] (2) Execute the compilation command to generate an executable chip screening file for a specific chip platform;

[0154] (3) Using a proprietary download tool, the screening program is downloaded to a proprietary hardware board (such as test board 61) via USB module 62;

[0155] (4) Use the dedicated host computer 63 to send a power-on start signal to the test board 61 via the USB module 62;

[0156] (5) When the chip receives power-on, the chip screening program starts running, establishes a chip screening environment without an operating system, enters the interface function of the xxx module, starts executing the test code of the module, configures the module register, executes the test logic, and returns the test result of the xxx module. If an error code is returned, the error code will be output to the host computer through the serial port, and then the program will stop, and the chip will be judged as a failed chip; if no error code is returned, the test of the yyy module will continue until all test modules have completed the test and returned the correct result (Pass);

[0157] If the host computer detects an error code, it will power down test board 61 and replace the chip. If no error code is detected throughout the process, and the test passes (Pass), the chip is considered good, and test board 61 is powered down. The next chip is then replaced for testing. This process is repeated.

[0158] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means.

[0159] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0160] In the several embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, and systems can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0161] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0162] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can be physically included separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or in a combination of hardware and software functional units. For example, for various devices or products applied to or integrated into a chip, each module / unit can be implemented using hardware such as circuits, or at least some modules / units can be implemented using software programs running on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware such as circuits; for various devices or products applied to or integrated into a chip module, each module / unit can be implemented using hardware such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0163] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0164] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0165] In the embodiments of this application, "multiple" refers to two or more.

[0166] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0167] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for screening failed chips, characterized in that, include: Obtain one or more register test programs, each register test program containing the running program of at least one functional module of the chip under test; Each register test program is run in a preset order, writes to the registers of the corresponding functional modules, and outputs the test results after the functional modules are run. Each functional module has preset theoretical input data and theoretical output data, as well as register write information determined based on the theoretical input data. If the test result of any functional module is inconsistent with the theoretical output data, the chip is determined to be a failed chip. The functional module includes a memory physical interface (PHY), and the preset theoretical input data and theoretical output data of the memory PHY are preset memory write data and memory read data, respectively.

2. The method according to claim 1, characterized in that, The memory is DDR, the memory PHY is DDRPHY, and the registers of the DDR PHY include registers for the DDR impedance control calibration ZQC controller and DDR data control registers for controlling data storage. The write operation to the register of the corresponding functional module includes: Enable the registers of the DDR PHY upon power-up; Configure the CPU voltage register to the preset voltage; Configure DDR type mode; Based on the register write information of the DDR PHY and the DDR type mode, resistor calibration is performed by writing to the register of the DDRZQC controller. If the calibration value obtained after resistance calibration is inconsistent with the preset resistance calibration threshold, the chip is determined to be a faulty chip.

3. The method according to claim 1, characterized in that, The functional module also includes a GPU; The write operation to the register of the corresponding functional module includes: Enable the registers of the GPU upon power-up; Write the register write information of the GPU and run the GPU so that the GPU performs GPU computing and drawing based on the register write information of the GPU; The preset theoretical output data of the GPU is the graph data of the preset GPU computing and drawing program. If the graph data obtained after GPU computing and drawing is inconsistent with the graph data of the preset GPU computing and drawing program, the chip is judged to be a faulty chip.

4. The method according to claim 3, characterized in that, The functional module also includes a CPU, whose registers include a CPU configuration voltage register, a CPU frequency register, and a CPU data register for data storage. The register write information determined based on the CPU's theoretical input data includes multiple sets of information. The write operation to the register of the corresponding functional module includes: Enable the registers of the CPU upon power-up; Write information to the registers of the CPU in groups and run the CPU, satisfying one or more of the following: the configuration voltage of the configuration voltage register of the CPU running earlier is less than or equal to the configuration voltage of the configuration voltage register of the CPU running later; the frequency of the frequency register of the CPU running earlier is less than or equal to the frequency of the frequency register of the CPU running later; and the read / write frequency of the data register of the CPU running earlier under the same configuration voltage and the same frequency is less than or equal to the read / write frequency of the data register of the CPU running later. If the data read by the CPU after operation is inconsistent with the theoretical output data of the CPU, then the chip is determined to be a faulty chip.

5. The method according to claim 4, characterized in that, The number of CPUs is multiple; Writing information to the CPU's registers group by group and running the CPU also includes: Write information to the registers of each CPU and run each CPU separately to test the registers of each CPU. The registers of each CPU are written together and each CPU is run simultaneously to test the registers of the combined CPUs.

6. The method according to claim 3, characterized in that, The functional module also includes HUK; The write operation to the register of the corresponding functional module includes: Enable the HUK register upon power-up; Write the register write information of the HUK and run the HUK so that the HUK performs encryption processing based on the register write information of the HUK; The preset theoretical output data of HUK is the processed data of the preset HUK encryption process. If the processed data obtained after HUK encryption is inconsistent with the processed data of the preset HUK encryption process, the chip is determined to be a faulty chip.

7. The method according to claim 4 or 6, characterized in that, The memory, GPU, CPU, and HUK have different register test programs; The testing order of each register test program is predetermined. If the test result of any functional module is inconsistent with the theoretical output data, the subsequent tests will be stopped.

8. The method according to claim 1, characterized in that, The method for screening failed chips is run on hardware devices without an operating system.

9. A faulty chip screening device, characterized in that, include: The program acquisition module is used to acquire one or more register test programs, each register test program containing the running program of at least one functional module of the chip under test; The register writing module is used to run each register test program in a preset order, perform write operations to the registers of the corresponding functional modules, and output the test results after the functional modules have run. Each functional module has preset theoretical input data and theoretical output data, as well as register writing information determined based on the theoretical input data. The judgment module is used to determine that the chip is a failed chip when the test result of any functional module is inconsistent with the theoretical output data; The functional module includes a memory physical interface (PHY), and the preset theoretical input data and theoretical output data of the memory PHY are preset memory write data and memory read data, respectively.

10. A readable storage medium having a computer program stored thereon, characterized in that, The computer program, when run by the processor, performs the steps of the failed chip screening method according to any one of claims 1 to 8.

11. A terminal comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the failed chip screening method according to any one of claims 1 to 8.

12. A failure chip screening system, characterized in that, include: The test board includes the terminal as described in claim 11 and a chip base, the chip base being used to support the chip to be tested; The USB module is used to carry a computer program that can run on the processor of the terminal, download the computer program to the terminal, send an enable power-on signal received from the host computer to the terminal, and send the failed chip information output by the terminal to the host computer.

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