大规模FPGA电路验证方法、装置及存储介质
By obtaining target module-level circuits at a higher level than a specified level in FPGA circuits and performing simulation verification, the problem of excessively long simulation time in large-scale FPGA circuit verification is solved, thereby improving verification efficiency and ensuring the accuracy of module functions and connection relationships.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN PANGO MICROSYST CO LTD
- Filing Date
- 2023-09-18
- Publication Date
- 2026-07-17
AI Technical Summary
As the scale of FPGA circuits increases, the number of modules and the complexity of connections also increase, leading to longer simulation times and reduced verification efficiency during chip verification.
By leveraging the hierarchical relationship of module-level circuits, the target module-level circuit is obtained from multiple module-level circuits. Its circuit function description netlist and circuit connection description netlist are then acquired, and the target module-level circuit is simulated and verified, thereby reducing the compilation depth and improving verification efficiency.
By reducing the size of the circuit function description netlist, simulation time is saved and verification efficiency is improved, while avoiding the risk of errors in module function and connection relationships that may be caused by higher-level module descriptions.
Smart Images
Figure CN117436384B_ABST