Display panel

Abstract

This invention discloses a display panel including a selection circuit and a control circuit. The selection circuit has an input terminal, an output terminal, a first control terminal, and a second control terminal. The output terminal is electrically connected to a pixel array and sequentially includes a first output terminal to an m-th output terminal. The input terminal sequentially includes a first input terminal to an (m+1)-th input terminal, where m is a positive integer. The control circuit is electrically connected to the input terminal of the selection circuit to provide a data signal. The first control terminal and the second control terminal have opposite potentials. The display panel determines the potentials of the first and second control terminals based on the pins of the control circuit and controls one of the first input terminal and the (m+1)-th input terminal to participate in transmitting the data signal, while the other of the first input terminal and the (m+1)-th input terminal does not participate in transmitting the data signal. This invention enables the display panel to be compatible with different control circuits, improving the versatility of the display panel.

Description

Technical Field

[0001] This invention relates to a display panel, and more particularly to a display panel with shared circuitry. Background Technology

[0002] With the continuous advancement of display technology, display panels are now widely used in various electronic products such as flat-screen TVs, laptops, smartphones, and automotive displays. Typical LCD displays use source driver and gate driver circuits to drive pixel units to display images. Because source driver circuits are more expensive than gate driver circuits, to reduce the amount of source driver circuitry used, [further measures are taken]. Figure 1 As shown, it is a schematic diagram of a display panel in the prior art. Figure 1 The illustration depicts a display panel 10' with a half-source driver (HSD) architecture, which halves the number of data lines corresponding to the source driver circuit and doubles the number of gate lines corresponding to the gate driver circuit, thereby reducing production costs. A chip (IC) providing the driver circuitry is electrically bonded to the display panel to provide data signals, for example, through electrical connections with the data lines within the display area.

[0003] In practice, the display effect can be improved by setting the connection relationship between pixel units and data lines. The chip has virtual pins that can also participate in the transmission of the aforementioned data signals. However, the location of these virtual pins varies between chips from different manufacturers, for example, they may be located to the left or right of the conventional pins. In this case, the display panel needs to be designed with different connection lines for different chips, thus increasing design complexity and manufacturing costs. Summary of the Invention

[0004] Therefore, the object of the present invention is to provide a display panel to solve the above-mentioned problems.

[0005] To achieve the above objectives, the present invention provides a display panel comprising a substrate, a pixel array, a selection circuit, and a control circuit. The substrate has an adjacent display area and a peripheral area; the pixel array is disposed in the display area; the selection circuit is disposed in the peripheral area, and the selection circuit has an input terminal, an output terminal, a first control terminal, and a second control terminal. The output terminal is electrically connected to the pixel array, and the output terminal sequentially includes a first output terminal to an m-th output terminal. The input terminal sequentially includes a first input terminal to an (m+1)-th input terminal, where m is a positive integer. The control circuit is disposed in the peripheral area and is electrically connected to the input terminal of the selection circuit to provide a data signal. The first control terminal and the second control terminal have opposite potentials. The display panel determines the potentials of the first control terminal and the second control terminal based on the pins of the control circuit and controls one of the first input terminal and the (m+1)-th input terminal to participate in transmitting the data signal, while the other of the first input terminal and the (m+1)-th input terminal does not participate in transmitting the data signal.

[0006] As an optional technical solution, the first control terminal is maintained at a first potential and the second control terminal is maintained at a second potential, the first potential being opposite to the second potential. The selection circuit controls the first input terminal to the m-th input terminal to participate in transmitting the data signal, while the m+1-th input terminal does not participate in transmitting the data signal. In this case, the first input terminal to the m-th input terminal corresponds one-to-one with the first output terminal to the m-th output terminal. Alternatively, the second control terminal is maintained at a first potential and the first control terminal is maintained at a second potential, the first potential being opposite to the second potential. The selection circuit controls the second input terminal to the m+1-th input terminal to participate in transmitting the data signal, while the first input terminal does not participate in transmitting the data signal. In this case, the second input terminal to the m+1-th input terminal corresponds one-to-one with the first output terminal to the m-th output terminal.

[0007] As an optional technical solution, the selection circuit includes a first to a m-th switching unit corresponding one-to-one with the first to the m-th output terminals. Each switching unit includes a first switching element and a second switching element. The control terminal of each first switching element is electrically connected to the first control terminal, and the control terminal of each second switching element is electrically connected to the second control terminal. In the n-th switching unit, the first terminal of the first switching element is electrically connected to the n-th input terminal of the selection circuit, and the first terminal of the second switching element in the n-th switching unit is electrically connected to the (n+1)-th input terminal of the selection circuit. The second terminals of the first and second switching elements in the n-th switching unit are both electrically connected to the n-th output terminal, where 1 ≤ n ≤ m.

[0008] As an optional technical solution, the display panel also includes multiple touch electrode lines and multiple touch electrodes arranged in an array. One end of each touch electrode line is electrically connected to the corresponding touch electrode, and the other end extends to the peripheral area and is electrically connected to the control circuit. In the selection circuit, each second switching element is located between each first switching element and the display area. Each input terminal is connected to the control circuit via a corresponding data signal lead. Each touch electrode line and each data signal lead are arranged alternately on the same layer. The data signal lead corresponding to the a-th input terminal is disconnected at the corresponding touch electrode line and achieves its own electrical connection through a layer transfer method, where 2≤a≤m.

[0009] As an optional technical solution, the control circuit includes a first virtual pin and m-1 first type pins. The first virtual pin is located on the first side of the m-1 first type pins. The first virtual pin and the m-1 first type pins are used to transmit the data signal. The first input terminal to the m-th input terminal are electrically connected to the first virtual pin and the m-1 first type pins in sequence. The display panel determines the potential of the first control terminal and the second control terminal and controls the first input terminal to the m-th input terminal to participate in transmitting the data signal. Alternatively, the control circuit includes m-1 first-type pins and a second virtual pin, with the second virtual pin located on the second side of the m-1 first-type pins. The m-1 first-type pins and the second virtual pin are used to transmit the data signal. The second input terminal to the m+1 input terminal are electrically connected to the m-1 first-type pins and the second virtual pin in sequence. The display panel determines the potential of the first control terminal and the second control terminal and controls the second input terminal to the m+1 input terminal to participate in transmitting the data signal.

[0010] As an optional technical solution, the control circuit also includes a second type of pin, wherein the first control terminal and the second control terminal are electrically connected to the second type of pin to receive opposite potentials.

[0011] As an optional technical solution, the display panel also includes multiple data lines, which are disposed in the display area and electrically connected to the pixel array, and the output terminal of the selection circuit is electrically connected to the multiple data lines.

[0012] As an optional technical solution, the display panel also includes a multiplexer circuit, which is disposed in the peripheral area and electrically connected between the output terminal of the selection circuit and the multiple data lines.

[0013] As an optional technical solution, the control circuit includes a half-source drive circuit.

[0014] As an optional technical solution, the display panel includes a first scan line, a second scan line, a third scan line, and a fourth scan line arranged in parallel for transmitting scan signals. The display panel also includes a first data line and a second data line arranged in parallel for transmitting data signals. The first data line and the second data line intersect the first scan line, the second scan line, the third scan line, and the fourth scan line, respectively. The pixel array includes a plurality of first pixel groups and a plurality of second pixel groups arranged alternately along the extension direction of the first data lines and disposed between the first data lines and the second data lines. Each first pixel group includes... The first pixel unit and the second pixel unit, each second pixel group including a third pixel unit and a fourth pixel unit, the first pixel unit including a first active element, the second pixel unit including a second active element, the third pixel unit including a third active element, the fourth pixel unit including a fourth active element, the first active element being electrically connected to the first scan line and the first data line, the second active element being electrically connected to the second scan line and the first data line, the third active element being electrically connected to the third scan line and the second data line, and the fourth active element being electrically connected to the fourth scan line and the second data line.

[0015] As an optional technical solution, the display panel further includes a third data line for transmitting the data signal and arranged parallel to the second data line. The second data line is disposed between the first data line and the third data line. The pixel array further includes a plurality of third pixel groups and a plurality of fourth pixel groups arranged alternately along the extension direction of the first data line and disposed between the second data line and the third data line. Each third pixel group includes a fifth pixel unit and a sixth pixel unit, and each fourth pixel group includes a seventh pixel unit and an eighth pixel unit. The fifth pixel unit includes a fifth active element, the sixth pixel unit includes a sixth active element, the seventh pixel unit includes a seventh active element, and the eighth pixel unit includes an eighth active element. The fifth active element is electrically connected to the first scan line and the second data line, the sixth active element is electrically connected to the second scan line and the second data line, the seventh active element is electrically connected to the third scan line and the third data line, and the eighth active element is electrically connected to the fourth scan line and the third data line.

[0016] The display panel of the present invention has a selection circuit provided between the control circuit and the pixel array. In this way, the potentials of the first control terminal and the second control terminal in the selection circuit can be determined according to the actual pin positions of the control circuit. The selection circuit selects the input terminal that participates in transmitting data signals based on the potentials of the first control terminal and the second control terminal, so that the display panel can be used with different control circuits and improve the versatility of the display panel.

[0017] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a display panel based on existing technology. Figure 2 This is a schematic diagram of the display panel of the present invention; Figure 3 for Figure 2 A magnified view of a portion of the central display panel; Figure 4A This is a schematic diagram of the electrical conduction of the selection circuit in one embodiment of the present invention; Figure 4B For the corresponding Figure 4A Timing diagram; Figure 5A This is a schematic diagram of the electrical conduction of the selection circuit in another embodiment of the present invention; Figure 5B For the corresponding Figure 5A Timing diagram; Figure 6A This is a partial schematic diagram of the selection circuit of the present invention; Figure 6B for Figure 6A A schematic cross-sectional view along line a. Detailed Implementation

[0019] The following descriptions of the embodiments are with reference to the accompanying drawings, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "up," "down," "front," "back," "left," "right," and "side," are merely directional references to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes only, and not for limiting the invention.

[0020] Please refer to Figures 2 to 5B . Figure 2 This is a schematic diagram of the display panel of the present invention. Figure 3 for Figure 2 A magnified view of a portion of the central display panel. Figure 4A This is a schematic diagram of the electrical conduction of the selection circuit in one embodiment of the present invention. Figure 4B For the corresponding Figure 4A Timing diagram, Figure 5A This is a schematic diagram of the electrical conduction of the selection circuit in another embodiment of the present invention. Figure 5B For the corresponding Figure 5A The timing diagram.

[0021] like Figure 2 and Figure 3As shown, the display panel 10 of the present invention includes a substrate 100, a pixel array 200, a selection circuit 300, and a control circuit 400. The substrate 100 has a display area AA and a peripheral area BA disposed adjacent to each other, the peripheral area BA surrounding at least one side of the display area AA. The pixel array 200 is disposed in the display area AA and includes a plurality of pixel units arranged in an array. The selection circuit 300 is disposed in the peripheral area BA and has an input terminal In, an output terminal Out, a first control terminal Ctrl1, and a second control terminal Ctrl2. The output terminal Out is electrically connected to the pixel array 200. Further, the output terminal Out sequentially includes a first output terminal out1 to an m-th output terminal outm, and the input terminal In sequentially includes a first input terminal in1 to an (m+1)-th input terminal inm+1, where m is a positive integer. In this invention, the number of input terminals in the input terminal In is greater than the number of output terminals in the output terminal Out, including but not limited to a greater than 1. The control circuit 400 is disposed in the peripheral area BA and is electrically connected to the input terminal In of the selection circuit 300 to provide a data signal. In this invention, after the control circuit 400 provides a data signal to the selection circuit 300, the selection circuit 300 transmits the data from its output terminal Out to the pixel array 200 for subsequent display.

[0022] Furthermore, the potentials of the first control terminal Ctrl1 and the second control terminal Ctrl2 are opposite. The display panel 10 determines the potentials of the first control terminal Ctrl1 and the second control terminal Ctrl2 according to the pins of the control circuit 400 and controls one of the first input terminal in1 and the (m+1)th input terminal inm+1 to participate in the transmission of data signals, while the other of the first input terminal in1 and the (m+1)th input terminal inm+1 does not participate in the transmission of data signals.

[0023] The display panel 10 of the present invention has a selection circuit 300 provided between the control circuit 400 and the pixel array 200. In this way, the potentials of the first control terminal Ctrl1 and the second control terminal Ctrl2 can be determined according to the actual pin positions of the control circuit 400. The selection circuit 300 selects the input terminal In to participate in the transmission of data signals according to the potentials of the first control terminal Ctrl1 and the second control terminal Ctrl2, thereby improving the versatility of the display panel 10 for different control circuits 400.

[0024] In practice, the control circuit 400 can be a driver chip (IC), a chip-on-film (COF) film, etc., which may have multiple pins for electrical connection to the input terminal In of the selection circuit 300. The positions of the virtual pins capable of transmitting data signals may differ between driver chips / COF films provided by different manufacturers; for example, the virtual pins capable of transmitting data signals may be located to the left or right of the conventional pins. By configuring the selection circuit 300, this invention allows the display panel 10 to be compatible with control circuits 400 provided by different manufacturers, thus improving the versatility of the display panel 10.

[0025] First embodiment: The virtual pin is located to the left of the conventional pin. like Figure 4A As shown, the control circuit 400 includes a first virtual pin D1 and m-1 first-type pins C. The first virtual pin D1 is located on the first side (e.g., the left side) of the m-1 first-type pins C, and the first-type pins C are, for example, conventional pins. The control circuit 400 has pins for transmitting data signals, including the first virtual pin D1 and the m-1 first-type pins C. Based on this, when manufacturing the display panel 10 (e.g., attaching the control circuit 400 to the display panel 10), the first input terminal in1 to the m-th input terminal inm can be sequentially electrically connected to the first virtual pin D1 and the m-1 first-type pins C.

[0026] like Figure 4B As shown, based on the actual pin configuration of the control circuit 400 at this time, the connection method between the input terminal In and the pins of the control circuit 400 is determined (the first input terminal in1 to the m-th input terminal inm are sequentially electrically connected to the first virtual pin D1 and m-1 first-type pins C, respectively). Therefore, the first control terminal Ctrl1 is maintained at the first potential and the second control terminal Ctrl2 is maintained at the second potential, with the first and second potentials being opposite. In this embodiment, the first potential is high (High), and the second potential is low (Low), ensuring that the first control terminal Ctrl1 is constantly high (High) and the second control terminal Ctrl2 is constantly low (Low). Figure 4A As shown, the selection circuit 300 controls the first input terminals in1 to the m-th input terminals inm, which are electrically connected to the first virtual pin D1 and m-1 first-type pins, to participate in the transmission of data signals. The first input terminals in1 to the m-th input terminals inm correspond one-to-one with the first output terminals out1 to the m-th output terminals outm. The first virtual pin D1 and the m-1 first-type pins C transmit the corresponding data signals to the first output terminals out1 to the m-th output terminals outm via the first input terminals in1 to the m-th input terminals inm, and then transmit them to the pixel array 200. At this time, the (m+1)-th input terminal inm+1 does not participate in the transmission of data signals.

[0027] In this embodiment, the first potential is High and the second potential is Low. However, this is not a limitation. In another embodiment, the first potential is Low and the second potential is High, such that the first control terminal Ctrl1 remains at Low and the second control terminal Ctrl2 remains at High. In this case, the selection circuit 300 controls the first input terminal in1 to the m-th input terminal inm to participate in the transmission of data signals.

[0028] Second embodiment: The virtual pin is located to the right of the conventional pin. like Figure 5A As shown, the control circuit 400 includes m-1 first-type pins C and a second virtual pin D2, with the second virtual pin D2 located on the second side (e.g., the right side) of the m-1 first-type pins C. The control circuit 400 has m-1 first-type pins C and a second virtual pin D2 as pins capable of transmitting data signals. Therefore, when manufacturing a display panel (e.g., attaching the control circuit 400 to the display panel 10), the second input terminal in2 to the (m+1)th input terminal inm+1 can be sequentially and electrically connected to the m-1 first-type pins C and the second virtual pin D2, respectively.

[0029] like Figure 5B As shown, based on the actual pin configuration of the control circuit 400 at this time, the connection method between the input terminal In and the pins of the control circuit 400 is determined (the second input terminal in2 to the (m+1)th input terminal inm+1 are sequentially electrically connected to m-1 first-type pins C and the second virtual pin D2). Therefore, the first control terminal Ctrl1 is maintained at the second potential, and the second control terminal Ctrl2 is maintained at the first potential; the first potential and the second potential are opposite. In this embodiment, the first potential is high, and the second potential is low, so that the first control terminal Ctrl1 is constantly at low potential (Low), and the second control terminal Ctrl2 is constantly at high potential (High). Figure 5A As shown, the selection circuit 300 controls the second input terminals in2 to inm+1, which are electrically connected to m-1 first-type pins and the second virtual pin D2, to participate in the transmission of data signals. The second input terminals in2 to inm+1 correspond one-to-one with the first output terminals out1 to outm. The m-1 first-type pins and the second virtual pin D2 transmit the corresponding data signals to the first output terminals out1 to outm via the second input terminals in2 to inm+1, and then to the pixel array 200. At this time, the first input terminal in1 does not participate in the transmission of data signals.

[0030] In this embodiment, the first potential is High and the second potential is Low. However, this is not a limitation. In another embodiment, the first potential is Low and the second potential is High, such that the first control terminal Ctrl1 remains at High and the second control terminal Ctrl2 remains at Low. In this case, the selection circuit 300 controls the second input terminal in2 to the (m+1)th input terminal inm+1 to participate in the transmission of data signals.

[0031] Third embodiment: Virtual pins are located to the left and right of conventional pins. The control circuit 400 includes a first virtual pin D1, m-1 first-type pins C, and a second virtual pin D2. The first virtual pin D1 and the second virtual pin D2 are located on opposite sides of the m-1 first-type pins C. If both the first virtual pin D1 and the second virtual pin D2 can transmit data signals, the control circuit 400 can connect to the selection circuit 300 in either the first embodiment or the second embodiment. For example, the first input terminal in1 to the m-th input terminal inm are electrically connected to the first virtual pin D1 and the m-1 first-type pins C in sequence, respectively; or, the second input terminal in2 to the (m+1)-th input terminal inm+1 are electrically connected to the m-1 first-type pins C and the second virtual pin D2 in sequence, respectively. After determining the connection method, the potentials of the first control terminal Ctrl1 and the second control terminal Ctrl2 are determined according to the connection method, so that one of the first virtual pin D1 and the second virtual pin D2 participates in transmitting data signals, while the other of the first virtual pin D1 and the second virtual pin D2 does not participate in transmitting data signals. In another embodiment, the first virtual pin D1 and the second virtual pin D2 may both participate in transmitting data signals, etc., and are not limited thereto.

[0032] In this invention, after determining the potentials of the first control terminal Ctrl1 and the second control terminal Ctrl2 of the selection circuit 300 according to the actual pin positions of the control circuit 400, the potentials of the first control terminal Ctrl1 and the second control terminal Ctrl2 will remain constant and will not change with the changes in the display screen / scanning interval, etc.

[0033] The display panel 10 of the present invention determines the potential of the first control terminal Ctrl1 and the second control terminal Ctrl2 in the selection circuit 300 according to the relative position relationship between the first type of pin and the virtual pin used for transmitting data signals in the control circuit 400. The selection circuit 300 selects the input terminal corresponding to the position of the pin for transmitting data signals in the control circuit 400 to participate in transmitting data signals according to the potential of the first control terminal Ctrl1 and the second control terminal Ctrl2, thereby improving the versatility of the display panel 10.

[0034] like Figure 3As shown, the selection circuit 300 includes first switch units 301 to m-th switch units 30m corresponding to the first output terminals out1 to outm. Each switch unit includes a first switch element F1 and a second switch element F2. The control terminal g1 of each first switch element F1 is electrically connected to the first control terminal Ctrl1, and the control terminal g2 of each second switch element F2 is electrically connected to the second control terminal Ctrl2. Specifically, the first terminal a1 of the first switch element F1 in the n-th switch unit 30n is electrically connected to the n-th input terminal inn of the selection circuit 300, the first terminal a2 of the second switch element F2 in the n-th switch unit 30n is electrically connected to the (n+1)-th input terminal inn+1 of the selection circuit 300, and the second terminals b1 of the first switch element F1 and b2 of the second switch element F2 in the n-th switch unit 30n are both electrically connected to the n-th output terminal outn, where 1 ≤ n ≤ m.

[0035] In one embodiment, combined with Figure 4A and Figure 4B The control circuit 400 includes a first virtual pin D1 and m-1 first-type pins C that can participate in transmitting data signals. The first virtual pin D1 is located on the first side (e.g., the left side) of the m-1 first-type pins C. Each first switching element F1 and each second switching element F2 is an N-type thin-film transistor. The first control terminal Ctrl1 is kept at a high potential (High) and the second control terminal Ctrl2 is kept at a low potential (Low), so that all first switching elements F1 are turned on and all second switching elements F2 are turned off. The selection circuit 300 controls the first input terminals in1 to the m-th input terminals inm, which are electrically connected to the first virtual pin D1 and the m-1 first-type pins, to participate in transmitting data signals. At this time, the first input terminals in1 to the m-th input terminals inm correspond one-to-one with the first output terminals out1 to the m-th output terminals outm.

[0036] In another embodiment, combined with Figure 5A and Figure 5BThe control circuit 400 includes m-1 first-type pins C and a second virtual pin D2, with the second virtual pin D2 located on the second side (e.g., the right side) of the m-1 first-type pins C. Each first switching element F1 and each second switching element F2 is an N-type thin-film transistor. The first control terminal Ctrl1 is kept at a low potential (Low), and the second control terminal Ctrl2 is kept at a high potential (High), causing all first switching elements F1 to be completely closed and all second switching elements F2 to be completely open. The selection circuit 300 controls the second input terminals in2 to the (m+1)th input terminals inm+1, which are electrically connected to the m-1 first-type pins and the second virtual pin D2, to participate in data signal transmission. At this time, the second input terminals in2 to the (m+1)th input terminals inm+1 correspond one-to-one with the first output terminals out1 to the mth output terminals outm.

[0037] It should be noted that the foregoing embodiments are described with each first switching element F1 and each second switching element F2 being an N-type thin-film transistor. The control method with each first switching element F1 and each second switching element F2 being a P-type thin-film transistor is similar to the above embodiments and will not be described again.

[0038] In one embodiment, the control circuit 400 further includes a second type of pin (not shown), with the first control terminal Ctrl1 and the second control terminal Ctrl2 electrically connected to the second type of pin to receive different potentials. In this case, the first control terminal Ctrl1 may include a first signal line T1, the second control terminal Ctrl2 may include a second signal line T2, the control terminal g1 of each first switching element F1 is electrically connected to the first signal line T1, the control terminal g2 of each second switching element F2 is electrically connected to the second signal line T2, and the first signal line T1 and the second signal line T2 are electrically connected to the second type of pin to receive corresponding potential signals.

[0039] In this invention, the control circuit 400 includes a half-source driver (HSD) circuit. For example... Figure 2As shown, the display panel 10 includes multiple scan lines arranged in parallel for transmitting scan signals, such as a first scan line G1, a second scan line G2, a third scan line G3, and a fourth scan line G4. The display panel 10 also includes multiple data lines arranged in parallel for transmitting data signals, such as a first data line S1 and a second data line S2. The first data line S1 and the second data line S2 intersect with the first scan line G1, the second scan line G2, the third scan line G3, and the fourth scan line G4, respectively. The pixel array 200 includes multiple first pixel groups and multiple second pixel groups arranged alternately along the extension direction of the first data line S1 and disposed between the first data line S1 and the second data line S2. Each first pixel group... It includes a first pixel unit p1 and a second pixel unit p2. Each second pixel group includes a third pixel unit p3 and a fourth pixel unit p4. The first pixel unit p1 includes a first active element t1, the second pixel unit p2 includes a second active element t2, the third pixel unit p3 includes a third active element t3, and the fourth pixel unit p4 includes a fourth active element t4. The first active element t1 is electrically connected to the first scan line G1 and the first data line S1. The second active element t2 is electrically connected to the second scan line G2 and the first data line S1. The third active element t3 is electrically connected to the third scan line G3 and the second data line S2. The fourth active element t4 is electrically connected to the fourth scan line G4 and the second data line S2.

[0040] Furthermore, such as Figure 2 As shown, the display panel 10 also includes a third data line S3 for transmitting data signals and is arranged parallel to the second data line S2. The second data line S2 is disposed between the first data line S1 and the third data line S3. The pixel array 200 also includes a plurality of third pixel groups and a plurality of fourth pixel groups arranged alternately along the extension direction of the first data line S1 and disposed between the second data line S2 and the third data line S3. Each third pixel group includes a fifth pixel unit p5 and a sixth pixel unit p6, and each fourth pixel group includes a seventh pixel unit p7 and an eighth pixel unit p8. Pixel unit p5 includes a fifth active element t5, sixth pixel unit p6 includes a sixth active element t6, seventh pixel unit p7 includes a seventh active element t7, and eighth pixel unit p8 includes an eighth active element t8. The fifth active element t5 is electrically connected to the first scan line G1 and the second data line S2, the sixth active element t6 is electrically connected to the second scan line G2 and the second data line S2, the seventh active element t7 is electrically connected to the third scan line G3 and the third data line S3, and the eighth active element t8 is electrically connected to the fourth scan line G4 and the third data line S3.

[0041] Taking the scanning period of one frame of the displayed image as an example, In the first scanning interval, the first scan line G1 is at a high potential, the first active element t1 and the fifth active element t5 are turned on, the first data line S1 transmits the corresponding data signal (e.g., a positive potential signal) to the first pixel unit p1, and the second data line S2 transmits the corresponding data signal (e.g., a negative potential signal) to the fifth pixel unit p5.

[0042] In the second scanning interval, the second scanning line G2 is at a high potential, the second active element t2 and the sixth active element t6 are turned on, the first data line S1 transmits the corresponding data signal (e.g., a positive potential signal) to the second pixel unit p2, and the second data line S2 transmits the corresponding data signal (e.g., a negative potential signal) to the sixth pixel unit p6.

[0043] In the third scan interval, the third scan line G3 is at a high potential, the third active element t3 and the seventh active element t7 are turned on, the second data line S2 transmits the corresponding data signal (e.g., negative potential signal) to the third pixel unit p3, and the third data line S3 transmits the corresponding data signal (e.g., positive potential signal) to the seventh pixel unit p7.

[0044] In the fourth scan interval, the fourth scan line G4 is at a high potential, the fourth active element t4 and the eighth active element t8 are turned on, the second data line S2 transmits the corresponding data signal (e.g., a negative potential signal) to the fourth pixel unit p4, and the third data line S3 transmits the corresponding data signal (e.g., a positive potential signal) to the eighth pixel unit p8.

[0045] In actual operation, during the scanning of the next frame of the display screen, the potential signals on each data line can be adjusted. For example, the first data line S1 and the third data line S3 can be changed to transmit negative potential signals, and the second data line S2 can be changed to transmit positive potential signals, so as to further improve the display effect.

[0046] As previously described, the display panel 10 includes multiple data lines, which are disposed in the display area AA and electrically connected to the pixel array 200. The output terminal Out of the selection circuit 300 is electrically connected to the multiple data lines. In one embodiment, the display panel 10 includes first data lines S1 to m-th data lines Sm, which are electrically connected to first output terminals out1 to m-th output terminals outm in a one-to-one correspondence to receive corresponding data signals. In another embodiment, the display panel 10 may further include a multiplexer circuit MUX (not shown), which is disposed in the peripheral area BA and electrically connected between the output terminal Out of the selection circuit 300 and the multiple data lines. In this case, the input terminals of the multiplexer circuit MUX can be electrically connected to the first output terminals out1 to m-th output terminals outm in a one-to-one correspondence.

[0047] Please refer to Figure 6Aand Figure 6B , Figure 6A This is a partial schematic diagram of the selection circuit of the present invention. Figure 6B for Figure 6A A cross-sectional view along line AA'. The display panel 10 of the present invention also has a touch function, comprising a plurality of touch electrodes (not shown) arranged in an array and touch electrode lines (in the form of...). Figure 6A and Figure 6B Taking the touch electrode line TP as an example, one end of each touch electrode line TP is electrically connected to the corresponding touch electrode. In the display area AA, the touch electrode lines TP can be arranged interleaved with each data line, and the other end of each touch electrode line TP can extend from the display area AA to the peripheral area BA and be electrically connected to the control circuit 400 to receive / transmit relevant touch signals. In one embodiment, the control circuit 400 also includes a third type of pin (not labeled), and each touch electrode line TP is electrically connected to the third type of pin to receive / transmit relevant touch signals.

[0048] like Figure 6A As shown, in each switching unit of the selection circuit 300, the first switching element F1 is located between the second switching element F2 and the control circuit 400. In other words, each second switching element F2 is located between each first switching element F1 and the display area AA. Each input terminal in1~inm+1 of the selection circuit 300 can be electrically connected to the corresponding pin in the control circuit 400 via corresponding data signal leads TL1~TLm+1. In actual operation, the data signal leads TL1~TLm+1 can be arranged on the same layer as each input terminal in1~inm+1 and extend from the corresponding input terminal. Furthermore, each data signal lead TL1~TLm+1 and the touch electrode line TP are arranged alternately on the same layer, for example, formed together via a second metal layer or a third metal layer. Thus, each touch electrode line TP is located between two adjacent input terminals (and their corresponding data signal leads), such as... Figure 6A As shown, each touch electrode line TP is located between two adjacent first switching elements F1 and also between two adjacent second switching elements F2. A portion of the data signal lead corresponding to the a-th input terminal ina needs to cross over the corresponding touch electrode line TP to connect to the corresponding second switching element F2, where 2 ≤ a ≤ m. To avoid short-circuiting with the corresponding touch electrode line TP when this portion of the data signal lead crosses over it, the data signal lead corresponding to the a-th input terminal ina is disconnected at the corresponding touch electrode line and electrically connected via a layer-by-layer transfer.

[0049] Reference Figure 4A and Figure 4BWhen the virtual pin (i.e., the first virtual pin D1) in the control circuit 400 that can participate in data signal transmission is located on the first side (e.g., the left side) of the conventional pin (i.e., the first type of pin C), the first output terminal out1 to the m-th output terminal outm correspond one-to-one with the first input terminal in1 to the m-th input terminal inm, respectively. Taking the second input terminal in2 as an example, it corresponds to the second output terminal out2. The corresponding data signal can be directly transmitted to the second input terminal in2 via the pin of the control circuit 400, and then transmitted to the second output terminal out2 via the first switching element F1, and then transmitted to the pixel array 200.

[0050] Reference Figure 5A and Figure 5B When the virtual pin (i.e., the second virtual pin D2) in the control circuit 400 that can participate in data signal transmission is located on the second side (e.g., the right side) of the conventional pin (i.e., the first type of pin C), the first output terminal out1 to the m-th output terminal outm correspond one-to-one with the second input terminal out2 to the (m+1)-th input terminal outm+1, respectively. Taking the second input terminal in2 as an example, it corresponds to the first output terminal out1. After the corresponding data signal is transmitted to the second input terminal in2 via the pin of the control circuit 400, it needs to be transmitted to the first output terminal out1 via the second switching element F2, and then transmitted to the pixel array 200. At this time, the data signal trace TL2 needs to cross from one side of the corresponding touch electrode line TP to the other side to be electrically connected to the corresponding second switching element F2. In order to avoid a short circuit between the output data signal trace TL2 and the corresponding touch electrode line TP which is arranged on the same layer, as follows: Figure 6B As shown, at the corresponding touch electrode line TP, the data signal trace TL2 is disconnected. Simultaneously, a layer transfer method is used to electrically connect the data signal traces TL2 on both sides of the touch electrode line TP. The layer transfer connection structure Co can be a transparent conductive layer, such as ITO, but is not limited thereto. An insulating layer Ins is provided between the layer transfer connection structure Co and the touch electrode line TP to prevent short circuits.

[0051] The display panel of the present invention has a selection circuit provided between the control circuit and the pixel array. In this way, the potentials of the first control terminal and the second control terminal in the selection circuit can be determined according to the actual pin positions of the control circuit. The selection circuit selects the input terminal that participates in transmitting data signals based on the potentials of the first control terminal and the second control terminal, so that the display panel can use different control circuits and improve the versatility of the display panel.

[0052] The detailed description of the preferred embodiments above is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of protection of the present invention by means of the preferred embodiments disclosed above. Rather, the aim is to cover various modifications and equivalent arrangements within the scope of protection of the claims to be made by the present invention. Therefore, the scope of protection of the claims of the present invention should be interpreted in the broadest possible sense based on the foregoing description, so as to cover all possible modifications and equivalent arrangements.

Claims

1. A display panel, characterized in that... include: The substrate has a display area and a peripheral area arranged adjacent to each other; A pixel array is located in this display area; A selection circuit is disposed in the peripheral area. The selection circuit has an input terminal, an output terminal, a first control terminal and a second control terminal. The output terminal is electrically connected to the pixel array. The output terminal sequentially includes a first output terminal to an m-th output terminal. The input terminal sequentially includes a first input terminal to an (m+1)-th input terminal, where m is a positive integer. as well as A control circuit is disposed in the peripheral area and is electrically connected to the input terminal of the selection circuit to provide a data signal; The first control terminal has an opposite potential to the second control terminal. The display panel determines the potential of the first control terminal and the second control terminal according to the pins of the control circuit and controls one of the first input terminal and the (m+1)th input terminal to participate in transmitting the data signal, while the other of the first input terminal and the (m+1)th input terminal does not participate in transmitting the data signal.

2. The display panel according to claim 1, characterized in that, The first control terminal is kept at the first potential and the second control terminal is kept at the second potential. The first potential is opposite to the second potential. The selection circuit controls the first input terminal to the m-th input terminal to participate in the transmission of the data signal, and the m+1-th input terminal does not participate in the transmission of the data signal. At this time, the first input terminal to the m-th input terminal corresponds one-to-one with the first output terminal to the m-th output terminal. or, The second control terminal is kept at the first potential and the first control terminal is kept at the second potential. The first potential is opposite to the second potential. The selection circuit controls the second input terminal to the (m+1)th input terminal to participate in the transmission of the data signal, while the first input terminal does not participate in the transmission of the data signal. At this time, the second input terminal to the (m+1)th input terminal corresponds one-to-one with the first output terminal to the mth output terminal.

3. The display panel of claim 2, wherein, The selection circuit includes a first to a m-th switching unit corresponding to the first to the m-th output terminals. Each switching unit includes a first switch element and a second switch element. The control terminal of each first switch element is electrically connected to the first control terminal, and the control terminal of each second switch element is electrically connected to the second control terminal. In the n-th switching unit, the first terminal of the first switch element is electrically connected to the n-th input terminal of the selection circuit, and the first terminal of the second switch element in the n-th switching unit is electrically connected to the (n+1)-th input terminal of the selection circuit. The second terminals of the first and second switches in the n-th switching unit are both electrically connected to the n-th output terminal, where 1 ≤ n ≤ m.

4. The display panel of claim 3, wherein, The display panel also includes multiple touch electrode lines and multiple touch electrodes arranged in an array. One end of each touch electrode line is electrically connected to the corresponding touch electrode, and the other end extends to the peripheral area and is electrically connected to the control circuit. In the selection circuit, each second switch element is located between each first switch element and the display area. Each input terminal is connected to the control circuit via a corresponding data signal lead. Each touch electrode line and each data signal lead are arranged alternately on the same layer. The data signal lead corresponding to the a-th input terminal is disconnected at the corresponding touch electrode line and achieves its own electrical connection through a layer transfer method, where 2≤a≤m.

5. The display panel of claim 1, wherein, The control circuit includes a first virtual pin and m-1 first-type pins. The first virtual pin is located on the first side of the m-1 first-type pins. The first virtual pin and the m-1 first-type pins are used to transmit the data signal. The first input terminal to the m-th input terminal are electrically connected to the first virtual pin and the m-1 first-type pins in sequence. The display panel determines the potential of the first control terminal and the second control terminal and controls the first input terminal to the m-th input terminal to participate in transmitting the data signal; or... The control circuit includes m-1 first-type pins and a second virtual pin. The second virtual pin is located on the second side of the m-1 first-type pins. The m-1 first-type pins and the second virtual pin are used to transmit the data signal. The second input terminal to the m+1 input terminal are electrically connected to the m-1 first-type pins and the second virtual pin in sequence. The display panel determines the potential of the first control terminal and the second control terminal and controls the second input terminal to the m+1 input terminal to participate in transmitting the data signal.

6. The display panel according to claim 5, characterized in that, The control circuit also includes a second type of pin, and the first control terminal and the second control terminal are electrically connected to the second type of pin to receive opposite potentials.

7. The display panel according to claim 1, characterized in that, The display panel also includes multiple data lines, which are disposed in the display area and electrically connected to the pixel array. The output terminal of the selection circuit is electrically connected to the multiple data lines.

8. The display panel according to claim 7, characterized in that, The display panel also includes a multiplexer circuit located in the peripheral area and electrically connected between the output of the selection circuit and the multiple data lines.

9. The display panel according to claim 1, characterized in that, The control circuit includes half of the source drive circuits.

10. The display panel according to claim 9, characterized in that, The display panel includes a first scan line, a second scan line, a third scan line, and a fourth scan line arranged in parallel for transmitting scan signals. The display panel also includes a first data line and a second data line arranged in parallel for transmitting data signals. The first data line and the second data line intersect the first scan line, the second scan line, the third scan line, and the fourth scan line, respectively. The pixel array includes a plurality of first pixel groups and a plurality of second pixel groups arranged alternately along the extension direction of the first data lines and disposed between the first data lines and the second data lines. Each first pixel group includes a first pixel unit. The first pixel unit includes a first active element, the second pixel unit includes a second active element, the third pixel unit includes a third active element, and the fourth pixel unit includes a fourth active element. The first active element is electrically connected to the first scan line and the first data line, the second active element is electrically connected to the second scan line and the first data line, the third active element is electrically connected to the third scan line and the second data line, and the fourth active element is electrically connected to the fourth scan line and the second data line.

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