Display panel, driving method thereof, and display device

Abstract

The embodiment of the present application discloses a display panel, a driving method thereof and a display device, the display panel comprising: a pixel circuit and a light emitting element; the pixel circuit comprising a data writing module, a driving module and a compensation module; the data writing module is used for selectively providing a data signal for the driving module; the driving module is used for providing a driving current for the light emitting element, and the driving module comprises a driving transistor; the compensation module is used for compensating a threshold voltage of the driving transistor; and a working process of the pixel circuit comprises a bias stage, in the bias stage, the data writing module and the driving module are turned on, and the compensation module is turned off, a data signal is written into a drain of the driving transistor, and used for adjusting a bias state of the driving transistor. In the embodiment of the present application, the bias stage is added, and the voltage of the gate, the source or the drain of the driving transistor is adjusted, so that the threshold voltage drift of the driving transistor caused by a non-bias stage is weakened.

Description

[0001] This application is a divisional application of application number 202011104404.7 filed on October 15, 2020, entitled "Display Panel and Driving Method Thereof and Display Device". Technical Field

[0002] The present invention relates to display technology, and more particularly to a display panel, a driving method thereof, and a display device. Background Technology

[0003] In a display panel, the pixel circuit provides the driving current required for the light-emitting elements of the display panel and controls whether the light-emitting elements enter the light-emitting stage. It is an indispensable component in most self-emissive display panels.

[0004] However, in existing display panels, as the usage time increases, the internal characteristics of the driving transistors in the pixel circuits change slowly, causing the threshold voltage of the driving transistors to drift, thereby affecting the overall characteristics of the driving transistors and consequently affecting display uniformity. Summary of the Invention

[0005] This invention provides a display panel, a driving method thereof, and a display device to improve the threshold voltage drift problem of existing driving transistors.

[0006] One aspect of this invention provides a display panel, comprising:

[0007] Pixel circuits and light-emitting elements;

[0008] The pixel circuit includes a data writing module, a driving module, and a compensation module;

[0009] The data writing module is used to selectively provide data signals to the driving module;

[0010] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor;

[0011] The compensation module is used to compensate the threshold voltage of the driving transistor; wherein,

[0012] The operation of the pixel circuit includes a biasing phase. During the biasing phase, the data writing module and the driving module are turned on, and the compensation module is turned off. The data signal is written from the source of the driving transistor to the drain of the driving transistor to adjust the bias state of the driving transistor.

[0013] Another aspect of the present invention provides a display panel, comprising:

[0014] Pixel circuits and light-emitting elements;

[0015] The pixel circuit includes a data writing module, a driving module, and a compensation module;

[0016] The data writing module is used to selectively provide data signals to the driving module;

[0017] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor;

[0018] The compensation module is used to compensate the threshold voltage of the driving transistor; wherein,

[0019] The operation of the pixel circuit includes a biasing stage. The data writing module is multiplexed as a biasing module. In the data writing stage, the data writing module is used to provide data signals. In the biasing stage, the data writing module is used to provide bias signals.

[0020] During the biasing phase, the data writing module and the driving module are turned on, and the compensation module is turned off. The bias signal is written to the drain of the driving transistor to adjust the bias state of the driving transistor.

[0021] Based on the same inventive concept, embodiments of the present invention also provide a driving method for a display panel, the display panel including pixel circuits and light-emitting elements;

[0022] The pixel circuit includes a data writing module, a driving module, and a compensation module;

[0023] The data writing module is used to selectively provide data signals to the driving module;

[0024] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor;

[0025] The compensation module is used to compensate the threshold voltage of the driving transistor; wherein,

[0026] The method for driving at least one frame of the display panel includes:

[0027] During the biasing phase, the data writing module and the driving module are turned on, and the compensation module is turned off. The data signal is written to the drain of the driving transistor to adjust the bias state of the driving transistor.

[0028] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel described above.

[0029] In this embodiment of the invention, the operation of the pixel circuit includes a biasing stage. During the biasing stage, the data writing module and the driving module are turned on, and the compensation module is turned off. The data signal is written to the drain of the driving transistor through the turned-on data writing module and driving module to adjust the drain potential of the driving transistor, thereby improving the potential difference between the gate potential and the drain potential of the driving transistor. It is known that a pixel circuit includes at least one unbiased stage. When a driving current is generated in the driving transistor, there may be a situation where the gate potential of the driving transistor is greater than the drain potential, causing the IV curve of the driving transistor to shift and the threshold voltage of the driving transistor to drift. During the biasing stage, by adjusting the gate potential and drain potential of the driving transistor, the shift phenomenon of the IV curve of the driving transistor in the unbiased stage can be balanced, the threshold voltage drift phenomenon of the driving transistor can be reduced, and the display uniformity of the display panel can be guaranteed. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, although the drawings described below are some specific embodiments of the present invention, those skilled in the art can extend and extend the basic concepts of the device structure, driving method and manufacturing method disclosed and indicated by various embodiments of the present invention to other structures and drawings. Undoubtedly, these should all be within the scope of the claims of the present invention.

[0031] Figure 1 This is a schematic diagram of the pixel circuit of a display panel provided in an embodiment of the present invention;

[0032] Figure 2 yes Figure 1 One of the schematic diagrams of the bias stage of the pixel circuit shown;

[0033] Figure 3 This is a schematic diagram of the drift of the Id-Vg curve of the driving transistor;

[0034] Figure 4 yes Figure 1 One of the schematic diagrams of the bias stage of the pixel circuit shown;

[0035] Figure 5 This is a schematic diagram of the pixel circuit of another display panel provided in an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of the pixel circuit of another display panel provided in an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of the first operating timing of a pixel circuit;

[0038] Figure 8 This is a schematic diagram of the second operating timing of the pixel circuit;

[0039] Figure 9 This is a schematic diagram of the third operating timing of the pixel circuit;

[0040] Figure 10 This is a schematic diagram of the fourth operating timing of the pixel circuit;

[0041] Figure 11 This is a schematic diagram of the fifth operating timing sequence of the pixel circuit;

[0042] Figure 12 This is a schematic diagram of the sixth operating timing sequence of the pixel circuit;

[0043] Figure 13 This is a schematic diagram of the seventh operating timing sequence of the pixel circuit;

[0044] Figure 14 This is a schematic diagram of the eighth operating timing of the pixel circuit;

[0045] Figure 15 This is a schematic diagram of the ninth operating timing sequence of the pixel circuit;

[0046] Figure 16 This is a schematic diagram of the tenth operating timing sequence of the pixel circuit;

[0047] Figure 17 This is a schematic diagram of the eleventh operating timing sequence of the pixel circuit;

[0048] Figure 18 This is a schematic diagram of the twelfth operating timing sequence of the pixel circuit;

[0049] Figure 19 This is a schematic diagram of the thirteenth operating timing sequence of the pixel circuit;

[0050] Figure 20 This is a schematic diagram of the fourteenth operating timing sequence of the pixel circuit;

[0051] Figure 21 This is a schematic diagram of the pixel circuit of another display panel provided in an embodiment of the present invention;

[0052] Figure 22 This is a schematic diagram of the pixel circuit of another display panel provided in an embodiment of the present invention;

[0053] Figure 23 This is a schematic diagram of a driving method for a display panel provided in an embodiment of the present invention;

[0054] Figure 24 This is a schematic diagram of a display device provided in an embodiment of the present invention;

[0055] Figure 25 This is a schematic diagram of the pixel circuit of a display panel provided in another embodiment of the present invention;

[0056] Figure 26 yes Figure 25 One of the timing diagrams of the pixel circuit shown;

[0057] Figure 27 yes Figure 25 One of the timing diagrams of the pixel circuit shown;

[0058] Figure 28 yes Figure 25 One of the timing diagrams of the pixel circuit shown. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the basic concepts disclosed and indicated in the embodiments of this invention, all other embodiments obtained by those skilled in the art are within the scope of protection of this invention.

[0060] refer to Figure 1 , Figure 1 This is a schematic diagram of a pixel circuit of a display panel provided in an embodiment of the present invention. The display panel provided in this embodiment includes: a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a data writing module 11, a driving module 12, and a compensation module 13; the data writing module 11 is used to selectively provide data signals to the driving module 12; the driving module 12 is used to provide driving current to the light-emitting element 20, and the driving module 12 includes a driving transistor T0; the compensation module 13 is used to compensate the threshold voltage of the driving transistor T0; wherein, the operation process of the pixel circuit 10 includes a biasing stage, in which the data writing module 11 and the driving module 12 are turned on, and the compensation module 13 is turned off, and the data signal is written to the drain of the driving transistor T0 to adjust the bias state of the driving transistor. Figure 2 yes Figure 1 The diagram shows one of the bias stage schematics of the pixel circuit, with the arrow indicating the direction of the signal path.

[0061] It is important to note that Figure 1 The above embodiments only schematically illustrate the key structures and do not include all the structures in which the circuit operates. The complete circuit structure will be gradually shown in the following description of this embodiment.

[0062] In this embodiment, the pixel circuit 10 includes a data writing module 11. The input terminal of the data writing module 11 receives a data signal Vdata, the control terminal of the data writing module 11 receives a scan signal S1, and the output terminal of the data writing module 11 is electrically connected to the input terminal of the driving module 12. The scan signal S1 received by the pixel circuit 10 is a pulse signal. A valid pulse of the scan signal S1 controls the transmission path between the input and output terminals of the data writing module 11 to be turned on, so as to provide the data signal to the driving module 12; an invalid pulse of the scan signal S1 controls the transmission path between the input and output terminals of the data writing module 11 to be turned off. Therefore, under the control of the scan signal S1, the data writing module 11 selectively provides data signals to the driving module 12.

[0063] The pixel circuit 10 includes a driving module 12, the output of which is coupled to the light-emitting element 20. The driving module 12 includes a driving transistor T0, which provides driving current to the light-emitting element 20 when turned on. The source of the driving transistor T0 is electrically connected to the input of the driving module 12, and the drain of the driving transistor T0 is electrically connected to the output of the driving module 12. In this embodiment, the data writing module 11 is connected to the source of the driving transistor T0. In other embodiments, optionally the drain of the driving transistor is electrically connected to the input of the driving module, and the source is electrically connected to the output of the driving module. It is understood that the source and drain of the transistor are not constant but change with the driving state of the transistor.

[0064] The pixel circuit 10 includes a compensation module 13, which compensates for the threshold voltage of the driving transistor T0. The first terminal of the compensation module 13 is electrically connected to the output terminal of the driving module 12, the control terminal of the compensation module 13 receives a scan signal S2, and the second terminal of the compensation module 13 is electrically connected to the control terminal of the driving module 12. The scan signal S2 received by the pixel circuit 10 is a pulse signal. A valid pulse of the scan signal S2 controls the conduction path of the first and second terminals of the compensation module 13 to adjust the voltage between the control terminal and the output terminal of the driving module 12 and compensate for the threshold voltage of the driving transistor T0; an invalid pulse of the scan signal S2 controls the conduction path of the first and second terminals of the compensation module 13 to turn off. Therefore, under the control of the scan signal S2, the compensation module 13 selectively compensates for the threshold voltage of the driving module 12.

[0065] The optional data writing module 11 includes a first transistor T1, the source of which receives a data signal Vdata, and the drain of which is connected to the source of a driving transistor T0. The compensation module 13 includes a second transistor T2, the source of which is connected to the drain of the driving transistor T0, and the drain of which is connected to the gate of the driving transistor T0. The gate of the first transistor T1 receives a scan signal S1, and the gate of the second transistor T2 receives a scan signal S2.

[0066] In the non-biased phases of pixel circuits, such as the light-emitting stage, the gate potential of the driving transistor may be greater than its drain potential. Over time, this setting can lead to ion polarization within the driving transistor, resulting in a built-in electric field and a continuous increase in the threshold voltage of the driving transistor. Figure 3 This is a schematic diagram of the drift of the Id-Vg curve of the driving transistor, as shown below. Figure 3 As shown, the Id-Vg curve shifts, which affects the driving current flowing into the light-emitting element and thus affects the uniformity of the display.

[0067] In this embodiment, a biasing stage is added to the operation of the pixel circuit 10. During the biasing stage, such as... Figure 2 With the data writing module 11 and driving module 12 enabled and the compensation module 13 disabled, the data signal Vdata is written to the source of driving transistor T0 through the enabled data writing module 11, and from the source of driving transistor T0 to the drain of driving transistor T0, thereby adjusting the drain potential of driving transistor T0 and improving the potential difference between the gate and drain potentials of driving transistor T0. In some cases, the gate potential of driving transistor T0 can be made lower than the drain potential of driving transistor T0, reducing the degree of ion polarization inside driving transistor T0 and lowering the threshold voltage of driving transistor T0. The threshold voltage of driving transistor T0 can be adjusted by biasing driving transistor T0.

[0068] Based on this, in some implementations, during the biasing phase, the potential difference between the gate and drain potentials of the driving transistor T0 can be adjusted. This adjustment balances the impact on the internal characteristics of the driving transistor T0 when the gate potential is greater than the drain potential during the unbiased phase. In other words, the decrease in the threshold voltage of the driving transistor T0 during the biasing phase balances the increase in the threshold voltage during the unbiased phase. This ensures that the Id-Vg curve does not shift, thereby guaranteeing the display uniformity of the display panel.

[0069] In this embodiment of the invention, the operation of the pixel circuit includes a biasing stage. During the biasing stage, the data writing module and the driving module are turned on, and the compensation module is turned off. The data signal is written to the drain of the driving transistor through the turned-on data writing module and driving module to adjust the drain potential of the driving transistor, thereby improving the potential difference between the gate potential and the drain potential of the driving transistor. It is known that a pixel circuit includes at least one unbiased stage. When a driving current is generated in the driving transistor, there may be a situation where the gate potential of the driving transistor is greater than the drain potential, causing the IV curve of the driving transistor to shift and the threshold voltage of the driving transistor to drift. During the biasing stage, by adjusting the gate potential and drain potential of the driving transistor, the shift phenomenon of the IV curve of the driving transistor in the unbiased stage can be balanced, the threshold voltage drift phenomenon of the driving transistor can be reduced, and the display uniformity of the display panel can be guaranteed.

[0070] refer to Figure 2 and Figure 4 , Figure 4 yes Figure 1 One of the schematic diagrams of the bias stage of the pixel circuit shown is provided. The optional pixel circuit 10 includes a light-emitting control module 14, which is used to selectively allow the light-emitting element to enter the light-emitting stage. The light-emitting control module 14 includes a first light-emitting control module 141 and a second light-emitting control module 142. The first light-emitting control module 141 is connected between the first power signal terminal PVDD and the source of the driving transistor T0, and the second light-emitting control module 142 is connected between the drain of the driving transistor T0 and the light-emitting element 20. In the bias stage, at least the second light-emitting control module 142 remains off.

[0071] Optionally, the light-emitting control module 14 includes a third transistor T3, which is connected between the driving transistor T0 and the light-emitting element 20; wherein, as shown... Figure 4 As shown, during the biasing phase, at least the third transistor T3 remains off.

[0072] In this embodiment, the gate of the third transistor T3 receives the light emission control signal EM. Under the control of the light emission control signal EM, the third transistor T3 is turned on or off. The operation of the pixel circuit 10 includes a light emission stage. In the light emission stage, the light emission control signal EM outputs an effective pulse to turn on the third transistor T3, and the driving current provided by the driving transistor T0 flows into the light-emitting element 20 to make it emit light. In the non-light emission stage, the light emission control signal EM outputs an invalid pulse to turn off the third transistor T3, and the light-emitting element 20 does not emit light. The non-light emission stage of the pixel circuit 10 includes a bias stage. In the bias stage, the compensation module 13 and the third transistor T3 remain off, and the data signal is written to the drain of the driving transistor T0 to adjust the drain potential of the driving transistor T0, changing the potential difference between the drain potential and the gate potential of the driving transistor T0, thus biasing the driving transistor T0.

[0073] The optional pixel circuit 10 also includes an initialization module 15, which is used to selectively provide an initialization signal Vini to the light-emitting element 20. In some embodiments, the initialization module 15 is not turned on during the bias phase, and in some other embodiments, the initialization module 15 remains on for at least a portion of the time period during the bias phase.

[0074] In this embodiment, the input terminal of the initialization module 15 receives the initialization signal Vini, the output terminal of the initialization module 15 is electrically connected to the light-emitting element 20, and the control terminal of the initialization module 15 receives the scan signal S4. During the initialization phase, the scan signal S4 provides a valid pulse to the pixel circuit 10 to enable the initialization module 15, and the initialization signal Vini is written to the light-emitting element 20 of the pixel circuit 10 for initialization. The initialization signal Vini is typically a negative voltage signal, so during the initialization phase, the anode of the light-emitting element 20 maintains a negative initial voltage. During at least a portion of the bias phase, the initialization module 15 remains on, so the anode of the light-emitting element 20 maintains its initial voltage during the portion of the bias phase.

[0075] During the bias phase, the initialization module 15 is turned on, which ensures that the light-emitting element 20 receives the initialization signal. Because during the bias phase, the data signal is written to the drain of the driving transistor T0. Although T3 is turned off at this time, the transistor may have a certain leakage current. Therefore, if the light-emitting element 20 does not receive the initialization signal, the light-emitting element 20 may be at risk of lighting up during the bias phase. However, by initializing the light-emitting element 20 during the bias phase, it can be further ensured that the light-emitting element does not emit light.

[0076] Figure 5This is a schematic diagram of a pixel circuit for another display panel provided in an embodiment of the present invention. The pixel circuit 10 further includes a reset module 16, which is used to selectively provide a reset signal to the gate of the driving transistor T0. The input terminal of the optional reset module 16 receives a reset signal Vref, the output terminal of the reset module 16 is electrically connected to the gate of the driving transistor T0, and the control terminal of the reset module 16 receives a scan signal S3. During the reset phase, the scan signal S3 provides a valid pulse to the pixel circuit 10 to enable the reset module 16, and the reset signal Vref is written to the gate of the driving transistor T0 for reset. For PMOS type driving transistors, the reset signal Vref is usually a negative voltage signal, such as -7V. During the reset phase, the gate of the driving transistor T0 maintains a negative voltage, facilitating subsequent bias adjustment and data writing.

[0077] Figure 6 This is a schematic diagram of the pixel circuit of another display panel provided in an embodiment of the present invention, such as... Figure 6 As shown, the input terminal of the optional reset module 16 receives the reset signal Vref, and the output terminal of the reset module 16 is electrically connected to the drain of the driving transistor T0. The control terminal of the reset module 16 receives the scan signal S3. During the reset phase, both scan signals S2 and S3 provide valid pulses to the pixel circuit 10 to enable the reset module 16 and the compensation module 13. The reset signal Vref is then written to the gate of the driving transistor T0 through the compensation module 13 for reset. The reset signal Vref is typically a negative voltage signal, such as -7V. During the reset phase, the gate of the driving transistor T0 maintains a negative voltage, facilitating subsequent bias adjustment and data writing.

[0078] For the pixel circuit 10 described in the above embodiment, the optional initialization module 15 includes a fourth transistor T4. The source of the fourth transistor T4 is used to receive the initialization signal Vini, the drain of the fourth transistor T4 is connected to the anode of the light-emitting element 20, and the gate of the fourth transistor T4 is used to receive the scan signal S4.

[0079] Optional reset module 16 includes a fifth transistor T5. For example... Figure 5 As shown, the source of the fifth transistor T5 receives the reset signal Vref, the drain of the fifth transistor T5 is electrically connected to the gate of the driving transistor T0, and the gate of the fifth transistor T5 receives the scan signal S3. Alternatively, as... Figure 6 As shown, the source of the fifth transistor T5 receives the reset signal Vref, the drain of the fifth transistor T5 is electrically connected to the drain of the driving transistor T0, and the gate of the fifth transistor T5 receives the scan signal S3.

[0080] The optional light-emitting control module 14 also includes a sixth transistor T6, which is connected between the driving transistor T0 and the power supply voltage terminal PVDD. During the biasing phase, the third transistor T3 and the sixth transistor T6 remain off. The gate of the sixth transistor T6 receives the light-emitting control signal EM, the source of the sixth transistor T6 receives the PVDD signal, and the drain of the sixth transistor T6 is connected to the source of the driving transistor T0.

[0081] Optionally, T0, T1, T3, T4, and T6 are PMOS transistors using polysilicon as the active layer, while T2 and T5 are NMOS transistors using oxide semiconductor as the active layer. It can be understood that the effective pulse of the scan signal for an NMOS transistor is high, while the effective pulse of the scan signal for a PMOS transistor is low. It should be noted that... Figures 1 to 6 The pixel circuit shown is merely an example, and the structure of the pixel circuit in this embodiment is not limited to this. For example, in other embodiments, the fifth transistor may be a PMOS using polysilicon as the active layer. It is understood that if the structure of the pixel circuit changes, the driving timing will change according to the structural change of the pixel circuit, provided that the driving principle remains unchanged. The following text will mainly focus on... Figure 5 Taking the pixel circuit shown as an example, the working process of the pixel circuit is described.

[0082] In this embodiment, optionally, the width-to-length ratio of the channel region of the NMOS transistor is greater than that of the PMOS transistor. Since the NMOS transistor mainly functions as a switching transistor in this application, it requires rapid response capability. A transistor with a large width-to-length ratio has a shorter channel region, which is beneficial to improving the transistor's response capability.

[0083] Furthermore, in this application, the four scan signals S1, S2, S3, and S4 can be different signals. Under certain specific conditions, such as when the timing meets certain requirements, at least two of the four signals S1, S2, S3, and S4 can also be the same signal. For example, when T4 and T5 are transistors of the same type, such as both being PMOS or both being NMOS, then S3 and S4 can be the same signal. The specific situation depends on the specific circuit structure and timing, and this embodiment does not impose any particular limitations on this.

[0084] For example, based on any of the above embodiments, the optional display panel includes k rows of light-emitting elements; wherein, during the operation of the pixel circuit 10 corresponding to the i-th row of light-emitting elements 20, in the bias phase, the data writing module 11 is turned on, and the data signal written to the drain of the driving transistor T0 is the current data signal on the data signal line connected to the pixel circuit 10; the current data signal is the data signal written by the pixel circuit corresponding to the j-th row of light-emitting elements in the data writing phase;

[0085] Where k≥1, and 1≤i≤k, 1≤j≤k.

[0086] The values ​​of i and j depend on the specific data writing process of the display panel. In one case, the display panel writes data signals line by line, in which case j = i-1 or j = i+1. In another case, the same data writing stage of the display panel involves multiple rows of light-emitting elements 20, such as light-emitting elements from row a to row b. Data signals are written in the same data writing stage, 1 ≤ a ≤ k, 1 ≤ b ≤ k. In this case, the values ​​of j and i can be determined according to the specific situation; i can be equal to j or not equal to j. This embodiment does not impose any special limitations on this. It should be noted that the data signals written in the data writing stage here refer to the data signals written to the gate of the driving transistor T0 during the data writing stage.

[0087] Optionally, in this embodiment, during the biasing stage, the drain voltage of the driving transistor T0 is greater than the gate voltage of the driving transistor T0. Since during the non-biasing stage, such as the light-emitting stage, there may be a situation where the drain voltage of the driving transistor T0 is less than the gate voltage, causing the threshold voltage of the driving transistor T0 to shift. However, during the biasing stage, if the drain voltage of the driving transistor T0 is set to be greater than the gate voltage of the driving transistor T0, the threshold voltage shift phenomenon in the non-biasing stage can be balanced.

[0088] The optional pixel circuit operation also includes at least one non-biased stage; in the biased stage, the gate voltage of the driving transistor is Vg1, the source voltage is Vs1, and the drain voltage is Vd1; in the non-biased stage, the gate voltage of the driving transistor is Vg2, the source voltage is Vs2, and the drain voltage is Vd2; wherein...

[0089] |Vg1-Vd1|<|Vg2-Vd2|

[0090] In this case, by reducing the potential difference between the gate potential and the drain potential of the driving transistor T0, the threshold voltage shift caused by the potential difference between the gate potential and the drain potential of the driving transistor T0 during the non-biased phase can be alleviated.

[0091] In addition, in some embodiments of this example...

[0092] (Vg1-Vs1)×(Vg2-Vs2)<0, or,

[0093] (Vg1-Vd1)×(Vg2-Vd2)<0.

[0094] During the operation of the pixel circuit, if a data signal is written from the source of the driving transistor to the drain of the driving transistor, the gate voltage and the drain voltage of the driving transistor satisfy (Vg1 - Vd1) × (Vg2 - Vd2) < 0. In the non - bias stage, the gate voltage of the driving transistor in the pixel circuit is greater than the drain voltage of the driving transistor, that is, Vg2 > Vd2, then Vg2 - Vd2 > 0. In the bias stage, the data signal is written to the drain of the driving transistor, making the gate voltage of the driving transistor less than the drain voltage of the driving transistor, that is, Vg1 < Vd1, then Vg1 - Vd1 < 0. Then (Vg1 - Vd1) × (Vg2 - Vd2) < 0.

[0095] In other embodiments, during the operation of the optional pixel circuit, if a data signal is written from the drain of the driving transistor to the source of the driving transistor, the gate voltage and the source voltage of the driving transistor satisfy (Vg1 - Vs1) × (Vg2 - Vs2) < 0. In the non - bias stage, the gate voltage of the driving transistor in the pixel circuit is greater than the source voltage of the driving transistor, that is, Vg2 > Vs2, then Vg2 - Vs2 > 0. In the bias stage, the data signal is written to the source of the driving transistor, making the gate voltage of the driving transistor less than the source voltage of the driving transistor, that is, Vg1 < Vs1, then Vg1 - Vs1 < 0. Then (Vg1 - Vs1) × (Vg2 - Vs2) < 0.

[0096] In addition, optionally, in this embodiment, since the time of the non - bias stage such as the light - emitting stage of the display panel is relatively long, and to fully balance the threshold voltage shift in the non - bias stage during the bias stage and avoid spending too much time in the bias stage, it can be set that Vd1 - Vg1 > Vg2 - Vd2 > 0. In this way, Vd1 - Vg1 in the bias stage is large enough, so that the expected bias effect can be achieved in a short time in the bias stage. In other embodiments, if the source and drain of the driving transistor are converted, it can also be set that Vs1 - Vg1 > Vg2 - Vs2 > 0, depending on the specific circuit situation.

[0097] Optionally, in other embodiments of this embodiment, the time length of the bias stage is t1, and the time length of the non - bias stage is t2, where,

[0098] (|Vg1 - Vs1| - |Vg2 - Vs2|) × (t1 - t2) < 0, or,

[0099] (|Vg1 - Vd1| - |Vg2 - Vd2|) × (t1 - t2) < 0.

[0100] In this embodiment, during the bias phase, the data signal is written from the source of the driving transistor to the drain of the driving transistor, making the drain voltage of the driving transistor greater than the gate voltage of the driving transistor, that is, Vg1 - Vd1 < 0. During the non-bias phase, the gate voltage of the driving transistor is greater than the drain voltage of the driving transistor, that is, Vg2 - Vd2 > 0. During the process of biasing the driving transistor, if the bias voltage is large, the bias time can be appropriately reduced; if the bias voltage is small, the bias time can be appropriately extended.

[0101] Based on this, if ∣Vg1 - Vd1∣ - ∣Vg2 - Vd2∣ > 0, it indicates that the bias voltage is large. At this time, the duration of the bias phase can be appropriately reduced, that is, t1 < t2, so as to reduce the deviation of the threshold voltage between the bias phase and the non-bias phase. If ∣Vg1 - Vd1∣ - ∣Vg2 - Vd2∣ < 0, it indicates that the bias voltage is small. At this time, the duration of the bias phase can be appropriately extended, that is, t1 > t2, so as to reduce the deviation of the threshold voltage between the bias phase and the non-bias phase.

[0102] In other embodiments, during the bias phase, the data signal is written from the drain of the driving transistor to the source of the driving transistor. Then, the gate and drain of the driving transistor in the bias phase and the non-bias phase satisfy (∣Vg1 - Vs1∣ - ∣Vg2 - Vs2∣) × (t1 - t2) < 0, which can reduce the threshold voltage deviation in the non-bias phase.

[0103] It should be noted that the bias phase and the non-bias phase in the above embodiments, especially when it comes to the comparison of time lengths, generally refer to the comparison between a continuous and uninterrupted bias phase and a continuous and uninterrupted non-bias phase.

[0104] Optionally, in this embodiment, the time of the bias phase is greater than 5 microseconds. In particular, the time of the bias phase can be greater than 20 microseconds. The inventors of this application have verified that when the time of the bias phase is greater than 5 microseconds, especially greater than 20 microseconds, it can effectively alleviate the phenomenon of threshold voltage shift. When the time of the bias phase is less than 5 microseconds, because the time of the bias phase is too short, the bias state of the driving transistor T0 cannot be adjusted sufficiently, and it cannot play a good role in alleviating the threshold voltage shift.

[0105] Optionally, the non-bias phase is the light-emitting phase of the display panel. Exemplarily, in one light-emitting phase, the source voltage of the driving transistor T0 is 4.6V, the gate voltage is 3V, and the drain voltage is 1V. The gate voltage of the driving transistor is greater than the drain voltage of the driving transistor. By biasing the driving transistor during the bias phase, the threshold voltage shift of the driving transistor during the light-emitting phase can be compensated.

[0106] Reference Figure 7 , Figure 7This is a schematic diagram of the first operating timing of the pixel circuit. It should be noted that the terms "first type" and similar terms used here and there are merely for distinguishing different schematic diagrams and should not be interpreted as implying a sequential relationship between the diagrams. For example... Figure 7 As shown, within one frame of the optional display panel, the operation of the pixel circuit includes a pre-processing stage and an emissive stage; wherein, within at least one frame of the display panel, the pre-processing stage of the pixel circuit includes a biasing stage.

[0107] In this embodiment, the pixel circuit's operation within one frame of the display panel includes a pre-processing stage and a light-emitting stage. In some cases, the pre-processing stage and the light-emitting stage can be performed sequentially. Within at least one frame, the pre-processing stage of the pixel circuit includes a biasing stage. In the biasing stage, a data signal is written from the source of the driving transistor to the drain of the driving transistor, adjusting the potential difference between the gate potential and the drain potential of the driving transistor. In some cases, the drain voltage of the driving transistor can be made greater than the gate voltage of the driving transistor to bias the driving transistor. In the non-biased stage, the gate voltage of the driving transistor is greater than the drain voltage of the driving transistor, causing an increase in the threshold voltage of the driving transistor. Therefore, within at least one frame, the pixel circuit adds a biasing stage. This biasing stage can at least partially balance the increase in the threshold voltage of the driving transistor in the non-biased stage, improving the display uniformity of the display panel.

[0108] like Figure 7 As shown, within one frame of the optional display panel, the operation of the pixel circuit includes a pre-amplification stage and a light-emitting stage; wherein, within at least one frame, the pre-amplification stage of the pixel circuit includes a biasing stage. The optional pre-amplification stage includes a reset stage and a biasing stage; in the reset stage, the gate of the driving transistor receives a reset signal to reset.

[0109] Combination Figure 5 and Figure 6 The pixel circuit 10 shown here has NMOS transistors (5th transistor T5 and 2nd transistor T2) and PMOS transistors (the other transistors are PMOS transistors). Figure 5 As shown, during the reset phase, the scan signal S3 outputs a high-level valid pulse, which turns on the fifth transistor T5. The reset signal Vref is written to the gate of the driving transistor T0, causing the gate of the driving transistor T0 to reset to a negative potential less than 0V. In other embodiments, alternatives may be selected as follows: Figure 6 In the pixel circuit 10 shown, during the reset phase, the scan signal S3 outputs a high-level valid pulse and the scan signal S2 outputs a high-level valid pulse. Then, both the fifth transistor T5 and the second transistor T2 are turned on, and the reset signal Vref is written to the gate of the driving transistor T0, so that the gate of the driving transistor T0 is reset to a negative potential less than 0V.

[0110] During the biasing phase, when the scan signal S1 outputs a low-level valid pulse, the first transistor T1 is turned on. In this embodiment, the second transistor is an oxide semiconductor and an NMOS transistor. When the scan signal S2 outputs a low-level valid pulse, the second transistor T2 is turned off, and the driving transistor T0 is turned on. Then, the data signal is written to the drain of the driving transistor T0, and the drain potential of the driving transistor T0 is adjusted.

[0111] The optional bias phase has a duration of t1, and the reset phase has a duration of t3, where t1 > t3.

[0112] The reset phase is only used to write the reset signal to the gate of the driving transistor, resetting the gate to a negative potential less than 0V. Therefore, the reset phase duration t3 can be relatively short. In the bias phase, the data signal is written to the drain of the driving transistor to adjust the potential difference between the gate and drain potentials, biasing the driving transistor to reduce the threshold voltage drift during the light-emitting phase. Because the non-biased phases, such as the light-emitting phase, are relatively long, the bias phase duration t1 is longer to sufficiently reduce the threshold voltage drift during the non-biased phases. Therefore, t1 is set to > t3.

[0113] Optional, such as Figure 7 As shown, at the end of the reset phase, the gate of the driving transistor is disconnected from the reset signal. Simultaneously, the data writing module is activated, and the pixel circuit enters the bias phase. In this embodiment, the data writing module can be activated to enter the bias phase at the end of the pixel circuit's reset phase, thus ensuring that the pre-processing phase of the pixel circuit is shortened as much as possible, thereby reducing the duration of a single frame and contributing to high-frequency display.

[0114] refer to Figure 8 , Figure 8 This is a schematic diagram of the second type of operating timing for a pixel circuit, as shown below. Figure 8 As shown, between the end of the optional reset phase and the start of the bias phase, the pre-phase also includes a first interval phase. During the first interval phase, the gate of the driving transistor is disconnected from the reset signal, and the data writing module remains off. In this embodiment, during the first interval phase, the scan signal S3 transitions from a high level to a low level, the fifth transistor T5 is turned off, thus disconnecting the gate of the driving transistor from the reset signal, and the data writing module remains off, allowing the driving transistor to have a stabilization period. At the end of the first interval phase, the data writing module is turned on, and the pixel circuit enters the bias phase. By stabilizing the driving transistor through the first interval phase after the reset phase before entering the bias phase, the stability of the pixel circuit can be improved.

[0115] The optional bias phase duration is t1, the reset phase duration is t3, and the first interval phase duration is t4, where t1 > t4 or t3 > t4. It can be understood that the reset phase is only used to reset the gate voltage of the driving transistor, and the first interval phase is used to stabilize the driving transistor. Therefore, the reset phase duration t3 and the first interval phase duration t4 only need to have one response time length, without needing to be too long. Therefore, t1 > t4 or t3 > t4 is set.

[0116] refer to Figure 9 , Figure 9 This is a schematic diagram of the third operating timing of the pixel circuit, as shown below. Figure 9 As shown, the time periods of the optional reset phase and the bias phase at least partially overlap.

[0117] for Figure 5 The pixel circuit shown has a reset module 16 directly connected to the gate of the driving transistor. Data signals are written to the drain of the driving transistor during the bias phase. Therefore, when the second transistor T2 is off, the operations of the reset and bias phases do not affect each other. Based on this, the time periods of the optional reset and bias phases can at least partially overlap. By performing the reset phase concurrently with the bias phase, the potential of the drain of the driving transistor T0 is adjusted via the data signal, and the potential of the gate of the driving transistor T0 is adjusted via the reset signal, thereby helping to improve the bias effect.

[0118] During the reset phase, the second transistor T2 is turned off and the fifth transistor T5 is turned on, so the reset signal Vref is written to the gate of the driving transistor T0. During the overlap of the bias and reset phases, the second transistor T2 remains off and the first transistor T1 is on, so the data signal Vdata is written to the drain of the driving transistor T0. Simultaneously, the fifth transistor T5 remains on, so the reset signal Vref continues to be written to the gate of the driving transistor T0, stabilizing the gate voltage of the driving transistor T0. During the non-overlapping phases of the bias and reset phases, the fifth transistor T5 is turned off and the first transistor T1 is on, so the data signal Vdata is written to the drain of the driving transistor T0.

[0119] During the bias phase, if the gate of the driving transistor T0 receives a low-level reset signal, and at the same time, the data signal Vdata is written to the drain of the driving transistor T0, this helps to adjust the gate potential and drain potential from both aspects, thereby better mitigating the threshold voltage offset caused by the gate potential being greater than the drain potential during the non-bias phase.

[0120] like Figure 9As shown, alternatively, the gate of the driving transistor can be disconnected from the reset signal before the end of the bias phase, after which the bias phase ends. In this embodiment, a portion of the bias phase overlaps with the reset phase, allowing the reset signal to be continuously written to the gate of the driving transistor, thus ensuring the gate of the driving transistor stably holds the reset signal and improving the bias effect. Before the end of the bias phase, the fifth transistor T5 is turned off, disconnecting the gate of the driving transistor from the reset signal, after which the bias phase ends. This ensures that the drain of the driving transistor T0 continues to receive data signals after the reset phase ends, guaranteeing the bias effect of the driving transistor T0.

[0121] like Figure 9 As shown, the initialization module is also turned on during the bias phase, ensuring that the initialization module continuously provides an initialization signal to the light-emitting element 20 during the bias phase, ensuring that the light-emitting element is in a non-light-emitting state.

[0122] refer to Figure 10 , Figure 10 This is a schematic diagram of the fourth operating timing of the pixel circuit, as shown below. Figure 10 As shown, optionally during the bias phase, the gate of the driving transistor retains a reset signal. For Figure 5 In the pixel circuit shown, during the biasing phase, the second transistor T2 remains off, the first transistor T1 is on, and the fifth transistor T5 remains on. The data signal Vdata is written to the drain of the driving transistor T0, while the reset signal Vref is continuously written to the gate of the driving transistor T0. This stabilizes the gate voltage of the driving transistor T0 during the biasing phase. Furthermore, the overlap between the reset and biasing phases shortens the pre-processing time of the pixel circuit, which is beneficial for achieving high-frequency displays. Moreover, performing the reset phase concurrently with the biasing phase allows for the adjustment of the drain potential of the driving transistor T0 via the data signal and the gate potential via the reset signal, thereby improving the biasing effect.

[0123] like Figure 10 As shown, alternatively, the gate of the driving transistor can be disconnected from the reset signal at the end of the bias phase. In this embodiment, the entire time period of the bias phase overlaps with the reset phase. The start time of the reset phase is earlier than or the same as the start time of the bias phase, and the end time of the reset phase is later than or the same as the end time of the bias phase. For example, in some embodiments, the gate of the driving transistor T0 is disconnected from the reset signal after the end of the bias phase. As described above, the reset signal is continuously written to the gate of the driving transistor during both the reset and bias phases, ensuring the stability of the gate voltage of the driving transistor before the data writing phase and improving the bias effect.

[0124] refer to Figure 11 , Figure 11This is a schematic diagram of the fifth operating timing sequence of the pixel circuit, as shown below. Figure 11 As shown, the optional reset phase includes a first reset phase and a second reset phase. In the first reset phase, which does not overlap with the bias phase, the gate of the driving transistor receives a first reset signal. During at least a portion of the bias phase, the gate of the driving transistor receives a second reset signal, and the bias phase and the second reset phase at least partially overlap. The first reset phase can be used to reset the gate potential of the driving transistor, making its gate potential lower than 0V. The second reset phase can be used to stabilize the gate potential of the driving transistor during the bias phase, realizing bias adjustment of the driving transistor. A portion of the optional bias phase overlaps with the second reset phase. In other embodiments, the entire optional bias phase may overlap with the second reset phase.

[0125] Optionally, the first reset signal and the second reset signal may have the same potential. In other embodiments, the first reset signal and the second reset signal may have different potentials. In some optional embodiments, the first reset signal needs to pull down the gate potential of the driving transistor, therefore the first reset signal is less than 0V. The second reset signal is used to stabilize the gate potential of the driving transistor during the biasing phase to improve the biasing effect. Based on this, the second reset signal can be the same as or different from the first reset signal. Those skilled in the art can flexibly design pixel circuits according to different design requirements.

[0126] Optionally, the absolute value of the potential of the first reset signal is greater than the absolute value of the potential of the second reset signal; the driving transistor is a PMOS transistor, and the potential of the first reset signal is lower than the potential of the second reset signal; or, the driving transistor is an NMOS transistor, and the potential of the first reset signal is higher than the potential of the second reset signal. Optionally, if the absolute value of the potential of the first reset signal is greater than the absolute value of the potential of the second reset signal, then, while the second reset signal plays a biasing role during the biasing phase, using a second reset signal with a lower absolute value can reduce the power consumption of the pixel circuit.

[0127] In another embodiment, optionally, the absolute value of the potential of the first reset signal is less than the absolute value of the potential of the second reset signal; the driving transistor is a PMOS transistor, and the potential of the second reset signal is lower than the potential of the first reset signal; or, the driving transistor is an NMOS transistor, and the potential of the second reset signal is higher than the potential of the first reset signal. Optionally, the absolute value of the potential of the first reset signal is less than the absolute value of the potential of the second reset signal. In specific cases of the display panel, such as high-frequency driving, during the reset phase, the level of the first reset signal is a relatively small negative potential, which can shorten the data writing phase time, thereby helping to achieve high-frequency driving.

[0128] refer to Figure 12 , Figure 12 This is a schematic diagram of the sixth operating timing sequence of the pixel circuit, as shown below. Figure 12 As shown, during the biasing phase, the second reset phase is performed at least twice, and the gate of the driving transistor is disconnected from the reset signal between adjacent second reset phases. In this embodiment, multiple second reset phases can be designed during the biasing phase, and each second reset phase can reset the gate potential of the driving transistor, which facilitates the bias adjustment of the driving transistor and further improves the biasing effect.

[0129] like Figure 7 As shown, within one frame of the optional display panel, the pixel circuit's operation includes a pre-amplification stage and a light-emitting stage; wherein, within at least one frame, the pre-amplification stage of the pixel circuit includes a biasing stage. The optional pre-amplification stage sequentially includes a biasing stage and a data writing stage; in the data writing stage, the data writing module, the driving module, and the compensation module are all turned on, and the data signal is written to the gate of the driving transistor.

[0130] In this embodiment, during the data writing stage, the scan signal S1 outputs a valid pulse signal to enable the data writing module and the driving module, and the scan signal S2 outputs a valid pulse signal to enable the compensation module. Then, the data signal is written to the control terminal of the driving module, i.e., the gate of the driving transistor, through the enabled data writing module, driving module, and compensation module.

[0131] The optional bias phase has a duration of t1, and the data writing phase has a duration of t5, where t1 > t5. It can be understood that the data writing phase is only used to write the data signal to the gate of the driving transistor, so the response time is sufficient. In the bias phase, the data signal is written to the drain of the driving transistor. The biased driving transistor is used to reduce the threshold voltage drift of the driving transistor during the light emission phase. Since the light emission phase is relatively long, the bias phase duration t1 is also relatively long to sufficiently reduce the threshold voltage drift during the unbiased phase. Therefore, t1 > t5 is set.

[0132] like Figure 7 As shown, the data writing module can be kept on during the time period from the bias phase to the data writing phase. In this embodiment, during the time period from the bias phase to the data writing phase, the scan signal S1 outputs a valid pulse signal to keep the data writing module on, and the driving transistor is also kept on. During the bias phase, the compensation module is off, and the data signal can be written to the drain of the driving transistor; during the data writing phase, the scan signal S2 outputs a valid pulse signal to turn on the compensation module, and the data signal can be written to the gate of the driving transistor.

[0133] refer to Figure 13 , Figure 13This is a schematic diagram of the seventh operating timing of the pixel circuit, as shown below. Figure 13 As shown, from the end of the optional bias phase to the start of the data writing phase, the pixel circuit includes a second interval phase, during which the data writing module is turned off. In this embodiment, during the second interval phase, when the scan signal S1 transitions from a low level to a high level, the data writing module is turned off, and the drain of the driving transistor is disconnected from the data signal, allowing the driving transistor to have a stabilization period. At the end of the second interval phase, when the scan signal S1 transitions from a high level to a low level, the data writing module is turned on, and the pixel circuit enters the data writing phase. By stabilizing the driving transistor through the second interval phase after the bias phase ends, the stability of the pixel circuit can be improved before entering the data writing phase.

[0134] The optional bias phase has a duration of t1, the data writing phase has a duration of t5, and the second interval phase has a duration of t6, where t1 > t6 or t5 > t6. It can be understood that the data writing phase is only used to write the data signal to the gate of the driving transistor, and the second interval phase is a transition phase used to stabilize the driving transistor. Therefore, the duration t5 of the data writing phase and the duration t6 of the second interval phase can have only one reaction time length, without needing to be too long. Therefore, t1 > t6 or t5 > t6 is set.

[0135] like Figure 7 As shown, the optional pre-stage includes a reset stage, a bias stage, and a data writing stage in sequence; in the reset stage, the gate of the driving transistor receives a reset signal to be reset; in the data writing stage, the data writing module, the driving module, and the compensation module are all turned on, and the data signal is written to the gate of the driving transistor.

[0136] In this embodiment, during the pre-processing stage of the pixel circuit, the gate of the driving transistor is first reset, causing the gate voltage of the driving transistor to be pulled down to a negative voltage below 0V, facilitating subsequent biasing of the driving transistor. Next, the driving transistor is biased, and the data signal is written to the drain of the driving transistor, reducing the threshold voltage drift of the driving transistor caused by the non-biasing stage. Finally, in the data writing stage, the data writing module, driving module, and compensation module are all activated, and the data signal is written to the gate of the driving transistor.

[0137] The optional bias phase duration is t1, the reset phase duration is t3, and the data write phase duration is t4, where t1 > t3 and t4. Within one frame, the non-bias phase causes threshold voltage drift in the driving transistor, and since the non-bias phase is relatively long, the bias phase duration is set to be longer to reduce threshold voltage drift in the non-bias phase. The data write phase is only used to write data signals to the gate of the driving transistor, so the data write phase duration is set to be shorter. The reset phase is only used to write reset signals to the gate of the driving transistor, so the reset phase duration is set to be shorter. Based on this, t1 > t3 and t4 are set.

[0138] refer to Figure 14 , Figure 14 This is a schematic diagram of the eighth working timing of the pixel circuit. For example, based on any of the above embodiments, the optional bias stage includes m sub-bias stages performed sequentially, where m ≥ 1; among the m sub-bias stages, the interval between two adjacent sub-bias stages is the third interval stage, in which the data writing module is turned off.

[0139] like Figure 14 The optional bias stage includes at least two sequentially performed sub-bias stages, with a third interval stage between adjacent sub-bias stages. During the sub-bias stage, the data writing module is enabled; during the third interval stage, the data writing module is disabled. Specifically, during the sub-bias stage, the scan signal S1 outputs a valid pulse signal, enabling the data writing module. The data signal is then sequentially written to the drain of the driving transistor through the data writing module and the driving module, thus biasing the driving transistor. During the third interval stage, the scan signal S1 outputs an invalid pulse signal, disabling the data writing module and disconnecting the data signal from the drain of the driving transistor. Since the bias stage includes multiple sub-bias stages, each sub-bias stage can reduce the threshold voltage drift of the driving transistor in the non-bias stage. Through multiple sub-bias stages, the threshold voltage drift of the driving transistor caused by the non-bias stage can be sufficiently reduced, further improving the biasing effect.

[0140] In other embodiments, alternatives may also be selected, such as Figure 7 The bias phase shown includes a sub-bias phase, namely the bias phase, during which the data writing module is always open.

[0141] refer to Figure 15 , Figure 15 This is a schematic diagram of the ninth operating timing of the pixel circuit, as shown below. Figure 15As shown, the optional bias stage includes at least two third interval stages, wherein the durations of the at least two third interval stages are not equal. The duration of the optional third interval stage increases or decreases sequentially with the m sub-bias stages. The duration of at least one optional third interval stage may be shorter than the duration of at least one sub-bias stage. The third interval stage is a transition stage between sub-bias stages; therefore, its duration can be shorter than the duration of the sub-bias stages. Specifically, the duration of any third interval stage is shorter than the duration of any sub-bias stage. It is understood that the durations of multiple third interval stages can be the same or different, or the durations of multiple third interval stages may satisfy rules such as increasing or decreasing. In this embodiment of the invention, the bias stages of the pixel circuit are flexibly designed according to the bias requirements of the pixel circuit under different conditions, and are not limited thereto.

[0142] refer to Figure 16 , Figure 16 This is a schematic diagram of the tenth operating timing sequence of the pixel circuit, as shown below. Figure 16 As shown, among the selectable m sub-biasing stages, at least two sub-biasing stages have unequal durations. The duration of the first selectable sub-biasing stage may be longer than the durations of the other sub-biasing stages. The duration of each selectable sub-biasing stage may decrease sequentially with each of the m sub-biasing stages. It is understood that the durations of multiple sub-biasing stages can be the same or different, or the durations of multiple sub-biasing stages may follow increasing or decreasing rules. In this embodiment of the invention, the biasing stages of the pixel circuit are flexibly designed according to the biasing requirements of the pixel circuit under different circumstances, and are not limited to this.

[0143] When the duration of the first sub-biasing stage is longer than that of other sub-biasing stages, biasing the driving transistor in the first sub-biasing stage can effectively reduce the threshold voltage drift of the driving transistor in the non-biasing stage. Subsequent sub-biasing stages with shorter durations can supplement the bias of the driving transistor, and the bias can be dynamically adjusted according to the bias situation. Thus, through multiple sub-biasing stages, the threshold voltage drift of the driving transistor in the non-biasing stage can be sufficiently reduced, thereby ensuring that the duration of the biasing stage is not too long.

[0144] Optional, combined Figure 16 and Figure 13 The duration of at least one third interval phase is not equal to the duration of the second interval phase. Since the third interval phase is the interval between any two adjacent sub-bias phases, and the second interval phase is the time interval between the bias phase and the data writing phase, the durations of the second and third interval phases can be flexibly set depending on the specific circumstances. In some implementations, the duration of the second interval phase is longer than the duration of the third interval phase. In other implementations, the duration of the second interval phase may be shorter than the duration of the third interval phase.

[0145] For example, based on any of the above embodiments, one data write cycle of the optional display panel includes S frames of refresh, including data write frames and hold frames, where S > 0. The data write frame includes a data write phase, in which the data write module writes a data signal to the gate of the driving transistor. The hold frame does not include a data write phase. At least the data write frame includes a bias phase. During the data write frame, the pixel circuit writes new display data; during the hold frame, the pixel circuit refreshes normally but retains the display data of the previous frame and does not write new display data. During the data write frame's duration, in the bias phase, the data write module and the driving module are turned on, and the compensation module is turned off. The data signal is written from the source of the driving transistor to the drain of the driving transistor to bias the voltage between the gate and drain of the driving transistor.

[0146] refer to Figure 17 , Figure 17 This is a schematic diagram of the eleventh operating timing of the pixel circuit. In this embodiment, at least one data frame and at least one hold frame may include a bias phase, and the duration of the bias phase within the at least one hold frame is longer than the duration of the bias phase within the data writing frame. During the hold frame's display time, in the bias phase, the data writing module and the driving module are turned on, and the compensation module is turned off. The data signal is written from the source of the driving transistor to the drain of the driving transistor to bias the voltage between the gate and drain of the driving transistor. The hold frame displays the previous frame and does not include the data writing phase, allowing for a longer bias adjustment period. The data writing frame displays the new frame, thus ensuring its normal light-emitting phase duration. Based on this, the duration of the bias phase within the at least one hold frame may be longer than the duration of the bias phase within the data writing frame, achieving a better bias effect while ensuring display quality.

[0147] refer to Figure 18 , Figure 18 This is a schematic diagram of the twelfth operating timing of the pixel circuit. The optional display panel includes at least two data write frames, wherein the bias phase durations of the at least two data write frames are different. The optional display panel includes a first data write frame and a second data write frame, with n second data write frames between any two adjacent first data write frames, where n≥1; the bias phase duration in the first data write frame is t7, and the bias phase duration in the second data write frame is t8, where t7>t8≥0.

[0148] The display panel includes multiple second data write frames. In each second data write frame, the bias phase has a duration of t8. During this phase, the gate and drain voltages of the driving transistor are biased, reducing the threshold voltage drift of the driving transistor. In practical applications, the bias phase in a second data write frame cannot reduce the threshold voltage drift of the driving transistor to zero. Therefore, after displaying multiple second data write frames, the accumulated drift over time will still cause changes in the internal characteristics of the driving transistor. Based on this, the bias phase in the first data write frame has a duration of t7. By increasing the duration of the bias phase in this frame, the accumulated threshold voltage drift of the driving transistor by the time the next frame is reduced, improving the bias effect and thus improving display uniformity.

[0149] In some implementations, the second data write frame may not include the bias phase, i.e., t8 = 0. In this case, it is not necessary to perform the bias phase in every data write frame. The bias phase can be set only in the first data write frame, thereby simplifying the driving process of the display panel.

[0150] refer to Figure 19 , Figure 19 This is a schematic diagram of the thirteenth operating timing of the pixel circuit. Alternatively, a data write cycle of the display panel may include S frames of screen refresh, including data write frames and hold frames, where S > 0. At least one hold frame includes a bias phase. Within the hold frame, the pre-processing phase sequentially includes a reset phase and a bias phase. In the reset phase, the gate of the driving transistor receives a reset signal to reset. There is no data write phase between the bias phase and the light-emitting phase. In this embodiment, during the hold frame, the pixel circuit refreshes normally but retains the display data of the previous frame. Since the hold frame does not include a data write phase, it displays the previous frame's display image. During the hold frame's duration, in the bias phase, the data signal of the previous frame is written from the source of the driving transistor to the drain of the driving transistor to bias the voltage between the gate and drain of the driving transistor. After this bias phase ends, the hold frame directly enters the light-emitting phase to display the image. This shortens the duration of the hold frame's pre-processing phase, thereby shortening the working time of the hold frame.

[0151] refer to Figure 20 , Figure 20This is a schematic diagram of the fourteenth operating timing of the pixel circuit. Alternatively, a data write cycle of the display panel may include S frames of screen refresh, including data write frames and hold frames, where S > 0. At least one hold frame includes a bias phase. Within the hold frame, the pre-set phase includes a reset phase and a bias phase. During the reset phase, the gate of the driving transistor receives a reset signal to reset. The reset phase and the bias phase at least partially overlap in time. In this embodiment, the reset phase and the bias phase at least partially overlap within the hold frame, which can further shorten the duration of the pre-set phase of the hold frame. Moreover, performing the reset phase simultaneously with the bias phase helps improve the bias effect by adjusting the potential of the drain of the driving transistor T0 through the data signal and the potential of the gate of the driving transistor T0 through the reset signal.

[0152] It should be noted that in this embodiment, only the pre-processing stage of the data write frame may include the bias stage, while the pre-processing stage of the hold frame may not include the bias stage. In this case, if the bias problem can be solved using only the data write frame, then there is no need to set the bias stage in the hold frame. Alternatively, only the pre-processing stage of the hold frame may include the bias stage, while the pre-processing stage of the data write frame may not include the bias stage. Since the data write frame also undertakes the work of the reset stage and the data write stage, if the hold frame can fully undertake the work of the bias stage, then there is no need to set the bias stage in the data write frame, thereby simplifying the timing of the data write frame.

[0153] Additionally, it should be noted that the above figures illustrate examples where the initialization phase and reset or bias phase of the light-emitting element at least partially overlap. However, this embodiment is not limited to this. In some other embodiments, the initialization phase may not overlap with the bias phase, or the initialization phase may be performed simultaneously throughout the entire bias phase, or the initialization phase may continue even after the bias phase ends. All of these solutions are acceptable. The design can be flexibly adapted to the specific circuit conditions.

[0154] Another aspect of this embodiment provides a display panel, wherein, reference Figure 21 , Figure 21This is a schematic diagram of a pixel circuit for another display panel provided in an embodiment of the present invention. The display panel includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a data writing module 11, a driving module 12, and a compensation module 13. The data writing module 11 is used to selectively provide data signals to the driving module 12. The driving module 12 is used to provide driving current to the light-emitting element 20 and includes a driving transistor T0. The compensation module 13 is used to compensate the threshold voltage of the driving transistor T0. The operation of the pixel circuit 10 includes a biasing stage. The data writing module 11 is multiplexed as a biasing module. In the data writing stage, the data writing module 11 is used to provide a data signal Vdata. In the biasing stage, the data writing module is used to provide a bias signal Vbias. In the biasing stage, the data writing module 11 and the driving module 12 are turned on, and the compensation module 13 is turned off. The bias signal Vbias is written to the drain of the driving transistor to adjust the bias state of the driving transistor.

[0155] Here, the bias signal Vbias can be the data signal Vdata provided on the data signal line connected to the pixel circuit 10, or it can be an additional bias signal provided by the driver chip. As long as the bias signal can be written to the drain of the driver transistor and adjust the bias state of the driver transistor when the data writing module and the driver module are turned on and the compensation module is turned off, it is within the protection scope of this embodiment.

[0156] refer to Figure 22 , Figure 22 This is a schematic diagram of a pixel circuit for another display panel provided in an embodiment of the present invention. In some embodiments, the data writing module may include a data writing transistor T1 and a bias transistor T8. The data writing transistor T1 is connected to the data signal input terminal for transmitting the data signal Vdata, and the bias transistor T8 is connected to the bias signal input terminal for transmitting the bias signal Vbias. The bias transistor T8 is connected to the bias control signal ST through its control terminal to control the switching on and off of the bias transistor.

[0157] Optionally, during the biasing phase, the potential of the bias signal Vbias is greater than the potential of the gate of the driving transistor T0, thereby raising the potential of the drain of the driving transistor T0 and alleviating the threshold voltage shift caused by the potential difference between the gate potential and the drain potential of the driving transistor T0.

[0158] It is important to note that Figure 21 and Figure 22 The diagram only schematically illustrates the key structures in the above embodiments and does not necessarily include all the structures in which the circuit operates.

[0159] In the driving process of other implementation methods, the driving method can refer to the driving method in any of the foregoing implementation methods, only the data signal in the bias stage needs to be replaced with the bias signal, and all of these should be understood as being within the protection scope of this embodiment. Based on this, it can be combined with... Figure 22 and Figure 5 When the bias transistor T8 and the fifth transistor T5 are the same type of transistor, such as both being PMOS or NMOS transistors, the bias control signal ST can be the same signal as the control signal S3 of the reset module; when the bias transistor T8 and the fourth transistor S4 are the same type of transistor, such as both being PMOS or NMOS transistors, the bias control signal ST can be the same signal as the control signal S4 of the initialization module.

[0160] Based on the same inventive concept, this embodiment of the invention also provides a driving method for a display panel. In this embodiment, the display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a data writing module, a driving module, and a compensation module; the data writing module is used to selectively provide data signals to the driving module; the driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor; the compensation module is used to compensate for the threshold voltage deviation of the driving transistor; wherein,

[0161] refer to Figure 23 , Figure 23 This is a schematic diagram of a driving method for a display panel provided in an embodiment of the present invention, as shown below. Figure 23 As shown, the method for driving at least one frame of the display panel includes:

[0162] During the biasing phase, the data writing module and the driving module are turned on, and the compensation module is turned off. The data signal is written from the source of the driving transistor to the drain of the driving transistor to adjust the bias state of the driving transistor.

[0163] Optional, such as Figure 23 As shown, the method for driving at least one frame of the display panel further includes:

[0164] During the reset phase, the gate of the driving transistor receives a reset signal to be reset.

[0165] In other implementation methods, the driving process used in any of the foregoing implementations can be referred to. This embodiment will not repeat the same content, but it should be understood that it is within the protection scope of the driving method in this embodiment.

[0166] In this embodiment of the invention, the operation of the pixel circuit includes a biasing stage. During the biasing stage, the data writing module and the driving module are turned on, and the compensation module is turned off. The data signal is written to the drain of the driving transistor through the turned-on data writing module and driving module to adjust the drain potential of the driving transistor, thereby improving the potential difference between the gate potential and the drain potential of the driving transistor. It is known that a pixel circuit includes at least one unbiased stage. When a driving current is generated in the driving transistor, there may be a situation where the gate potential of the driving transistor is greater than the drain potential, causing the IV curve of the driving transistor to shift and the threshold voltage of the driving transistor to drift. During the biasing stage, by adjusting the gate potential and drain potential of the driving transistor, the shift phenomenon of the IV curve of the driving transistor in the unbiased stage can be balanced, the threshold voltage drift phenomenon of the driving transistor can be reduced, and the display uniformity of the display panel can be guaranteed.

[0167] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel as described in any of the above embodiments. Optionally, the display panel can be an organic light-emitting display panel or a micro LED display panel.

[0168] refer to Figure 24 , Figure 24 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 24 As shown, this display device can be optionally applied to electronic devices 100 such as smartphones and tablets. It is understood that the above embodiments only provide partial examples of the pixel circuit structure and the driving method of the pixel circuit; the display panel also includes other structures, which will not be described in detail here.

[0169] refer to Figure 25 , Figure 25This is a schematic diagram of a pixel circuit for a display panel according to another embodiment of the present invention. The display panel includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a data writing module 11, a driving module 12, a compensation module 13, and a reset module 16. The data writing module 11 is connected between a data signal input terminal and the source of a driving transistor T0, and is used to provide a data signal Vdata to the driving module 12. The driving module 12 is used to provide a driving current to the light-emitting element 20, and includes a driving transistor T0. The compensation module 13 is connected between the gate and drain of the driving transistor T0, and is used to compensate for the threshold voltage of the driving transistor T0. Voltage; Reset module 16 is connected between the reset signal terminal and the drain of driving transistor T0, and is used to provide a reset signal Vref to the gate of driving transistor T0; wherein, reset module 16 is also multiplexed as a bias module; the operation process of the pixel circuit includes a reset stage and a bias stage; in the reset stage, reset module 16 and compensation module 13 are turned on, and the reset signal terminal provides a reset signal to the gate of driving transistor T0 to reset the gate of driving transistor T0; in the bias stage, reset module 16 is turned on and compensation module 13 is turned off, and reset signal terminal provides a bias signal Vbias to the drain of driving transistor T0 to adjust the bias state of driving transistor T0.

[0170] Optionally, the control terminal of the data writing module 11 is connected to the first scan signal terminal to receive the first scan signal S1, which controls the data writing module 11 to turn on and off. Further, the data writing module 11 includes a first transistor T1, whose gate is connected to the first scan signal terminal, its source is connected to the data signal input terminal, and its drain is connected to the source of the driving transistor T0. The control terminal of the compensation module 13 is connected to the second scan signal terminal to receive the second scan signal S2, which controls the compensation module 13 to turn on and off. Further, the compensation module 13 includes a second transistor T2, whose gate is connected to the second scan signal terminal, its source is connected to the drain of the driving transistor T0, and its drain is connected to the gate of the driving transistor T0. The control terminal of the reset module 16 is connected to the third scan signal terminal to receive the third scan signal S3. The third scan signal S3 controls the opening and closing of the reset module 16. Further, the reset module 16 includes a fifth transistor T5. The gate of the fifth transistor T5 is connected to the third scan signal S5, the source is connected to the reset signal terminal, and the drain is connected to the drain of the driving transistor T0.

[0171] In this embodiment, the reset module is reused as a bias module. On one hand, the reset module can provide a reset signal to the gate of the driving transistor during the reset phase; on the other hand, the reset module can provide a bias signal to the drain of the driving transistor during the bias phase. Because the display panel includes non-bias phases such as the light-emitting phase, when the driving transistor is turned on, there may be a situation where the gate potential of the driving transistor is higher than the drain potential. This would cause a shift in the Id-Vg curve of the driving transistor, as described in this specification. Figure 3 As shown, this causes the threshold voltage Vth of the driving transistor to shift. To improve this phenomenon, a bias stage is set to adjust the potential difference between the gate potential and the source potential of the driving transistor, thereby reducing the shift of the Id-Vg curve and thus reducing the shift of the threshold voltage Vth of the driving transistor.

[0172] like Figure 25 As shown, in this embodiment, the pixel circuit 10 further includes a light-emitting control module 14. The light-emitting control module 14 is used to selectively allow the light-emitting element 20 to enter the light-emitting stage. The light-emitting control module 14 includes a first light-emitting control module 141 and a second light-emitting control module 142. The first light-emitting control module 141 is connected between the first power supply signal terminal and the source of the driving transistor T0, and the second light-emitting control module is connected between the drain of the driving transistor T0 and the light-emitting element 20. During the bias stage, at least the second light-emitting control module 142 is turned off. Because it is necessary to ensure that the light-emitting element 20 does not emit light during the bias stage, setting the second light-emitting control module 142 to be turned off can ensure that the light-emitting element 20 does not emit light. Alternatively, the first light-emitting control module 141 can also be turned off during the bias stage. Setting the first light-emitting control module 141 to be turned off is to avoid the first power supply signal PVDD affecting the drain voltage of the driving transistor T0, and the drain potential of the driving transistor T0 is adjusted separately by the bias signal Vbias. In some special cases, during the biasing phase, the first light-emitting control module 141 can also be turned on, and the first power supply signal PVDD and the bias signal Vbias jointly participate in the adjustment of the drain potential of the driving transistor T0. However, this situation only applies when the control terminals of the first light-emitting control module 141 and the second light-emitting control module 142 are controlled by different signals.

[0173] Optionally, the control terminal of the first light-emitting control module 141 is connected to the light-emitting control signal terminal to receive the light-emitting control signal EM. The light-emitting control signal EM controls the first light-emitting control module 141 to turn on and off. Further, the first light-emitting control module 141 includes a sixth transistor T6, the gate of which is connected to the light-emitting control signal terminal, the source of which is connected to the first power supply signal terminal, and the drain of which is connected to the source of the driving transistor T0. The control terminal of the second light-emitting control module 142 is connected to the light-emitting control signal terminal to receive the light-emitting control signal EM. The light-emitting control signal EM controls the second light-emitting control module 142 to turn on and off. Further, the second light-emitting control module 142 includes a third transistor T3, the gate of which is connected to the light-emitting control signal terminal, the source of which is connected to the drain of the driving transistor T0, and the drain of which is connected to the light-emitting element 20.

[0174] like Figure 25 As shown, in this embodiment, the pixel circuit 10 further includes an initialization module 15, which is connected between the initialization signal terminal and the light-emitting element 20, and is used to provide an initialization signal Vini to the light-emitting element 20. In some embodiments, the initialization module 15 is not turned on during the bias phase; in other embodiments, optionally, the initialization module 15 is turned on for at least a portion of the bias phase. Because the bias phase requires ensuring that the light-emitting element 20 does not emit light, but the transistor may have the risk of leakage current, which may cause the light-emitting element 20 to light up intermittently during the bias phase, the initialization module 15 being turned on for at least a portion of the bias phase ensures that the light-emitting element 20 receives the initialization signal, thereby fully ensuring that the light-emitting element 20 does not emit light.

[0175] Optionally, the control terminal of the initialization module 15 is connected to the fourth scan signal terminal to receive the fourth scan signal S4. The fourth scan signal S4 controls the opening and closing of the initialization module 15. Further, the initialization module 15 includes a fourth transistor T4. The gate of the fourth transistor T4 is connected to the fourth scan signal terminal, the source is connected to the initialization signal terminal, and the drain is connected to the light-emitting element 20.

[0176] Optionally, in this embodiment, the driving transistor T0 is a PMOS transistor, and the voltage of the bias signal Vbias is higher than the voltage of the reset signal Vref. Because during the reset phase, it is necessary to fully reset the gate voltage of the driving transistor T0 to ensure that the driving transistor T0 is turned on, the reset signal Vref is usually a low-level signal. During the bias phase, it is necessary to appropriately raise the drain voltage of the driving transistor T0 to mitigate the threshold voltage shift phenomenon of the driving transistor T0. Therefore, generally, the voltage of the bias signal Vbias is set higher than the voltage of the reset signal Vref. Based on this, the signal received at the reset signal terminal will be converted between the reset signal Vref and the bias signal Vbias. For ease of description, the signal received at the reset signal terminal will be referred to as V0 in the following text.

[0177] Optionally, in this embodiment, the operation of the pixel circuit 10 further includes at least one non-biased stage; in the biased stage, the gate voltage of the driving transistor T0 is Vg1, the source voltage is Vs1, and the drain voltage is Vd1; in the non-biased stage, the gate voltage of the driving transistor is Vg2, the source voltage is Vs2, and the drain voltage is Vd2.

[0178] In some implementations, |Vg1-Vd1| < |Vg2-Vd2|. Here, by setting |Vg1-Vd1| < |Vg2-Vd2|, the difference between the gate voltage and drain voltage of the driving transistor T0 during the bias stage is smaller than the difference between the gate voltage and drain voltage of the driving transistor T0 during the unbiased stage, thereby helping to alleviate the threshold voltage offset phenomenon of the driving transistor T0.

[0179] In other implementations, (Vg1-Vd1)×(Vg2-Vd2)<0. Here, by setting (Vg1-Vd1)×(Vg2-Vd2)<0, the potential difference between the gate and drain potentials of the driving transistor T0, which was originally in the unbiased stage, is reversed in the biased stage, thereby effectively balancing the threshold voltage offset of the driving transistor T0 caused by the unbiased stage.

[0180] Alternatively, Vd1-Vg1 > Vg2-Vd2 > 0. Here, setting Vd1-Vg1 > Vg2-Vd2 > 0, by setting a larger difference of (Vd1-Vg1), allows the potential difference between the gate and drain potentials of the driving transistor T0 in the unbiased stage to be balanced by another, larger reverse potential difference in the biased stage, thereby helping to shorten the biased stage time.

[0181] Alternatively, if the duration of the bias phase is t1 and the duration of the non-bias phase is t2, then (∣Vg1-Vd1∣﹣∣Vg2-Vd2∣)×(t1-t2)<0. Here, it is set that when ∣Vg1-Vd1∣ is greater than ∣Vg2-Vd2∣, that is, the reverse potential difference used for bias is larger, therefore, the duration of the bias phase can be set shorter than that of the non-bias phase; conversely, if ∣Vg1-Vd1∣ is less than ∣Vg2-Vd2∣, that is, the reverse potential difference used for bias is smaller, then the duration of the bias phase can be set longer than that of the non-bias phase. The purpose of the above design is to fully offset the problem of the threshold voltage offset of the driving transistor generated in the non-bias phase during the bias phase, while avoiding other problems caused by excessive bias phase.

[0182] In the foregoing embodiments, optionally, the non-biased stage is the light-emitting stage of the display panel, because during the light-emitting stage, the driving transistor T0 provides driving current to the light-emitting element 20, such as... Figure 25 In the pixel circuit shown, before the light-emitting element 20 enters the light-emitting stage, a data signal Vdata is written to the gate of the driving transistor T0 until the gate potential of the driving transistor T0 reaches (Vdata-Vth). After this, the light-emitting stage begins. Therefore, during the light-emitting stage, the gate potential of the driving transistor T0 is relatively high. In some cases, for example, during the light-emitting stage, the source potential of the driving transistor T0 is 4.6V, the gate potential is 3V, and the drain potential is 1V. Therefore, during the light-emitting stage, the driving transistor T0 is turned on, but the gate potential is higher than the drain potential, causing a shift in the Id-Vg curve and a shift in the threshold voltage Vth of the driving transistor T0. Therefore, in this embodiment, the light-emitting stage is set as a non-biased stage to solve the aforementioned technical problems caused by the light-emitting stage.

[0183] Optionally, in this embodiment, the operation of the pixel circuit during one frame of the display panel includes a pre-processing stage and a light-emitting stage; wherein, during at least one frame of the display panel, the pre-processing stage of the pixel circuit includes a biasing stage.

[0184] refer to Figure 26 and 27 , Figure 26 yes Figure 25 One of the timing diagrams of the pixel circuit shown is shown. Figure 27 yes Figure 25 One of the timing diagrams for the operation of the pixel circuit is shown. Optional features include... Figure 26As shown, within one frame, there are two stages: a pre-processing stage and a light-emitting stage. The pre-processing stage includes a reset stage and a bias stage. During the reset stage, the second scan signal S2 controls the reset module 16 to turn on. Here, the fifth transistor T5 in the reset module 16 can be a PMOS transistor or an NMOS transistor. The NMOS transistor can be an oxide semiconductor transistor. The figure shows an NMOS transistor as an example. The third scan signal S3 controls the compensation module 13 to turn on. Here, the second transistor T2 in the compensation module 13 can be a PMOS transistor or an NMOS transistor. The NMOS transistor can be an oxide semiconductor transistor. The figure shows an NMOS transistor as an example. At this time, the reset signal terminal provides a reset signal Vref to the gate of the driving transistor T0 through the turned-on reset module 16 and compensation module 13. VO is Vref at this time, which is a relatively low-level signal.

[0185] At the end of the reset phase, the compensation module 13 is turned off. Optionally, at the same time as the compensation module 13 is turned off, i.e., at the falling edge of the second scan signal S2, the VO signal at the reset signal terminal rises from the low level Vref to the relatively high level signal Vbias. At this time, the reset module 16 remains on, and the pixel circuit 10 enters the bias phase. The reset signal terminal provides the bias signal Vbias to the drain of the driving transistor T0. Here, by setting the bias phase to start at the same time as the end of the reset phase, the duration of the pre-phase can be shortened.

[0186] Additionally, optional, such as Figure 26 As shown, optionally, at the end of the reset phase, the compensation module 13 is first turned off. After a time interval, the VO signal at the reset signal terminal rises from a low level (Vref) to a relatively high level (Vbias). The reset module 16 remains on, and the pixel circuit 10 enters the bias phase. Here, a time interval is set between the reset phase and the bias phase to avoid multiple signals switching simultaneously, which could cause instability in the driving transistor. Stabilizing the driving transistor through a time interval before proceeding to the next operation improves the stability of the pixel circuit. Optionally, the length of this time interval can be shorter than the length of the reset phase, or shorter than the length of the bias phase, because this time interval is only set to stabilize the driving transistor, and therefore does not need to be too long.

[0187] Optional, such as Figure 27As shown, after the reset phase ends, the reset module 16 is turned off, while the compensation module 13 remains on for a certain period. After this period, the compensation module 13 is turned off, and simultaneously, or subsequently, the reset module 16 is turned on again. Simultaneously, or before this, the VO signal at the reset signal terminal rises from a low level (Vref) to a relatively high level (Vbias), and the pixel circuit enters the bias phase. During this process, if all signals change simultaneously, it helps to shorten the pre-set phase time; conversely, if there is a time interval between the signal changes, it helps stabilize the driving transistor. The specific design can be flexibly configured according to the specific situation.

[0188] Optional, such as Figure 27 As shown, after the reset phase ends, the time period between the shutdown of the reset module 16 and the shutdown of the compensation module 13 also includes a data writing phase. After the reset phase ends, the first scan signal S1 controls the data writing module 11 to turn on, and the data signal Vdata is written to the gate of the driving transistor T0 through the turned-on data writing module 11, the driving module 12, and the compensation module 13. After the data writing phase ends, the compensation module 13 is turned off, and the reset module 16 is turned on again to perform the biasing phase.

[0189] Optionally, in this embodiment, the duration of the aforementioned reset phase is shorter than the duration of the bias phase. This is because the purpose of the reset phase is to write the reset signal to the gate of the driving transistor, so a longer duration is not required. The bias phase, however, is used to cancel the threshold voltage offset of the non-bias phase; therefore, a certain duration is needed to achieve the desired effect. Hence, this setting exists. Additionally, as... Figure 27 As shown, the data writing phase is shorter than the bias phase because the purpose of the data writing phase is to write the data signal into the gate of the driving transistor, which does not require a long time. The bias phase is used to offset the threshold voltage offset of the non-bias phase, so a certain amount of time is required to achieve the desired effect. Hence, this setting exists.

[0190] In the aforementioned embodiments, a reset phase is set before the bias phase. This is achieved by first resetting the gate potential of the driving transistor T0 to a lower low-level signal using the reset signal Vref, and then raising the drain potential of the driving transistor T0 to a higher high-level signal using the bias signal Vbias. This achieves the goal of simultaneously lowering the gate potential of the driving transistor T0 and raising the drain potential of the driving transistor T0 during the bias phase. By adjusting from two aspects, it is more conducive to improving the potential difference between the gate and drain of the driving transistor T0, enhancing the effect of the bias phase, and fully offsetting the threshold voltage offset of the driving transistor T0 during the non-bias phase.

[0191] refer to Figure 28 , Figure 28 yes Figure 25 The diagram illustrates one of the timing diagrams of the pixel circuit. Optionally, the pre-amplification stage in this embodiment includes N bias stages, where N ≥ 1. Any two adjacent bias stages among the N bias stages include an intermediate stage. The reset stage in the aforementioned embodiment can be located before the first bias stage at the start of the bias stage; that is, the gate of the driving transistor T0 is reset first, and then the bias stage begins. Alternatively, the reset stage can also be located in the intermediate stage between any two adjacent bias stages, such as the intermediate stage between the first and second bias stages, or the intermediate stage between the second and third bias stages, etc.; that is, at least one bias stage is performed before the reset stage begins. Alternatively, the reset stage can also be located after the last bias stage of the pre-amplification stage, i.e., before the light-emitting stage. In this case, it should be noted that a data writing stage must be performed after the reset stage before entering the light-emitting stage. In the other aforementioned embodiments, a data writing stage can be performed after the reset stage, or the bias stage can be entered directly without a data writing stage, depending on the specific circumstances.

[0192] For example, Figure 28 The diagram shows two bias stages, but in practice, there are more than two. For example... Figure 28 As shown, optionally, the durations of any two bias stages in the pre-amplifier stage can be unequal. For example, the duration of the first bias stage can be longer than that of the other bias stages. This can be understood as the first bias stage being the main bias stage, primarily responsible for offsetting the threshold voltage deviation in the non-bias stages. However, to prevent incomplete biasing in the first bias stage, other supplementary bias stages can be set to fully compensate for the biasing effect. Based on this, the durations of the bias stages in the pre-amplifier stage can be sequentially decreased, thus allowing later bias stages to compensate for insufficient biasing in earlier stages. Based on the same concept, the opposite can also be achieved, such as the last bias stage having a duration longer than the other bias stages. In particular, the durations of the bias stages in the pre-amplifier stage can be sequentially increased, gradually achieving the biasing effect through progressively increasing bias stages. In addition, based on the above ideas, the duration of a certain bias phase in the middle can be set to be longer than the duration of the first bias phase and also longer than the duration of the second bias phase. That is, the bias phase at the end is used as a supplement, while the bias phase in the middle is the main bias phase.

[0193] Optionally, in this embodiment, one data writing cycle of the display panel includes S frames of screen refresh, including data writing frames and holding frames, where S > 0; the data writing frame includes a data writing phase, in which the data writing module writes data signals to the gate of the driving transistor; the holding frame does not include a data writing phase.

[0194] In one embodiment of this invention, the pre-processing stage of at least one data write frame includes an offset stage. In this case, reference can be made to... Figure 27 As shown, the data writing phase can be performed before the bias phase, after the bias phase, or between two adjacent bias phases. When the data writing phase is performed before the bias phase, it is sufficient to ensure that the compensation module 13 is turned off during the bias phase and that the data signal is latched onto the gate of the driving transistor T0.

[0195] Optionally, in this embodiment, if the length of the pre-stage is T11 and the total time of all the bias stages in the pre-stage is T22, the inventors have verified that when T22≤2 / 3×T11, it can avoid the bias stages occupying too long in the pre-stage, which would lead to an increase in the pre-stage time and a decrease in the refresh rate of the display panel, thus affecting the display effect.

[0196] In another embodiment of this example, the pre-conception phase of at least one hold frame includes an offset phase. In this case, the pre-conception phase may include an offset phase but not a data writing phase. Optionally, the pre-conception phase may also include a reset phase, such as... Figure 26 As shown, the reset phase can also be omitted, and the bias phase can be performed directly. In this case, if the length of the pre-set phase is T11, the total time of all bias phases in the pre-set phase is T22. The inventor has verified that T22 can be equal to T11, that is, the entire pre-set phase is a bias phase, or T22≥2 / 3T11, so that the time of the pre-set phase is fully utilized for the bias phase, thereby avoiding the pre-set phase being too long and achieving a better bias effect.

[0197] It should be noted that in this embodiment, only the pre-processing stage of the data write frame may include the bias stage, while the pre-processing stage of the hold frame may not include the bias stage. In this case, if the bias problem can be solved using only the data write frame, then there is no need to set the bias stage in the hold frame. Alternatively, only the pre-processing stage of the hold frame may include the bias stage, while the pre-processing stage of the data write frame may not include the bias stage. Since the data write frame also undertakes the work of the reset stage and the data write stage, if the hold frame can fully undertake the work of the bias stage, then there is no need to set the bias stage in the data write frame, thereby simplifying the timing of the data write frame.

[0198] In another embodiment of this example, both the pre-construction phase of at least one hold frame and the pre-construction phase of at least one data write frame may include an offset phase. This configuration allows the hold frame and the data write frame to jointly perform the work of the offset phase, ensuring its effectiveness. Optionally, the duration of the offset phase in the hold frame may be longer than the duration of at least one offset phase in the data write frame. As mentioned earlier, the pre-construction phase of the hold frame does not include a data write phase, therefore its timing is relatively simple, allowing for a longer offset phase in the hold frame and a shorter duration for at least one offset phase in the data write frame, thus preventing the pre-construction phase of the data write frame from being too long. Furthermore, the total duration of the offset phases in the hold frame may be greater than or equal to the total duration of the offset phases in the data write frame. Further, optionally, the duration of the offset phases in the hold frame may be longer than the duration of any single offset phase in the data write frame, to sufficiently prevent the pre-construction phase of the data write frame from being too long.

[0199] In addition, in this embodiment, as Figure 26 As described above, the start time of the initialization module 15, i.e. the initialization phase of the pixel circuit, may not overlap with the bias phase, or may partially overlap with the bias phase. The initialization phase may end at the same time as the bias phase, or the initialization phase may end before or after the bias phase, depending on the specific circumstances.

[0200] Furthermore, in this embodiment, the display panel may also include an integrated chip. This integrated chip provides the necessary driving signals to the pixel circuit, such as a data signal Vdata, a reset signal Vref, a bias signal Vbias, etc. Based on the same inventive concept, the integrated chip provided in this embodiment provides a reset signal Vref to the reset signal terminal during the reset phase of the pixel circuit and a bias signal Vbias to the reset signal terminal during the bias phase of the pixel circuit, thereby ensuring the operation of the pixel circuit in this embodiment. Specific information regarding the reset signal Vref and the bias signal Vbias can be found in the descriptions of the foregoing embodiments.

[0201] Based on the same inventive concept, targeting Figure 25The pixel circuit shown in this embodiment of the invention also provides a driving method for a display panel, wherein the display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a data writing module 11, a driving module 12, a compensation module 13, and a reset module 16; the data writing module 11 is connected between a data signal input terminal and the source of a driving transistor T0, and is used to provide a data signal Vdata to the driving module 12; the driving module is used to provide a driving current to the light-emitting element 20, and the driving module 12 includes a driving transistor T0; the compensation module 13 is connected between the gate and the drain of the driving transistor T0, and is used to compensate for the threshold voltage of the driving transistor T0; the reset module 16 is connected between a reset signal terminal and the drain of the driving transistor T0, and is used to provide a reset signal Vref to the gate of the driving transistor T0; wherein the reset module 16 is also multiplexed as a bias module;

[0202] The driving methods for the display panel include:

[0203] Reset phase: During the reset phase, the reset module 16 and the compensation module 13 are turned on, and the reset signal terminal provides a reset signal to the gate of the driving transistor T0 to reset the gate of the driving transistor T0.

[0204] Bias phase: During the bias phase, the reset module 16 is turned on and the compensation module 13 is turned off. The reset signal terminal provides a bias signal Vbias to the drain of the driving transistor T0 to adjust the bias state of the driving transistor T0.

[0205] In other embodiments of this example, the driving method may include the driving method used in the operation of the pixel circuit in any of the foregoing embodiments. This example will not repeat the same content, but it should be considered that they are all within the protection scope of the driving method provided in this example.

[0206] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel. For details regarding the display device, please refer to the description herein. Figure 24 The relevant descriptions will not be repeated in this embodiment.

[0207] In this embodiment, the reset module is reused as a bias module. On the one hand, the reset module can provide a reset signal to the gate of the driving transistor during the reset phase; on the other hand, the reset module can provide a bias signal to the drain of the driving transistor during the bias phase. Because the display panel includes non-bias phases such as the light-emitting phase, when the driving transistor is turned on, there may be a situation where the gate potential of the driving transistor is higher than the drain potential. This will cause the Id-Vg curve of the driving transistor to shift, thereby causing the threshold voltage Vth of the driving transistor to shift. In order to improve this phenomenon, a bias phase is set to adjust the potential difference between the gate potential and the source potential of the driving transistor, reduce the shift phenomenon of the Id-Vg curve, and thus reduce the shift phenomenon of the threshold voltage Vth of the driving transistor.

[0208] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a data writing transistor, a bias transistor, a driving module, a reset module, and a compensation module; The driving module includes a driving transistor; The data writing transistor is connected to the source of the driving transistor and is used to transmit data signals; The bias transistor is used to transmit bias signals; The reset module is connected to the gate of the driving transistor; The compensation module is connected between the gate of the driving transistor and the drain of the driving transistor. The operation of the pixel circuit includes a biasing stage, in which the biasing transistor is turned on to provide the biasing signal to the driving transistor. The operation of the display panel includes data writing frames and holding frames; wherein... At least two of the data are written into frames, and the duration of the offset phase is different.

2. The display panel according to claim 1, characterized in that, The operation of the display panel includes a first data write frame and a second data write frame. In the first data write frame, the time length of the offset phase is t7, and in the second data write frame, the time length of the offset phase is t8. t7>t8≥0.

3. The display panel according to claim 2, characterized in that, Between any two adjacent first data write frames, there are n second data write frames, where n ≥ 1.

4. The display panel according to claim 1, characterized in that, The control terminal of the bias transistor is used to receive a bias control signal and control the switching on and off of the bias transistor.

5. The display panel according to claim 1, characterized in that, The bias transistor is connected to the source of the driving transistor.

6. The display panel according to claim 1, characterized in that, The pixel circuit also includes: An initialization module is used to selectively provide initialization signals to the light-emitting element; A light-emitting control module is used to selectively allow the light-emitting element to enter the light-emitting phase; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between a first power signal terminal and the source of the driving transistor, and the second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element. During the biasing phase, at least the second light-emitting control module remains off; and / or, The initialization module remains on for at least a portion of the bias phase.

7. The display panel according to claim 1, characterized in that, The driving transistor is a P-type transistor, or the driving transistor is an N-type transistor.

8. The display panel according to claim 1, characterized in that, The reset module includes a fifth transistor, and the active layer of the fifth transistor includes an oxide semiconductor. The compensation module includes a second transistor, the active layer of which includes an oxide semiconductor.

9. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a data writing transistor, a bias transistor, a driving module, a reset module, and a compensation module; The driving module includes a driving transistor; The data writing transistor is connected to the source of the driving transistor and is used to transmit data signals; The bias transistor is used to transmit bias signals; The reset module is connected to the gate of the driving transistor, and the reset module includes a fifth transistor, which is an N-type transistor; The compensation module is connected between the gate and the drain of the driving transistor, and the compensation module includes a second transistor, which is an N-type transistor. The operation of the pixel circuit includes a biasing stage, in which the biasing transistor is turned on to provide the biasing signal to the driving transistor. The operation of the display panel includes data writing frames and holding frames; wherein... At least two of the data are written into frames, and the duration of the offset phase is different.

10. The display panel according to claim 9, characterized in that, The operation of the display panel includes a first data write frame and a second data write frame. In the first data write frame, the time length of the offset phase is t7, and in the second data write frame, the time length of the offset phase is t8. t7>t8≥0.

11. The display panel according to claim 10, characterized in that, Between any two adjacent first data write frames, there are n second data write frames, where n ≥ 1.

12. The display panel according to claim 9, characterized in that, The control terminal of the bias transistor is used to receive a bias control signal and control the switching on and off of the bias transistor.

13. The display panel according to claim 9, characterized in that, The bias transistor is connected to the source of the driving transistor.

14. The display panel according to claim 9, characterized in that, The pixel circuit also includes: An initialization module is used to selectively provide initialization signals to the light-emitting element; A light-emitting control module is used to selectively allow the light-emitting element to enter the light-emitting phase; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between a first power signal terminal and the source of the driving transistor, and the second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element. During the biasing phase, at least the second light-emitting control module remains off; and / or, The initialization module remains on for at least a portion of the bias phase.

15. The display panel according to claim 9, characterized in that, The driving transistor is a P-type transistor, or the driving transistor is an N-type transistor.

16. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a data writing transistor, a bias transistor, a driving module, a reset module, and a compensation module; The driving module includes a driving transistor; The data writing transistor is connected to the source of the driving transistor and is used to transmit data signals; The bias transistor is used to transmit bias signals; The reset module is connected to the gate of the driving transistor; The compensation module is connected between the gate of the driving transistor and the drain of the driving transistor. The operation of the pixel circuit includes a biasing stage and a reset stage. During the biasing phase, the biasing transistor is turned on to provide the bias signal to the driving transistor; During the reset phase, the reset module is turned on and the compensation module is turned off, providing a reset signal to the gate of the driving transistor; The operation of the display panel includes data writing frames and holding frames; wherein... At least two of the data are written into frames, and the duration of the offset phase is different.

17. The display panel according to claim 16, characterized in that, The operation of the display panel includes a first data write frame and a second data write frame. In the first data write frame, the time length of the offset phase is t7, and in the second data write frame, the time length of the offset phase is t8. t7>t8≥0.

18. The display panel according to claim 17, characterized in that, Between any two adjacent first data write frames, there are n second data write frames, where n ≥ 1.

19. The display panel according to claim 16, characterized in that, The control terminal of the bias transistor is used to receive a bias control signal and control the switching on and off of the bias transistor.

20. The display panel according to claim 16, characterized in that, The bias transistor is connected to the source of the driving transistor.

21. The display panel according to claim 16, characterized in that, The pixel circuit also includes: An initialization module is used to selectively provide initialization signals to the light-emitting element; A light-emitting control module is used to selectively allow the light-emitting element to enter the light-emitting phase; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between a first power signal terminal and the source of the driving transistor, and the second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element. During the biasing phase, at least the second light-emitting control module remains off; and / or, The initialization module remains on for at least a portion of the bias phase.

22. The display panel according to claim 16, characterized in that, The driving transistor is a P-type transistor, or the driving transistor is an N-type transistor.

23. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a data writing transistor, a bias transistor, and a driving module; The driving module includes a driving transistor; The data writing transistor is connected to the source of the driving transistor and is used to transmit data signals; The bias transistor is used to transmit bias signals; The operation of the pixel circuit includes a biasing stage, in which the biasing transistor is turned on to provide the biasing signal to the driving transistor. The operation of the display panel includes data writing frames and holding frames; wherein... Within one frame of the display panel, the operation of the pixel circuit includes a pre-processing stage and a light-emitting stage. Within at least one frame, the pre-processing stage includes the bias stage. The pre-processing stage of at least one data writing frame includes the bias stage. The duration of the pre-processing stage is T11, and the total duration of the bias stage in the pre-processing stage is T22, where T22 ≤ 2 / 3 × T11. The operation of the display panel includes data writing frames and holding frames; wherein... At least two of the data are written into frames, and the duration of the offset phase is different.

24. The display panel according to claim 23, characterized in that, The operation of the display panel includes a first data write frame and a second data write frame. In the first data write frame, the time length of the offset phase is t7, and in the second data write frame, the time length of the offset phase is t8. t7>t8≥0.

25. The display panel according to claim 24, characterized in that, Between any two adjacent first data write frames, there are n second data write frames, where n ≥ 1.

26. The display panel according to claim 23, characterized in that, The pre-stage of the data writing frame includes m sub-bias stages, where m ≥ 1.

27. The display panel according to claim 23, characterized in that, The pre-stage of the data writing frame includes at least two sub-bias stages.

28. The display panel according to claim 23, characterized in that, The control terminal of the bias transistor is used to receive a bias control signal and control the switching on and off of the bias transistor.

29. The display panel according to claim 23, characterized in that, The bias transistor is connected to the source of the driving transistor.

30. The display panel according to claim 23, characterized in that, The pixel circuit also includes: An initialization module is used to selectively provide initialization signals to the light-emitting element; A light-emitting control module is used to selectively allow the light-emitting element to enter the light-emitting phase; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between a first power signal terminal and the source of the driving transistor, and the second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element. During the biasing phase, at least the second light-emitting control module remains off; and / or, The initialization module remains on for at least a portion of the bias phase.

31. The display panel according to claim 23, characterized in that, The driving transistor is a P-type transistor, or the driving transistor is an N-type transistor.

32. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a data writing transistor, a bias transistor, a driving module, and a reset module; The driving module includes a driving transistor; The data writing transistor is connected to the source of the driving transistor and is used to transmit data signals; The bias transistor is used to transmit bias signals; The reset module is connected to the gate of the driving transistor; The operation of the pixel circuit includes a biasing stage, a data writing stage, and a reset stage. During the biasing phase, the biasing transistor is turned on to provide the bias signal to the driving transistor; During the data writing phase, the data writing transistor is turned on to provide a data signal to the driving transistor; During the reset phase, the reset module is activated to provide a reset signal to the gate of the driving transistor; The time length of the bias phase is t1, the time length of the reset phase is t3, and the time length of the data writing phase is t5, wherein t1 > t3, and / or t1 > t5; The operation of the display panel includes data writing frames and holding frames; wherein... At least two of the data are written into frames, and the duration of the offset phase is different.

33. The display panel according to claim 32, characterized in that, The operation of the display panel includes a first data write frame and a second data write frame. In the first data write frame, the time length of the offset phase is t7, and in the second data write frame, the time length of the offset phase is t8. t7>t8≥0.

34. The display panel according to claim 33, characterized in that, Between any two adjacent first data write frames, there are n second data write frames, where n ≥ 1.

35. The display panel according to claim 32, characterized in that, The control terminal of the bias transistor is used to receive a bias control signal and control the switching on and off of the bias transistor.

36. The display panel according to claim 32, characterized in that, The bias transistor is connected to the source of the driving transistor.

37. The display panel according to claim 32, characterized in that, The pixel circuit also includes: An initialization module is used to selectively provide initialization signals to the light-emitting element; A light-emitting control module is used to selectively allow the light-emitting element to enter the light-emitting phase; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between a first power signal terminal and the source of the driving transistor, and the second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element. During the biasing phase, at least the second light-emitting control module remains off; and / or, The initialization module remains on for at least a portion of the bias phase.

38. The display panel according to claim 32, characterized in that, The driving transistor is a P-type transistor, or the driving transistor is an N-type transistor.

39. An integrated chip for providing signals to a display panel according to any one of claims 1-38, characterized in that, The integrated chip provides the bias signal to the bias transistor; and / or, The integrated chip provides the data signal to the data writing transistor.

40. A display device, characterized in that, Includes the display panel as described in any one of claims 1-38.

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