Memory device and operating method thereof

Abstract

The disclosure relates to a memory device and an operating method thereof. A memory device includes memory cells connected to a plurality of word lines. The memory device further includes a read operation executor configured to perform a read operation of applying an equalization voltage to the plurality of word lines and applying a read voltage to a selected word line. The memory device further includes a fail cell counter configured to count a number of on cells among selected memory cells connected to the selected word line at each point of time. The memory device further includes a read operation controller configured to control the read operation executor to determine a length of an evaluation period based on a result of comparing the number of on cells at each point of time, and configured to sense voltages of bit lines respectively connected to the selected memory cells after the evaluation period elapses from a time when the voltage of the selected word line reaches the read voltage.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0002] A memory system is a device that stores data under the control of a host device such as a computer or smartphone. A memory system may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices or non-volatile memory devices.

[0003] Non-volatile memory devices are devices in which data is not lost even when power is off. Memory cells included in a non-volatile memory device can store data. Each memory cell can have a different threshold voltage distribution depending on the data to be stored. The threshold voltage distribution of a memory cell may change over time. After the threshold voltage distribution of a memory cell changes, even when reading the data stored in the memory cell using the same read voltage as before, the threshold voltage distribution of the memory cell will still change. Because a large number of error bits may be included, the reliability of the data obtained using that read voltage may be low. To accurately retrieve the data stored in the memory cell, the read voltage can be changed, or the timing of retrieving the data stored in the memory cell can be changed. Summary of the Invention

[0004] Embodiments of this disclosure provide a memory device and a method of operating the same that can improve the reliability of data read from the memory device.

[0005] According to one embodiment of this disclosure, a memory device includes: a memory cell connected to a plurality of word lines; a read operation actuator configured to perform a read operation that applies an equalization voltage to the plurality of word lines and applies a read voltage to a selected word line among the plurality of word lines; a failure cell counter configured to count the number of active cells in the selected memory cell connected to the selected word line at each of the following time points: a first time point after a predetermined time elapsed from the time when the read voltage is applied, a second time point after a predetermined time elapsed from the first time point, and a third time point when the voltage of the selected word line reaches the read voltage; and a read operation controller configured to control the read operation actuator to determine the length of an evaluation period during a read operation based on a comparison of the number of active cells at the first time point, the second time point, and the third time point, and configured to sense the voltages of the bit lines respectively connected to the selected memory cell after the evaluation period has elapsed from the time when the voltage of the selected word line reaches the read voltage.

[0006] According to one embodiment of this disclosure, a method of operating a memory device includes: performing a read operation of applying an equalization voltage to a plurality of word lines and applying a read voltage to a selected word line among the plurality of word lines; counting the number of active cells in a selected memory cell connected to the selected word line at each of the following time points: a first time point when the voltage of the selected word line reaches a first search voltage lower than the equalization voltage, a second time point when the voltage of the selected word line reaches a second search voltage lower than the first search voltage, and a third time point when the voltage of the selected word line reaches a read voltage higher than the second search voltage; determining the length of an evaluation period based on a comparison of the number of active cells at the first, second, and third time points; and sensing the voltages of the bit lines respectively connected to the selected memory cell after the evaluation period has elapsed from the time when the voltage of the selected word line reaches the read voltage.

[0007] According to one embodiment of this disclosure, a memory device includes: a memory cell connected to a plurality of word lines; a read operation actuator configured to perform a read operation that applies an equalization voltage to the plurality of word lines and applies a first search voltage less than the equalization voltage, a second search voltage less than the first search voltage, and a read voltage greater than the second search voltage to a selected word line among the plurality of word lines; a failure cell counter configured to count the number of active cells in the selected memory cell connected to the selected word line, each identified by the first search voltage, the second search voltage, and the read voltage; and a read operation controller configured to control the read operation actuator to sense the voltages of the bit lines respectively connected to the selected memory cell during the read operation, after an evaluation period determined based on a comparison of the number of each identified active cell, from the time when the voltage of the selected word line reaches the read voltage. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating a memory system including a memory device according to one embodiment of the present disclosure.

[0009] Figure 2 It is shown Figure 1 A diagram of the structure of a memory device.

[0010] Figure 3 It is shown Figure 2 A diagram of one embodiment of a memory cell array.

[0011] Figure 4 It is shown Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0012] Figure 5 It is shown Figure 3 A circuit diagram of another embodiment of storage block BLKb of any one of storage blocks BLK1 to BLKz.

[0013] Figure 6 It is shown Figure 3 A circuit diagram of another embodiment of storage block BLKi from storage blocks BLK1 to BLKz.

[0014] Figure 7 This is a graph showing the threshold voltage distribution of memory cells.

[0015] Figure 8 This is a graph showing the distribution of threshold voltages as memory cells change.

[0016] Figure 9 This is a diagram illustrating a read operation of a memory device.

[0017] Figure 10 This is a diagram showing the evaluation period determined based on the read operation of the memory device.

[0018] Figure 11 This is a diagram illustrating another embodiment of the evaluation period determined based on a read operation of a memory device.

[0019] Figure 12 This is a diagram illustrating yet another embodiment of the evaluation period determined based on a read operation of the memory device.

[0020] Figure 13 This is a diagram illustrating another embodiment of the read operation of a memory device.

[0021] Figure 14 This is a diagram illustrating the read operation of a memory device using multiple read voltages.

[0022] Figure 15 This is a flowchart illustrating a read operation of a memory device. Detailed Implementation

[0023] The specific structural or functional descriptions of the embodiments disclosed in this specification or application are merely illustrative of embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0024] Figure 1 This is a diagram illustrating a memory system including a memory device according to one embodiment of the present disclosure.

[0025] Reference Figure 1The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device for storing data under the control of a host 300, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system.

[0026] Depending on the host interface, which serves as the communication method with the host 300, the memory system 50 can be manufactured as one of various types of storage devices. For example, the memory system 50 can be configured as any of various types of storage devices such as SSDs, multimedia cards (in the form of MMC, eMMC, RS-MMC, and micro-MMC), secure digital cards (in the form of SD, mini-SD, and micro-SD), universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card storage devices, peripheral component interconnect (PCI) card storage devices, high-speed PCI (PCI-E) card storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0027] The memory system 50 can be manufactured in any of a variety of package types. For example, the memory system 50 can be manufactured in any of a variety of package types such as PoP, System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0028] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0029] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0030] In one embodiment, the memory device 100 may utilize Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that the memory device 100 uses NAND flash memory.

[0031] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access address-selected regions in a memory cell array. Memory device 100 can perform operations instructed by commands on the address-selected regions. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. Memory device 100 can program, read, or erase data in the address-selected regions.

[0032] In one embodiment, the memory device 100 may include a read operation actuator 140, a fail cell counter 150, and a read operation controller 160. In some embodiments, the read operation actuator 140, the fail cell counter 150, and / or the read operation controller 160 may be read operation actuator circuitry, fail cell counter circuitry, and / or read operation controller circuitry.

[0033] The read operation actuator 140 can perform read operations on memory cells. A read operation can be an operation to obtain data stored in a memory cell. A read operation can be an operation to apply a read voltage to a memory cell storing data and to sense the data stored in the memory cell while the read voltage is applied. Because the threshold voltage of a memory cell is determined based on the stored data, the read operation can be an operation to identify which state the threshold voltage of each memory cell is in. For example, when programming each memory cell in a three-level cell (TLC) storing three bits of data, seven read voltages can be applied to the word lines connected to the memory cells to identify which state the threshold voltage of the memory cell corresponds to among the erase state and the first to seventh programming states.

[0034] The failure cell counter 150 can count the number of memory cells in the memory cell whose threshold voltage is less than the voltage applied to the word line connected to the memory cell. For example, when a read voltage is applied to the word line, the failure cell counter 150 can count the number of memory cells in the memory cell whose threshold voltage is less than the read voltage. As another example, the failure cell counter 150 can count the number of memory cells in the memory cell whose threshold voltage is less than a first search voltage, which is greater than the read voltage. As yet another example, the failure cell counter 150 can count the number of memory cells in the memory cell whose threshold voltage is less than a second search voltage, which is less than the read voltage. In the memory cell, memory cells whose threshold voltage is less than the voltage applied to the word line connected to the memory cell can be identified as on cells. In the memory cell, memory cells whose threshold voltage is greater than the voltage applied to the word line connected to the memory cell can be identified as off cells.

[0035] The read operation controller 160 can control the read operation performed by the read operation executor 140. Furthermore, the read operation controller 160 can compare the number of memory cells counted by the failure cell counter 150. The read operation controller 160 can determine the length of the evaluation period included in the read operation based on the result of comparing the number of memory cells. The evaluation period can be the period during which the voltage of the bit line changes according to the threshold voltage of the memory cell when a read voltage is applied to the word line. The read operation controller 160 can control the read operation executor 140 to sense the voltage of the bit line after the evaluation period has elapsed during the read operation. The read operation controller 160 can control the read operation executor 140 to obtain the data stored in the memory cell during the read operation based on the result of comparing the voltage of the bit line with a reference voltage after the evaluation period has elapsed.

[0036] The memory controller 200 can control the overall operation of the memory system 50.

[0037] When power is applied to the memory system 50, the memory controller 200 can execute firmware (FW). In one embodiment, the memory controller 200 can execute firmware to control communication between the host 300 and the memory device 100. In one embodiment, the memory controller 200 can translate the logical block address of the host into the physical block address of the memory device.

[0038] The memory controller 200 can control the memory device 100 to perform write operations, read operations, erase operations, etc., according to the request of the host 300. The memory controller 200 can provide commands, physical block addresses, or data to the memory device 100 according to the write operations, read operations, and erase operations.

[0039] In one implementation, the memory controller 200 can independently generate commands, addresses, and data regardless of requests from the host 300, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data for performing read and write operations that accompany wear leveling, read recycling, garbage collection, etc.

[0040] In one embodiment, the memory controller 200 can control at least two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method can be a method of controlling the operation of at least two memory devices 100 to overlap with each other.

[0041] The host 300 can communicate with the memory system 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Non-Volatile Memory Fast (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-off DIMM (LRDIMM).

[0042] In one embodiment, memory system 50 may include buffer memory (not shown). For example, buffer memory may temporarily store data received from host 300 or memory device 100, or it may temporarily store metadata of memory device 100 (e.g., a mapping table). Buffer memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0043] Figure 2 It is shown Figure 1 A diagram of the structure of a memory device.

[0044] Reference Figure 2The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0045] Memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to address decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells are defined as a page. That is, memory cell array 110 is composed of a plurality of pages. According to one embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKz included in memory cell array 110 may include a plurality of dummy cells. At least one of the dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0046] Each memory cell of the memory device 100 can be configured as a single-level cell (SLC) that stores one bit of data, a multi-level cell (MLC) that stores two bits of data, a three-level cell (TLC) that stores three bits of data, a four-level cell (QLC) that can store four bits of data, or a memory cell that can store five or more bits of data.

[0047] Peripheral circuitry 120 drives memory cell array 110. For example, peripheral circuitry 120 can drive memory cell array 110 to perform programming operations, read operations, and erase operations. As another example, peripheral circuitry 120 can apply various operating voltages to or release the applied voltages to row lines RL and bit lines BL1 to BLm according to the control of control logic 130.

[0048] The peripheral circuitry 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0049] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to one embodiment of this disclosure, word lines may include normal word lines and dummy word lines. According to one embodiment of this disclosure, row lines RL may also include transistor select lines.

[0050] Address decoder 121 is configured to operate in response to control by control logic 130. Address decoder 121 receives address RADD from control logic 130.

[0051] Address decoder 121 is configured to decode the block address of the received address RADD. Address decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 is also configured to decode the row address of the received address RADD. Address decoder 121 can select at least one word line of the selected memory block by applying a voltage supplied from voltage generator 122 to at least one word line WL based on the decoded row address.

[0052] During programming operations, address decoder 121 may apply a programming voltage to selected word lines and a pass voltage with a level lower than the programming voltage to unselected word lines. During programming verification operations, address decoder 121 may apply a verification voltage to selected word lines and a verification pass voltage with a level higher than the verification voltage to unselected word lines.

[0053] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and a read pass voltage with a level greater than the read voltage to the unselected word line.

[0054] Erasure operations on memory device 100 are performed on a block-by-block basis. During the erase operation, the address RADD input to memory device 100 includes the block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0055] Address decoder 121 can be configured to decode the column address of the transmitted address RADD. The decoded column address can be transmitted to page buffer group 123. As an example, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0056] Voltage generator 122 is configured to generate multiple operating voltages Vop by using an external power supply voltage provided to memory device 100. Voltage generator 122 operates in response to control of control logic 130.

[0057] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0058] In one embodiment, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to an operation signal OPSIG. Voltage generator 122 can use an external or internal power supply voltage to generate multiple operating voltages Vop. Voltage generator 122 can be configured to generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0059] In order to generate multiple operating voltages Vop with various voltage levels, voltage generator 122 may include multiple pump capacitors that receive internal voltages and selectively activate the multiple pump capacitors in response to control logic 130 to generate multiple operating voltages Vop.

[0060] Multiple generated operating voltages Vop can be provided to the memory cell array 110 by the address decoder 121.

[0061] Page buffer group 123 includes first page buffer PB1 to m-th page buffer PBm. First page buffer PB1 to m-th page buffer PBm are respectively connected to memory cell array 110 via first bit line BL1 to m-th bit line BLm. First page buffer PB1 to m-th page buffer PBm operate in response to control logic 130.

[0062] Page buffers PB1 through PBm communicate with the data input / output circuit 124 for data DATA. During programming, page buffers PB1 through PBm receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0063] During programming operations, page buffers PB1 through PBm (page m to page m) transfer data DATA received from data input / output circuit 124 to a selected memory cell via bit lines BL1 through BLm. The selected page's memory cell is programmed based on the transferred data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied may have an increased threshold voltage. Memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied may have a maintained threshold voltage. During programming verification operations, page buffers PB1 through PBm (page m to page m) read data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 through BLm.

[0064] During a read operation, page buffer group 123 can read data DATA from the memory cell of the selected page via bit line BL and store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0065] During an erase operation, page buffer group 123 can float the bit line BL. In one embodiment, page buffer group 123 may include column select circuitry.

[0066] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates in response to the control logic 130.

[0067] Data input / output circuitry 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, data input / output circuitry 124 may receive data DATA to be stored from an external controller (not shown). During read operations, data input / output circuitry 124 may output data DATA transferred from the first page buffer PB1 to the m-th page buffer PBm included in page buffer group 123 to the external controller. For example, data input / output circuitry 124 may output data DATA transferred from the first page buffer PB1 to the m-th page buffer PBm to the external controller in response to a data output control signal received from control logic 130.

[0068] During a read or verification operation, the sensing circuit 125 may generate a reference current in response to the signal of the enable bit VRYBIT generated by the control logic 130, and may compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal or a failure signal to the control logic 130.

[0069] In one embodiment, the sensing circuit 125 can compare a sensed voltage VPB received from the page buffer group 123 with a reference voltage to identify whether a memory cell connected to a bit line is an on or off cell. For example, when the sensed voltage VPB is less than the reference voltage, the sensing circuit 125 can identify the memory cell connected to the bit line as an on cell. As another example, when the sensed voltage VPB is greater than the reference voltage, the sensing circuit 125 can identify the memory cell connected to the bit line as an off cell. In one embodiment, the sensing circuit 125 can count the number of on cells in the memory cell whose threshold voltage is less than the read voltage or the verification voltage during a read operation or a verification operation.

[0070] Control logic 130 can be connected to address decoder 121, voltage generator 122, page buffer group 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 can be configured to control all operations of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from an external device. Control logic 130 can be implemented as hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0071] Control logic 130 can generate various signals to control peripheral circuitry 120 in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, address RADD, page buffer control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, address RADD to address decoder 121, page buffer control signal to page buffer group 123, and enable bit VRYBIT to sensing circuit 125. In one embodiment, control logic 130 can be controlled by page buffer control signal PBSIGNALS to transfer data stored in first page buffer PB1 to m-th page buffer PBm to data input / output circuitry 124.

[0072] In one implementation method Figure 1 The read operation actuator 140 shown may include a memory cell array 110, a voltage generator 122, an address decoder 121, and a page buffer group 123. Under the control of a read operation controller 160, the read operation actuator 140 can generate voltages for read operations and apply these voltages to word lines and bit lines. Under the control of the read operation controller 160, the read operation actuator 140 can sense the voltages on the bit lines.

[0073] In one implementation method Figure 1 The failure cell counter 150 shown may include sensing circuitry 125. The failure cell counter 150 can count the number of memory cells in the memory cell whose threshold voltage is less than the voltage applied to the word line.

[0074] In one implementation method Figure 1 The read operation controller 160 shown can be included in the control logic 130. The read operation controller 160 can determine the length of the evaluation period during a read operation based on the result of counting the number of memory cells. The read operation controller 160 can control the read operation actuator 140 to sense the voltage of the bit line after the evaluation period has elapsed during the read operation.

[0075] Figure 3 It is shown Figure 2 A diagram of one embodiment of a memory cell array.

[0076] Reference Figure 3 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged in the +X, +Y, and +Z directions. (Refer to...) Figure 4 , Figure 5 and Figure 6 Describe the structure of each storage block in more detail.

[0077] Figure 4 It is shown Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0078] Reference Figure 4 The storage block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the storage block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 4 In this diagram, two unit strings are arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0079] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a tube transistor PT, and at least one drain selection transistor DST.

[0080] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In one embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0081] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0082] In one implementation, source-select transistors in cell strings arranged in the same row are connected to source-select lines extending in the row direction, and source-select transistors in cell strings arranged in different rows are connected to different source-select lines. Figure 4 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0083] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0084] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0085] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in the direction opposite to the +Z direction and connected in series between the source selection transistor SST and the transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and connected in series between the transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are interconnected with each other via the transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0086] The gate of the tubular transistor PT in each cell string is connected to the pipeline PL.

[0087] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0088] A string of cells arranged in the column direction is connected to a bit line extending in the column direction. Figure 4In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0089] In a row-oriented cell string, memory cells connected to the same word line constitute a page. For example, memory cells in the cell strings CS11 to CS1m of the first row connected to the first word line WL1 constitute one page. Memory cells in the cell strings CS21 to CS2m of the second row connected to the first word line WL1 constitute another page. A cell string arranged in a row direction can be selected by choosing either drain select line DSL1 or DSL2. A page of a selected cell string can be selected by choosing any of the word lines WL1 to WLn.

[0090] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings in the row-direction cell strings CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings in the row-direction cell strings CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0091] In one implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn.

[0092] Figure 5 It is shown Figure 3 A circuit diagram of another embodiment of storage block BLKb of any one of storage blocks BLK1 to BLKz.

[0093] Reference Figure 5 The memory block BLKb includes multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends in the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) located below the memory block BLKb.

[0094] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a single source select line.

[0095] In addition to excluding tubular transistors (PTs) from each cell string, Figure 5 The storage block BLKb shown has the same characteristics as... Figure 4 The equivalent circuit of the storage block BLKa is similar to the equivalent circuit.

[0096] Figure 6 It is shown Figure 3 A circuit diagram of another embodiment of storage block blk1 from storage blocks BLK1 to BLKz.

[0097] Reference Figure 6 Multiple word lines can be arranged parallel to each other between the first select line and the second select line. Here, the first select line can be the source select line SSL, and the second select line can be the drain select line DSL. More specifically, the memory block BLKi can include multiple string STs connected between bit lines BL1 to BLn and the common source line SL. Bit lines BL1 to BLn can be connected to string STs individually, and the common source line SL can be connected to string STs collectively. Because string STs can be configured identically to each other, the string ST connected to the first bit line BL1 will be described specifically as an example.

[0098] A string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series between a common source line SL and a first bit line BL1. A string ST may include at least one or more of the source selection transistor SST and the drain selection transistor DST.

[0099] The source of the source select transistor SST can be connected to the common source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Multiple memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST, included in different string STs, can be connected to the source select line SSL, the gate of the drain select transistor DST, can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different string STs can be called a physical page PG. Therefore, a memory block BLKi can include a number of physical pages PG across multiple word lines WL1 to WL16.

[0100] A memory cell can store one bit of data. This is often referred to as SLC. In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0101] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPGs) of data. In one implementation, when a memory cell stores three bits of data, the data stored in a physical page can include three logical pages. Specifically, the three logical pages can include a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page.

[0102] Figure 7 This is a graph showing the threshold voltage distribution of memory cells.

[0103] exist Figure 7 In the graph, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells: the number of cells.

[0104] exist Figure 7 In this example, we assume that a memory cell in a TLC storing three bits of data is being programmed. (Refer to...) Figure 7 Through programming operations, the threshold voltage of a memory cell can be increased to a threshold voltage corresponding to any of the erase state E and the first programming states PV1 to the seventh programming states PV7. The data stored in the memory cell can vary depending on the programming state of the memory cell. Depending on which of the erase state E and the first programming states PV1 to the seventh programming states PV7 the memory cell's threshold voltage corresponds to, the memory cell can store different data.

[0105] The memory device 100 can perform a read operation to obtain data stored in the memory cell. Specifically, the memory device 100 can sense the voltage of the bit line connected to the memory cell that changes when a read voltage is applied to the word line connected to the memory cell, and compare the sensed voltage with a reference voltage to obtain the data stored in the memory cell.

[0106] In one embodiment, the memory device 100 may use multiple read voltages to perform read operations on multiple logical pages. The multiple logical pages may include LSB pages, CSB pages, and MSB pages. The multiple read voltages may include a first read voltage Vr1 through a seventh read voltage Vr7. Each of the first read voltages Vr1 through the seventh read voltage Vr7 may be a voltage that distinguishes between erase state E and each of the first programming states PV1 through the seventh programming states PV7. For example, the memory device 100 may use a third read voltage Vr3 and a seventh read voltage Vr7 to perform a read operation on a CSB page, where the third read voltage Vr3 distinguishes between erase state E, the first programming state PV1, the second programming state PV2, and the third programming states PV3 through the seventh programming states PV7, and the seventh read voltage Vr7 distinguishes between erase state E, the first programming states PV1 through the sixth programming states PV6, and the seventh programming state PV7.

[0107] Figure 8 This is a graph showing the distribution of threshold voltages as memory cells change.

[0108] exist Figure 8 As an example, the text describes a case where a memory cell is programmed with threshold voltages corresponding to a first programming state PV1 and a second programming state PV2. Over time, the threshold voltages corresponding to... Figure 7 The threshold voltage distribution of the memory cell in the first programming state PV1 and the second programming state PV2 shown can be changed to have a corresponding threshold voltage distribution. Figure 8 The threshold voltage distribution of the memory cell is shown for the first programming state PV1 and the second programming state PV2. For example, as the number of programming and erasing operations performed on the memory cell increases, the threshold voltage distribution of the memory cell may change. Figure 8 The threshold voltage distribution of the memory cells is shown. Therefore, when using differentiation... Figure 7 When the second read voltage Vr2 of the first programming state PV1 and the second programming state PV2 reads data stored in the memory cell, it may include a large number of failure bits. Therefore, it may be necessary to change the read voltage that distinguishes the first programming state PV1 and the second programming state PV2 to a different magnitude than the second read voltage Vr2.

[0109] exist Figure 8As an example, a cell programmed with threshold voltages corresponding to a first programming state PV1 and a second programming state PV2 is described. However, in multiple programming states, the threshold voltage distribution of memory cells programmed with threshold voltages corresponding to adjacent programming states may differ over time. Figure 8 The same method is used to change it.

[0110] Figure 9 This is a diagram illustrating a read operation of a memory device.

[0111] Reference Figure 9 The memory device 100 can perform a read operation. The read operation may include an initialization period and a first read period (Read1).

[0112] Time periods t1 to t2 can be initialization periods. Initialization periods can be periods used to initialize the channel regions of memory cells. During time periods t1 to t2, memory device 100 can apply an equalization voltage Veq to multiple word lines. The multiple word lines can include selected word lines Sel_WL and unselected word lines Unsel_WL. During time periods t1 to t2, the voltages of the multiple word lines can be increased to the equalization voltage Veq. During time periods t1 to t2, memory device 100 can apply a precharge voltage Vpre to the bit lines connected to the memory cells. During time periods t1 to t2, the voltages of the bit lines can be increased to the precharge voltage Vpre. During time periods t1 to t2, memory device 100 can apply a turn-on voltage Von to selected drain select lines and selected source select lines Sel_DSL and SSL. The turn-on voltage Von can be a voltage higher than the threshold voltages of the drain select transistor and source select transistor connected to the selected drain select line and selected source select lines Sel_DSL and SSL, respectively. During time period t1 to t2, memory device 100 may apply a turn-on voltage Von to the unselected drain select line and the unselected source select line UnselDSL and SSL.

[0113] Time periods t2 to t7 can be the first read time period Read1. The first read time period Read1 can be a time period used to obtain data stored in a selected memory cell connected to the selected word line Sel_WL. In one implementation, when performing a read operation on a CSB page, the first read time period Read1 can be used to... Figure 7 The seventh read voltage Vr7 shown is used to obtain the time period of data stored in the selected memory cell. At this time, the read voltage Vr can be the seventh read voltage Vr7.

[0114] During periods t2 to t7, the memory device may apply a read voltage Vr to the selected word line Sel_WL. During periods t2 to t7, the magnitude of the voltage on the selected word line may decrease from the equalization voltage Viq to a voltage lower than the read voltage Vr, and may then have the same magnitude as the read voltage Vr.

[0115] The memory device 100 may apply a read voltage Vr at time t2, and count the number of active cells of the selected memory cell after a predetermined time has elapsed since the time when the read voltage Vr was applied. The time point when the predetermined time has elapsed may be time point t3, time point t4, or time point t5.

[0116] During time periods t2 to t3, the voltage of the selected word line can decrease from the equalization voltage Viq to the first search voltage Vs1. The memory device 100 can perform a first sensing operation S1 at time point t3 when the voltage of the selected word line decreases to the first search voltage Vs1. The sensing operation can be an operation of sensing the voltage of the bit line that changes based on the threshold voltage of the selected memory cell. Data stored in the selected memory cell can be identified based on the magnitude of the sensed bit line voltage. In one embodiment, the first sensing operation S1 can be an operation of sensing the voltage of the bit line that changes when the magnitude of the voltage of the selected word line Sel_WL is the first search voltage Vs1. Specifically, the voltage of the bit line connected to the memory cell in the selected memory cell whose threshold voltage is higher than the first search voltage Vs1 can be maintained at the precharge voltage Vpre. Data stored in the memory cell whose threshold voltage is higher than the first search voltage Vs1 can be identified as data corresponding to the off cell. Furthermore, the voltage of the bit line connected to the memory cell in the selected memory cell whose threshold voltage is lower than the first search voltage Vs1 can be lower than the precharge voltage Vpre. Data stored in the memory cell whose threshold voltage is lower than the first search voltage Vs1 can be identified as data corresponding to the on cell.

[0117] The memory device 100 can count the first number of conducting cells identified by the first search voltage Vs1 in the selected memory cells at time point t3. The first number of conducting cells can be the number of memory cells in the selected memory cells whose threshold voltage is lower than the first search voltage Vs1.

[0118] The memory device 100 can perform a first sensing operation S1, and before performing a second sensing operation S2, precharge the voltage of the bit line connected to the selected memory cell back to the precharge voltage Vpre. Specifically, the voltage of the bit line connected to the memory cell whose threshold voltage is lower than the first search voltage Vs1 may be lower than the precharge voltage Vpre after performing the first sensing operation S1, and may be increased back to the precharge voltage Vpre before performing the second sensing operation S2. However, as described later... Figure 9 and Figure 13 In this case, the changes in the magnitude of the bit line voltage in the first sensing operation S1, the second sensing operation S2, and the third sensing operation S3 are omitted, and for ease of description, the magnitude of the bit line voltage is shown as constant. That is, as described above, the bit line voltage that is lower than the pre-charge voltage Vpre in any sensing operation can be increased back to the pre-charge voltage Vpre before the next sensing operation.

[0119] During time periods t3 to t4, the voltage of the selected word line can decrease from the first search voltage Vs1 to the second search voltage Vs2. The memory device 100 can perform a second sensing operation S2 at time point t4 when the voltage of the selected word line decreases to the second search voltage Vs2. The second sensing operation S2 can be an operation that senses the change in bit line voltage when the magnitude of the voltage of the selected word line Sel_WL is equal to the second search voltage Vs2. Specifically, the memory device 100 can count a second number of active cells identified by the second search voltage Vs2 in the selected memory cell at time point t4. The second number of active cells can be the number of memory cells in the selected memory cell whose threshold voltage is lower than the second search voltage Vs2. The voltage of the bit line connected to the memory cell whose threshold voltage is lower than the second search voltage Vs2 can be lower than the precharge voltage Vpre after the second sensing operation S2 is performed, and can increase to the precharge voltage Vpre before the third sensing operation S3 is performed.

[0120] During time intervals t4 and t5, the voltage of the selected word line can increase from the second search voltage Vs2 to the read voltage Vr. The memory device 100 can perform a third sensing operation S3 at time point t5 when the voltage of the selected word line increases to the read voltage Vr. The third sensing operation S3 can be an operation that senses the change in the voltage of the bit line when the magnitude of the selected word line voltage is the read voltage Vr. Specifically, the memory device 100 can count a third number of active cells identified by the read voltage Vr in the selected memory cell at time point t5. The third number of active cells can be the number of memory cells in the selected memory cell whose threshold voltage is lower than the read voltage Vr. The voltage of the bit line connected to the memory cell whose threshold voltage is lower than the read voltage Vr can fall below the precharge voltage Vpre after the execution of the third sensing operation S3, and can increase back to the precharge voltage Vpre before the execution of the fourth sensing operation S4.

[0121] During the time period t5 to t6, the voltage of the selected word line Sel_WL can be maintained at the magnitude of the read voltage Vr.

[0122] In one implementation, as the voltage of the selected word line Sel_WL decreases from the equalization voltage Veq to the read voltage Vr, the memory device 100 may perform a sensing operation at each time point when the voltage of the selected word line Sel_WL reaches the first search voltage Vs1, the second search voltage Vs2, and the read voltage Vr. The memory device 100 may count the number of active cells identified by each of the first search voltage Vs1, the second search voltage Vs2, and the read voltage Vr in the selected memory cells. In one implementation, at the time points when the voltage reaches the first search voltage Vs1, the second search voltage Vs2, and the read voltage Vr, the memory device 100 may perform a sensing operation only on some of the memory cells in the selected memory cells. For example, when the selected memory cells are configured in 16KB units, the memory device 100 may perform a sensing operation only on 8KB, which is part of the 16KB. As another example, when the selected memory cells are configured in 16KB units, the memory device 100 may perform a sensing operation only on 4KB, which is part of the 16KB.

[0123] In one implementation, the magnitude difference ΔV1 between the first search voltage and the read voltage can be the same as the magnitude difference ΔV2 between the read voltage and the second search voltage.

[0124] During periods t2 to t7, memory device 100 may apply a pass voltage Vpass to the unselected word line Unsel_WL. During periods t2 to t7, the magnitude of the voltage on the unselected word line Unsel_WL may increase from the equalization voltage Viq to the pass voltage Vpass.

[0125] During the time period t2 to t6, the voltage of the bit line can be maintained at the level of the pre-charge voltage.

[0126] During periods t2 to t7, memory device 100 may apply a turn-on voltage Von to the selected drain select line and the selected source select line Sel_DSL and SSL. During periods t2 to t7, memory device 100 may apply a ground voltage to the unselected drain select line and the unselected source select line Unsel_DSL and SSL.

[0127] The time period t6 to t7 can be an evaluation period. The evaluation period can be a time period used to sense the voltage of the bit line that changes according to the magnitude of the threshold voltage of the selected memory cell. The memory device 100 can perform a fourth sensing operation S4 after the evaluation period has elapsed, in which the bit line voltage changes to a voltage lower than the pre-charge voltage Vpre. The fourth sensing operation S4 can be an operation that obtains data stored in the selected memory cell based on the result of comparing a reference voltage with the bit line voltage that changed after the evaluation period.

[0128] In one implementation, the length of the evaluation period can be varied. The memory device 100 determines the length of the evaluation period based on a comparison of the number of active cells identified by the first sensing operation S1, the second sensing operation S2, and the third sensing operation S3. See later. Figures 10 to 12 Describe the method for determining the length of the evaluation period.

[0129] Figure 10 This is a diagram showing the evaluation period determined based on the read operation of the memory device.

[0130] Figure 10 The threshold voltage distribution of the memory cells shown indicates adjacent programming states among multiple programming states. Figure 10 In the graph shown on the left, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells (#). Figure 10 In the graph shown on the right, the horizontal axis represents time (Time), and the vertical axis represents voltage (V).

[0131] Reference Figure 10 In the graph shown on the left, the memory cells in the first segment C1 can be memory cells with a threshold voltage lower than the second search voltage Vs2. The memory cells in the second segment C2 can be memory cells with a threshold voltage higher than the second search voltage Vs2 and lower than the read voltage Vr. The memory cells in the third segment C3 can be memory cells with a threshold voltage higher than the read voltage Vr and lower than the first search voltage Vs1. The memory cells in the fourth segment C4 can be memory cells with a threshold voltage higher than the first search voltage Vs1.

[0132] The memory device 100 can count the number of active cells in a selected memory cell identified by a first search voltage Vs1, a second search voltage Vs2, and a read voltage Vr. The memory device 100 can compare the number of active cells identified by the first search voltage Vs1, the second search voltage Vs2, and the read voltage Vr, respectively.

[0133] The memory device 100 can count a first number of valley cells, which is the difference between a first number of active cells identified by a first search voltage Vs1 and a third number of active cells identified by a read voltage Vr. The first number of valley cells may be the number of memory cells in the third segment C3. The memory device 100 can also count a second number of valley cells, which is the difference between a third number of active cells identified by a read voltage Vr and a second number of active cells identified by a second search voltage Vs2. The second number of valley cells may be the number of memory cells in the second segment C2.

[0134] Reference Figure 10 The graph on the right shows that during the evaluation period, the voltage of the bit lines can be reduced to a level lower than the pre-charge voltage. Specifically, the degree to which the voltage of the bit lines is reduced during the evaluation period varies depending on the threshold voltage of the memory cell connected to the bit line. For example, the voltage of the bit line connected to the memory cell in the first segment C1 can be reduced with the maximum slope. The voltage of the bit line connected to the memory cell in the second segment C2 can be reduced with a lower slope than that of the bit line connected to the memory cell in the first segment C1. The voltage of the bit line connected to the memory cell in the third segment C3 can be reduced with a lower slope than that of the bit line connected to the memory cell in the second segment C2. The voltage of the bit line connected to the memory cell in the fourth segment C4 can be reduced with the lowest slope.

[0135] The memory device 100 can sense the voltage of the bit line after an evaluation period, where the evaluation period is the interval from when the bit line voltage decreases to below the pre-charge voltage to when a predetermined time has elapsed. Specifically, the memory device 100 can obtain data stored in the memory cells connected to the bit line based on the result of comparing the bit line voltage with the reference voltage Vref at a reference evaluation time point eval_def. When the bit line voltage is greater than the reference voltage Vref at the reference evaluation time point eval_def, the memory device 100 can identify the memory cell connected to the bit line as an off cell. For example, the memory device 100 can obtain data with a logic value of 0 from the memory cell identified as an off cell. When the bit line voltage is less than the reference voltage Vref at the reference evaluation time point eval_def, the memory device 100 can identify the memory cell connected to the bit line as an on cell. For example, the memory device 100 can obtain data with a logic value of 1 from the memory cell identified as an on cell.

[0136] Because the voltage on the bit line of the memory cell connected to the first segment C1 is less than the reference voltage Vref at the reference evaluation time point eval_def, the memory cell of the first segment C1 can be identified as an On cell. Because the voltage on the bit line of the memory cell connected to the second segment C2 is less than the reference voltage Vref at the reference evaluation time point eval_def, the memory cell of the second segment C2 can be identified as an On cell. Because the voltage on the bit line of the memory cell connected to the third segment C3 is greater than the reference voltage Vref at the reference evaluation time point eval_def, the memory cell of the third segment C3 can be identified as an Off cell. Because the voltage on the bit line of the memory cell connected to the fourth segment C4 is greater than the reference voltage Vref at the reference evaluation time point eval_def, the memory cell of the fourth segment C4 can be identified as an Off cell.

[0137] In one embodiment, the memory device 100 can determine the length of an evaluation period based on a comparison of a first number of valley cells and a second number of valley cells. Specifically, when the difference between the first number of valley cells and the second number of valley cells is less than the number of reference cells, the memory device can determine the length of the evaluation period as a first evaluation period evaluation. The first evaluation period evaluation can be the period from the time when the voltage of the bit line decreases to the reference evaluation time point eval_def. The memory device 100 can sense the voltage of the bit line after the first evaluation period evaluation.

[0138] In other words, when the difference between the first number of valley cells and the second number of valley cells is not large, the memory device 100 can determine that the read voltage Vr is the optimal read voltage for distinguishing adjacent programming states.

[0139] Figure 11 This is a diagram illustrating another embodiment of the evaluation period determined based on a read operation of a memory device.

[0140] exist Figure 11 In the graph shown on the left, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells (#). Figure 11 In the graph shown on the right, the horizontal axis represents time (Time), and the vertical axis represents voltage (V). (Referring to...) Figure 11 The description omits the related terms. Figure 10 The content is repeated.

[0141] Reference Figure 11The memory device 100 can determine the length of the evaluation period based on a comparison of a first number of valley cells and a second number of valley cells. The first number of valley cells can be the number of memory cells in the third segment C3. The second number of valley cells can be the number of memory cells in the second segment C2. When the difference between the first number of valley cells and the second number of valley cells is greater than the number of reference cells, the memory device 100 can change the length of the evaluation period. That is, when the first number of valley cells is greater than the second number of valley cells and the difference between the first number of valley cells and the second number of valley cells is large, the memory device 100 can determine that the read voltage Vr is not the optimal read voltage for distinguishing adjacent programming states. In this case, the optimal read voltage for distinguishing adjacent programming states can be the second search voltage Vs2.

[0142] Reference Figure 11 In the graph on the right, at the reference evaluation time point `eval_def`, the voltage on the bit line connected to the memory cell in the second segment C2 can be less than the reference voltage `Vref`. That is, when the voltage on the bit line connected to the memory cell in the second segment C2 is sensed at the reference evaluation time point `eval_def`, the memory cell in the second segment C2 can be identified as an on cell. However, at the first evaluation time point `eval_1`, the voltage on the bit line connected to the memory cell in the second segment C2 can be greater than the reference voltage `Vref`. That is, when the voltage on the bit line connected to the memory cell in the second segment C2 is sensed at the first evaluation time point `eval_1`, which is earlier than the reference evaluation time point `eval_def`, the memory cell in the second segment C2 can be identified as an off cell.

[0143] In other words, when the difference between the first number of valley cells and the second number of valley cells is greater than the number of reference cells, the memory device 100 can determine the length of the evaluation period to be shorter than the reference period. Figure 10 The second evaluation period is described in the first evaluation period. The second evaluation period can be the period from the time when the voltage of the bit line decreases to the first evaluation time point eval_1. The memory device 100 can obtain the same effect as obtaining the data stored in the memory cell by sensing the voltage of the bit line after the second evaluation period.

[0144] Figure 12 This is a diagram illustrating yet another embodiment of the evaluation period determined based on a read operation of the memory device.

[0145] exist Figure 12In the graph shown on the left, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells (#). Figure 12 In the graph shown on the right, the horizontal axis represents time (Time), and the vertical axis represents voltage (V). (Referring to...) Figure 12 The description omits the related terms. Figure 10 and Figure 11 The content is repeated.

[0146] Reference Figure 12 The memory device 100 can determine the length of the evaluation period based on a comparison of a first number of valley cells and a second number of valley cells. The first number of valley cells can be the number of memory cells in the third segment C3. The second number of valley cells can be the number of memory cells in the second segment C2. When the difference between the second number of valley cells and the first number of valley cells is greater than the number of reference cells, the memory device 100 can change the length of the evaluation period. That is, when the second number of valley cells is greater than the first number of valley cells and the difference between the first number of valley cells and the second number of valley cells is large, the memory device 100 can determine that the read voltage Vr is not the optimal read voltage for distinguishing adjacent programming states. In this case, the optimal read voltage for distinguishing adjacent programming states can be the first search voltage Vs1.

[0147] Reference Figure 12 In the graph on the right, at the reference evaluation time point `eval_def`, the voltage on the bit line connected to the memory cell in the third segment C3 can be greater than the reference voltage `Vref`. That is, when the voltage on the bit line connected to the memory cell in the third segment C3 is sensed at the reference evaluation time point `eval_def`, the memory cell in the third segment C3 can be identified as an off cell. However, at the second evaluation time point `eval_2`, the voltage on the bit line connected to the memory cell in the third segment C3 can be less than the reference voltage `Vref`. That is, when the voltage on the bit line connected to the memory cell in the third segment C3 is sensed at the second evaluation time point `eval_2`, which is later than the reference evaluation time point `eval_def`, the memory cell in the third segment C3 can be identified as an on cell.

[0148] In other words, when the difference between the second number of valley cells and the first number of valley cells is greater than the number of reference cells, the memory device can determine the length of the evaluation period as greater than the reference number. Figure 10The description describes a third evaluation period that is longer than the first evaluation period. The third evaluation period can be a time interval from the time when the bit line voltage decreases to the second evaluation time point. The memory device 100 can obtain the same effect as obtaining data stored in the memory cell by sensing the bit line voltage after the third evaluation period.

[0149] Figure 13 This is a diagram illustrating another embodiment of the read operation of a memory device.

[0150] In reference Figure 13 In the description, the omission of and Figure 9 The content is repeated. (Refer to...) Figure 13 The read operation of the memory device may include an initialization period and a first read period (Read1).

[0151] During time period t1 to t2, memory device 100 can apply an equalization voltage Veq to a selected word line Sel_WL.

[0152] During time periods t2 to t4, the voltage of the selected word line can decrease from the equalization voltage Veq to the first search voltage Vs1, and then to the second search voltage Vs2. In one implementation, the selected word line Sel_WL can be a word line Sel_WL that is physically close to the address decoder (near) or a word line Sel_WL that is physically far from the address decoder (far). For example, refer to... Figure 5 When the selected word line Sel_WL is the first word line WL1, the word line Sel_WL (near) that is physically closer to the address decoder can be the word line in the first word line that connects to the 11th memory cell string CS11' and the 1m memory cell string CS1m'. The word line Sel_WL (far) that is physically farther from the address decoder can be the word line in the first word line that connects to the 21st memory cell string CS21' and the 2m memory cell string CS2m'.

[0153] During time intervals t2 to t4, the degree of voltage reduction for word lines physically closer to the address decoder (Sel_WL(near)) and the degree of voltage reduction for word lines physically farther from the address decoder (Sel_WL(far)) can differ.

[0154] Specifically, during time periods t2 to t3, the memory device 100 may apply a first search voltage Vs1, less than the equalization voltage Viq, to ​​the selected word line Sel_WL. During time periods t2 to t3, the voltage of the word line Sel_WL (near) the address decoder, which is physically close to it, may remain at the magnitude of the first search voltage Vs1 for a predetermined period. The memory device 100 may perform a first sensing operation S1 at time point t3 when the voltage of the selected word line decreases from the equalization voltage Viq to the first search voltage Vs1. The memory device 100 may count the first number of active cells identified by the first search voltage Vs1 in the selected memory cell at time point t3.

[0155] During time periods t3 to t4, memory device 100 may apply a second search voltage Vs2, which is less than the first search voltage Vs1, to the selected word line Sel_WL. During time periods t3 to t4, the voltage of the word line Sel_WL (near) the address decoder at a physical distance may be maintained at the magnitude of the second search voltage Vs2 for a predetermined period of time.

[0156] The memory device 100 can perform a second sensing operation S2 at time point t4 when the voltage of the selected word line Sel_WL decreases from the first search voltage Vs1 to the second search voltage Vs2. The memory device 100 can also count the second number of conducting cells identified by the second search voltage Vs2 in the selected memory cell at time point t4.

[0157] During time intervals t2 to t4, the voltage of the word line Sel_WL (far) that is physically far from the address decoder can be sequentially reduced from the equalization voltage Veq to the second search voltage Vs2.

[0158] During time intervals t4 and t5, the memory device 100 may apply a read voltage Vr greater than the second search voltage Vs2 to the selected word line Sel_WL. The memory device may perform a third sensing operation S3 at time point t5 when the voltage of the selected word line increases from the second search voltage Vs2 to the read voltage Vr. At time point t5, the memory device 100 may count a third number of active cells identified by the read voltage Vr in the selected memory cell.

[0159] In one embodiment, the memory device 100 may apply an equalization voltage Veq to a selected word line, perform a first sensing operation S1 after applying a first search voltage Vs1, perform a second sensing operation S2 after applying a second search voltage Vs2, and perform a third sensing operation S3 after applying a read voltage Vr. In one embodiment, the memory device 100 may perform sensing operations only on selected memory cells connected to word lines Sel_WL (near) that are physically close to the address decoder, thereby preventing prolonged read operation time. Furthermore, the memory device 100 may perform sensing operations on selected memory cells when the magnitude of the voltage on the word line Sel_WL (near) that is physically close to the address decoder is stable at each of the first search voltage Vs1, the second search voltage Vs2, and the read voltage Vr.

[0160] In one implementation, the difference ΔV1 between the first search voltage and the read voltage can be the same as the difference ΔV2 between the read voltage and the second search voltage.

[0161] The time period t6 to t7 can be an evaluation period. The memory device 100 can perform a fourth sensing operation S4 after the evaluation period in which the voltage of the bit line changes to a voltage lower than the pre-charge voltage. The memory device 100 can determine the length of the evaluation period based on the result of comparing the number of conducting cells identified by the first sensing operation S1, the second sensing operation S2, and the third sensing operation S3, respectively.

[0162] In one embodiment, when the difference between the first number of valley cells and the second number of valley cells is less than the number of reference cells, the memory device 100 can determine the length of the evaluation period as a first period. The first number of valley cells is the difference between the first number of conducting cells identified by the first search voltage Vs1 and the second number of conducting cells identified by the read voltage Vr, and the second number of valley cells is the difference between the second number of conducting cells and the third number of conducting cells identified by the second search voltage Vs2.

[0163] In one implementation, when the difference between the first number of valley cells and the second number of valley cells is greater than the number of reference cells, the memory device 100 can determine the length of the evaluation period as a second period shorter than the first period.

[0164] In one implementation, when the difference between the second number of valley cells and the first number of valley cells is greater than the number of reference cells, the memory device 100 can determine the length of the evaluation period as a third period that is longer than the first period.

[0165] In one embodiment, when the number of programming and erasing operations performed on the memory cells exceeds a preset number, the memory device 100 can determine the length of the evaluation period based on the number of conducting cells identified by the first search voltage Vs1, the second search voltage Vs2, and the read voltage Vr, respectively.

[0166] Figure 14 This is a diagram illustrating the read operation of a memory device using multiple read voltages.

[0167] Reference Figure 14 The read operation can include initialization of the initialization period, a first read period (Read1), and a second read period (Read2). The initialization period and the first read period (Read1) can be compared with a reference... Figure 9 The initialization period described is the same as the first read period (Read1). The second read period (Read2) can be a period that uses a different read voltage than the one used in the first read period (Read1) to obtain the data stored in the memory cell. For example, refer to... Figure 7 When performing a read operation on a CSB page, the read voltage used in the first read period Read1 can be the seventh read voltage Vr7, and the read voltage used in the second read period Read2 can be the third read voltage Vr3, which is less than the seventh read voltage Vr7.

[0168] In one embodiment, during the second read period Read2, the memory device 100 can obtain data stored in the memory cell by comparing the voltage of the bit line with a reference voltage after an evaluation period of equal length to the evaluation period determined in the first read period Read1.

[0169] In one embodiment, during the second read period (Read2), the memory device 100 may determine the length of the evaluation period included in the second read period based on a comparison of the number of conducting cells identified by a third search voltage greater than the read voltage used in the second read period (Read2), a fourth search voltage less than the read voltage, and the read voltage used in the second read period (Read2) as the voltage of the selected word line decreases to the read voltage used in the second read period (Read2). The difference between the magnitude of the third search voltage and the magnitude of the read voltage used in the second read period (Read2) may be the same as the difference between the magnitude of the read voltage used in the second read period (Read2) and the magnitude of the fourth search voltage.

[0170] In one embodiment, the read operation may further include a third read period following the second read period Read2. The third read period may be a period in which data stored in the memory cell is obtained using a read voltage different from the read voltage used in the first read period Read1 and the second read period Read2. During the third read period, the memory device 100 may determine the length of the evaluation period in the same way as the first read period Read1 or the second read period Read2.

[0171] Figure 15 This is a flowchart illustrating a read operation of a memory device.

[0172] Reference Figure 15 In step S1501, the memory device 100 can use an equalization voltage to initialize the channel region of the memory cell.

[0173] In step S1503, the memory device 100 can count the number of conducting cells in the memory cell that are identified by the first search voltage, the second search voltage, and the read voltage. The magnitude of the first search voltage can be greater than the read voltage. The magnitude of the second search voltage can be less than the read voltage.

[0174] In step S1505, the memory device 100 may determine the length of an evaluation period for sensing the voltage of the bit line connected to the memory cell based on a comparison of the number of active cells identified by the first search voltage, the second search voltage, and the read voltage. The memory device 100 may determine the length of the evaluation period differently depending on whether the difference between a first number of valley cells and a second number of valley cells is less than the number of reference cells. The first number of valley cells is the difference between the first number of active cells identified by the first search voltage and the second number of active cells identified by the read voltage, and the second number of valley cells is the difference between the second number of active cells and a third number of active cells identified by the second search voltage.

[0175] In step S1507, the memory device 100 may acquire data stored in the memory cell during the evaluation period. The memory device 100 may acquire the data stored in the memory cell based on the result of comparing the voltage of the bit line connected to the memory cell with a reference voltage.

[0176] Cross-reference to related applications

[0177] This application claims priority to Korean Patent Application No. 10-2022-0090045, filed on July 21, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A memory cell connected to multiple word lines; A read operation actuator performs a read operation that applies an equalization voltage to the plurality of word lines and a read voltage to a selected word line among the plurality of word lines; A failure cell counter counts the number of active cells in a selected memory cell connected to the selected word line at each of the following time points: a first time point after a predetermined time has elapsed since the time when the read voltage was applied, a second time point after a predetermined time has elapsed since the first time point, and a third time point when the voltage of the selected word line reaches the read voltage. as well as A read operation controller controls the read operation actuator to determine the length of an evaluation period during the read operation based on a comparison of the number of on-cells at the first, second, and third time points, and senses the voltages of the bit lines connected to the selected memory cells after the evaluation period has elapsed from the time when the voltage of the selected word line reaches the read voltage.

2. The memory device according to claim 1, wherein, The read operation controller controls the read operation actuator to obtain the data stored in the selected memory cell based on the result of comparing the voltage of the bit line with the reference voltage after the evaluation period.

3. The memory device according to claim 2, wherein, The voltage of the selected word line at the second time point is less than the read voltage.

4. The memory device according to claim 3, wherein, When the difference between the first number of valley units and the second number of valley units is less than the number of reference units, the read operation controller determines the length of the evaluation period as a first period. The first number of valley units is the difference between the first number of conducting units identified at the first time point and the second number of conducting units identified at the third time point, and the second number of valley units is the difference between the second number of conducting units and the third number of conducting units identified at the second time point.

5. The memory device according to claim 4, wherein, When the difference between the first number of valley units and the second number of valley units is greater than the number of reference units, the read operation controller determines the length of the evaluation period to be a second period shorter than the first period.

6. The memory device according to claim 4, wherein, When the difference between the second number of valley units and the first number of valley units is greater than the number of reference units, the read operation controller determines the length of the evaluation period to be a third period longer than the first period.

7. The memory device according to claim 2, wherein, The read operation controller controls the read operation executor to obtain the data stored in the selected memory cell after the evaluation period during subsequent read operations following the read operation.

8. The memory device according to claim 1, wherein, The difference between the magnitude of the selected word line voltage and the magnitude of the read voltage at the first time point is the same as the difference between the magnitude of the read voltage and the magnitude of the selected word line voltage at the second time point.

9. The memory device according to claim 1, wherein, The read operation controller controls the read operation executor to sense the voltage of the bit line after an evaluation period determined based on the result of comparing the number of the number of the selected memory cell when the number of programming and erasing operations performed on the selected memory cell is greater than a preset number.

10. The memory device according to claim 1, wherein, The selected memory cell is the memory cell that is physically closer to the address decoder that provides the read voltage to the selected word line compared to the other memory cells in the memory cell.

11. A method of operating a memory device, the method comprising the steps of: Perform a read operation by applying an equalization voltage to multiple word lines and applying a read voltage to a selected word line among the multiple word lines; At each of the following time points, namely a first time point when the voltage of the selected word line reaches a first search voltage lower than the equalization voltage, a second time point when the voltage of the selected word line reaches a second search voltage lower than the first search voltage, and a third time point when the voltage of the selected word line reaches the read voltage higher than the second search voltage, the number of conducting cells in the selected memory cell connected to the selected word line is counted. as well as The length of the evaluation period is determined based on a comparison of the number of the conducting cells at the first time point, the second time point, and the third time point, and the voltages of the bit lines connected to the selected memory cells are sensed after the evaluation period has elapsed from the time when the voltage of the selected word line reaches the read voltage.

12. The method according to claim 11, wherein, The step of sensing the voltage of the bit line includes the following steps: obtaining data stored in the selected memory cell based on the result of comparing the voltage of the bit line with a reference voltage.

13. The method according to claim 12, wherein, When the difference between the first number of valley units and the second number of valley units is less than the number of reference units, the length of the evaluation period is determined as the first period. The first number of valley units is the difference between the first number of conducting units identified by the first search voltage and the second number of conducting units identified by the read voltage, and the second number of valley units is the difference between the second number of conducting units and the third number of conducting units identified by the second search voltage.

14. The method according to claim 13, wherein, The step of determining the length of the evaluation period includes the following steps: when the difference between the first number of valley units and the second number of valley units is greater than the number of reference units, the length of the evaluation period is determined to be a second period shorter than the first period.

15. The method according to claim 13, wherein, The step of determining the length of the evaluation period includes the following steps: when the difference between the second number of valley units and the first number of valley units is greater than the number of reference units, the length of the evaluation period is determined to be a third period that is longer than the first period.

16. The method according to claim 12, wherein, During subsequent read operations following the read operation, data stored in the selected memory cell is obtained after the evaluation period has elapsed.

17. The method according to claim 11, wherein, The difference between the magnitude of the first search voltage and the magnitude of the read voltage is the same as the difference between the magnitude of the read voltage and the magnitude of the second search voltage.

18. A memory device, the memory device comprising: A memory cell connected to multiple word lines; A read operation executor performs a read operation that applies an equalization voltage to the plurality of word lines and applies a first search voltage less than the equalization voltage, a second search voltage less than the first search voltage, and a read voltage greater than the second search voltage to a selected word line among the plurality of word lines; A failure cell counter, which counts the number of conducting cells in selected memory cells connected to the selected word line that are identified by the first search voltage, the second search voltage, and the read voltage; as well as A read operation controller controls the read operation actuator to sense the voltages of the bit lines connected to the selected memory cell during the read operation, after an evaluation period determined based on a comparison of the number of each identified conducting cell, starting from the time when the voltage of the selected word line reaches the read voltage.

19. The memory device according to claim 18, wherein, The read operation controller determines the length of the evaluation period based on the difference between a first number of valley units and a second number of valley units compared to the number of reference units. The first number of valley units is the difference between a first number of conducting units identified by the first search voltage and a second number of conducting units identified by the read voltage. The second number of valley units is the difference between the second number of conducting units and a third number of conducting units identified by the second search voltage.

20. The memory device according to claim 19, wherein, The read operation controller controls the read operation actuator to obtain the data stored in the selected memory cell based on the result of comparing the voltage of the bit line with the reference voltage after the evaluation period.

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