Dual-sided optoelectronic interconnect package structure and method of making same

Abstract

The application provides a double-sided photoelectric interconnection packaging structure and a preparation method thereof. A double-sided composite functional chip is prepared, so that the double-sided composite functional chip has a composite optical waveguide wiring layer inside to combine an optical chip for optical transmission. Circuit areas on the upper and lower sides of the composite optical waveguide wiring layer in the double-sided composite functional chip combine metal connecting pieces with the optical chip and a rewiring layer for electrical transmission, so that photoelectric interconnection integration is realized, the packaging size is reduced, power consumption is lowered, reliability is improved, the structure is suitable for high-density integrated packaging, and good photoelectric signal transmission can be realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to a double-sided optoelectronic interconnect packaging structure and its preparation method. Background Technology

[0002] With the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communication, global data traffic is growing explosively. Lower cost, more reliable, faster, and higher density circuits are the goals pursued by integrated circuit packaging.

[0003] In semiconductor packaging structures, functional chips such as ASIC (Application Specific Integrated Circuit) chips and HBM (High Bandwidth Memory) chips are usually placed on RDL (Re-distribution Layer) and are electrically connected and communicate signals through RDL. However, the electrical connection and signal communication between functional chips through RDL may lead to signal distortion due to the length and distribution of the transmission path.

[0004] Because light possesses excellent properties such as low signal attenuation, low power consumption, high bandwidth, and compatibility with CMOS, the industry generally believes that introducing optical technology into semiconductor manufacturing processes can reduce chip size, lower costs and power consumption, and improve reliability. Functional chips can be coupled optically via fiber optics using edge coupling. However, as chip spacing decreases, the application of fiber optic coupling has become limited.

[0005] Therefore, it is necessary to provide a double-sided optoelectronic interconnect packaging structure and its fabrication method. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a double-sided optoelectronic interconnect packaging structure and its preparation method, so as to solve the signal transmission problem between functional chips in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a double-sided optoelectronic interconnect packaging structure, comprising the following steps:

[0008] A first wafer-level electrical chip and a second wafer-level electrical chip are provided. The first wafer-level electrical chip includes a first circuit region located at the top and a first substrate region located at the bottom. The second wafer-level electrical chip includes a second circuit region located at the top and a second substrate region located at the bottom.

[0009] The first wafer-level electrical chip is patterned to form a first groove in the first substrate region, and the second wafer-level electrical chip is patterned to form a second groove in the second substrate region;

[0010] A first optical waveguide wiring layer is formed in the first groove, and a second optical waveguide wiring layer is formed in the second groove;

[0011] The first wafer-level electrical chip and the second wafer-level electrical chip are bonded together, and the first optical waveguide wiring layer and the second optical waveguide wiring layer are connected to form a composite optical waveguide wiring layer;

[0012] A first metal connector is formed on the surface of the first circuit area and is electrically connected to the first circuit area; a second metal connector is formed on the surface of the second circuit area and is electrically connected to the second circuit area.

[0013] Cutting is performed to form a double-sided composite functional chip, and in the double-sided composite functional chip, an adhesive layer is formed on the surface of the first circuit area to expose the first metal connector.

[0014] A support substrate with a separation layer on its surface is provided, metal pillars are formed on the separation layer, and the double-sided composite functional chip is bonded to the separation layer by the adhesive layer;

[0015] An encapsulation layer is formed, which covers the metal pillar, the double-sided composite functional chip and the separation layer, and exposes the second end of the metal pillar and the second metal connector;

[0016] A second redistribution layer is formed on the encapsulation layer, and the second redistribution layer is electrically connected to the second end of the metal pillar and the second metal connector;

[0017] Remove the separation layer and the supporting substrate to expose the first end of the metal pillar and the first metal connector.

[0018] A first redistribution layer is formed on the encapsulation layer, and the first redistribution layer is electrically connected to the first end of the metal pillar and the first metal connector.

[0019] Patterning is performed from the first rewiring layer to form a first waveguide port exposing the composite optical waveguide wiring layer, and patterning is performed from the second rewiring layer to form a second waveguide port exposing the composite optical waveguide wiring layer.

[0020] A first optical chip and a second optical chip are provided. The first optical chip is bonded to the first redistribution layer, and the second optical chip is bonded to the second redistribution layer. The first optical chip is electrically connected to the first redistribution layer. The first photosensitive area of ​​the first optical chip is correspondingly disposed with the first waveguide optical port. The second optical chip is electrically connected to the second redistribution layer, and the second photosensitive area of ​​the second optical chip is correspondingly disposed with the second waveguide optical port.

[0021] Optionally, the composite optical waveguide wiring layer has an axisymmetric pattern along the bonding surface or an asymmetric pattern along the bonding surface.

[0022] Optionally, the method further includes the step of forming a first light-shielding protective layer covering the bottom and sidewalls of the first groove; and / or the method further includes the step of forming a second light-shielding protective layer covering the bottom and sidewalls of the second groove.

[0023] Optionally, the method for forming the first light-shielding protective layer includes a semiconductor exposure and development method, wherein the first light-shielding protective layer formed includes a metallic first light-shielding protective layer or an organic-inorganic composite first light-shielding protective layer; the method for forming the second light-shielding protective layer includes a semiconductor exposure and development method, wherein the second light-shielding protective layer formed includes a metallic second light-shielding protective layer or an organic-inorganic composite second light-shielding protective layer.

[0024] Optionally, the method for forming the first optical waveguide wiring layer includes a semiconductor exposure and development method, and the first optical waveguide wiring layer formed includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer; the method for forming the second optical waveguide wiring layer includes a semiconductor exposure and development method, and the second optical waveguide wiring layer formed includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.

[0025] Optionally, the method for cutting to form the double-sided composite functional chip includes mechanical cutting or laser cutting.

[0026] Optionally, the method further includes the step of forming a third metal connector electrically connected to the first redistribution layer and / or the second redistribution layer.

[0027] The present invention also provides a double-sided optoelectronic interconnect packaging structure, the double-sided optoelectronic interconnect packaging structure comprising:

[0028] First redistribution layer and second redistribution layer;

[0029] A double-sided composite functional chip, located between a first redistribution layer and a second redistribution layer, includes a composite optical waveguide wiring layer, a first circuit area above the composite optical waveguide wiring layer, an adhesive layer, and a first metal connector electrically connected to both the first circuit area and the first redistribution layer, and a second circuit area below the composite optical waveguide wiring layer and a second metal connector electrically connected to both the second circuit area and the second redistribution layer;

[0030] A first waveguide port and a second waveguide port, wherein the first waveguide port exposes the composite optical waveguide wiring layer from the first redistribution layer, and the second waveguide port exposes the composite optical waveguide wiring layer from the second redistribution layer;

[0031] A metal pillar is located between the first redistribution layer and the second redistribution layer, with a first end of the metal pillar electrically connected to the first redistribution layer and a second end of the metal pillar electrically connected to the second redistribution layer.

[0032] An encapsulation layer is located between the first redistribution layer and the second redistribution layer, covering the metal pillar, the double-sided composite functional chip, the first redistribution layer, and the second redistribution layer;

[0033] A first optical chip and a second optical chip, wherein the first optical chip is bonded to and electrically connected to the first redistribution layer, and the second optical chip is bonded to and electrically connected to the second redistribution layer, wherein the first photosensitive area of ​​the first optical chip is correspondingly disposed to the first waveguide port, and the second photosensitive area of ​​the second optical chip is correspondingly disposed to the second waveguide port.

[0034] Optionally, it also includes a light-shielding protective layer covering the composite optical waveguide wiring layer.

[0035] Optionally, the composite optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.

[0036] As described above, the double-sided optoelectronic interconnect packaging structure and its fabrication method of the present invention, by fabricating a double-sided composite functional chip, enables the double-sided composite functional chip to have a composite optical waveguide wiring layer inside to combine with the optical chip for optical transmission. The circuit areas located on the upper and lower sides of the composite optical waveguide wiring layer in the double-sided composite functional chip are combined with metal connectors to conduct electrical transmission with the optical chip and the rewiring layer, thereby realizing optoelectronic interconnect integration, reducing package size, reducing power consumption, improving reliability, and being suitable for high-density integrated packaging, and can achieve good optoelectronic signal transmission. Attached Figure Description

[0037] Figure 1 The diagram shows a process flow diagram of the double-sided optoelectronic interconnect packaging structure in an embodiment of the present invention.

[0038] Figure 2 The diagram shown is a schematic diagram of the structure of the first wafer-level electrical chip in an embodiment of the present invention.

[0039] Figure 3 The diagram shown is a schematic representation of the structure after the first groove is formed in an embodiment of the present invention.

[0040] Figure 4 The diagram shown is a schematic representation of the structure after the formation of the first optical waveguide wiring layer in an embodiment of the present invention.

[0041] Figure 5 Displayed as Figure 4 A top-view structural diagram.

[0042] Figure 6 The diagram shown is a schematic diagram of the structure of a second wafer-level electrical chip having a second optical waveguide wiring layer in an embodiment of the present invention.

[0043] Figure 7 The diagram shown is a schematic representation of the structure after bonding the first wafer-level electrical chip and the second wafer-level electrical chip in an embodiment of the present invention.

[0044] Figure 8 The diagram shown is a schematic representation of the structure of a double-sided composite functional chip after being cut in an embodiment of the present invention.

[0045] Figure 9 The diagram shown is a schematic representation of a support substrate with a separation layer in an embodiment of the present invention.

[0046] Figure 10 The diagram shows the structure of the metal pillar and the bonded double-sided composite functional chip in an embodiment of the present invention.

[0047] Figure 11 The diagram shown is a schematic representation of the structure after the encapsulation layer is formed in an embodiment of the present invention.

[0048] Figure 12 The diagram shown is a schematic representation of the structure after the formation of the second redistribution layer in an embodiment of the present invention.

[0049] Figure 13 The diagram shown is a schematic representation of the structure after the first redistribution layer is formed in an embodiment of the present invention.

[0050] Figure 14 The diagram shown is a schematic representation of the structure after the formation of the first waveguide port and the second waveguide port in an embodiment of the present invention.

[0051] Figure 15The diagram shows the structure after bonding the first optical chip and the second optical chip in an embodiment of the present invention.

[0052] Component designation explanation

[0053] 100 - Double-sided composite functional chip; 101 - First wafer-level electrical chip; 101a - First circuit region; 101b - First substrate region; 102 - First pad; 103 - First groove; 104 - First optical waveguide wiring layer; 105 - First metal connector; 201 - Second wafer-level electrical chip; 201a - Second circuit region; 201b - Second substrate region; 202 - Second pad; 204 - Second optical waveguide wiring layer; 205 - Second metal connector Connector; 301-Composite optical waveguide wiring layer; 200-Support substrate; 300-Separation layer; 400-Metal pillar; 401-Adhesive layer; 500-Encapsulation layer; 610-First redistribution layer; 620-Second redistribution layer; 710-First waveguide port; 720-Second waveguide port; 810-First optical chip; 811-First photosensitive area; 820-Second optical chip; 821-Second photosensitive area; 900-Third metal connector. Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0056] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0057] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] like Figure 1 This embodiment provides a method for fabricating a double-sided optoelectronic interconnect packaging structure. By fabricating a double-sided composite functional chip, a composite optical waveguide wiring layer is formed inside the double-sided composite functional chip to combine with the optical chip for optical transmission. The circuit areas located on the upper and lower sides of the composite optical waveguide wiring layer in the double-sided composite functional chip are connected with metal connectors to conduct electrical transmission with the optical chip and the circuit board, thereby realizing optoelectronic interconnect integration, reducing package size, reducing power consumption, improving reliability, and being suitable for high-density integrated packaging, which can achieve good optoelectronic signal transmission.

[0059] The following is in conjunction with the appendix Figures 2 to 15 The fabrication of the aforementioned double-sided optoelectronic interconnect packaging structure is further described, specifically including:

[0060] First, refer to Figure 1 , Figure 2 and Figure 6 In step S1, a first wafer-level electrical chip 101 and a second wafer-level electrical chip 201 are provided. The first wafer-level electrical chip 101 includes a first circuit region 101a at the top and a first substrate region 101b at the bottom. The second wafer-level electrical chip 201 includes a second circuit region 201a at the top and a second substrate region 201b at the bottom.

[0061] Specifically, the dimensions of the first wafer-level electrical chip 101 and the second wafer-level electrical chip 201 may include, for example, 4 inches, 6 inches, 8 inches, 12 inches, etc. The dimensions of the first wafer-level electrical chip 101 and the second wafer-level electrical chip 201 are not limited to these and can be selected as needed.

[0062] The specific types of the first wafer-level electrical chip 101 and the second wafer-level electrical chip 201 can be selected as needed. The first circuit region 101a is disposed on the top of the first wafer-level electrical chip 101 for electrical signal transmission. The first substrate region 101b of the first wafer-level electrical chip 101 can provide space for the subsequent fabrication of the first optical waveguide wiring layer 104. Similarly, the second circuit region 201a is disposed on the top of the second wafer-level electrical chip 201 for electrical signal transmission. The second substrate region 201b of the second wafer-level electrical chip 201 can provide space for the subsequent fabrication of the second optical waveguide wiring layer 204.

[0063] Figure 2 and Figure 6 The diagram only shows the first pad 102 for electrical lead-out in the first circuit area 101a and the second pad 202 for electrical lead-out in the second circuit area 201a. The configuration of the metal wiring layer in the first circuit area 101a and the second circuit area 201a is not shown.

[0064] Next, refer to Figure 1 , Figure 3 and Figure 6 In step S2, the first wafer-level electrical chip 101 is graphically depicted forming a first groove 103 in the first substrate region 101b, and the second wafer-level electrical chip 201 is graphically depicted forming a second groove (not shown) in the second substrate region 201b.

[0065] Specifically, the bottom non-circuit area of ​​the first wafer-level electrical chip 101 can be patterned using semiconductor photolithography to form a reserved channel, i.e., the first groove 103, for the fabrication of the first optical waveguide wiring layer 104. Similarly, the bottom non-circuit area of ​​the second wafer-level electrical chip 201 can be patterned using semiconductor photolithography to form a reserved channel, i.e., the second groove, for the fabrication of the second optical waveguide wiring layer 204. The morphology of the first groove 103 and the second groove can be selected as needed, and no excessive restrictions are imposed here.

[0066] Next, refer to Figure 1 , Figure 4 and Figure 6 Step S3 is executed, in which a first optical waveguide wiring layer 104 is formed in the first groove 103, and a second optical waveguide wiring layer 204 is formed in the second groove.

[0067] As an example, the method for forming the first optical waveguide wiring layer 104 may include a semiconductor exposure and development method. The first optical waveguide wiring layer 104 formed may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer, etc. For example, the material of the organic polymer optical waveguide wiring layer may be polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC) epoxy resin, fluorinated polyimide, etc. The method for forming the second optical waveguide wiring layer 204 may include a semiconductor exposure and development method. The second optical waveguide wiring layer 204 formed may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer, etc. For example, the material of the organic polymer optical waveguide wiring layer may be polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC) epoxy resin, fluorinated polyimide, etc.

[0068] Figure 5 It indicated Figure 4 The top view of the structure is shown. The material, distribution and fabrication of the first optical waveguide wiring layer 104 and the second optical waveguide wiring layer 204 are not subject to excessive restrictions here.

[0069] Furthermore, it may also include the step of forming a first light-shielding protective layer (not shown) covering the bottom and sidewalls of the first groove 103; and / or may also include the step of forming a second light-shielding protective layer (not shown) covering the bottom and sidewalls of the second groove, so as to protect the corresponding optical waveguide wiring layer formed by the first light-shielding protective layer and / or the second light-shielding protective layer, so as to reduce light loss.

[0070] The method for forming the first light-shielding protective layer may include a semiconductor exposure and development method. The first light-shielding protective layer formed may include a metal first light-shielding protective layer, such as copper, gold, aluminum, silver, platinum, titanium, etc., or the first light-shielding protective layer formed may be an organic-inorganic composite first light-shielding protective layer, etc., so as to cover the first optical waveguide wiring layer 104 through the first light-shielding protective layer to reduce light loss.

[0071] Similarly, the method for forming the second light-shielding protective layer may include semiconductor exposure and development method. The formed second light-shielding protective layer may include a metal second light-shielding protective layer, such as copper, gold, aluminum, silver, platinum, titanium, etc., or the formed second light-shielding protective layer may be an organic-inorganic composite second light-shielding protective layer, etc., so as to cover the second optical waveguide wiring layer 204 through the second light-shielding protective layer to reduce light loss.

[0072] Next, refer to Figure 1 and Figure 7 In step S4, the first wafer-level electrical chip 101 and the second wafer-level electrical chip 201 are bonded together, and the first optical waveguide wiring layer 104 and the second optical waveguide wiring layer 204 are connected to form a composite optical waveguide wiring layer 301.

[0073] As an example, the composite optical waveguide wiring layer 301 may have an axisymmetric pattern along the bonding surface or an asymmetric pattern along the bonding surface.

[0074] For details, please refer to Figure 7In this embodiment, the first wafer-level electrical chip 101 and the second wafer-level electrical chip 201 preferably have the same structure before bonding, so that after bonding, the composite optical waveguide wiring layer 301 can have an axisymmetric pattern along the bonding surface. However, it is not limited to this. Depending on the requirements of the manufacturing process, in another embodiment, the first wafer-level electrical chip 101 and the second wafer-level electrical chip 201 may also have different morphologies, so that after bonding, the composite optical waveguide wiring layer 301 has an asymmetric pattern along the bonding surface. This is not an excessive limitation.

[0075] Next, refer to Figure 1 and Figure 8 In step S5, a first metal connector 105 is formed on the surface of the first circuit region 101a and electrically connected to the first circuit region 101a. A second metal connector 205 is formed on the surface of the second circuit region 201a and electrically connected to the second circuit region 201a.

[0076] For details, please refer to Figure 8 In this embodiment, both the first metal connector 105 and the second metal connector 205 adopt the structure of metal pillars. The first metal connector 105 is electrically connected to the first pad 102, and the second metal connector 205 is electrically connected to the second pad 202. The types of the first metal connector 105 and the second metal connector 205 are not limited to these. For example, they can also be metal bumps or composite structures of metal pillars and metal bumps. There are no excessive restrictions here, and they can be selected as needed.

[0077] Next, refer to Figure 1 and Figure 8 Step S6 is executed to cut the chip to form a double-sided composite functional chip 100. In the double-sided composite functional chip 100, an adhesive layer 401 is formed on the surface of the first circuit area 101a to expose the first metal connector 105.

[0078] As an example, the method for cutting to form the double-sided composite functional chip 100 may include mechanical cutting or laser cutting, which can be selected as needed.

[0079] Specifically, during the cutting process, a dual-film support structure (not shown) can be provided. The adhesive layer 401 is located on the surface of this dual-film support structure. During the cutting process, the adhesive layer 401 is also cut and separated, resulting in the surface of the separated double-sided composite functional chip 100 having the adhesive layer 401, facilitating subsequent bonding processes through the adhesive layer 401. The specific material of the dual-film support structure is not excessively limited here and can be selected as needed.

[0080] Next, refer to Figure 1 , Figure 9 and Figure 10 In step S7, a support substrate 200 with a separation layer 300 on its surface is provided, metal pillars 400 are formed on the separation layer 300, and the double-sided composite functional chip 100 is bonded to the separation layer 300 by the adhesive layer 401.

[0081] Specifically, the separation layer 300 may include, but is not limited to, adhesive tape and polymer layer. For example, the separation layer 300 may be a photothermal conversion layer, so that the separation layer 300 can be heated by means of a laser to remove the support substrate 200, thereby improving the ease of operation.

[0082] The order in which the metal pillars 400 are formed and the double-sided composite functional chip 100 is formed is not overly restricted and can be selected as needed. The metal pillars 400 can be made of metals such as copper, but are not limited to this. The method for preparing the metal pillars 400 is not limited here.

[0083] Next, refer to Figure 1 and Figure 11 Step S8 is executed to form an encapsulation layer 500, which covers the metal pillar 400, the double-sided composite functional chip 100 and the separation layer 300, and exposes the second end of the metal pillar 400 and the second metal connector 205.

[0084] Specifically, the encapsulation layer 500 can be made of commonly used epoxy resin, and the method of forming the encapsulation layer 500 can include molding, vacuum lamination and spin coating, etc. No restrictions are placed here on the material and forming method of the encapsulation layer 500.

[0085] After the encapsulation layer 500 is formed, grinding can be used to expose the second end of the metal pillar 400 and the second metal connector 205. The grinding process can reduce the thickness of the encapsulation layer 500 and obtain a flat surface. The grinding process can include chemical mechanical polishing (CMP), physical polishing, or a combination of physical polishing and CMP. No excessive limitation is made here.

[0086] Next, refer to Figure 1 and Figure 12 In step S9, a second redistribution layer 620 is formed on the encapsulation layer 500. The second redistribution layer 620 is electrically connected to the second end of the metal pillar 400 and the second metal connector 205.

[0087] Specifically, the second redistribution layer 620 includes an insulating dielectric layer and a metal wiring layer, through which electrical connections can be made. The specific materials, structure and fabrication of the second redistribution layer 620 are not excessively limited here and can be selected as needed.

[0088] Next, refer to Figure 1 and Figure 13 Step S10 is executed to remove the separation layer 300 and the support substrate 200, exposing the first end of the metal pillar 400 and the adhesive layer 401.

[0089] Specifically, when the separation layer 300 is a photothermal conversion layer, the separation layer 300 can be heated by laser or the like to remove the support substrate 200 and expose the first end of the metal pillar 400 and the adhesive layer 401.

[0090] Next, refer to Figure 1 and Figure 13 In step S11, a first redistribution layer 610 is formed on the encapsulation layer 500. The first redistribution layer 610 is electrically connected to the first end of the metal pillar 400 and the first metal connector 105.

[0091] Specifically, the first rewiring layer 610 includes an insulating dielectric layer and a metal wiring layer. Electrical connections can be made through the metal wiring layer. The specific materials, structure, and fabrication of the first rewiring layer 610 are not limited here and can be selected as needed.

[0092] Next, refer to Figure 1 and Figure 14 In step S12, the first rewiring layer 610 is patterned to form a first waveguide port 710 that exposes the composite optical waveguide wiring layer 400, and the second rewiring layer 620 is patterned to form a second waveguide port 720 that exposes the composite optical waveguide wiring layer 400.

[0093] As an example, a method for patterning the first waveguide port 710 and / or the second waveguide port 720 may include laser etching.

[0094] Specifically, the first redistribution layer 610, the second redistribution layer 620, and the adhesive layer 401 can be patterned using laser etching to form the first waveguide port 710 and the second waveguide port 720 of the composite optical waveguide wiring layer 400, thereby facilitating light transmission. The shape and size of the first waveguide port 710 and the second waveguide port 720 are not excessively limited here.

[0095] Next, refer to Figure 1 and Figure 15 In step S13, a first optical chip 810 and a second optical chip 820 are provided. The first optical chip 810 is bonded to the first redistribution layer 610, and the second optical chip 820 is bonded to the second redistribution layer 620. The first optical chip 810 is electrically connected to the first redistribution layer 610. The first photosensitive area 811 of the first optical chip 810 is correspondingly set to the first waveguide optical port 710. The second optical chip 820 is electrically connected to the second redistribution layer 620, and the second photosensitive area 821 of the second optical chip 820 is correspondingly set to the second waveguide optical port 720.

[0096] Specifically, the first optical chip 810 has an electrical lead-out terminal and a first photosensitive area 811, and the electrical lead-out terminal is electrically connected to the first redistribution layer 610. The first photosensitive area 811 is correspondingly disposed with the first waveguide optical port 710. The second optical chip 820 has an electrical lead-out terminal and a second photosensitive area 821, and the electrical lead-out terminal is electrically connected to the second redistribution layer 620. The second photosensitive area 821 is correspondingly disposed with the second waveguide optical port 720. Thus, the first optical chip 810 and the second optical chip 820 can transmit light through the composite optical waveguide wiring layer 301.

[0097] The types and sizes of the first optical chip 810 and the second optical chip 820 are not subject to excessive restrictions here.

[0098] Furthermore, such as Figure 15 It may also include the step of forming a third metal connector 900 electrically connected to the first redistribution layer 610 and / or the second redistribution layer 620, wherein the third metal connector 900 may include metal bumps, metal pillars, etc., which are not limited here.

[0099] Understandably, in order to increase production capacity, Figure 15 The double-sided optoelectronic interconnect packaging structure described above can be considered as a single-unit structure formed after a cutting process. Of course, depending on the needs, Figure 15 The double-sided optoelectronic interconnect packaging structure described herein can also be a single-unit structure that is directly prepared, and no excessive restrictions are imposed here.

[0100] See Figures 2 to 15 This embodiment also provides a double-sided optoelectronic interconnect packaging structure. The double-sided optoelectronic interconnect packaging structure can be directly prepared using the above-described preparation process. Therefore, the materials, preparation processes, etc. of the double-sided optoelectronic interconnect packaging structure can be found in the above content. Of course, the double-sided optoelectronic interconnect packaging structure can also be prepared using other preparation processes as needed.

[0101] Specifically, in this embodiment, the double-sided optoelectronic interconnect packaging structure includes: a first redistribution layer 610, a second redistribution layer 620, a double-sided composite functional chip 100, a first waveguide port 710, a second waveguide port 720, a metal pillar 400, a packaging layer 500, a first optical chip 810, and a second optical chip 820.

[0102] The dual-sided composite functional chip 100 is located between the first redistribution layer 610 and the second redistribution layer 620, and includes a composite optical waveguide wiring layer 301, a first circuit region 101a, an adhesive layer 401, and a first metal connector 105 electrically connected to both the first circuit region 101a and the first redistribution layer 610 located above the composite optical waveguide wiring layer 301, a second circuit region 201a, and a second metal connector 205 electrically connected to both the second circuit region 201a and the second redistribution layer 620 located below the composite optical waveguide wiring layer 301; a first waveguide port 710 exposes the composite optical waveguide wiring layer 301 from the first redistribution layer 610, and a second waveguide port 720 exposes the composite optical waveguide wiring layer 301 from the second redistribution layer 620; a metal pillar 400 is located between the first redistribution layer 610 and the second redistribution layer 620. Between 0 and 0, the first end of the metal pillar 400 is electrically connected to the first redistribution layer 610, and the second end of the metal pillar 400 is electrically connected to the second redistribution layer 620; the encapsulation layer 500 is located between the first redistribution layer 610 and the second redistribution layer 620, covering the metal pillar 400, the double-sided composite functional chip 100, the first redistribution layer 610 and the second redistribution layer 620; the first optical chip 810 is bonded to the first redistribution layer 610 and electrically connected to the first redistribution layer 610, the second optical chip 820 is bonded to the second redistribution layer 620 and electrically connected to the second redistribution layer 620, and the first photosensitive area 811 of the first optical chip 810 is correspondingly arranged with the first waveguide optical port 710, and the second photosensitive area 821 of the second optical chip 820 is correspondingly arranged with the second waveguide optical port 720, so as to perform optical transmission.

[0103] As an example, a light-shielding protective layer (not shown) may also be included covering the composite optical waveguide wiring layer 301.

[0104] The light-shielding protective layer may include a metal light-shielding protective layer, such as a metal light-shielding protective layer made of copper, gold, aluminum, silver, platinum, titanium, etc., or the light-shielding protective layer may be an organic-inorganic composite light-shielding protective layer, etc., so as to protect the composite optical waveguide wiring layer 301 through the light-shielding protective layer and reduce light loss.

[0105] As an example, the composite optical waveguide wiring layer 301 may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.

[0106] As an example, a third metal connector 900 electrically connected to the first redistribution layer 610 and / or the second redistribution layer 620 may also be included. The third metal connector 900 may include metal bumps, metal pillars, etc., which are not limited here.

[0107] In summary, the double-sided optoelectronic interconnect packaging structure and its fabrication method of the present invention, by fabricating a double-sided composite functional chip, enables the double-sided composite functional chip to have a composite optical waveguide wiring layer inside to combine with the optical chip for optical transmission. The circuit areas located on the upper and lower sides of the composite optical waveguide wiring layer in the double-sided composite functional chip are combined with metal connectors to conduct electrical transmission with the optical chip and the rewiring layer, thereby realizing optoelectronic interconnect integration, reducing package size, reducing power consumption, improving reliability, and being suitable for high-density integrated packaging, and can achieve good optoelectronic signal transmission.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a double-sided optoelectronic interconnect packaging structure, characterized in that, Includes the following steps: A first wafer-level electrical chip and a second wafer-level electrical chip are provided. The first wafer-level electrical chip includes a first circuit region located at the top and a first substrate region located at the bottom. The second wafer-level electrical chip includes a second circuit region located at the top and a second substrate region located at the bottom. The first wafer-level electrical chip is patterned to form a first groove in the first substrate region, and the second wafer-level electrical chip is patterned to form a second groove in the second substrate region; A first optical waveguide wiring layer is formed in the first groove, and a second optical waveguide wiring layer is formed in the second groove; The first wafer-level electrical chip and the second wafer-level electrical chip are bonded together, and the first optical waveguide wiring layer and the second optical waveguide wiring layer are connected to form a composite optical waveguide wiring layer; A first metal connector is formed on the surface of the first circuit area and is electrically connected to the first circuit area; a second metal connector is formed on the surface of the second circuit area and is electrically connected to the second circuit area. Cutting is performed to form a double-sided composite functional chip, and in the double-sided composite functional chip, an adhesive layer is formed on the surface of the first circuit area to expose the first metal connector. A support substrate with a separation layer on its surface is provided, metal pillars are formed on the separation layer, and the double-sided composite functional chip is bonded to the separation layer by the adhesive layer; An encapsulation layer is formed, which covers the metal pillar, the double-sided composite functional chip and the separation layer, and exposes the second end of the metal pillar and the second metal connector; A second redistribution layer is formed on the encapsulation layer, and the second redistribution layer is electrically connected to the second end of the metal pillar and the second metal connector; Remove the separation layer and the supporting substrate to expose the first end of the metal pillar and the first metal connector. A first redistribution layer is formed on the encapsulation layer, and the first redistribution layer is electrically connected to the first end of the metal pillar and the first metal connector. Patterning is performed from the first rewiring layer to form a first waveguide port exposing the composite optical waveguide wiring layer, and patterning is performed from the second rewiring layer to form a second waveguide port exposing the composite optical waveguide wiring layer. A first optical chip and a second optical chip are provided. The first optical chip is bonded to the first redistribution layer, and the second optical chip is bonded to the second redistribution layer. The first optical chip is electrically connected to the first redistribution layer. The first photosensitive area of ​​the first optical chip is correspondingly disposed with the first waveguide optical port. The second optical chip is electrically connected to the second redistribution layer, and the second photosensitive area of ​​the second optical chip is correspondingly disposed with the second waveguide optical port.

2. The method for fabricating the double-sided optoelectronic interconnect packaging structure according to claim 1, characterized in that: The composite optical waveguide wiring layer has an axisymmetric pattern along the bonding surface or an asymmetrical pattern along the bonding surface.

3. The method for fabricating the double-sided optoelectronic interconnect packaging structure according to claim 1, characterized in that: It also includes the step of forming a first light-shielding protective layer covering the bottom and sidewalls of the first groove; and / or the step of forming a second light-shielding protective layer covering the bottom and sidewalls of the second groove.

4. The method for fabricating the double-sided optoelectronic interconnect packaging structure according to claim 3, characterized in that: The method for forming the first light-shielding protective layer includes a semiconductor exposure and development method, and the first light-shielding protective layer formed includes a metallic first light-shielding protective layer or an organic-inorganic composite first light-shielding protective layer; the method for forming the second light-shielding protective layer includes a semiconductor exposure and development method, and the second light-shielding protective layer formed includes a metallic second light-shielding protective layer or an organic-inorganic composite second light-shielding protective layer.

5. The method for fabricating a double-sided optoelectronic interconnect packaging structure according to claim 1, characterized in that: The method for forming the first optical waveguide wiring layer includes a semiconductor exposure and development method, and the first optical waveguide wiring layer formed includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer; the method for forming the second optical waveguide wiring layer includes a semiconductor exposure and development method, and the second optical waveguide wiring layer formed includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.

6. The method for fabricating a double-sided optoelectronic interconnect packaging structure according to claim 1, characterized in that: The methods for cutting the double-sided composite functional chip include mechanical cutting or laser cutting.

7. The method for fabricating a double-sided optoelectronic interconnect packaging structure according to claim 1, characterized in that: It also includes the step of forming a third metal connector that is electrically connected to the first redistribution layer and / or the second redistribution layer.

8. A double-sided optoelectronic interconnect packaging structure, characterized in that, The double-sided optoelectronic interconnect packaging structure includes: First redistribution layer and second redistribution layer; A double-sided composite functional chip, located between a first redistribution layer and a second redistribution layer, includes a composite optical waveguide wiring layer, a first circuit area above the composite optical waveguide wiring layer, an adhesive layer, and a first metal connector electrically connected to both the first circuit area and the first redistribution layer, and a second circuit area below the composite optical waveguide wiring layer and a second metal connector electrically connected to both the second circuit area and the second redistribution layer; A first waveguide port and a second waveguide port, wherein the first waveguide port exposes the composite optical waveguide wiring layer from the first redistribution layer, and the second waveguide port exposes the composite optical waveguide wiring layer from the second redistribution layer; A metal pillar is located between the first redistribution layer and the second redistribution layer, with a first end of the metal pillar electrically connected to the first redistribution layer and a second end of the metal pillar electrically connected to the second redistribution layer. An encapsulation layer is located between the first redistribution layer and the second redistribution layer, covering the metal pillar, the double-sided composite functional chip, the first redistribution layer, and the second redistribution layer; A first optical chip and a second optical chip, wherein the first optical chip is bonded to and electrically connected to the first redistribution layer, and the second optical chip is bonded to and electrically connected to the second redistribution layer, wherein the first photosensitive area of ​​the first optical chip is correspondingly disposed to the first waveguide port, and the second photosensitive area of ​​the second optical chip is correspondingly disposed to the second waveguide port.

9. The double-sided optoelectronic interconnect packaging structure according to claim 8, characterized in that: It also includes a light-shielding protective layer covering the composite optical waveguide wiring layer.

10. The double-sided optoelectronic interconnect packaging structure according to claim 8, characterized in that: The composite optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.

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