Electrostatic discharge protection device and method of forming the same

Abstract

An electrostatic discharge protection device and a forming method thereof, wherein the structure comprises: a substrate, the substrate comprises a diode region and a lead-out region, both the diode region and the lead-out region have a well region, and the well region has a first conductive type; a plurality of first dummy gates on the diode region, the diode region on both sides of the first dummy gate has a first doped region, the first doped region has a second conductive type, and the first conductive type is opposite to the second conductive type; a plurality of second dummy gates on the lead-out region, the lead-out region on both sides of the second dummy gate has a second doped region, the second doped region has the first conductive type; a first conductive layer, a second conductive layer and a third conductive layer on the substrate, the first conductive layer is electrically connected with the plurality of first dummy gates and the first doped region, the second conductive layer is electrically connected with the second doped region, and the third conductive layer is electrically connected with the first conductive layer and the plurality of second dummy gates, a new parasitic capacitance is introduced, so that the overshoot voltage is reduced, and the influence on the response speed is small.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an electrostatic discharge protection device and its forming method. Background Technology

[0002] Electrostatic discharge (ESD) can damage the internal circuitry of components, directly affecting the product's lifespan and even causing complete destruction. Therefore, it is essential to incorporate ESD protection devices at the internal ports of a chip during the chip design process.

[0003] In the design of electrostatic discharge (ESD) protection devices, diodes are a common component. Low-capacitance diodes can achieve high-speed response, ensuring rapid discharge of static electricity. However, if the capacitance is too low, overshoot voltage can easily occur, leading to gate oxide failure of the protected circuitry.

[0004] Therefore, the performance of existing diode electrostatic discharge protection devices urgently needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide an electrostatic discharge protection device and a method for forming the same, so as to improve the performance of the formed electrostatic discharge protection device.

[0006] To solve the above-mentioned technical problems, the present invention provides an electrostatic discharge protection device, comprising: a substrate, the substrate including a diode region and a lead-out region, and an isolation structure located between the diode region and the lead-out region, wherein both the diode region and the lead-out region have a well region, and the well region has a first conductivity type; a plurality of first dummy gates located on the diode region, the first dummy gate sidewalls having first dummy gate sidewalls, the diode region on both sides of the first dummy gate having a first doped region, the first doped region having a second conductivity type, the first conductivity type being opposite to the second conductivity type; a plurality of second dummy gates located on the lead-out region, the second dummy gate sidewalls having second dummy gate sidewalls, the lead-out region on both sides of the second dummy gate having a second doped region, the second doped region having a first conductivity type; a first conductive layer, a second conductive layer, and a third conductive layer located on the substrate, the first conductive layer being electrically connected to the plurality of first dummy gates and the first doped region, the second conductive layer being electrically connected to the second doped region, and the third conductive layer being electrically connected to the first conductive layer and the plurality of second dummy gates.

[0007] Optionally, each of the first dummy gates has a first dummy gate oxide layer between it and the substrate; each of the second dummy gates has a second dummy gate oxide layer between it and the substrate.

[0008] Optionally, the plurality of first pseudo-gates and the plurality of second pseudo-gates are all arranged along the first direction.

[0009] Accordingly, the technical solution of the present invention also provides a method for forming an electrostatic discharge protection device, comprising: providing a substrate, the substrate including a diode region and a lead-out region, and an isolation structure located between the diode region and the lead-out region, wherein both the diode region and the lead-out region have well regions, and the well regions each have a first conductivity type; forming a plurality of first dummy gates, first dummy gate sidewalls of the first dummy gate sidewalls, and first doped regions within the diode region located on both sides of the first dummy gates on the diode region, wherein the first doped regions have a second conductivity type, and the first conductivity type is opposite to the second conductivity type; and forming in the lead-out region... A plurality of second dummy gates, second dummy gate sidewalls, and second doped regions located in the lead-out regions on both sides of the second dummy gates are formed on the substrate. The second doped regions have a first conductivity type. After forming the plurality of first dummy gates, the plurality of second dummy gates, the first doped regions, and the second doped regions, a first conductive layer, a second conductive layer, and a third conductive layer are formed on the substrate. The first conductive layer is electrically connected to the plurality of first dummy gates and the first doped regions, the second conductive layer is electrically connected to the second doped regions, and the third conductive layer is electrically connected to the first conductive layer and the plurality of second dummy gates.

[0010] Optionally, a first conductive plug is provided between the first conductive layer and the plurality of first dummy gates, and between the first conductive layer and the first doped region, wherein the first conductive layer, the plurality of first dummy gates, and the first doped region are electrically connected through the first conductive plug; a second conductive plug is provided between the second conductive layer and the second doped region, wherein the second conductive layer and the second doped region are electrically connected through the second conductive plug; and a third conductive plug is provided between the third conductive layer and the plurality of second dummy gates, wherein the third conductive layer and the plurality of second dummy gates are electrically connected through the third conductive plug.

[0011] Optionally, before forming the first conductive layer, the second conductive layer, and the third conductive layer, the method further includes forming a dielectric layer on the surfaces of the plurality of first dummy gates, the plurality of second dummy gates, the first doped region, and the second doped region.

[0012] Optionally, the method for forming the first conductive layer, the second conductive layer, and the third conductive layer includes: forming a first trench and a first via located below and communicating with the first trench in the dielectric layer, wherein the bottom of the first via exposes the top surface of the plurality of first dummy gates and the first doped region; forming a second trench and a second via located below and communicating with the second trench in the dielectric layer, wherein the bottom of the second via exposes the top surface of the second doped region; forming a third trench and a third via located below and communicating with the third trench in the dielectric layer, wherein the bottom of the third via exposes the top surface of the plurality of second dummy gates; forming a first conductive plug in the first via; forming the first conductive layer in the first trench; forming a second conductive plug in the second via; forming the second conductive layer in the second trench; forming the third conductive plug in the third via; and forming the third conductive layer in the third trench.

[0013] Optionally, each of the first dummy gates has a first dummy gate oxide layer between it and the substrate; each of the second dummy gates has a second dummy gate oxide layer between it and the substrate.

[0014] Optionally, the plurality of first pseudo-gates and the plurality of second pseudo-gates are all arranged along the first direction.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0016] In the electrostatic discharge protection device provided by this invention, a plurality of second dummy gates on the lead-out region are electrically connected to the first dummy gate and the first doped region of the diode region through a third conductive layer. This makes the plurality of second dummy gates have the same potential as the plurality of first dummy gates and the first doped region, increasing the parasitic capacitance between the well region and the third conductive layer, as well as the parasitic capacitance between the second dummy gates and the well region. In summary, without changing the existing manufacturing process and ensuring compatibility with it, and without altering the area of ​​the electrostatic discharge protection device, new parasitic capacitances are introduced by changing the metal trace layout, thereby reducing overshoot voltage with minimal impact on response speed.

[0017] Furthermore, each conductive layer is electrically connected to the doped region or dummy gate through several conductive plugs. For example, there is a second conductive plug between the second conductive layer and the second doped region. Especially in more advanced processes, the smaller the size of the dummy gate, the surrounding conductive plugs, and the metal conductive layer, the larger the new parasitic capacitance generated, which is more conducive to reducing overshoot voltage.

[0018] In the method for forming the electrostatic discharge protection device provided by the present invention, a plurality of second dummy gates on the lead-out region are electrically connected to the first dummy gate and the first doped region of the diode region through a third conductive layer. This makes the plurality of second dummy gates have the same potential as the plurality of first dummy gates and the first doped region, thereby increasing the parasitic capacitance between the well region and the third conductive layer, as well as the parasitic capacitance between the second dummy gates and the well region. In summary, without changing the existing manufacturing process and ensuring compatibility with it, and without changing the area of ​​the electrostatic discharge protection device, new parasitic capacitances are introduced by changing the metal trace layout, thereby reducing the overshoot voltage and having a minimal impact on the response speed. Attached Figure Description

[0019] Figure 1 This is a schematic cross-sectional view of an electrostatic discharge protection device.

[0020] Figure 2 This is a cross-sectional structural diagram of another electrostatic discharge protection device;

[0021] Figures 3 to 5 This is a schematic diagram of the structure corresponding to each step in the electrostatic discharge protection device formation method of this invention. Detailed Implementation

[0022] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0023] As described in the background section, the performance of existing electrostatic discharge (ESD) protection devices urgently needs improvement. This paper will now analyze and explain an existing ESD protection device.

[0024] Figure 1 This is a cross-sectional structural diagram of an electrostatic discharge protection device.

[0025] Please refer to Figure 1The electrostatic discharge protection device includes: a substrate 100, the substrate 100 including a diode region I, a lead-out region II, and an isolation region III located between the diode region I and the lead-out region II, the substrate 100 having a well region 101 having a first conductivity type; a plurality of first dummy gate structures located on the diode region I, the first dummy gate structures including a first dummy gate oxide layer 102 and a first dummy gate 103 located on the first dummy gate oxide layer 102; and a plurality of second dummy gate structures located on the lead-out region II, the second dummy gate structures including a second dummy gate oxide layer 104 and a second dummy gate located on the second dummy gate oxide layer 104. 105; a first doped region 106 located in the well region 101 on both sides of the first pseudo-gate structure, the first doped region 106 having a second conductivity type, the first conductivity type being opposite to the second conductivity type; a second doped region 107 located in the well region 101 on both sides of the second pseudo-gate structure, the second doped region 107 having a first conductivity type; an insulating layer 108 located in the isolation region III; a first conductive layer 109 and a second conductive layer 110 located on the substrate 100, the first conductive layer 109 being electrically interconnected with the plurality of first doped regions 106, and the second conductive layer 110 being interconnected with the plurality of second doped regions 107.

[0026] In the aforementioned electrostatic discharge protection device, a diode is formed between the first doped region 106 and the well region 101, and the second doped region 107 is used to lead out the diode current. The parasitic capacitance includes capacitance C1 between the first conductive layer 109 and the first dummy gate 103 in diode region I, and capacitance C2 between the first dummy gate 103 and the substrate 101. The total capacitance formed by the series connection of these two capacitors is C1*C2 / (C1+C2), resulting in a low total capacitance value.

[0027] Figure 2 This is a cross-sectional structural diagram of another electrostatic discharge protection device.

[0028] Please Figure 1 Based on this, continue to refer to Figure 2 In the electrostatic discharge protection device, the first conductive layer 109 is also electrically interconnected with the plurality of first dummy gates 103, and the second conductive layer 110 is also electrically interconnected with the plurality of second dummy gates 105.

[0029] In this embodiment, the first conductive layer 109 and the first dummy gate 103 are electrically connected, and the parasitic capacitance exists between the first dummy gate 103 and the substrate 101. Compared with the previous embodiment, the capacitance of the electrostatic discharge protection device is improved.

[0030] However, electrostatic discharge protection devices are usually formed together with other devices in a parasitic manner. Under the condition of being compatible with existing manufacturing processes, the parasitic capacitance sometimes still needs to be appropriately increased while ensuring the smallest possible area budget, in order to avoid voltage overshoot and failure of the gate oxide layer of the protected circuit device.

[0031] To address the aforementioned problems, this invention provides an electrostatic discharge (ESD) protection device and its formation method. A third conductive layer electrically connects a plurality of second dummy gates on the lead-out region to the first dummy gate and the first doped region of the diode region. This ensures that the plurality of second dummy gates have the same potential as the plurality of first dummy gates and the first doped region, thereby increasing the parasitic capacitance between the well region and the third conductive layer, as well as the parasitic capacitance between the second dummy gates and the well region. In summary, without altering existing manufacturing processes and while maintaining compatibility with existing processes, and without changing the area of ​​the ESD protection device, this invention introduces new parasitic capacitances by changing the metal trace layout, thereby reducing overshoot voltage with minimal impact on response speed.

[0032] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Figures 3 to 5 This is a schematic diagram of the structure corresponding to each step in the electrostatic discharge protection device formation method of this invention.

[0034] Please refer to Figure 3 A substrate 200 is provided, the substrate 200 including a diode region I and a lead-out region II, and an isolation structure 202 located between the diode region I and the lead-out region II, each of the diode region I and the lead-out region II having a well region 201, each of the well regions 201 having a first conductivity type.

[0035] The first conductivity type includes N-type and P-type. In this embodiment, the first conductivity type is P-type.

[0036] In this embodiment, the substrate 200 includes a substrate (not shown in the figure), a device layer (not shown in the figure) on the substrate, and a dielectric layer (not shown in the figure) on the surface of the substrate and the device layer. The device layer includes an isolation structure (not shown in the figure) and a device structure (not shown in the figure) located within the isolation structure. The device structure includes transistors, diodes, triodes, capacitors, inductors, or conductive structures, etc.

[0037] The diode region I is used to form a diode, and the lead-out region II is used to lead out the signal from the diode.

[0038] Specifically, the substrate 200 further includes an isolation region III located between the diode region I and the lead-out region II, and the isolation structure 202 is located within the isolation region III. The isolation structure 202 is made of silicon oxide and serves to isolate the diode region I and the lead-out region II.

[0039] Please refer to Figure 4 A plurality of first dummy gates 203, a first dummy gate sidewall (not shown in the figure) are formed on the diode region I, and a first doped region 204 located on both sides of the first dummy gate 203 within the diode region I. The first doped region 204 has a second conductivity type, which is opposite to the second conductivity type. A plurality of second dummy gates 205, a second dummy gate sidewall (not shown in the figure) are formed on the lead-out region II, and a second doped region 206 located on both sides of the second dummy gate 205 within the lead-out region II. The second doped region 206 has a first conductivity type.

[0040] The second conductivity type includes N-type and P-type. In this embodiment, the second conductivity type is N-type. The first doped region 204 and the well region 201 have different conductivity types, thereby forming a diode. Subsequently, several first doped regions 204 are connected to improve the diode area and the stability of diode performance while ensuring the uniformity of the doped regions.

[0041] The formation process of the first doped region 204 includes an epitaxial growth process; the formation process of the second doped region 206 also includes an epitaxial growth process. The smaller area of ​​each of the first doped regions 204 is beneficial for improving the uniformity of the first doped regions 204; the smaller area of ​​each of the second doped regions 206 is beneficial for improving the uniformity of the second doped regions 206.

[0042] In this embodiment, a first dummy gate oxide layer 207 is provided between each of the first dummy gates 203 and the substrate 200; a second dummy gate oxide layer 208 is provided between each of the second dummy gates 205 and the substrate 200.

[0043] In this embodiment, the plurality of first pseudo-gates 203 and the plurality of second pseudo-gates 205 are all arranged along the first direction X.

[0044] Please refer to Figure 5After forming the plurality of first dummy gates 203, the plurality of second dummy gates 205, the first doped region 204 and the second doped region 206, a first conductive layer 209, a second conductive layer 210 and a third conductive layer 211 are formed on the substrate 200. The first conductive layer 209 is electrically connected to the plurality of first dummy gates 203 and the first doped region 204, the second conductive layer 210 is electrically connected to the second doped region 206, and the third conductive layer 211 is electrically connected to the first conductive layer 209 and the plurality of second dummy gates 205.

[0045] Thus, by connecting the plurality of second dummy gates 205 on the lead-out region II to the first dummy gate 203 and the first doped region 204 of the diode region I via the third conductive layer 211, the plurality of second dummy gates 205 have the same potential as the plurality of first dummy gates 203 and the first doped region 204. This increases the parasitic capacitance between the well region 201 and the third conductive layer 211, as well as the parasitic capacitance between the third conductive layer 211 and the second dummy gates 203 and the well region 201. In summary, without changing the existing manufacturing process and while maintaining compatibility with the existing process, the area of ​​the electrostatic discharge protection device is not increased. At the same time, new parasitic capacitances are introduced, thereby reducing the overshoot voltage and having a minimal impact on the response speed.

[0046] It should be noted that in the actual wiring layout design process, designers can flexibly choose to use the method provided by this technical solution in the layout of electrostatic discharge protection devices or adopt it as a whole, according to specific needs.

[0047] In this embodiment, a first conductive plug 212 is provided between the first conductive layer 209 and the plurality of first dummy gates 203, and between the first conductive layer 209 and the first doped region 204, and the first conductive layer 209, the plurality of first dummy gates 203, and the first doped region 204 are electrically connected through the first conductive plug 212; a second conductive plug 213 is provided between the second conductive layer 210 and the second doped region 206, and the second conductive layer 210 and the second doped region 206 are electrically connected through the second conductive plug 213; a third conductive plug 214 is provided between the third conductive layer 211 and the plurality of second dummy gates 205, and the third conductive layer 211 and the plurality of second dummy gates 205 are electrically connected through the third conductive plug 214.

[0048] Each conductive layer is electrically connected to the doped region or dummy gate through several conductive plugs. Especially in more advanced processes, the smaller the size of the dummy gate, the surrounding conductive plugs, and the metal conductive layer, the larger the new parasitic capacitance generated, which is more conducive to reducing overshoot voltage.

[0049] In this embodiment, before forming the first conductive layer 209, the second conductive layer 210 and the third conductive layer 211, a dielectric layer (not shown in the figure) is also formed on the surfaces of the plurality of first dummy gates 203, the plurality of second dummy gates 205, the first doped region 204 and the second doped region 206.

[0050] In this embodiment, the method for forming the first conductive layer 209, the second conductive layer 210, and the third conductive layer 211 includes: forming a first trench (not shown in the figure) and a first via (not shown in the figure) located below and connected to the first trench in the dielectric layer, wherein the bottom of the first via exposes the top surfaces of the plurality of first dummy gates 203 and the first doped region 204; forming a second trench (not shown in the figure) and a second via (not shown in the figure) located below and connected to the second trench in the dielectric layer, wherein the bottom of the second via exposes the top surface of the second doped region. A third trench (not shown in the figure) and a third through hole (not shown in the figure) located below and communicating with the third trench are formed in the dielectric layer, the bottom of the third through hole exposing the top surface of the plurality of second dummy gates 205; a first conductive plug 212 is formed in the first through hole; a first conductive layer 209 is formed in the first trench; a second conductive plug 213 is formed in the second through hole; a second conductive layer 210 is formed in the second trench; a third conductive plug 214 is formed in the third through hole; and a third conductive layer 211 is formed in the third trench.

[0051] In this embodiment, the formation process of the first conductive layer 209, the second conductive layer 210 and the third conductive layer 211 includes the damascus process.

[0052] Accordingly, this invention also provides an electrostatic discharge protection device formed using the above method. Please refer to [link / reference needed]. Figure 5The system includes: a substrate 200, which includes a diode region I and a lead-out region II, and an isolation structure 202 located between the diode region I and the lead-out region II. Both the diode region I and the lead-out region II have well regions 201, each well region 201 having a first conductivity type; a plurality of first dummy gates 203 located on the diode region I, each first dummy gate 203 having a first dummy gate sidewall (not shown in the figure); first doped regions 204 located in the diode region I on both sides of the first dummy gates 203, each first doped region 204 having a second conductivity type, the first conductivity type being opposite to the second conductivity type; and an isolation structure 202 located between the lead-out region II and the lead-out region II. A plurality of second dummy gates 205 on region II, the second dummy gate sidewalls having second dummy gate sidewalls (not shown in the figure), and a second doped region 206 in the lead-out region II on both sides of the second dummy gate 205, the second doped region 206 having a first conductivity type; a first conductive layer 209, a second conductive layer 210 and a third conductive layer 211 located on the substrate 200, the first conductive layer 209 being electrically connected to the plurality of first dummy gates 203 and the first doped region 204, the second conductive layer 210 being electrically connected to the second doped region 206, and the third conductive layer 211 being electrically connected to the first conductive layer 209 and the plurality of second dummy gates 205.

[0053] Thus, by electrically connecting the plurality of second dummy gates 205 on the lead-out region II to the first dummy gate 203 and the first doped region 204 of the diode region I through the third conductive layer 211, the plurality of second dummy gates 205 have the same potential as the plurality of first dummy gates 203 and the first doped region 204, thereby increasing the parasitic capacitance between the well region 201 and the third conductive layer 211, as well as the parasitic capacitance between the third conductive layer 211 and the second dummy gates 203 and the well region 201. In summary, without changing the existing manufacturing process and while maintaining compatibility with the existing manufacturing process, and without changing the area of ​​the electrostatic discharge protection device, a new parasitic capacitance is introduced by changing the metal trace layout, thereby reducing the overshoot voltage and having a small impact on the response speed.

[0054] Specifically, the substrate 200 further includes an isolation region III located between the diode region I and the lead-out region II, and the isolation structure 202 is located within the isolation region III.

[0055] In this embodiment, a first dummy gate oxide layer 207 is provided between each of the first dummy gates 203 and the substrate 200; a second dummy gate oxide layer 208 is provided between each of the second dummy gates 205 and the substrate 200.

[0056] In this embodiment, the plurality of first pseudo-gates 203 and the plurality of second pseudo-gates 205 are all arranged along the first direction X.

[0057] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrostatic discharge protection device, characterized in that, include: A substrate comprising a diode region and a lead-out region, and an isolation structure located between the diode region and the lead-out region, wherein both the diode region and the lead-out region have well regions, and each well region has a first conductivity type; A plurality of first dummy gates are located on the diode region, the first dummy gate sidewalls have first dummy gate sidewalls, the diode region on both sides of the first dummy gates has a first doped region, the first doped region has a second conductivity type, and the first conductivity type is opposite to the second conductivity type; A plurality of second pseudo-gates are located on the lead-out region, the sidewalls of the second pseudo-gates have second pseudo-gate sidewalls, and the lead-out region on both sides of the second pseudo-gates has a second doped region, the second doped region having a first conductivity type; A first conductive layer, a second conductive layer, and a third conductive layer are located on the substrate. The first conductive layer is electrically connected to the plurality of first dummy gates and the first doped region. The second conductive layer is electrically connected to the second doped region. The third conductive layer is electrically connected to the first conductive layer and the plurality of second dummy gates.

2. The electrostatic discharge protection device as described in claim 1, characterized in that, A first pseudo-gate oxide layer is provided between each of the first pseudo-gates and the substrate; a second pseudo-gate oxide layer is provided between each of the second pseudo-gates and the substrate.

3. The electrostatic discharge protection device as described in claim 1, characterized in that, The plurality of first pseudo-gates and the plurality of second pseudo-gates are all arranged along the first direction.

4. A method for forming an electrostatic discharge protection device, characterized in that, include: A substrate is provided, the substrate including a diode region and a lead-out region, and an isolation structure located between the diode region and the lead-out region, wherein both the diode region and the lead-out region have well regions, and the well regions each have a first conductivity type; A plurality of first dummy gates, a first dummy gate sidewall, and a first doped region located on both sides of the first dummy gates are formed on the diode region. The first doped region has a second conductivity type, which is opposite to the second conductivity type. A plurality of second dummy gates, second dummy gate sidewalls, and second doped regions located in the lead-out regions on both sides of the second dummy gates are formed on the lead-out regions, wherein the second doped regions have a first conductivity type. After forming the plurality of first dummy gates, the plurality of second dummy gates, the first doped region, and the second doped region, a first conductive layer, a second conductive layer, and a third conductive layer are formed on the substrate. The first conductive layer is electrically connected to the plurality of first dummy gates and the first doped region, the second conductive layer is electrically connected to the second doped region, and the third conductive layer is electrically connected to the first conductive layer and the plurality of second dummy gates.

5. The method for forming the electrostatic discharge protection device as described in claim 4, characterized in that, A first conductive plug is provided between the first conductive layer and the plurality of first dummy gates, and between the first conductive layer and the first doped region, and the first conductive layer, the plurality of first dummy gates, and the first doped region are electrically connected through the first conductive plug; A second conductive plug is provided between the second conductive layer and the second doped region, and the second conductive layer and the second doped region are electrically connected through the second conductive plug; a third conductive plug is provided between the third conductive layer and the plurality of second dummy gates, and the third conductive layer and the plurality of second dummy gates are electrically connected through the third conductive plug.

6. The method for forming the electrostatic discharge protection device as described in claim 5, characterized in that, Before forming the first conductive layer, the second conductive layer and the third conductive layer, the method further includes: forming a dielectric layer on the surface of the plurality of first dummy gates, the plurality of second dummy gates, the first doped region and the second doped region.

7. The method for forming the electrostatic discharge protection device as described in claim 6, characterized in that, The method for forming the first conductive layer, the second conductive layer, and the third conductive layer includes: forming a first trench and a first via located below and connected to the first trench in the dielectric layer, wherein the bottom of the first via exposes the top surfaces of the plurality of first dummy gates and the first doped region; forming a second trench and a second via located below and connected to the second trench in the dielectric layer, wherein the bottom of the second via exposes the top surface of the second doped region; forming a third trench and a third via located below and connected to the third trench in the dielectric layer, wherein the bottom of the third via exposes the top surfaces of the plurality of second dummy gates; forming a first conductive plug in the first via; forming the first conductive layer in the first trench; forming a second conductive plug in the second via; forming the second conductive layer in the second trench; forming the third conductive plug in the third via; and forming the third conductive layer in the third trench.

8. The method for forming the electrostatic discharge protection device as described in claim 4, characterized in that, A first pseudo-gate oxide layer is provided between each of the first pseudo-gates and the substrate; a second pseudo-gate oxide layer is provided between each of the second pseudo-gates and the substrate.

9. The method for forming the electrostatic discharge protection device as described in claim 4, characterized in that, The plurality of first pseudo-gates and the plurality of second pseudo-gates are all arranged along the first direction.

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