Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a semiconductor substrate, an insulating buried layer, a drift region and a plurality of dielectric isolation structures. The insulating buried layer is located on the semiconductor substrate, the drift region is located on the insulating buried layer, a part of the upper surface of the drift region is provided with a drain region, the plurality of dielectric isolation structures are located in the drift region and are arranged at intervals in the direction towards the drain region, and at least one dielectric isolation structure is protruded from the insulating buried layer and is bent towards the drain region. The lateral withstand voltage capacity and the longitudinal withstand voltage capacity of the semiconductor device can be greatly improved, and the breakdown voltage of the semiconductor device can also be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods. Background Technology

[0002] Silicon-on-insulator (SOI) devices have gained widespread attention in the field of very large-scale integrated circuits due to their higher operating speed and integration density, better insulation performance, stronger radiation resistance, and self-locking effect.

[0003] However, traditional silicon-on-insulator devices have drawbacks such as low breakdown voltage and poor heat dissipation. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and a method for fabricating the same, in order to solve at least one of the above-mentioned technical problems.

[0005] To achieve the objectives of this application, the following technical solution is adopted:

[0006] A semiconductor device, comprising:

[0007] Semiconductor substrate;

[0008] An insulating buried layer is located on the semiconductor substrate;

[0009] A drift region is located on the insulating buried layer, and a portion of the upper surface of the drift region is provided with a leakage area;

[0010] Multiple dielectric isolation structures are located within the drift region and on the buried insulating layer, and are spaced apart in the direction toward the drain region. At least one of the dielectric isolation structures protrudes from the buried insulating layer and bends toward the drain region.

[0011] In one embodiment, each of the dielectric isolation structures protrudes from the insulating buried layer and bends toward the drain region.

[0012] In one embodiment, the dielectric isolation structure, which protrudes from the insulating buried layer and bends toward the drain area, includes a support portion and a blocking portion;

[0013] One end of the support portion is in direct contact with the insulating buried layer, and the other end of the support portion is connected to one end of the blocking portion. The other end of the blocking portion bends and extends toward the leakage area, and the blocking portion and the insulating buried layer are spaced apart.

[0014] In one embodiment, the blocking portion is arranged parallel to the insulating buried layer.

[0015] In one embodiment, the support portion and the blocking portion are connected in an arc shape or vertically.

[0016] In one embodiment, the plurality of media isolation structures include a plurality of first media isolation structures and at least one second media isolation structure, wherein the height of each of the first media isolation structures is lower than the height of each of the second media isolation structures, and the second media isolation structure is disposed on the side of the plurality of media isolation structures away from the leak area, and the second media isolation structure partially surrounds at least one of the first media isolation structures.

[0017] In one embodiment, the plurality of media isolation structures includes a plurality of second media isolation structures, wherein the height of the second media isolation structure is higher the farther away from the drain region.

[0018] In one embodiment, the projection of the second dielectric isolation structure onto the buried insulating layer overlaps with the projection of at least one of the first dielectric isolation structures adjacent to the second dielectric isolation structure onto the buried insulating layer.

[0019] In one embodiment, each of the media isolation structures includes a support portion and a blocking portion;

[0020] One end of the support portion is in direct contact with the insulating buried layer, and the other end of the support portion is connected to one end of the blocking portion. The other end of the blocking portion bends and extends toward the leakage area, and the blocking portion and the insulating buried layer are spaced apart.

[0021] The height of the support portion of the second dielectric isolation structure is greater than the height of the support portion of the first dielectric isolation structure, and the height of the support portion is the dimension of the support portion in the thickness direction of the semiconductor device; and / or;

[0022] The length of the blocking portion of the second medium isolation structure is greater than the length of the blocking portion of the first medium isolation structure, and the length of the blocking portion is the dimension of the blocking portion in the direction toward the leak area.

[0023] In one embodiment, the dielectric constant of at least two of the dielectric isolation structures gradually decreases along the direction toward the drain region; or

[0024] Multiple dielectric isolation structures are arranged to form a first dielectric isolation group, a second dielectric isolation group, and a third dielectric isolation group, which are spaced apart along the direction toward the drain region. The dielectric constant of each dielectric isolation structure in the first dielectric isolation group is greater than the dielectric constant of each dielectric isolation structure in the second dielectric isolation group, and the dielectric constant of each dielectric isolation structure in the second dielectric isolation group is greater than the dielectric constant of each dielectric isolation structure in the third dielectric isolation group.

[0025] In one embodiment, the semiconductor device further includes:

[0026] The first and second well regions are located on a portion of the upper surface of the drift region;

[0027] The first well region has an outlet region and a source region, which are located on the upper surface of the first well region. The potential of the outlet region of the first well region is short-circuited with that of the source region. The drain region is located on the upper surface of the second well region.

[0028] A gate structure is disposed on the first well region, with one end extending to the drift region and the other end extending to the source region;

[0029] Wherein, all of the aforementioned media isolation structures are disposed between the source region and the drain region;

[0030] The first well region and the first well region exit region both have a first conductivity type, and the drift region, the second well region, the source region and the drain region all have a second conductivity type, with the first conductivity type and the second conductivity type being opposite.

[0031] A method for fabricating a semiconductor device, comprising:

[0032] Provide semiconductor substrates;

[0033] An insulating buried layer is formed on the semiconductor substrate;

[0034] Multiple dielectric isolation structures are formed at intervals on the insulating buried layer;

[0035] A drift region is formed on the insulating buried layer, and the plurality of dielectric isolation structures are located within the drift region;

[0036] A leak area is formed on a portion of the upper surface of the drift region;

[0037] The plurality of dielectric isolation structures are spaced apart along the direction toward the drain region; at least one of the dielectric isolation structures protrudes from the insulating buried layer and bends toward the drain region.

[0038] In one embodiment, the formation of a plurality of spaced dielectric isolation structures on the buried insulating layer includes:

[0039] A dielectric isolation layer is formed on the insulating buried layer;

[0040] The dielectric isolation layer is etched to form a plurality of spaced dielectric isolation structures.

[0041] In one embodiment, the formation of a plurality of spaced dielectric isolation structures on the buried insulating layer includes:

[0042] A silicon layer is formed on the insulating buried layer;

[0043] The silicon layer is etched to form a plurality of trenches spaced apart in the silicon layer;

[0044] A dielectric isolation material is coated on the silicon layer and filled into each of the trenches, and the dielectric isolation material is etched to form the dielectric isolation structure.

[0045] The semiconductor device and its fabrication method provided above, since at least one dielectric isolation structure protrudes from the buried insulating layer and bends toward the drain region, it can be understood that the dielectric isolation structure is used to block the interface charge formed on the upper surface of the buried insulating layer between two adjacent dielectric isolation structures, and to block the interface charge between the dielectric isolation structure and the buried insulating layer. That is, the interface charge in the interface inversion layer can be blocked between two adjacent dielectric isolation structures, and between the dielectric isolation structure and the buried insulating layer, which can improve the dielectric electric field of the buried insulating layer. At the same time, due to the shielding effect of the interface charge, the strong electric field of the drain region is reduced, avoiding the electric field rise of the drain region from breaking down earlier than the source region, which is beneficial to improving the lateral breakdown voltage capability of the semiconductor device. Furthermore, multiple dielectric isolation structures are spaced apart in the drift region along the direction toward the drain region. It can be understood that the dielectric isolation structure that protrudes from the buried insulating layer and bends toward the drain region is equivalent to a layer of SOI structure, which can form a double dielectric withstand voltage with the buried insulating layer, which can greatly improve the longitudinal withstand voltage capability of the semiconductor device. Therefore, the use of multiple dielectric isolation structures can improve the lateral withstand voltage capability and longitudinal withstand voltage capability of the semiconductor device, and ultimately improve the breakdown voltage of the semiconductor device. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0047] Figure 2 This is a schematic diagram of the semiconductor device in another embodiment;

[0048] Figure 3 This is a front view of a semiconductor device in another embodiment;

[0049] Figure 4 This is a schematic diagram of the dielectric isolation structure of a semiconductor device in another embodiment;

[0050] Figure 5 This is a schematic diagram of the semiconductor device in another embodiment;

[0051] Figure 6 This is a schematic diagram of the semiconductor device in another embodiment;

[0052] Figure 7 This is a schematic flowchart of the semiconductor device fabrication method in the first embodiment;

[0053] Figure 8 This is a schematic flowchart of the semiconductor device fabrication method in the first embodiment;

[0054] Figure 9 This is a schematic flowchart of the semiconductor device fabrication method in the second embodiment;

[0055] Figure 10 This is a schematic flowchart of the semiconductor device fabrication method in the third embodiment.

[0056] In the figure: 111, semiconductor substrate; 112, buried insulating layer; 120, drift region; 130, dielectric isolation structure; 131, first dielectric isolation structure; 132, second dielectric isolation structure; 1301, support portion; 1302, blocking portion; 133, opening; 130a, first dielectric isolation group; 130b, second dielectric isolation group; 130c, third dielectric isolation group; 140, source region; 150, drain region; 160, gate structure; 161, field oxide layer; 162, gate; 171, first well region; 172, first well region lead-out region; 180, second well region. Detailed Implementation

[0057] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0060] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0063] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0064] The inventors of this application discovered through research and development that in SOI high-voltage devices, taking N-type LDMOS as an example, on the one hand, the depletion layer formed by the P-type well region and the drift region continuously widens; on the other hand, the buried insulating layer and the semiconductor substrate form an inverted MIS structure. When the reverse voltage increases to a certain level, the depletion layer formed at the interface between the drift region and the buried insulating layer in the inverted MIS structure no longer widens, and an interface inversion layer is formed at the interface between the drift region and the buried insulating layer. When the reverse voltage continues to increase, the depletion layers formed by the P-type well region and the drift region and the depletion layers formed by the buried insulating layer and the drift region merge to form a depletion region. At the same time, almost all the interface charge at the interface inversion layer is extracted, resulting in a lower breakdown voltage of the SOI high-voltage device.

[0065] In order to solve at least one of the aforementioned technical problems, the inventors of this application, through in-depth research, designed a semiconductor device that utilizes a dielectric isolation structure to greatly prevent the extraction of interface charges while improving the distribution of electric field lines on the device surface, thereby significantly improving the device's withstand voltage.

[0066] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application.

[0067] In some embodiments, please refer to Figure 1The semiconductor device provided in one embodiment of this application includes a semiconductor substrate 111, an insulating buried layer 112, a drift region 120, and a plurality of dielectric isolation structures 130. The insulating buried layer 112 is located on the semiconductor substrate 111, the drift region 120 is located on the insulating buried layer 112, a drain region 150 is provided on a portion of the upper surface of the drift region 120, and a plurality of dielectric isolation structures 130 are located within the drift region 120 and on the insulating buried layer 112, and are spaced apart in a direction toward the drain region 150. At least one dielectric isolation structure 130 protrudes from the insulating buried layer 112 and bends toward the drain region 150. It is understood that each dielectric isolation structure 130 is in contact with the insulating buried layer 112.

[0068] Taking a laterally diffused metal-oxide-semiconductor (LDMOS) device as an example, in this embodiment, a first well region 171 and a second well region 180 are provided on part of the upper surface of the drift region 120, the source region 140 is provided on the upper surface of the first well region 171, the drain region 150 is provided on the upper surface of the second well region 180, and the entire dielectric isolation structure 130 is provided between the source region 140 and the drain region 150.

[0069] The semiconductor substrate 111 and the first well region 171 have a first conductivity type, and the drift region 120, the second well region 180, the source region 140 and the drain region 150 all have a second conductivity type. The first conductivity type and the second conductivity type are opposite.

[0070] In this embodiment, one of the first conductivity type and the second conductivity type is P-type, and the other is N-type. For example, the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type. For instance, in this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the semiconductor substrate 111 has a P-type conductivity type, and the drift region 120 has an N-type conductivity type.

[0071] In the aforementioned semiconductor device, when a reverse bias is applied, the depletion layer formed by the first well region 171 and the drift region 120 merges with the depletion layer formed by the buried insulating layer 112 and the drift region 120. An interface inversion layer is also formed on the upper surface of the buried insulating layer 112, in which interface charges are formed. Since at least one dielectric isolation structure 130 protrudes from the buried insulating layer 112 and bends toward the drain region 150, it can be understood that the dielectric isolation structure 130 is used to block the interface charges formed on the upper surface of the buried insulating layer 112 between two adjacent dielectric isolation structures 130. It is used to block interface charges between the dielectric isolation structure 130 and the insulating buried layer 112. In this way, the interface charges in the interface inversion layer can be blocked between two adjacent dielectric isolation structures 130 and between the dielectric isolation structure 130 and the insulating buried layer 112. When the depletion region expands on a large scale, it can effectively improve the ability to block interface inversion charges and increase the dielectric electric field of the insulating buried layer 112. At the same time, due to the shielding effect of the interface charges, the strong electric field of the drain region 150 is reduced, preventing the electric field of the drain region 150 from rising and breaking down before the source region 140, which is beneficial to improving the lateral breakdown voltage of the semiconductor device.

[0072] Furthermore, multiple dielectric isolation structures 130 are spaced apart in the drift region 120 along the direction toward the drain region 150. It can be understood that the dielectric isolation structure 130, which protrudes from the buried insulating layer 112 and bends toward the drain region 150, is equivalent to an SOI structure and can form a double dielectric withstand voltage with the buried insulating layer 112, which can greatly improve the longitudinal withstand voltage capability of the semiconductor device. Therefore, by using multiple dielectric isolation structures 130, the lateral withstand voltage capability and longitudinal withstand voltage capability of the semiconductor device can be improved, and ultimately the breakdown voltage of the semiconductor device can be improved.

[0073] It should be noted that the above description only uses a laterally double-diffused metal-oxide-semiconductor device as an example. The "multiple dielectric isolation structures 130" can also be applied to other types of semiconductor devices, which can greatly improve the lateral and longitudinal breakdown voltage of semiconductor devices.

[0074] The aforementioned "at least one dielectric isolation structure 130 protrudes from the insulating buried layer 112 and bends toward the drain area 150" can be one dielectric isolation structure 130 protruding from the insulating buried layer 112 and bending toward the drain area 150, or two dielectric isolation structures 130 protruding from the insulating buried layer 112 and bending toward the drain area 150, or all dielectric isolation structures 130 protruding from the insulating buried layer 112 and bending toward the drain area 150, and no specific limitation is made here. Figures 1 to 3 and Figure 5 An example is given where the entire dielectric isolation structure 130 protrudes from the insulating buried layer 112 and bends toward the drain region 150.

[0075] Specifically, such as Figure 6 In the embodiment shown, three dielectric isolation structures 130 closer to the drain region 150 protrude from the insulating buried layer 112 and bend toward the drain region 150, while the remaining dielectric isolation structures 130 do not bend.

[0076] In some embodiments of this application, please refer to Figures 1 to 3 Each dielectric isolation structure 130 protrudes from the insulating buried layer 112 and bends toward the drain area 150.

[0077] In some embodiments of this application, please refer to Figures 1 to 3 The semiconductor device also includes a gate structure 160, which is disposed on the first well region 171, with one end extending to cover the drift region 120 and the other end extending to cover the source region 140. It is understood that the edge of the projection region of the gate structure 160 on the drift region 120 overlaps with the edge of the projection region of the source region 140 on the drift region 120. On the one hand, under the control of an applied voltage, the overlapping region in the first well region 171 with the gate structure 160 is used to form a conductive channel; on the other hand, during the fabrication of the semiconductor device, the gate structure 160 can also serve as an implantation barrier layer for doping the source region 140, enabling self-aligned implantation of the source region 140 and ensuring the width of the conductive channel.

[0078] Please continue reading. Figure 2 The gate structure 160 includes a gate dielectric layer and a gate 162. For example, the gate dielectric layer may be a gate oxide layer, and the material of the gate 162 may be polysilicon, metal, metal nitride, or metal silicide, without specific limitations.

[0079] In some embodiments of this application, please refer to Figures 1 to 3 The semiconductor device also includes a field oxide layer 161. Please continue reading. Figure 3 After the gate structure 160 extends to cover the drift region 120, the gate 162 in the gate structure 160 continues to extend to cover the field oxide layer 161.

[0080] In some embodiments of this application, please refer to Figures 1 to 3 The semiconductor device also includes a first well region lead-out region 172, which is located on the upper surface of the first well region 171 and is shorted to the potential of the source region 140.

[0081] By leading out the source region 140 as the source electrode, it can be understood that the source region 140, the first well region lead-out region 172, and the drift region 120 together constitute a parasitic NPN transistor. The first well region lead-out region 172 of the first conductivity type is located on the upper surface of the first well region 171 of the first conductivity type, which can increase the base region concentration of the parasitic NPN transistor. The minority carrier lifetime is reduced and cannot cross to the emitter of the parasitic NPN transistor, thus effectively preventing the parasitic NPN transistor from turning on at the source end.

[0082] In some embodiments of this application, both the source region 140 and the first well region 172 are heavily doped regions, with a doping concentration greater than that of the first well region 171. This effectively creates a gradually varying channel doping in the first well region 172 and the first well region 171, which can adjust the threshold voltage, reduce the resistance of the semiconductor substrate 111, prevent parasitic NPN transistors from turning on, increase the concentration of the first well region 171, shorten the channel length, reduce the on-resistance, and decrease the device area.

[0083] In some embodiments of this application, please refer to Figures 1 to 3 The semiconductor device also includes a second well region 180 disposed on the upper surface layer of the drift region 120. The second well region 180 is located on the side of the gate structure 160 away from the source region 140 and is spaced apart from the gate structure 160. A drain region 150 is disposed on the upper surface layer of the second well region 180. The drain region 150 is a heavily doped region, and the doping concentration of the drain region 150 is greater than the doping concentration of the second well region 180.

[0084] In some embodiments of this application, the drain region 150 is led out as the drain electrode. When the semiconductor device enters the turn-off process, the charge carriers stored in the drift region 120 that generate conductivity modulation effect in the on state can quickly flow to the drain electrode through the second well region 180 and the drain region 150 of the second conductivity type, so as to effectively shorten the turn-off time.

[0085] In some embodiments of this application, please refer to Figures 1 to 3 Each medium isolation structure is set at equal intervals of 130.

[0086] Because the dielectric isolation structures 130 are equally spaced, the potential between the drain and the source is segmented uniformly, and the lateral electric field between the drain region 150 and the source region 140 is uniformly distributed, thereby improving the lateral breakdown voltage of the device.

[0087] In some embodiments of this application, please refer to Figures 1 to 4The dielectric isolation structure 130, which protrudes from the insulating buried layer 112 and bends toward the drain area 150, includes a support portion 1301 and a blocking portion 1302. One end of the support portion 1301 is in direct contact with the insulating buried layer 112, and the other end of the support portion 1301 is connected to one end of the blocking portion 1302. The other end of the blocking portion 1302 bends and extends toward the drain area 150, and the blocking portion 1302 is spaced apart from the insulating buried layer 112.

[0088] On the one hand, at least one dielectric isolation structure 130 has a blocking portion 1302 that bends and extends toward the drain region 150. Combined with multiple dielectric isolation structures 130 arranged at intervals along the direction toward the drain region 150, it can be understood that the blocking portion 1302 of the dielectric isolation structure 130 that protrudes from the insulating buried layer 112 and bends toward the drain region 150 is equivalent to a layer of SOI structure, which can form a double-layer dielectric withstand voltage with the insulating buried layer 112, which can greatly improve the longitudinal withstand voltage capability of the semiconductor device.

[0089] On the other hand, since the blocking portion 1302 of the dielectric isolation structure 130, which protrudes from the buried insulating layer 112 and bends toward the drain region 150, is spaced apart from the buried insulating layer 112, it can be understood that the dielectric isolation structure 130, which protrudes from the buried insulating layer 112 and bends toward the drain region 150, partially surrounds the interface charge formed on the upper surface of the buried insulating layer 112. Combined with the electrical isolation characteristics of the dielectric isolation structure 130, the interface charge can be blocked between the dielectric isolation structure 130 and the buried insulating layer 112 by the dielectric isolation structure 130, which protrudes from the buried insulating layer 112 and bends toward the drain region 150, and the interface charge can also be blocked between two adjacent dielectric isolation structures 130. This can further effectively improve the dielectric electric field of the buried insulating layer 112 and further improve the lateral breakdown voltage capability of the semiconductor device.

[0090] In some embodiments of this application, the blocking portion 1302 is arranged parallel to the insulating buried layer 112. This facilitates the formation of a double-layer dielectric withstand voltage between the blocking portion 1302 of the multiple dielectric isolation structures 130 and the insulating buried layer 112, which can greatly improve the longitudinal withstand voltage capability of the semiconductor device.

[0091] In some embodiments of this application, the insulating buried layer 112 and each dielectric isolation structure 130 are made of silicon oxide, such as silicon dioxide.

[0092] In some embodiments of this application, the support portion 1301 and the blocking portion 1302 are connected in an arc shape or vertically.

[0093] The support part 1301 and the blocking part 1302 can be connected in an arc shape or in a vertical shape, depending on the specific process requirements.

[0094] In some implementations of this application, please refer to Figure 2 and Figure 3 The plurality of dielectric isolation structures 130 protruding from the insulating buried layer 112 and bent toward the drain region 150 include a plurality of first dielectric isolation structures 131 and at least one second dielectric isolation structure 132. The height of each of the first dielectric isolation structures 131 is lower than the height of the second dielectric isolation structure 132. The second dielectric isolation structure 132 is disposed on the side of the plurality of dielectric isolation structures 130 away from the drain region 150. The second dielectric isolation structure 132 partially surrounds at least one first dielectric isolation structure 131.

[0095] The second dielectric isolation structure 132, which is further away from the drain region 150, can effectively prevent strong extraction of inversion layer charge at the source end of the device. It can form a further blocking effect and better block the interface charge between the second dielectric isolation structure 132 and the first dielectric isolation structure 131 adjacent to the second dielectric isolation structure 132, or between two adjacent second dielectric isolation structures 132. This better prevents the interface charge from being extracted. The interface charge blocked between the second dielectric isolation structure 132 and the first dielectric isolation structure 131 adjacent to the second dielectric isolation structure 132, or between two adjacent second dielectric isolation structures 132, can well bear part of the electric field of the source end charge, so as to effectively improve the lateral breakdown voltage capability of the semiconductor device.

[0096] The plurality of dielectric isolation structures 130 may include a second dielectric isolation structure 132 that protrudes from the buried insulating layer 112 and bends toward the drain region 150, wherein a second dielectric isolation structure 132 partially surrounds a first dielectric isolation structure 131 or a plurality of first dielectric isolation structures 131. Figure 2 and Figure 3 In the illustrated embodiment, the first dielectric isolation structure 131 is a structure that protrudes from the buried insulating layer 112 and bends toward the drain region 150. In other embodiments, the first dielectric isolation structure 131 may also be a structure that protrudes from the buried insulating layer 112 but does not bend. Of course, the plurality of dielectric isolation structures 130 may also include a plurality of second dielectric isolation structures 132 that protrude from the buried insulating layer 112 and bend toward the drain region 150. No specific limitation is made here.

[0097] In some embodiments of this application, the plurality of media isolation structures 130 include a plurality of second media isolation structures 132, and the height of the second media isolation structure 132 is higher the farther away from the drain region 150.

[0098] The overall structure formed by the plurality of second dielectric isolation structures 132 that protrude from the insulating buried layer 112 and bend toward the drain area 150 can partially surround one or more first dielectric isolation structures 131 or all of the first dielectric isolation structures 131, without being specifically limited here.

[0099] With this configuration, the number of dielectric isolation structures 130 protruding from the buried insulating layer 112 and bending towards the drain region 150 increases the dielectric withstand voltage, thereby further improving the withstand voltage performance of the semiconductor device. Of course, the number of dielectric isolation structures 130 protruding from the buried insulating layer 112 and bending towards the drain region 150 is also taken into consideration when determining the heat dissipation performance of the semiconductor device.

[0100] In some implementations of this application, please refer to Figures 1 to 3 Each dielectric isolation structure 130 protruding from the insulating buried layer 112 and bending toward the drain region 150 forms an opening 133 in the direction toward the drain region 150. Taking two adjacent first dielectric isolation structures 131 that protrude from the insulating buried layer 112 and bend toward the drain region 150 as an example, the two adjacent first dielectric isolation structures 131 include a left first dielectric isolation structure 131 and a right first dielectric isolation structure 131. The interface charge on the right side of the right first dielectric isolation structure 131 is blocked between the two adjacent first dielectric isolation structures 131 through the opening 133 of the left first dielectric isolation structure 131.

[0101] In some implementations of this application, please refer to Figure 2 and Figure 3 The projection of the second dielectric isolation structure 132, which protrudes from the buried insulating layer 112 and bends toward the drain region 150, onto the buried insulating layer 112 overlaps with the projection of at least one first dielectric isolation structure 131, which is adjacent to the second dielectric isolation structure 132, protrudes from the buried insulating layer 112, and bends toward the drain region 150, onto the buried insulating layer 112. This arrangement allows the interface charge between the at least one first dielectric isolation structure 131 adjacent to the second dielectric isolation structure 132 and the buried insulating layer 112 to remain between the second dielectric isolation structure 132 and the buried insulating layer 112 during extraction. This utilizes the shielding effect of the interface charge to reduce the strong electric field of the drain region 150, effectively improving the dielectric electric field of the buried insulating layer 112 and enhancing the lateral breakdown voltage capability of the semiconductor device.

[0102] In some implementations of this application, please refer to Figure 2 and Figure 3 The height of the support portion 1301 of the second dielectric isolation structure 132, which protrudes from the buried insulating layer 112 and bends towards the drain region 150, is greater than the height of the support portion 1301 of the first dielectric isolation structure 131, which protrudes from the buried insulating layer 112 and bends towards the drain region 150. The height of the support portion 1301 is the dimension of the support portion 1301 in the thickness direction of the semiconductor device (e.g., in...). Figure 1In the illustrated embodiment, the thickness direction of the semiconductor device is parallel to the y-axis. Thus, the support portion 1301 of the second dielectric isolation structure 132 has a higher height, which can better semi-enclose the first dielectric isolation structure 131 adjacent to the second dielectric isolation structure 132, so that the second dielectric isolation structure 132, which is further away from the drain region 150, can better form a further blocking effect, thereby preventing interface charge from being extracted, and effectively improving the lateral breakdown voltage capability of the semiconductor device.

[0103] In other embodiments of this application, please refer to Figure 2 and Figure 3 The length of the blocking portion 1302 of the second dielectric isolation structure 132, which protrudes from the buried insulating layer 112 and bends towards the drain region 150, is greater than the length of the blocking portion 1302 of the first dielectric isolation structure 131, which protrudes from the buried insulating layer 112 and bends towards the drain region 150. The length of the blocking portion 1302 is the dimension of the blocking portion 1302 in the direction towards the drain region 150 (e.g., in...). Figure 1 In the illustrated embodiment, the blocking portion 1302 is parallel to the x-axis in the direction toward the drain region 150. Thus, the blocking portion 1302 of the second dielectric isolation structure 132 is longer, so that the interface charge between the first dielectric isolation structure 131 adjacent to the second dielectric isolation structure 132 and the insulating buried layer 112 can be more easily blocked by the blocking portion 1302 of the second dielectric isolation structure 132 during extraction, thereby effectively improving the lateral breakdown voltage capability of the semiconductor device.

[0104] In some other embodiments of this application, please refer to Figure 2 and Figure 3 The height of the support portion 1301 of the second dielectric isolation structure 132, which protrudes from the buried insulating layer 112 and bends towards the drain region 150, is greater than the height of the support portion 1301 of the first dielectric isolation structure 131, which protrudes from the buried insulating layer 112 and bends towards the drain region 150; and the length of the blocking portion 1302 of the second dielectric isolation structure 132, which protrudes from the buried insulating layer 112 and bends towards the drain region 150, is greater than the length of the blocking portion 1302 of the first dielectric isolation structure 131, which protrudes from the buried insulating layer 112 and bends towards the drain region 150. This arrangement improves the lateral and longitudinal breakdown voltage capabilities of the semiconductor device.

[0105] In some embodiments of this application, each dielectric isolation structure 130 protruding from the buried insulating layer 112 and bending toward the drain region 150 penetrates the drift region 120 along the z-axis, so that the projection of the multiple dielectric isolation structures 130 on the buried insulating layer 112 covers more area, thereby improving the blocking effect of the multiple dielectric isolation structures 130 on the interface charge formed on the upper surface of the buried insulating layer 112.

[0106] In some embodiments of this application, the dielectric constant of at least two dielectric isolation structures 130 gradually decreases along the direction toward the drain region 150.

[0107] Along the direction toward the drain region 150, the dielectric constants of at least two dielectric isolation structures 130 decrease sequentially, which is equivalent to a gradual change in the concentration of the drift region 120, increasing the electric field integral of the drift region 120, and further improving the breakdown voltage of the semiconductor device without increasing the resistance.

[0108] In other embodiments of this application, please refer to Figure 5 Multiple dielectric isolation structures 130 are arranged to form a first dielectric isolation group 130a, a second dielectric isolation group 130b, and a third dielectric isolation group 130c, which are spaced apart along the direction toward the drain region 150. The dielectric constant of each dielectric isolation structure 130 in the first dielectric isolation group 130a is greater than the dielectric constant of each dielectric isolation structure 130 in the second dielectric isolation group 130b, and the dielectric constant of each dielectric isolation structure 130 in the second dielectric isolation group 130b is greater than the dielectric constant of each dielectric isolation structure 130 in the third dielectric isolation group 130c.

[0109] This configuration is equivalent to a gradual change in concentration in the drift region 120, which increases the electric field integral in the drift region 120 and further improves the breakdown voltage of the semiconductor device without increasing the resistance.

[0110] Specifically, such as Figure 5 In the illustrated embodiment, the dielectric isolation structure 130 of the first dielectric isolation group 130a is made of high-K dielectric, the dielectric isolation structure 130 of the second dielectric isolation group 130b is made of silicon dioxide, and the dielectric isolation structure 130 of the third dielectric isolation group 130c is made of low-K dielectric.

[0111] The following is combined with Figures 7-10 The method for fabricating the semiconductor device proposed in this invention will be described.

[0112] In some embodiments of this application, please refer to Figure 7 The methods for fabricating semiconductor devices include:

[0113] S210 provides a semiconductor substrate.

[0114] S220, An insulating buried layer is formed on a semiconductor substrate.

[0115] S230, Multiple dielectric isolation structures are formed at intervals on the insulating buried layer.

[0116] S240, A drift region is formed on the insulating buried layer, and multiple dielectric isolation structures are located within the drift region.

[0117] S250, a leak zone is formed in part of the upper surface layer of the drift zone.

[0118] In this configuration, multiple dielectric isolation structures are spaced apart along the direction toward the drain region, and at least one dielectric isolation structure protrudes from the buried insulating layer and bends toward the drain region.

[0119] On the one hand, the semiconductor device of this application can increase the dielectric electric field of the buried insulating layer during use. At the same time, due to the shielding effect of the interface charge, the strong electric field of the drain region is reduced, preventing the electric field of the drain region from rising and breaking down prematurely before the source region, which is beneficial to improving the lateral breakdown voltage of the semiconductor device. On the other hand, multiple dielectric isolation structures are arranged at intervals in the drift region along the direction towards the drain region. It can be understood that the dielectric isolation structure protruding from the buried insulating layer and bending towards the drain region is equivalent to a layer of SOI structure, which can form a double-layer dielectric breakdown voltage with the buried insulating layer, which can greatly improve the longitudinal breakdown voltage of the semiconductor device. Therefore, the use of multiple dielectric isolation structures can improve the lateral breakdown voltage and longitudinal breakdown voltage of the semiconductor device, and ultimately improve the breakdown voltage of the semiconductor device.

[0120] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type; correspondingly, the semiconductor substrate is a P-type silicon substrate and the drift region is an N-drift region. In other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type.

[0121] In some embodiments, the insulating buried layer can be prepared by oxygen injection oxidation or bonding.

[0122] In some embodiments, the insulating buried layer is made of silicon oxide, such as silicon dioxide.

[0123] In some embodiments, the drift region is achieved by high-temperature push-in after injection, which requires a certain doping concentration to ensure the current path.

[0124] In some embodiments, the dielectric isolation structure can be fabricated by oxygen implantation oxidation or bonding. The dielectric isolation structure is made of silicon oxide, such as silicon dioxide.

[0125] It should be noted that the formation of the first well region, source region, drain region, first well region lead-out region, second well region, gate structure, and field oxide layer of the semiconductor device proposed in this invention all adopt the conventional fabrication method of lateral double-diffused metal-oxide semiconductor devices, and will not be described in detail here. The following mainly describes the formation process of the "multiple dielectric isolation structures" and drift region of the semiconductor device proposed in this invention.

[0126] In some embodiments of this application, please refer to Figure 8 Step S230, which involves forming a plurality of spaced dielectric isolation structures on an insulating buried layer, includes:

[0127] S231. A dielectric isolation layer is formed on the insulating buried layer.

[0128] S232, Etch the dielectric isolation layer to form a dielectric isolation structure with multiple spaced intervals.

[0129] In other embodiments of this application, please refer to Figure 9 Step S230, which involves forming a plurality of spaced dielectric isolation structures on an insulating buried layer, includes:

[0130] S2301, A silicon layer is formed on the insulating buried layer.

[0131] S2302, Etch the silicon layer to form multiple trenches spaced apart in the silicon layer.

[0132] S2303. A dielectric isolation material is covered on the silicon layer and filled into each trench with dielectric isolation material. The dielectric isolation material is then etched to form multiple dielectric isolation structures.

[0133] In the process of covering the silicon layer with a dielectric isolation material and filling each trench with the dielectric isolation material, the dielectric isolation material can be covered on the silicon layer by growth or deposition, and of course, the dielectric isolation material can also be filled into each trench by growth or deposition. No specific limitation is made here.

[0134] In some embodiments, the plurality of media isolation structures includes a plurality of first media isolation structures and a second media isolation structure; see [link to relevant documentation]. Figure 10 Step S230, which involves forming a plurality of spaced dielectric isolation structures on an insulating buried layer, includes:

[0135] S2311. A first silicon layer is formed on the insulating buried layer.

[0136] S2312. Etch the first silicon layer to form a plurality of first trenches spaced apart in the first silicon layer.

[0137] S2313. A dielectric isolation material is coated on the first silicon layer and filled into each first trench with dielectric isolation material. The dielectric isolation material is then etched to form a plurality of first dielectric isolation structures. Each first dielectric isolation structure extends to cover the upper surface of the first silicon layer.

[0138] S2314. A second silicon layer covering multiple first dielectric isolation structures is formed on the upper surface of the first silicon layer.

[0139] S2315, Etch the first silicon layer and the second silicon layer to form a second trench penetrating the first silicon layer and the second silicon layer.

[0140] S2316. Cover the second silicon layer with a dielectric isolation material and fill the second trench with the dielectric isolation material, and etch the dielectric isolation material to form a second dielectric isolation structure that is in contact with the insulating buried layer, the second dielectric isolation structure extending to cover the upper surface of the second silicon layer.

[0141] In this embodiment, please refer to Figure 10 Step 240, which involves forming a drift region on the buried insulating layer, with multiple dielectric isolation structures located within the drift region, includes:

[0142] S2401, A third silicon layer covering the second dielectric isolation structure is formed on the upper surface of the second silicon layer.

[0143] S2402, Ion implantation is performed on the first silicon layer, the second silicon layer and the third silicon layer to form a drift region, and multiple dielectric isolation structures are located in the drift region.

[0144] Figure 10 The illustrated embodiment provides an example of multiple dielectric isolation structures including multiple first dielectric isolation structures and one second dielectric isolation structure. If the multiple dielectric isolation structures include multiple first dielectric isolation structures and multiple second dielectric isolation structures, the formation process of the multiple first dielectric isolation structures and multiple second dielectric isolation structures can also be referred to. Figure 10 The formation process of the multiple first dielectric isolation structures and the second dielectric isolation structure in the illustrated embodiment will not be described in detail here.

[0145] The semiconductor device fabricated by the above-described method has the following characteristics: Firstly, when a reverse bias is applied to the semiconductor device, the depletion layer formed by the first well region and the drift region merges with the depletion layer formed by the buried insulating layer and the drift region. An interface inversion layer is also formed on the upper surface of the buried insulating layer, containing interface charges. Since the dielectric isolation structure serves to block the interface charges formed on the upper surface of the buried insulating layer between two adjacent dielectric isolation structures, and also between the dielectric isolation structure and the buried insulating layer, the interface charges in the interface inversion layer can be blocked between two adjacent dielectric isolation structures and between the dielectric isolation structure and the buried insulating layer. Furthermore, the second dielectric isolation structure, which is closer to the first well region, provides further blocking, better preventing the interface charges from being extracted between the second dielectric isolation structure and the first dielectric isolation structure adjacent to it. According to Gauss's law of interfaces, interface charge directly affects the electric field of the dielectric layer. Compared with semiconductor devices without dielectric isolation structures, the semiconductor device of this application can increase the dielectric electric field of the buried insulating layer during use. At the same time, due to the shielding effect of the interface charge, the strong electric field of the drain region is reduced, preventing the electric field rise in the drain region from causing premature breakdown before the source region, which is beneficial to improving the lateral breakdown voltage of the semiconductor device. On the other hand, multiple dielectric isolation structures are arranged at intervals in the drift region along the direction from the first well region to the drain region. It can be understood that a dielectric isolation structure that protrudes from the buried insulating layer and bends towards the drain region is equivalent to a layer of SOI structure, which can form a double-layer dielectric breakdown voltage with the buried insulating layer, which can greatly improve the longitudinal breakdown voltage of the semiconductor device.

[0146] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the above flowcharts may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps. It should be noted that the different embodiments described above can be combined with each other.

[0147] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; An insulating buried layer is located on the semiconductor substrate; A drift region is located on the insulating buried layer, and a portion of the upper surface of the drift region is provided with a leakage area; Multiple dielectric isolation structures are located within the drift region and on the insulating buried layer, and are spaced apart in the direction toward the drain region. At least one of the dielectric isolation structures protrudes from the insulating buried layer and bends toward the drain region. Each of the aforementioned dielectric isolation structures protrudes from the insulating buried layer and bends toward the drain area; The dielectric isolation structure, which protrudes from the insulating buried layer and bends toward the leakage area, includes a support portion and a blocking portion; One end of the support portion is in direct contact with the insulating buried layer, and the other end of the support portion is connected to one end of the blocking portion. The other end of the blocking portion bends and extends toward the leakage area, and the blocking portion and the insulating buried layer are spaced apart.

2. The semiconductor device according to claim 1, characterized in that, The blocking portion is arranged parallel to the insulating buried layer.

3. The semiconductor device according to claim 1, characterized in that, The support and the blocking parts are connected in an arc shape or vertically.

4. The semiconductor device according to claim 1, characterized in that, The plurality of media isolation structures include a plurality of first media isolation structures and at least one second media isolation structure. The height of each of the first media isolation structures is lower than the height of the second media isolation structure. The second media isolation structure is disposed on the side of the plurality of media isolation structures away from the leak area. The second media isolation structure partially surrounds at least one of the first media isolation structures.

5. The semiconductor device according to claim 4, characterized in that, The plurality of media isolation structures include a plurality of second media isolation structures, with the height of the second media isolation structure being higher the farther away from the leak region.

6. The semiconductor device according to claim 4, characterized in that, The projection of the second dielectric isolation structure onto the insulating buried layer overlaps with the projection of at least one of the first dielectric isolation structures adjacent to the second dielectric isolation structure onto the insulating buried layer.

7. The semiconductor device according to claim 4, characterized in that, Each of the aforementioned media isolation structures includes a support portion and a blocking portion; One end of the support portion is in direct contact with the insulating buried layer, and the other end of the support portion is connected to one end of the blocking portion. The other end of the blocking portion bends and extends toward the leakage area, and the blocking portion and the insulating buried layer are spaced apart. The height of the support portion of the second dielectric isolation structure is greater than the height of the support portion of the first dielectric isolation structure, and the height of the support portion is the dimension of the support portion in the thickness direction of the semiconductor device; and / or; The length of the blocking portion of the second medium isolation structure is greater than the length of the blocking portion of the first medium isolation structure, and the length of the blocking portion is the dimension of the blocking portion in the direction toward the leak area.

8. The semiconductor device according to claim 1, characterized in that, Along the direction toward the drain region, the dielectric constant of at least two of the dielectric isolation structures gradually decreases; or Multiple dielectric isolation structures are arranged to form a first dielectric isolation group, a second dielectric isolation group, and a third dielectric isolation group, which are spaced apart along the direction toward the drain region. The dielectric constant of each dielectric isolation structure in the first dielectric isolation group is greater than the dielectric constant of each dielectric isolation structure in the second dielectric isolation group, and the dielectric constant of each dielectric isolation structure in the second dielectric isolation group is greater than the dielectric constant of each dielectric isolation structure in the third dielectric isolation group.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The first and second well regions are located on a portion of the upper surface of the drift region; The first well region has an outlet region and a source region, which are located on the upper surface of the first well region. The potential of the outlet region of the first well region is short-circuited with that of the source region. The drain region is located on the upper surface of the second well region. A gate structure is disposed on the first well region, with one end extending to the drift region and the other end extending to the source region; Wherein, all of the aforementioned media isolation structures are disposed between the source region and the drain region; The first well region and the first well region exit region both have a first conductivity type, and the drift region, the second well region, the source region and the drain region all have a second conductivity type, with the first conductivity type and the second conductivity type being opposite.

10. A method for fabricating a semiconductor device, characterized in that, include: Provide semiconductor substrates; An insulating buried layer is formed on the semiconductor substrate; Multiple dielectric isolation structures are formed at intervals on the insulating buried layer; A drift region is formed on the insulating buried layer, and the plurality of dielectric isolation structures are located within the drift region; A leak area is formed on a portion of the upper surface of the drift region; The plurality of dielectric isolation structures are spaced apart along the direction toward the drain region, and at least one of the dielectric isolation structures protrudes from the insulating buried layer and bends toward the drain region; Each of the aforementioned dielectric isolation structures protrudes from the insulating buried layer and bends toward the drain area; The dielectric isolation structure, which protrudes from the insulating buried layer and bends toward the leakage area, includes a support portion and a blocking portion; One end of the support portion is in direct contact with the insulating buried layer, and the other end of the support portion is connected to one end of the blocking portion. The other end of the blocking portion bends and extends toward the leakage area, and the blocking portion and the insulating buried layer are spaced apart.

11. The preparation method according to claim 10, characterized in that, The plurality of dielectric isolation structures spaced apart on the buried insulating layer include: A dielectric isolation layer is formed on the insulating buried layer; The dielectric isolation layer is etched to form a plurality of spaced dielectric isolation structures.

12. The preparation method according to claim 10, characterized in that, The plurality of dielectric isolation structures spaced apart on the buried insulating layer include: A silicon layer is formed on the insulating buried layer; The silicon layer is etched to form a plurality of trenches spaced apart in the silicon layer; A dielectric isolation material is coated on the silicon layer and filled into each of the trenches, and the dielectric isolation material is etched to form the dielectric isolation structure.

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