Lateral diffused metal oxide semiconductor device and method of manufacturing the same

Abstract

The present application relates to a lateral diffusion metal oxide semiconductor device and a manufacturing method thereof, the lateral diffusion metal oxide semiconductor device comprising: a second conductive type well region; a source region and a drain region in the second conductive type well region; a gate on the second conductive type well region between the drain region and the source region; a first insulating isolation structure in the second conductive type well region between the drain region and the source region, and arranged close to the drain region; a top second conductive type region arranged between the source region and the first insulating isolation structure, and arranged close to a top of the second conductive type well region, the top second conductive type region having a doping concentration greater than that of the second conductive type well region; and at least one second conductive type buried region having a doping concentration greater than that of the second conductive type well region. The present application can increase the sustain voltage, and the region which is not turned on due to current concentration can have a chance to be turned on with the increase of the sustain voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a laterally diffused metal-oxide-semiconductor device, and also to a method for manufacturing a laterally diffused metal-oxide-semiconductor device. Background Technology

[0002] With the development of automotive electronics and power integrated circuits, the use of high-voltage MOS (metal-oxide-semiconductor) devices in ESD (electrostatic discharge) protection has received increasing attention. For example, when an N-channel LDMOS (laterally diffused metal-oxide-semiconductor) device is used as an ESD protection device, its drain is connected to an I / O pin, and the gate, source, and substrate are shorted and connected to ground; this configuration is called GG-NLDMOS. Grounding the gate prevents leakage. When a forward ESD pulse occurs at the drain, the reverse-biased PN junction of the GG-NLDMOS undergoes avalanche breakdown, generating electron-hole pairs. The holes flow through the p-well resistor Rp-well of the LDMOS and finally to ground. Because the source and substrate are shorted, when the number of holes is large enough, the voltage drop across the resistor Rp-well is large enough, the PN junction turns on, triggering the parasitic NPN transistor and initiating the discharge of a large ESD current.

[0003] LDMOS, a common high-voltage device using BCD technology, presents several challenges when used as an ESD protection device. Two particularly prominent issues are current unevenness concentration and excessively low sustaining voltage. Current unevenness concentration is a major reason for the poor ESD protection performance of LDMOS devices. Summary of the Invention

[0004] Therefore, it is necessary to provide a laterally diffused metal-oxide-semiconductor device that can improve ESD protection capability when used as an ESD protection device.

[0005] A laterally diffused metal-oxide-semiconductor device includes: a second conductivity type well region; a drain region having a first conductivity type and located in the second conductivity type well region; the first conductivity type and the second conductivity type are opposite conductivity types; a source region having a first conductivity type and located in the second conductivity type well region; a gate region disposed on the second conductivity type well region between the drain region and the source region; and a first insulating isolation structure disposed in the second conductivity type well region between the drain region and the source region, and disposed close to the drain region, the first insulating isolation structure extending downward from the top of the second conductivity type well region and having a depth greater than that of the drain region. Depth; a top second conductivity type region, disposed between the source region and the first insulating isolation structure, and near the top of the second conductivity type well region, wherein the doping concentration of the top second conductivity type region is greater than the doping concentration of the second conductivity type well region; at least one second conductivity type buried region, wherein the doping concentration is greater than the doping concentration of the second conductivity type well region, and each second conductivity type buried region is at least partially disposed in a first drift region, wherein the range of the first drift region is: longitudinally from the bottom of the second conductivity type well region to the top of the second conductivity type well region, and in the conductive channel length direction from the outside of the source region to the outside of the drain region.

[0006] The aforementioned laterally diffused metal-oxide-semiconductor (MOS) devices, by incorporating a first insulating isolation structure, block the lateral movement of current between the source and drain. This forces the current path to change from lateral, close to the surface of the second conductivity type well region, to longitudinal, bypassing the first insulating isolation structure. This lengthens the current path to prevent current concentration, thereby enhancing the ESD protection capability of the MOS device as an ESD protection device. Furthermore, the introduction of a second conductivity type region at the top and a second conductivity type buried region with a concentration greater than that of the drift region increases the base region concentration of the parasitic transistor, raising the sustaining voltage. Areas in the device's drift region that were previously closed due to current concentration can now be activated with the increased sustaining voltage, further improving ESD protection capability.

[0007] In one embodiment, the number of second conductive type buried areas is at least two, and each second conductive type buried area is dispersedly disposed in the first drift area.

[0008] In one embodiment, one side of the top second conductivity type region extends to the source region and the other side extends to the first insulating isolation structure.

[0009] In one embodiment, the top of the top second conductivity type region partially overlaps with the top of the second conductivity type well region, and the depth of the top second conductivity type region is less than the depth of the source region.

[0010] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a second conductivity type lead-out region disposed in the second conductivity type well region, wherein the doping concentration of the lead-out region is greater than the doping concentration of the second conductivity type well region.

[0011] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a second insulating isolation structure and a third insulating isolation structure disposed on both sides of the lead-out region, wherein the second insulating isolation structure is located between the lead-out region and the source region, and the second insulating isolation structure and the third insulating isolation structure are located in the second conductivity type well region.

[0012] In one embodiment, the second and third insulating isolation structures extend downward from the top of the second conductivity type well region and have a depth greater than the depth of the source region and the depth of the lead-out region.

[0013] In one embodiment, the first insulating isolation structure is in direct contact with the drain region.

[0014] In one embodiment, the orthographic projection of the gate onto the upper surface of the second conductivity type well region at least partially overlaps with the edge of the drain region.

[0015] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0016] It is also necessary to provide an ESD protection device, including the laterally diffused metal-oxide-semiconductor device described in any of the foregoing embodiments, wherein the laterally diffused metal-oxide-semiconductor device is a GGNLDMOSFET.

[0017] It is also necessary to provide a method for manufacturing a laterally diffused metal-oxide-semiconductor device.

[0018] A method for manufacturing a laterally diffused metal-oxide-semiconductor device includes: obtaining a substrate, the substrate including a second conductivity type well region, a top second conductivity type region, and at least one second conductivity type buried region, wherein the doping concentration of the top second conductivity type region and the doping concentration of each second conductivity type buried region are greater than the doping concentration of the second conductivity type well region; the top second conductivity type region is located in the second conductivity type well region and is disposed near the top of the second conductivity type well region; forming a first insulating isolation structure extending downward from the top of the second conductivity type well region; forming a gate on the second conductivity type well region; and forming second conductivity types on both sides of the gate. A source region and a drain region are formed in a trap region; wherein the source region and the drain region have a first conductivity type, the first insulating isolation structure is located on the side of the drain region facing the source region and is disposed close to the drain region, and the top second conductivity type region is located between the source region and the first insulating isolation structure; each second conductivity type buried region is at least partially disposed in a first drift region, the first drift region being: longitudinally from the bottom of the second conductivity type trap region to the top of the second conductivity type trap region, and in the direction of the length of the conductive channel from the outside of the source region to the outside of the drain region; the first conductivity type and the second conductivity type are opposite conductivity types.

[0019] In one embodiment, after the step of forming a first insulating isolation structure extending downward from the surface of the second conductivity type well region, the step of forming an exit region in the second conductivity type well region, wherein the doping concentration of the exit region is greater than that of the second conductivity type well region. Attached Figure Description

[0020] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0021] Figure 1 This is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device in one embodiment;

[0022] Figure 2 This is a flowchart of a method for manufacturing a laterally diffused metal-oxide-semiconductor device in one embodiment. Detailed Implementation

[0023] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0026] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0029] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0030] A common method to improve current non-uniformity in low-voltage processes is to increase the distance between the drain contact and the gate when using multi-finger MOS devices as ESD protection devices, thus forming a ballast resistor. When the ESD device discharges current, an additional on-state voltage drop is generated through the ballast resistor, further increasing the trigger voltage and allowing previously unactivated portions to turn on and discharge the ESD current together. However, while this method improves current uniformity, it also increases the device layout.

[0031] This application proposes a laterally diffused metal-oxide-semiconductor device that can avoid current concentration problems, improve the uniformity of current distribution, and does not increase the device layout area.

[0032] Figure 1This is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device in one embodiment, including a second conductivity type well region 103, a top second conductivity type region 110, a drain region 108, a source region 107, a gate 109, a first insulating isolation structure 104, and at least one second conductivity type buried region 102.

[0033] The drain region 108 and source region 107 are located in the well region 103 of the second conductivity type, and have the first conductivity type. Figure 1 In the illustrated embodiment, the drain region 108 and the source region 107 are disposed near the upper surface of the second conductivity type well region 103. Figure 1 In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments of this application, the first conductivity type may be P-type and the second conductivity type may be N-type. A gate 109 is disposed on a second conductivity type well region 103 between the drain region 108 and the source region 107. A first insulating isolation structure 104 is disposed in the second conductivity type well region 103 between the drain region 108 and the source region 107, and is disposed close to the drain region 108. Figure 1 In the illustrated embodiment, the first insulating isolation structure 104 is in direct contact with the drain region 108. The first insulating isolation structure 104 extends downward from the upper surface of the second conductivity type well region 103 and has a depth greater than the depth of the drain region 108. The top second conductivity type region 110 is disposed between the source region 107 and the first insulating isolation structure 104, and is located close to the top of the second conductivity type well region 103. The doping concentration of the top second conductivity type region 110 is greater than the doping concentration of the second conductivity type well region 103. The doping concentration of the second conductivity type buried region 102 is greater than the doping concentration of the second conductivity type well region 103. To facilitate the description of the location of the second conductivity type buried region 102, the range of the first drift region is defined as: longitudinally from the bottom to the top of the second conductivity type well region 103, and in the direction of the conductive channel length from the outside of the source region 107 (i.e., Figure 1 From the left side of the source region 107 to the outside of the drain region 108 (i.e. Figure 1 The region to the right of the drain region 108; each of the second conductivity type buried regions 102 has at least a portion of its structure located in the first drift region.

[0034] When the aforementioned laterally diffused metal-oxide-semiconductor (MOSFET) devices are used as ESD protection devices, if they are N-channel LDMOS (first conductivity type is N-type, second conductivity type is P-type), they can be connected using a GGNLDMOS configuration (gate 109, source region 107, and substrate shorted and connected to ground). When a forward ESD pulse appears at the drain, the drain PN junction is reverse-biased, forming a leakage current. When the voltage reaches a certain level, the reverse-biased PN junction undergoes avalanche breakdown, generating electron-hole pairs. The holes flow through the resistor Rp-well formed by the second conductivity type well region 103 and finally flow to ground. Since the source and substrate are shorted, when the number of holes is large enough, the voltage drop across the resistor Rp-well is large enough. When the voltage drop across the second conductivity type well region 103 reaches the forward bias turn-on voltage, the PN junction turns on, triggering the parasitic NPN transistor and starting to discharge the large ESD current. Due to factors such as process uniformity and environment, LDMOS will exhibit a current non-uniformity across its entire drift region. The biggest impact of this current non-uniformity is that areas with higher current in the device will turn on preferentially, leading to a decrease in the holding voltage. This prevents some areas that have not yet turned on from turning on properly, thus affecting the ESD current discharge capability.

[0035] The aforementioned laterally diffused metal-oxide-semiconductor (LDMOS) device, by setting a first insulating isolation structure 104, blocks the lateral movement of current between the source and drain, forcing the current path to change from lateral (close to the surface of the second conductivity type well region 103) to longitudinal (bypassing the first insulating isolation structure 104), lengthening the current path to avoid current concentration, thereby improving the ESD protection capability of the LDMOS device as an ESD protection device. Furthermore, due to the introduction of a second conductivity type region 110 at the top and a second conductivity type buried region 102 with a concentration greater than that of the drift region, the base region concentration of the parasitic transistor (NPN transistor for N-channel LDMOS) increases, raising the holding voltage. Regions in the device's drift region that were previously closed due to current concentration can now be activated with the increased holding voltage, further improving ESD protection capability. Moreover, the aforementioned laterally diffused metal-oxide-semiconductor device does not require an increase in device area.

[0036] Furthermore, the depletion regions can be made independent of each other by adjusting the position and concentration of the top second conductivity type region 110 and each second conductivity type buried region 102, thus maintaining the device's turn-on voltage unchanged. The top second conductivity type region 110 has the same function as the second conductivity type buried region 102; in one embodiment of this application, the doping concentration of the top second conductivity type region 110 is the same as that of the second conductivity type buried region 102.

[0037] In one embodiment of this application, the number of second conductive type buried areas 102 is at least two, and each second conductive type buried area 102 is dispersedly disposed in the first drift area. To enable more areas in the drift area that are not activated due to uneven current to be activated, the second conductive type buried areas 102 are dispersed to affect more areas. In one embodiment of this application, the second conductive type buried areas 102 and the top second conductive type area 110 are evenly distributed along the longitudinal direction of the first drift area; each second conductive type buried area 102 is disposed around the center point of the first drift area.

[0038] exist Figure 1 In the embodiment shown, one side of the top second conductivity type region 110 extends to the source region 107 and the other side extends to the first insulating isolation structure 104.

[0039] In one embodiment of this application, the top of the top second conductivity type region 110 at least partially overlaps with the top of the second conductivity type well region 103, and the depth of the top second conductivity type region 110 is less than the depth of the source region 107.

[0040] In one embodiment of this application, the gate layer 109 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 109.

[0041] A gate dielectric layer can also be disposed at the bottom of the gate layer 109. Figure 1 (Not shown). The gate dielectric layer may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxides of nitride having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may comprise a dielectric material with a generally higher dielectric constant having a dielectric constant from about 20 to at least about 100. Such a higher dielectric constant dielectric material may include, but is not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0042] exist Figure 1 In the illustrated embodiment, the laterally diffused metal-oxide-semiconductor device further includes a substrate 101 of a second conductivity type. A low-doped second conductivity type well region 103 is disposed on the substrate 101. The low doping concentration of the second conductivity type well region 103 can achieve a high device breakdown voltage (high-voltage well). Figure 1In the illustrated embodiment, the laterally diffused metal-oxide-semiconductor device includes two second conductivity type buried regions 102. The upper part of one second conductivity type buried region 102 is in a second conductivity type well region 103, the lower part is in a substrate 101, and it is located below the source region 107. Its top is lower than the bottom of the other second conductivity type buried region 102 in the vertical direction. The other second conductivity type buried region 102 is located in the second conductivity type well region 103 below the top second conductivity type region 110.

[0043] exist Figure 1 In the illustrated embodiment, the laterally diffused metal-oxide-semiconductor device further includes a second conductivity type lead-out region 106 disposed in the second conductivity type well region 103. The doping concentration of the lead-out region 106 is greater than the doping concentration of the second conductivity type well region 103, serving as a lead-out of the second conductivity type well region 103. The lead-out region 106 can be disposed near the surface of the second conductivity type well region 103. Figure 1 In the embodiment shown, the lead-out region 106 is a P+ region, and the source region 107 and the drain region 108 are N+ regions.

[0044] exist Figure 1 In the illustrated embodiment, the laterally diffused metal-oxide-semiconductor device further includes a second insulating isolation structure 105a and a third insulating isolation structure 105b disposed on both sides of the lead-out region 106. The second insulating isolation structure 105a is located between the lead-out region 106 and the source region 107, and the third insulating isolation structure 105b is located on the other side of the lead-out region 106, and the second insulating isolation structure 105a and the third insulating isolation structure 105b are located in the second conductivity type well region 103.

[0045] exist Figure 1 In the illustrated embodiment, the second insulating isolation structure 105a and the third insulating isolation structure 105b extend downward from the upper surface of the second conductivity type well region 103, and their depth is greater than the depth of the source region 107 and the depth of the lead-out region 106.

[0046] In one embodiment of this application, the first insulating isolation structure 104, the second insulating isolation structure 105a, and the third insulating isolation structure 105b include an insulating material, such as silicon dioxide.

[0047] exist Figure 1 In the embodiment shown, the orthographic projection of the gate 109 onto the upper surface of the second conductivity type well region 103 at least partially overlaps with the edge of the drain region 108.

[0048] This application provides a method for manufacturing a laterally diffused metal-oxide-semiconductor device, which can be used to manufacture the laterally diffused metal-oxide-semiconductor device of any of the above embodiments. Figure 2This is a flowchart of a method for manufacturing a laterally diffused metal-oxide-semiconductor device in one embodiment, including the following steps:

[0049] S210, Obtain the substrate.

[0050] The wafer substrate includes a second conductivity type well region, a second conductivity type buried region, and a top second conductivity type region. The top second conductivity type region is located within the second conductivity type well region and is positioned near the top of the second conductivity type well region. At least a portion of the structure of the second conductivity type buried region is located within the second conductivity type well region. The doping concentration of the top second conductivity type region and the doping concentration of each second conductivity type buried region are greater than the doping concentration of the second conductivity type well region.

[0051] In one embodiment of this application, a second conductivity type well region can be formed by epitaxial growth or by ion implantation followed by push-in. The second conductivity type well region has a lower doping concentration to serve as a high-voltage well, controlling the device's breakdown voltage. Each second conductivity type buried region can be formed by high-energy ion implantation or multiple epitaxial growth methods. The top second conductivity type region can be formed by ion implantation.

[0052] S220, forming a first insulating isolation structure extending downward from the top of the second conductivity type well region.

[0053] In one embodiment of this application, step S220 includes trench etching of the second conductivity type well region, followed by filling the trench with an insulating material. In one embodiment of this application, the insulating material includes silicon dioxide.

[0054] S230, a gate is formed on the well region of the second conductivity type.

[0055] The gate is formed by depositing a gate material, followed by photolithography and etching. In one embodiment of this application, polysilicon is deposited as the gate material using low-pressure chemical vapor deposition.

[0056] S240 forms a source region and a drain region in a second conductivity type well region on both sides of the gate.

[0057] The source and drain regions have a first conductivity type and can be formed by ion implantation into a well region of a second conductivity type. Since a gate has already been formed, the source-drain implantation can be self-aligned. A first insulating isolation structure is located on the side of the drain region facing the source region and is disposed close to the drain region. In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment of this application, the first conductivity type is P-type and the second conductivity type is N-type.

[0058] After step S240, an interlayer dielectric layer can be formed on the wafer, followed by the formation of contact holes and metal interconnect layers.

[0059] The aforementioned method for manufacturing a laterally diffused metal-oxide-semiconductor (MOS) device, by setting a first insulating isolation structure, blocks the lateral movement of current between the source and drain. This forces the current path to change from lateral (close to the surface of the second conductivity type well region) to longitudinal (bypassing the first insulating isolation structure), lengthening the current path to avoid current concentration. This enhances the ESD protection capability of the MOS device as an ESD protection device. Furthermore, the introduction of a second conductivity type region at the top and a second conductivity type buried region with a concentration greater than that of the drift region increases the base region concentration of the parasitic transistor, raising the holding voltage. Areas in the device's drift region that were previously closed due to current concentration can now be activated with the increased holding voltage, further improving ESD protection capability.

[0060] In one embodiment of this application, step S210 further includes performing field oxidation before forming the top second conductivity type region, thereby forming an oxide layer in the terminal region outside the active region.

[0061] In one embodiment of this application, after step S220, a step of forming a lead-out region in the second conductivity type well region is further included. The doping concentration of the lead-out region is greater than the doping concentration of the second conductivity type well region, and it serves as the lead-out of the second conductivity type well region.

[0062] In one embodiment of this application, the step of forming a second insulating isolation structure and a third insulating isolation structure extending downward from the top of the second conductivity type well region is included before step S230. Specifically, trench etching is performed on the second conductivity type well region to form two trenches, and then insulating material is filled into the trenches to form the second insulating isolation structure and the third insulating isolation structure. In one embodiment of this application, the insulating material includes silicon dioxide. A lead-out region is formed between the second insulating isolation structure and the third insulating isolation structure, and a source region and a top second conductivity type region are formed between the second insulating isolation structure and the first insulating isolation structure.

[0063] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0064] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A laterally diffused metal-oxide-semiconductor device, characterized in that, include: Second type of conductivity well region; The drain region, having a first conductivity type, is located in the well region of the second conductivity type; The first conductivity type and the second conductivity type are opposite conductivity types; The source region, having a first conductivity type, is located in the well region of the second conductivity type; A gate is disposed on a second conductivity type well region between the drain region and the source region; A first insulating isolation structure is disposed in a second conductivity type well region between the drain region and the source region, and is disposed close to the drain region. The first insulating isolation structure extends downward from the top of the second conductivity type well region and has a depth greater than the depth of the drain region. A top second conductivity type region is disposed between the source region and the first insulating isolation structure, and is disposed near the top of the second conductivity type well region. One side of the top second conductivity type region extends to the source region and the other side extends to the first insulating isolation structure. The doping concentration of the top second conductivity type region is greater than the doping concentration of the second conductivity type well region. At least one second conductivity type buried region has a doping concentration greater than that of the second conductivity type well region. Each second conductivity type buried region is at least partially located in a first drift region. The first drift region extends from the bottom of the second conductivity type well region to the top of the second conductivity type well region in the longitudinal direction, and from the outside of the source region to the outside of the drain region in the conductive channel length direction.

2. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The number of the second conductive type buried areas is at least two, and each of the second conductive type buried areas is dispersed in the first drift area.

3. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

4. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The top of the top second conductivity type region coincides with the top of the second conductivity type well region, and the depth of the top second conductivity type region is less than the depth of the source region.

5. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, It also includes a second conductivity type lead-out region disposed in the second conductivity type well region, wherein the doping concentration of the lead-out region is greater than the doping concentration of the second conductivity type well region.

6. The laterally diffused metal-oxide-semiconductor device according to claim 5, characterized in that, It also includes a second insulating isolation structure and a third insulating isolation structure disposed on both sides of the lead-out region, wherein the second insulating isolation structure is located between the lead-out region and the source region, and the second insulating isolation structure and the third insulating isolation structure are located in the second conductivity type well region.

7. The laterally diffused metal-oxide-semiconductor device according to claim 6, characterized in that, The second and third insulating isolation structures extend downward from the top of the second conductivity type well region and have a depth greater than the depth of the source region and the depth of the lead-out region.

8. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The first insulating isolation structure is in direct contact with the drain region.

9. An ESD protection device, characterized in that, Includes the laterally diffused metal-oxide-semiconductor device as described in any one of claims 1-8, wherein the laterally diffused metal-oxide-semiconductor device is a GGNLDMOSFET.

10. A method for manufacturing a laterally diffused metal-oxide-semiconductor device, comprising: A substrate is obtained, the substrate comprising a second conductivity type well region, a top second conductivity type region, and at least one second conductivity type buried region, wherein the doping concentration of the top second conductivity type region and the doping concentration of each second conductivity type buried region are greater than the doping concentration of the second conductivity type well region; the top second conductivity type region is located in the second conductivity type well region and is disposed near the top of the second conductivity type well region; A first insulating isolation structure is formed extending downward from the top of the second conductivity type well region; A gate is formed on the well region of the second conductivity type; A source region and a drain region are formed in a second conductivity type well region on both sides of the gate; The source region and drain region have a first conductivity type. The first insulating isolation structure is located on the side of the drain region facing the source region and is disposed close to the drain region. The top second conductivity type region is located between the source region and the first insulating isolation structure. One side of the top second conductivity type region extends to the source region and the other side extends to the first insulating isolation structure. Each second conductivity type buried region is at least partially disposed in a first drift region. The first drift region extends longitudinally from the bottom of the second conductivity type well region to the top of the second conductivity type well region, and in the direction of the conductive channel length, it extends from the outside of the source region to the outside of the drain region. The first conductivity type and the second conductivity type are opposite conductivity types.

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