N-phase staggered control method for primary-side isolated dc-dc converter

Abstract

The application belongs to the field of electrical control, and specifically provides an N-phase staggered control method for a primary side isolated DC-DC converter, which comprises a leading A single-phase power channel and N-1 auxiliary power channels; the isolated feedback communication of the N-phase primary side is only completed through the isolated feedback communication of the primary side of the leading A single-phase power channel; the control condition for implementing the staggered control of the N-phase inductor current critical discontinuity and discontinuity is that the time Ton during which the N-phase inductor currents reach their respective peak values from zero N The application only needs one-way side-to-primary communication to ensure that the isolated N-phase output inductor currents work in critical discontinuity or discontinuity, which is beneficial to reduce the implementation cost and simplify the circuit complexity.

Description

Technical Field

[0001] This invention belongs to the field of electrical control, specifically relating to an N-phase misalignment control method for a primary-secondary-side isolated DC-DC converter. Background Technology

[0002] In primary-secondary-side isolated DC-DC converter applications, as output power increases, the voltage and current stress on each power device in a single-phase (or single-channel) forward converter circuit also increases accordingly. This is especially true when the output inductor current of the power circuit operates under critical discontinuous current conditions; the peak output inductor current will be twice the average output current, and the corresponding ripple current will be the current from 0 to the peak value. If N-phase staggered control is used, the ripple will be significantly reduced. Figure 1 As shown, for example, using 4-phase staggered control, the corresponding output ripple current is less than one-quarter of the critical discontinuous current ripple of a single-phase circuit. Using N-phase staggered control in a power circuit increases the number of active power switches and passive components by N times; simultaneously, due to primary-secondary side isolation requirements, the cost of primary-secondary side signal transmission channels is relatively high. If N-phase control requires N primary-secondary side signal transmission channels, this will significantly increase the cost and complexity of implementing N-phase control; this is why N-phase staggered control is typically only used in non-isolated DC-DC converters.

[0003] For isolated single-phase output power supplies, from the perspective of passive components, as output power increases, the size of the forward converter isolation transformer and output inductor increases, leading to increased manufacturing costs. This increased size of passive components also reduces the power supply's space utilization. However, by employing N-phase staggered control, the power transmitted by each phase power channel is 1 / N of the total power, and the corresponding passive component size will be 1 / N of the size of the passive components in a single-phase output, thus improving the power supply's space utilization. As output power increases, the hotspot temperature, where losses occur in active power switches and passive components, also increases. For isolated single-phase output power supplies, due to the single-phase output, the corresponding hotspots are concentrated. With N-phase staggered control, the power transmitted by each power channel is 1 / N of the total power, and the corresponding hotspots are dispersed, reducing the hotspot temperature. This reduction in hotspot temperature is crucial for increasing output power.

[0004] When the output inductor current operates under critical discontinuous or intermittent conditions, the corresponding switching period varies with the input and output voltages, output current, and output inductance value. In other words, the switching period from zero to peak value and then back to zero for the output inductor current is variable depending on the input and output voltages, output current, and output inductance value. N-phase staggered control requires that the output inductor current of each phase occur precisely at N equal divisions of the same switching period. Clearly, a necessary condition for this is that the repetition period of the output inductor current in each phase must be identical. Furthermore, considering the ±20% error distribution factor in the output inductance value of each phase during mass production, appropriate control is necessary to ensure that the switching periods corresponding to the inductor current in each phase are equal.

[0005] In single-channel output power supply solutions with isolation requirements, if the output inductor current is required to operate at a critically discontinuous or discontinuous state, and if this output inductor is on the secondary side, communication between the secondary and primary sides is necessary. This communication requires the secondary side to inform the primary side when the output inductor current has decayed to zero, when the next switching cycle begins, and whether the output inductor current controlled by the primary side is appropriate. Because these three pieces of information need to be transmitted, commonly used optocouplers are insufficient due to their limited response speed; a suitable communication circuit is needed to transmit this information in real time. Various implementation schemes for such a suitable communication circuit are available but are not discussed in this invention. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an N-phase misalignment control scheme for an isolated DC-DC converter.

[0007] To address the aforementioned technical problems, this invention provides an N-phase misalignment control method for a primary-secondary side isolated DC-DC converter: comprising a dominant A-phase single-phase power channel and an N-1 phase auxiliary power channel; the isolation feedback communication between the N-phase primary and secondary sides is accomplished solely through the isolation feedback communication between the primary and secondary sides of the dominant A-phase single-phase power channel; the control condition for implementing critical discontinuity and discontinuous misalignment control of the N-phase inductor current is the duration Ton of each N-phase inductor current reaching its respective peak value from zero. N same.

[0008] As an improvement to the N-phase misalignment control method of the primary-secondary-side isolated DC-DC converter of the present invention: the dominant single-phase power channel is phase A, and one of the N-1 phase auxiliary power channels is phase I;

[0009] The inductor current I that dominates the single-phase power channel A LA From zero to its peak value ΔI A Duration Ton A The inductor currents I of the phase I auxiliary power channel LI From zero to their respective peak values ​​ΔI IDuration Ton I Same, i.e., Ton A =Ton I .

[0010] As a further improvement to the N-phase misalignment control method of the primary-secondary-side isolated DC-DC converter of the present invention:

[0011] The forward N-phase misalignment control power circuit includes a primary-side control module, an isolation communication module, a secondary-side control module, a dominant A single-phase power channel, and several parallel power channels I (I represents any one of B to N);

[0012] The primary control module has a corresponding output Dr A and Dr Ⅰ The Dr Ⅰ Including Dr B Dr N (i.e., Dr) Ⅰ Representing Dr B Dr N (any one of them);

[0013] The primary-side control module is equipped with a corresponding primary-side current detection input terminal Vcsp. A and Vcsp Ⅰ The Vcsp Ⅰ Including Vcsp B ...,Vcsp N (i.e., Vcsp) Ⅰ Represents Vcsp B ...,Vcsp N (any one of them);

[0014] The secondary control module has corresponding output Dr A1 and Dr I1 The Dr I1 Including Dr B1 Dr N1 (i.e., Dr) I1 Representing Dr B1 Dr N1 (any one of them);

[0015] The auxiliary edge control module has a corresponding Dr A2 and Dr I2 The Dr I2 Including Dr B2 Dr N2 (i.e., Dr) I2 Representing Dr B2 Dr N2 (any one of them);

[0016] Regarding the dominant single-phase power channel A, including the primary-side power switch Q A Secondary-side power switch MOSFET A1 Secondary-side power switch MOSFET A2 Primary winding Np A Secondary winding Ns A And the primary-side current detection voltage circuit, the corresponding output voltage is Vcsp. A Primary power switch Q A The output Dr on the gate and primary-side control module A Connected, primary-side power switch Q A The drain and primary winding Np A Connect the non-identical terminals; primary-side power switch Q A The source electrode is connected to ground via a current detection circuit; one end of the primary voltage source Vin is connected to the primary winding Np. A The same-named terminal is connected; the other terminal is grounded; the connection between the primary-side voltage source Vin and the primary-side control module provides feedback for the primary-side voltage; the secondary-side power switch MOS... A1 Output Dr on the gate and secondary side control module A1 Connected, secondary power switch MOS A1 The drain and secondary winding Ns A Non-identical terminals are connected; secondary power switch MOS A1 The source is connected to the secondary side ground; the secondary side power switch MOS A2 Output Dr on the gate and secondary side control module A2 Connected, secondary power switch MOS A2 The drain and secondary winding Ns A The same name terminal and inductor L A One end is connected; secondary power switch MOS A2 The source and secondary side are connected to ground; inductor L A The other end is connected to the secondary voltage Vo; the connection between the secondary voltage Vo and the secondary control module is to provide feedback for the output voltage Vo.

[0017] For the parallel power channel I (I represents any one of B to N), its connection relationship is equivalent to the dominant single-phase power channel A.

[0018] Note: Ⅰ represents any one of B to N. The primary-side power switch Q of phase I... I For example, Q represents the primary-side power switch of phase I. B～ Primary power switch Q N Any one of them. That is, output Dr. I For Dr B Dr N Any one of them, and so on for the rest.

[0019] As a further improvement to the N-phase misalignment control method of the primary-secondary side isolated DC-DC converter of the present invention: due to the inductor current I of each phase LI From zero to their respective peak values ​​ΔI I Duration Ton I The inductors in each phase have the same energy storage volt-second value, therefore the inductor current I corresponding to each phase power channel is the same. LI From its peak value ΔI I The duration Toff that decays to zero I They are also equal. Because the inductance L of each phase... I Current rise duration Ton I The same duration Toff decays to zero I They are also equal, the inductor current I in each phase is... LI The switching repetition cycles are equal.

[0020] As a further improvement to the N-phase misalignment control method of the primary-secondary-side isolated DC-DC converter of the present invention:

[0021] In an N-phase isolated power circuit, the primary and secondary power switches Q that dominate the A-phase isolated power circuit are... A MOS A1 and MOS A2 The on / off control is influenced by the input / output voltage and the output inductance L. A Medium current magnitude control; secondary side control circuit module based on output inductance L A The change in current generates a corresponding control signal to control the power switch MOS. A1 and MOS A2 And set the corresponding primary-side power switch Q. A The relevant control information is transmitted from the isolated communication module to the primary control module via the self-side; the primary control module adjusts the primary power switch Q according to the received information. A Perform conduction time control;

[0022] The primary-side power switch Q of phase I in an isolated N-phase power circuit I The conduction time Ton is controlled by this primary control module. I That is, the primary-side power switch Q of phase I. I On-time Ton I Equal to the primary-side power switch Q of phase A A On-time Ton A Similarly, the secondary-side power switch MOS of the I-phase of the N-phase power circuit is isolated. I1 and MOS I2 All of these are controlled by the side control module.

[0023] Ultimately, the switching on-time Ton of each phase's main power switch is controlled. Isame.

[0024] As a further improvement to the N-phase misalignment control method of the primary-secondary-side isolated DC-DC converter of the present invention: Phase A is the dominant single-phase power channel; the secondary-side control module of Phase A sends corresponding pulses to the primary-side control module of Phase A and receives them through the isolation communication interface module; the output of the isolation communication interface module is respectively given to the accumulator and phase splitter modules of the control section of Phase A;

[0025] Since the primary-side power switches of phase A and phase I have the same on-time, it can be ensured that the switching cycles corresponding to the inductor currents in each phase are equal.

[0026] Therefore, only one communication path from the secondary side to the primary side is needed to ensure that the isolated N-phase output inductor currents all operate at critical discontinuous or intermittent conditions.

[0027] As a further improvement to the N-phase misalignment control method of the primary-secondary-side isolated DC-DC converter of the present invention: the secondary-side control module sends corresponding pulses to the primary-side control module, which are received by the isolation communication interface module; the output of the isolation communication interface module is given to the accumulator A and the phase splitter module respectively; the accumulator A determines the increase, decrease or maintenance of the output voltage of the accumulator A according to the output of the isolation communication interface module; the phase splitter performs N-phase phase splitting according to the pulse repetition period corresponding to the output of the isolation communication interface module, generating corresponding N-phase pulses and levels.

[0028] As a further improvement to the N-phase misalignment control method of the primary-secondary-side isolated DC-DC converter of the present invention:

[0029] Make the power switch on-time Ton in the I-phase power channel I Equal to and following the on-time Ton of the A-phase power switch A It is necessary to change the value of accumulator I, Vref, in the I-phase power channel. I This is achieved indirectly by reducing the on-time Ton of the power switch within the I-phase power channel. I Equal to and following the on-time Ton of the A-phase power switch A .

[0030] As a further improvement to the N-phase misalignment control method of the primary-secondary-side isolated DC-DC converter of the present invention:

[0031] Make the power switch on-time Ton in the I-phase power channel I Equal to and following the on-time Ton of the A-phase power switch A It is necessary to control the on-time (Ton) of the A-phase power switch. A The rising and falling edges are reconstructed by comparing the phase voltage of phase I with the phase voltage of phase I through two integrator circuits. This makes the on-time Ton of the power switch in the phase I power channel... IEqual to and following the on-time Ton of the A-phase power switch A .

[0032] This invention has the following characteristics:

[0033] 1. It has a suitable control method to ensure that the switching repetition period corresponding to the output inductor current in each phase can be equal;

[0034] 2. Only one communication path from the secondary side to the primary side is needed to ensure that the isolated N-phase output inductor currents all operate at critical discontinuous or discontinuous levels; this helps to reduce implementation costs and simplify circuit complexity.

[0035] 3. Facilitates the generation of N-phase misalignment control pulse sequences to control the on / off state of N-phase power devices;

[0036] 4. Compared with single-phase isolated output power supply, since the output power of each phase is one-Nth of the total output power, the hot spot temperature of the N-phase staggered control output power supply will be significantly reduced. Attached Figure Description

[0037] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0038] Figure 1 The graph shows the total output inductor current ripple of the existing multiphase non-isolated control scheme. It is clear that the output ripple of the N-phase misalignment control system decreases as the number of phases N increases.

[0039] Figure 2 A simplified diagram of the forward-type isolated N-phase power circuit and control circuit for implementing the technical solution of this invention is provided (the reset circuit of the forward transformer is omitted for the purpose of discussing the control method in a targeted manner).

[0040] Figure 3 To achieve the solution of embodiment 1 of the present invention Figure 2 The block diagram related to the primary edge control module is shown below.

[0041] Figure 4 To achieve the solution of embodiment 2 of the present invention Figure 2 The relevant block diagram of the primary edge control module in the diagram.

[0042] Figure 5 for Figure 3 , Figure 4 or Figure 6 A block diagram illustrating the specific implementation of the phase splitter in the diagram;

[0043] Figure 6 To achieve the solution of embodiment 3 of the present invention Figure 2 The relevant block diagram of the primary edge control module in the diagram. Detailed Implementation

[0044] The present invention will be further described below with reference to specific embodiments, but the scope of protection of the present invention is not limited thereto:

[0045] The overall technical concept of this invention is as follows:

[0046] The N-phase misalignment control technology of this invention is conceived as follows: it consists of a dominant A-phase single-phase power channel and N-1 phase auxiliary power channels; the isolation feedback communication between the primary and secondary sides of the N-phase is accomplished solely through the isolation feedback communication between the primary and secondary sides of the dominant A-phase single-phase power channel. The control condition for implementing this N-phase inductor current critical discontinuity and discontinuous misalignment control is the duration (Ton) for each N-phase inductor current to reach its respective peak value from zero. N The same, that is, the inductor current I that dominates the single-phase power channel A. LA From zero to its peak value ΔI A Duration Ton A The inductor currents I of the phase I auxiliary power channel LI From zero to their respective peak values ​​ΔI I Duration Ton I Same, i.e., Ton A =Ton I .

[0047] Specifically, such as Figure 2 As shown in the simplified diagram of the forward N-phase misalignment control power circuit,

[0048] It includes a primary-side control module, an isolation communication module, a secondary-side control module, a dominant A single-phase power channel, and several parallel power channels I (I represents any one of B to N);

[0049] The primary control module has a corresponding output Dr A and Dr Ⅰ The Dr Ⅰ Including Dr B Dr N (i.e., Dr) Ⅰ Representing Dr B Dr N (any one of them);

[0050] The primary-side control module is equipped with a corresponding primary-side current detection input terminal Vcsp. A and Vcsp Ⅰ The Vcsp Ⅰ Including Vcsp B ...,Vcsp N (i.e., Vcsp) Ⅰ Represents Vcsp B ...,Vcsp N (any one of them);

[0051] The secondary control module has corresponding output Dr A1 and Dr I1 The Dr I1 Including Dr B1 Dr N1 (i.e., Dr) I1 Representing Dr B1 Dr N1 (any one of them);

[0052] The auxiliary edge control module has a corresponding Dr A2 and Dr I2 The Dr I2 Including Dr B2 Dr N2 (i.e., Dr) I2 Representing Dr B2 Dr N2 (any one of them);

[0053] Regarding the dominant single-phase power channel A, including the primary-side power switch Q A Secondary-side power switch MOSFET A1 Secondary-side power switch MOSFET A2 Primary winding Np A Secondary winding Ns A And the primary-side current detection voltage circuit, the corresponding output voltage is Vcsp. A Primary power switch Q A The output Dr on the gate and primary-side control module A Connected, primary-side power switch Q A The drain and primary winding Np A Connect the non-identical terminals; primary-side power switch Q A The source electrode is connected to ground via a current detection circuit; one end of the primary voltage source Vin is connected to the primary winding Np. A The primary side is connected to the same terminal; the other terminal is grounded; the connection between the primary-side voltage source Vin and the primary-side control module provides feedback for the primary-side voltage. Secondary-side power switch MOS. A1 Output Dr on the gate and secondary side control module A1 Connected, secondary power switch MOS A1 The drain and secondary winding Ns A Non-identical terminals are connected; secondary power switch MOS A1 The source is connected to the secondary side ground. Secondary-side power switch MOS. A2 Output Dr on the gate and secondary side control module A2 Connected, secondary power switch MOS A2 The drain and secondary winding Ns A The same name terminal and inductor L AOne end is connected; secondary power switch MOS A2 The source and secondary side are connected to ground; inductor L A The other end is connected to the secondary voltage Vo. The connection between the secondary voltage Vo and the secondary control module is to provide feedback for the output voltage Vo.

[0054] For the parallel power channel I (I represents any one of B to N), its connection relationship is equivalent to the dominant single-phase power channel A.

[0055] That is, including the primary-side power switch Q I Secondary-side power switch MOSFET I1 Secondary-side power switch MOSFET I2 Primary winding Np I Secondary winding Ns I And the primary-side current detection voltage circuit, the corresponding output voltage is Vcsp. I Primary power switch Q I The output Dr on the gate and primary-side control module I Connected, primary-side power switch Q I The drain and primary winding Np I Connect the non-identical terminals; primary-side power switch Q I The source electrode is connected to ground via a current detection circuit; one end of the primary voltage Vin is connected to the primary winding Np. I One terminal is connected to the same terminal; the other terminal is grounded. Secondary-side power switch MOSFET I1 Output Dr on the gate and secondary side control module I1 Connected, secondary power switch MOS I1 The drain and secondary winding Ns I Non-identical terminals are connected; secondary power switch MOS I1 The source is connected to the secondary side ground; the secondary side power switch MOS I2 Output Dr on the gate and secondary side control module I2 Connected, secondary power switch MOS I2 The drain and secondary winding Ns I The same name terminal and inductor L I One end is connected; secondary power switch MOS I2 The source and secondary side are connected to ground; inductor L I The other end is connected to the secondary voltage Vo.

[0056] Note: The subscript Ⅰ represents any one of B to N. The primary-side power switch Q... I For example, Q represents the primary-side power switch of phase I. B～ Primary power switch Q N Any of them.

[0057] For ease of explanation, assume that the turns ratio n of the primary and secondary windings of each forward isolation transformer is 1. When the power originates from the primary winding Np I Transmitted to secondary winding Ns I At that time, the primary-side power switch Q of phase I I On-time Ton I That is, the inductor current I of phase I power channel LI From zero to its peak value ΔI I Duration Ton I for:

[0058]

[0059] The corresponding inductor current I of the I-phase power channel LI From its peak value ΔI I The duration Toff that decays to zero I for:

[0060]

[0061] like Figure 2 As shown, for an N-phase power channel, the primary input voltage of each phase power channel is Vin, while the secondary output voltage of each phase power channel is V. O From expressions (1) and (2), it can be seen that: if the on-time of the primary power switch of each phase is Ton I Equal, that is:

[0062] Ton A =Ton B =....=Ton I =Ton I+1 =....=Ton N

[0063] This means that the energy storage volt-seconds of each phase inductor are equal, that is:

[0064] L A *ΔI A =L B *ΔI B =....=L I *ΔI I =L I+1 *ΔI I+1 =....=L N *ΔI N

[0065] Since the energy storage volt-seconds of the inductors in each phase are equal, it can be seen from expression 2 that the inductor current I corresponding to each phase power channel is... LI From its peak value ΔI I The duration Toff that decays to zero IThey are equal.

[0066] When power is transferred from the primary side to the secondary side, if the on-time of the primary-side power switches in each phase can be reduced to Ton... I If they are the same, the inductor current I in each phase power channel can be made the same. LI From its peak value ΔI I The duration Toff that decays to zero I They are also equal, thus allowing the inductor current I in each phase power channel to be equal. LI The repetition period Ts I same.

[0067] Due to the on-time Ton of the primary-side power switches of each phase I The same energy storage capacity ensures that the volt-seconds of each phase inductor are equal, even if the inductance L... I The value changes by ±20%, corresponding to the switch on-time Ton. I Corresponding inductor current I LI From its peak value ΔI I The duration Toff that decays to zero I They are also equal. Considering the inductance L... I The value typically varies by ±20%, which will only affect ΔI. I The magnitude of the change in inductor current I in each phase power channel LI The repetition period Ts I Keep it the same.

[0068] When power is transferred from the primary side to the secondary side, if the power switches Q of each phase's primary side can be made to... I On-time Ton I If they are the same, the inductance L of each phase power channel can be made the same. I The current can be satisfied strictly according to the necessary condition of appearing at N equal times in a switching cycle, that is, the repetition period of the inductor current in each phase power channel is the same.

[0069] Specifically, such as Figure 2 For the N-phase misalignment control power circuit diagram shown, for ease of explanation, it is assumed that the turns ratio n of the primary and secondary windings of each isolation transformer is 1. When power is transferred from the secondary side to the primary side, the power switches MOS of each phase secondary side... I2 On-time Ton I That is, the inductor current I of phase I power channel LI The duration of Ton from zero to its peak I for:

[0070]

[0071] The corresponding power channel inductor current I LI From its peak value ΔI IThe duration Toff that decays to zero I for:

[0072]

[0073] For an N-phase power channel, the primary-side output voltage of each power channel is V. IN The secondary input voltage of each power channel is V. O From expressions (3) and (4), it can be seen that: if the power switches MOS on the secondary side of each phase... I2 On-time Ton I Equal, that is:

[0074] Ton A =Ton B =....=Ton I =Ton I+1 =.....=Ton N

[0075] This means that the energy storage volt-seconds of each phase inductor are equal, that is:

[0076] L A *ΔI A =L B *ΔI B =....=L I *ΔI I =L I+1 *ΔI I+1 =....=L N *ΔI N

[0077] Since the energy storage volt-seconds of the inductors in each phase are equal, it can be seen from expression 4 that the inductor current I corresponding to each phase power channel is... LI From its peak value ΔI I The duration Toff that decays to zero I They are equal.

[0078] When power is transferred from the secondary side to the primary side, if it can make the power switching MOS of each phase secondary side... I2 On-time Ton I If they are the same, the inductor current I in each phase power channel can be made the same. LI From its peak value ΔI I The duration Toff that decays to zero I They are also equal, thus allowing the inductor current I in each phase power channel to be equal. LI The repetition period Ts I same.

[0079] Due to the power switching MOS of each phase side I2 On-time TonI The same can make each phase inductance L I The energy storage volt-seconds are equal, even if the inductor L I The value changes by ±20%, corresponding to the switch on-time Ton. I Corresponding inductor current I LI From its peak value ΔI I The duration Toff that decays to zero I They are also equal. Considering the inductance L... I A change of ±20% in the value only affects ΔI. I The magnitude of the change in inductor current I in each phase power channel LI The repetition period Ts I Keep it the same.

[0080] When power is transferred from the secondary side to the primary side, if it can make the power switching MOS of each phase secondary side... I2 On-time Ton I If they are the same, the inductance L of each phase power channel can be made the same. I The current can be satisfied strictly according to the necessary condition of appearing at N equal times in a switching cycle, that is, the repetition period of the inductor current in each phase power channel is the same.

[0081] Based on the above-described technical control concept of the present invention. Figure 2 This is a simplified diagram of the isolated multiphase power circuit and control circuit of the present invention. In this N-phase isolated power circuit, the primary and secondary power switches Q that dominate the A-phase isolated power circuit are... A MOS A1 and MOS A2 The on / off control is influenced by the input / output voltage and the output inductance L. A Medium current magnitude control. The secondary-side control circuit module is based on the output inductance L. A The change in current generates a corresponding control signal to control the power switch MOS. A1 and MOS A2 And set the corresponding primary-side power switch Q. A Relevant control information is transmitted from the isolated communication module to the primary control module. The primary control module then adjusts the primary power switch Q based on the received information. A Control the conduction time.

[0082] The primary-side power switch Q of the I-phase of this isolated N-phase power circuit I The conduction time Ton is controlled by this primary control module. I That is, the primary-side power switch Q of phase I. I On-time Ton I Equal to the primary-side power switch Q of phase A A On-time Ton ASimilarly, the secondary-side power switch MOS of the I-phase of this isolated N-phase power circuit. I1 and MOS I2 All of these are controlled by this primary-side control module. Specifically, how does the primary-side control module control the primary-side power switch Q of phase I? I On-time Ton I Equal to the primary-side power switch Q of phase A A On-time Ton A As illustrated in the following embodiments.

[0083] The specific control methods provided in these embodiments aim to ultimately control the on-time (Ton) of each phase's main power switch. I The control methods are identical for both forward power transmission (power transfer from the primary side to the secondary side) and reverse power transmission (power transfer from the secondary side to the primary side). The following discussion will focus on forward power transmission, specifically the primary side control module. The same principle applies to reverse power transmission. Since it is an N-phase staggered control, that is, the power switches Q of each phase power channel... I The conduction timing is staggered, and the power switching Q of each phase power channel must be synchronized. I On-time Ton I There are multiple implementation schemes to achieve this N-phase misalignment control.

[0084] Example 1: As Figure 3 As shown Figure 2 A circuit block diagram of the internal part of a primary-side control module.

[0085] exist Figure 3 In the block diagram shown, phase A is the dominant single-phase power channel. The secondary-side control module of phase A sends corresponding pulses to the primary-side control module of phase A. Figure 3 The isolated communication interface module shown receives signals; its output is sent to the accumulator and phase splitter modules of the A-phase control section. The accumulator can be implemented in various ways, for example, by combining a digital up / down counter with a digital-to-analog converter. The accumulator determines whether its output voltage increases, decreases, or remains constant based on the output of the isolated communication interface module. The phase splitter performs N-phase splitting based on the pulse repetition period corresponding to the output of the isolated communication interface module, generating corresponding N-phase pulses and levels. A more detailed implementation diagram is shown below. Figure 5 As shown.

[0086] exist Figure 3 In the block diagram shown, the control section corresponding to phase A in the primary control module has an accumulator output level Vref that is passed through the phase A comparator U. A Compare the output voltage Cs of the primary-side current detection voltage circuit of phase A; the phase splitter in the primary-side control module outputs the phase A pulse, which will then... A When the flip-flop is set to "1", comparator UA The output of D A The trigger is reset to "0". D A The trigger output pulse is converted into an analog voltage V via a time-to-voltage conversion and holding circuit (TV-Holder). TONA This simulates voltage V TONA The on-time control of the primary-side power switches used to control other power channels, i.e. Figure 3 As shown, the phase splitter outputs an I-phase pulse (this I-phase power channel represents a power channel for N-phase misalignment control) to D I When the flip-flop is set to "1", comparator U I The output of D I The flip-flop is reset to "0"; note the comparator U. I The input voltages are analog voltages V TONA and D I The output pulse width of the trigger corresponds to the analog voltage V. I (t); Analog voltage V I (t) is D I The output pulse width of the trigger is obtained via a time-to-voltage converter (T-V_I). A Triggers and D I The trigger output pulse is output as Dr via the corresponding drive circuit. A and Dr I Used for driving Figure 2 The primary-side power switch Q A and Q I .

[0087] For the dominant A-phase power channel, the output inductance L A On the secondary side, the control circuit on the secondary side will detect the output inductance L. A Average current, output inductance L A The zero-crossing time of the current and the determination of when to start a new switching cycle. The secondary-side control circuit transmits data to the primary-side control circuit through an isolated communication channel from the secondary side to the primary side: output inductor L A The moment when the current crosses zero, the start of the next switching cycle, and the output inductance L A The average current requirement information; the primary-side control circuit determines when to start the next switching cycle based on the received information; the phase splitter in the primary-side control module divides the time into N equal parts according to the length of the previous switching cycle; the phase splitter outputs N phase pulses in a staggered manner to start the corresponding A~N phase primary-side power switches to conduct, that is, due to the A phase pulse output by the phase splitter, after passing through D... A The Set input of the flip-flop makes the D phase of phase A... A The trigger outputs logic "1", meaning the primary-side power switch Q of phase A channel is 1. A Dr. AThe primary-side power switch Q is set to a high level. A On. Primary-side power switch Q A The cutoff time is determined by the output inductor L. A The timing of when the current reaches its peak value is determined by this.

[0088] Based on the output inductance L A The time of current zero crossing and the required output inductance L A The average current is used in the accumulator circuit corresponding to phase A in the primary-side control circuit (this accumulator can be composed of an up / down counter + analog-to-digital converter DAC, or other circuits such as a switched capacitor circuit) to maintain and adjust the reference level Vref of the maximum current required to flow through the primary-side power switch, which corresponds to the output inductor L. A The current reflected to the primary side detection voltage Vcs is continuously compared with the reference level Vref; after the primary side power switch conduction time Ton A When the current flowing through the primary-side power switch increases from zero to the peak current of the output inductor corresponding to the reference level Vref, the comparator U... A The output logic high level jumps up via the Ck clock, causing D to... A The trigger outputs logic "0", which makes the output drive Dr A The lower limit is zero level, and the primary-side power switch Q... A Up to; D A The trigger output is the input to the TV-Holder time-to-voltage converter module, which sets the primary-side power switch on for a time Ton. A The quantity is converted into a voltage quantity with a fixed slope k, when the primary-side power switch is on for Ton. A The maximum voltage V at the end of this conversion TonA The output will be sampled and preserved; V TonA It will be refreshed with each subsequent switching cycle. Note: The time-to-voltage conversion and hold module (TV-Holder) can be implemented using various circuits, such as in D... A When the flip-flop outputs a logic high level, a fixed current source charges a fixed capacitor. The magnitude of the current source and the capacitor value determine a fixed slope k; in D A At the moment the trigger outputs down, the fixed current source stops charging the fixed capacitor, and the voltage across the fixed capacitor is sampled and held; alternatively, a high-frequency clock and counter can be used to control D. A The flip-flop output is a logic high-level timer for a specific period, and the counter reading is stored in a register. The digital value of the counter stored in the register is then output as an analog value via an analog-to-digital converter. This high-frequency clock frequency, the number of bits in the counter, and the corresponding analog-to-digital converter determine a fixed slope k.

[0089] The I-phase pulse output from the phase splitter is processed by D. I The Set input of the flip-flop makes the D phase of phase I... I The trigger output is logic "1", meaning the primary-side power switch Q of phase I channel is 1. I Dr. I The primary-side power switch Q is set to a high level. I On. The primary-side power switch Q of phase I channel is turned on. I The cutoff time is determined by the conduction time Ton of the dominant A phase. A It was decided.

[0090] Due to the time-to-voltage conversion and the TV-Holder module output, the on-time of the dominant A phase, Ton, is... A The corresponding output voltage V TonA The on-time Ton of the primary-side power switch of phase I I Subject to output voltage V TonA Control, specifically the on-time Ton of the primary-side power switch of phase I. I This can be achieved via a time-to-voltage converter module (TVI). (Note: A time-to-voltage converter module (TVI) can be implemented using various circuits, such as in D...) I When the flip-flop outputs a logic high level, a fixed current source charges a fixed capacitor. The magnitude of the current source and the capacitor value determine a fixed slope k; in D I At the moment the trigger output jumps, this fixed current source charges a fixed capacitor; alternatively, a high-frequency clock and counter can be used to charge D. I The trigger output times out during a logic high-level period, and the digital value of the counter is converted to an analog value by an analog-to-digital converter. The high-frequency clock, the number of bits in the counter, and the corresponding analog-to-digital converter determine a fixed slope k; the primary-side power switch Q... I On-time Ton I The quantity is converted into a voltage quantity V with a fixed slope k. I (t); when V I (Ton I () Greater than or equal to V TonA At that time, comparator U I The comparator outputs a high level, and the rising edge of this comparator is input via the clock ck, causing D to... I When the trigger outputs logic "0", the corresponding drive output pulse Dr I The down-switch is at "0" level, and the primary-side power switch Q of phase I is... I Up to this point, since the time-to-voltage converter TV uses the same fixed slope k, the primary-side power switch Q of phase I... I On-time Ton I It is equal to the power switch Q that dominates phase A. A On-time Ton A Because of VTonA The on-time Ton of the primary-side power switch of phase I will be refreshed with each subsequent switching cycle. I It will also be refreshed with each subsequent switching cycle. The secondary-side control circuit can transmit information such as the average current of the A-phase output inductor, the load current, and the output voltage to the primary-side control circuit via the isolated communication channel from the secondary side to the primary side. This information includes the zero-crossing time of the A-phase output inductor current, the start time of the next switching cycle, and the average current requirement of the output inductor current. In this way, it can adjust the appropriate on-time Ton of the power switches of each of the N phases on the primary side. A ...Ton I ...Ton N To balance input and output power, so that the output voltage V O Within the predetermined range.

[0091] In this embodiment, the primary-side control circuit has only one accumulator circuit controlling the A-phase power channel to maintain and adjust the reference level Vref of the maximum current required to flow through the A-phase primary-side power switch, which corresponds to the peak current of the A-phase output inductor. Due to the effect of this maximum current reference level Vref, the primary-side input voltage V... IN The change will not change the peak current of the output inductor, but will change the on-time Ton of the dominant phase A. A The change occurs, that is, with the change in the primary input voltage V IN The increase in the dominance of the A phase's conduction time Ton A The decrease is conversely, the increase is also conversely; that is, due to the effect of the reference level Vref of this maximum current, this loop control has feedforward control characteristics. This is due to the on-time Ton of the primary-side power switch of phase I. I It is equal to and follows the conduction time Ton of the dominant A phase. A The on-time Ton of the primary-side power switch of phase I I The control also has feedforward control characteristics.

[0092] Since the primary-side power switches of phases A and I have the same on-time, the switching cycles corresponding to the inductor currents in each phase can be guaranteed to be equal. Thus, only one communication path from the secondary side to the primary side is needed to ensure that the isolated N-phase output inductor currents all operate at critical discontinuous or intermittent states. This helps reduce implementation costs and simplify circuit complexity. It also facilitates the generation of N-phase staggered control pulse sequences to control the on / off state of the N-phase power devices. Compared to single-phase isolated output power supplies, since the output power of each phase is only one-Nth of the total output power, the hot spot temperature of the N-phase staggered control output power supply will be significantly reduced.

[0093] Example 2: Figure 4 As shown Figure 2 Another type of primary-side control module internal circuit block diagram.

[0094] exist Figure 4 In the block diagram shown, the secondary-side control module sends corresponding pulses to the primary-side control module. Figure 4 The isolated communication interface module shown receives data; its output is sent to accumulator A and phase splitter module respectively. Accumulator A can be implemented in various ways, for example, by combining a digital up / down counter with a digital-to-analog converter. Accumulator A determines whether its output voltage increases, decreases, or remains constant based on the output of the isolated communication interface module. The phase splitter performs N-phase splitting based on the pulse repetition period corresponding to the output of the isolated communication interface module, generating corresponding N-phase pulses and levels. A more detailed implementation diagram is shown below. Figure 5 As shown.

[0095] exist Figure 4 In the block diagram shown, the output level Vref of accumulator A corresponding to the dominant power channel of phase A is... A via A phase comparator U A The output voltage Cs of the primary current detection voltage circuit of phase A A Comparison; the phase splitter outputs phase A pulses to phase D A When the flip-flop is set to "1", comparator U A The output of D A The trigger is reset to "0". D A The trigger output pulse is converted into an analog voltage V via a time-to-voltage conversion and holding circuit (TV-Holder). TONA This simulates voltage V TONA The on-time control of the primary-side power switches used to control other power channels, i.e. Figure 4 As shown, the phase splitter outputs the I-phase pulse, which will then... I When the flip-flop is set to "1", comparator U2 I The output of D I The flip-flop is reset to "0"; note comparator U2. I The input voltages are respectively the output level Vref of the I-phase accumulator I. I The output voltage Cs of the primary current detection voltage circuit of phase I I The I-phase accumulator I is composed of the I-phase pulse from the phase splitter and comparator U1. I The control determines the output level Vref of accumulator I. I Size; Comparator U1 I The input voltage is an analog voltage V. TONA and D I The output pulse width of the trigger corresponds to the analog voltage V. I (t); Analog voltage V I (t) is D I The output pulse width of the trigger is obtained through a time-to-voltage converter and a TV-Holder. ATriggers and D I The trigger output pulse is output as Dr via the corresponding drive circuit. A and Dr I Used to drive the primary-side power switch Q A and Q I .

[0096] For the dominant A-phase power channel, the output inductance L A On the secondary side, the control circuit on the secondary side will detect the output inductance L. A Average current, output inductance L A Information on the zero-crossing current and information determining when to begin a new switching cycle. The secondary-side control circuit transmits this information to the primary-side control circuit via an isolated communication channel from the secondary side to the primary side: output inductor L A The moment when the current crosses zero, the start of the next switching cycle, and the output inductance L A The average current requirement information; the primary-side control circuit determines when to start the next switching cycle based on the received information; within the primary-side control module, the phase splitter divides the time into N equal parts according to the duration of the previous switching cycle; the phase splitter outputs staggered I-phase pulses to start the corresponding I-phase primary-side power switch, that is, due to the A-phase pulse output by the phase splitter, after passing through D... A The Set input of the flip-flop makes the D phase of phase A... A The trigger outputs logic "1", meaning the primary-side power switch Q of phase A channel is 1. A Dr. A The primary-side power switch Q is set to a high level. A On. Primary-side power switch Q A The cutoff time is determined by the output inductor L of phase A power channel. A The timing of when the current reaches its peak value is determined by this.

[0097] Based on the output inductance L A The time of current zero crossing and the required output inductance L A The average current is used by accumulator A in the primary-side control circuit to maintain and adjust the reference level Vref, which represents the maximum current required to flow through the primary-side power switch. A That is, the output inductance L corresponding to the A-phase power channel A The peak current; after passing through the primary-side power switch Q A On-time Ton A Primary power switch Q A Detection voltage V of the current flowing through it CSA Increment from zero to the corresponding reference level Vref A The peak current of the corresponding output inductor; when the detected voltage V CSA Equal to and greater than the reference level Vref A Comparator UA The transition to logic high level is caused by a jump on the Ck clock, which causes D to... A The trigger outputs logic "0", which makes the output drive Dr A The lower limit is zero level, and the primary-side power switch Q... A As of now; the primary-side control circuit contains a time-to-voltage conversion and holding module TV-Holder_A, which switches the primary-side power switch Q... A On-time Ton A The quantity is converted into a voltage quantity with a fixed slope k, when the primary-side power switch is on for Ton. A The maximum voltage V at the end of this conversion TonA The output will be sampled and preserved; V TonA It will be refreshed with each subsequent on / off cycle.

[0098] In the primary-side control circuit of phase I, phase I has an accumulator circuit to maintain and adjust the reference level Vref corresponding to the maximum current required to flow through the primary-side power switch of that phase. I That is, the corresponding output inductance L I The peak current, and a time-to-voltage conversion and holding module TV-Holder_I, which sets the on-time Ton of the primary-side power switch of phase I. I The quantity is converted into a voltage quantity V with a fixed slope k. TonI And sample and hold.

[0099] Due to the dominance of the A-phase conduction time Ton of the time-to-voltage converter module TV-Holder_A output... A The corresponding output voltage V TonA The primary power switch Q of phase I I On-time Ton I It can indirectly accept the output voltage V TonA control.

[0100] Because the I-phase pulse output by the phase splitter, after passing through D... I The Set input of the flip-flop makes the D phase of phase I... I The trigger output is logic "1", meaning the primary-side power switch Q of phase I channel is 1. I Dr. I The primary-side power switch Q is set to a high level. I On. Primary-side power switch Q I The cutoff time is determined by the output inductor L of the I-phase power channel. I The timing of when the current reaches its corresponding peak value is determined by the current.

[0101] The accumulator circuit of phase I is used to maintain and regulate the primary-side power switch Q. I Reference level Vref for the maximum current required to flowI The detection voltage V of phase I CSI Signal and reference level Vref I via comparator U2 I Comparison, when the detection voltage V CSI Equal to and greater than the reference level Vref I Comparator U2 I The transition to logic high level is caused by a jump on the Ck clock, which causes D to... I The trigger outputs logic "0", which makes the output drive Dr I The lower limit is zero level, and the primary-side power switch Q... I As of now.

[0102] The primary power switch Q of phase I I On-time Ton I The time-to-voltage converter and hold circuit TV-Holder_I converts the primary-side power switch Q of phase I. I On-time Ton I Quantity converted to voltage V TonI Comparator U1 I V TonA With V TonI Compare, if V TonA >V TonI Comparator U1 I The output is high, which means Vref I <Vref A Vref needs to be added. I Comparator U1 I The output enables the accumulator to increment, so that Vref is increased in the next switching cycle. I This allows for an increase in the primary-side power switch Q of phase I. I On-time Ton I In the next switching cycle, comparator U1 I V again TonA With V TonI Compare, if V TonA >V TonI Comparator U1 I The output logic level controls the accumulator to increment, until V. TonI Equal to and follow V TonA ;vice versa.

[0103] Due to V TonA The on-time Ton of the primary-side power switch of phase I will be refreshed with each subsequent switching cycle. IIt will also be refreshed with each subsequent switching cycle. The secondary-side control circuit can transmit the average current of the A-phase output inductor, the load current, and the output voltage to the primary-side control circuit via the isolated communication channel from the secondary side to the primary side. The output inductance L A Information such as the current zero-crossing moment, the start time of the next switching cycle, and the average current requirement of the output inductor current is used to adjust the appropriate on-time Ton of the primary-side N-phase power switch. A ...Ton J ...Ton N To balance input and output power, so that the output voltage V O Within the predetermined range.

[0104] In this embodiment, in the primary-side control circuit of the N-phase power channel, each phase has an accumulator circuit to maintain and adjust the reference level Vref of the maximum current required to flow through the primary-side power switch. I This refers to the peak current of the output inductor of that phase; due to the reference level Vref of this maximum current. I The function of the primary input voltage V IN The change will not change the peak current of the output inductor, but will change the on-time Ton of the N-phase. I The change occurs, that is, with the change in the primary input voltage V IN Increase the conduction time Ton of the N phase I Decrease, and vice versa; that is, due to the reference level Vref of this maximum current. I This loop control has feedforward control characteristics.

[0105] In Example 2, the accumulator value Vref of the dominant A-phase power channel A The value Vref is controlled by the secondary side feedback signal, which increases or decreases accordingly. However, the accumulator value Vref in other N-1 phase power channels, such as the I-phase power channel, is also affected. I It does not directly follow the increase or decrease controlled by the secondary side feedback signal. The value Vref of the accumulator in the I-phase power channel. I It is determined by continuously comparing the on-time Ton of the A-phase power switch. A With the power switch on-time Ton in the I-phase power channel I During the calibration process, Vref I It is generated by increasing and decreasing from zero.

[0106] In Example 2, the on-time Ton of the power switch in the I-phase power channel is set. I Equal to and following the on-time Ton of the A-phase power switch A It is necessary to change the value Vref of the accumulator in the I-phase power channel. IThis is achieved indirectly by reducing the on-time Ton of the power switch within the I-phase power channel. I Equal to and following the on-time Ton of the A-phase power switch A Because it is an indirect method, the on-time Ton of the power switch in the I-phase power channel is reduced. I Equal to and following the on-time Ton of the A-phase power switch A This means the on-time Ton I It gradually converges to Ton whether it is greater than or less than Ton. A That is, it cannot be guaranteed that the conduction time Ton will be minimized within one switching cycle. I Equal to and following the on-time Ton of the A-phase power switch A In Example 1, the conduction time Ton is made possible within one switching cycle. I Equal to and following the on-time Ton of the A-phase power switch A .

[0107] In the block diagrams of the primary-side control module in Examples 1 and 2, there is a phase splitter. Its function is to divide the previous switching cycle, i.e., the switching cycle of the dominant A-phase power channel, into N equally divided N-phase pulses to achieve N-phase misalignment control. This phase splitter can be implemented in various ways, including analog, digital, and hybrid digital-analog schemes. Here, a hybrid digital-analog scheme is used as an example... Figure 5 Let me illustrate this with the example shown. For instance... Figure 5 As shown:

[0108] In this hybrid digital-analog scheme, the switching pulse period signal Ts obtained through the isolated communication interface is integrated into an integrated voltage V by an integrator circuit with a fixed integration slope k. INT_Ts (t) A linearly increasing waveform from zero, with a reset pulse TsB at the end of each switching cycle to reset the integrator pulse. The output of the integrator circuit with a fixed integration slope k is the input of a follower. This follower consists of a resettable adder counter (reset pulse is TsB), a clock ck, a comparator U, and an analog-to-digital converter DAC1. The output of the integrator circuit is the input of the follower circuit, ensuring that the output voltage of the follower's analog-to-digital converter DAC1 follows the output voltage V of the integrator circuit. INT_Ts (t) Linearly increasing waveform from zero. At the end of this switching cycle, the data in the resettable adder counter is first stored in the register of the corresponding bit, i.e., the register of the corresponding bit is refreshed; then the resettable adder counter and the integrator circuit with a fixed integration slope k are reset by the reset pulse TsB. The follower circuit consisting of the resettable adder counter, clock ck, comparator U, and analog-to-digital converter DAC1 enters the next switching cycle to integrate the voltage V. INT_Ts(t) The waveform voltage is linearly increased from zero to perform a follow-up operation. Clearly, different switching cycles correspond to different output voltages. This switching cycle is measured and updated cycle by cycle, so the data in the corresponding bit register is refreshed at the end of each switching cycle, and the output voltage of the analog-to-digital converter DAC2 (which has the same performance as DAC1) also changes cycle by cycle. The analog voltage output by the corresponding bit register through DAC2 is the analog voltage V corresponding to the previous switching cycle. INT_Ts (Ts N-1 Thus, the analog voltage V output by the analog-to-digital converter DAC2 in the previous switching cycle... INT_Ts (Ts N-1 The voltage divider network outputs the trigger levels and pulses corresponding to phases B, C, ..., I and N, respectively. B V C ...V I and V N Thus, the analog voltage V of the previous switching cycle INT_Ts (Ts N-1 The trigger levels of phases B, C, ..., I and N, output through an equally divided voltage divider resistor network, are V. B V C ...V I and V N This will be used to determine when the conduction pulses of phase B, phase C, ..., phase I and phase N appear within this switching cycle. Obviously, the pulse at the beginning of each switching cycle corresponds to the phase A pulse.

[0109] Example 3, such as Figure 6 As shown Figure 2 Another type of primary-side control module internal circuit block diagram.

[0110] like Figure 6 As shown: In Figure 6 In the block diagram shown, the secondary-side control module sends corresponding pulses to the primary-side control module. Figure 6 The isolated communication interface module shown receives data; its output is sent to accumulator A and phase splitter module respectively. Accumulator A can be implemented in various ways, for example, by combining a digital up / down counter with a digital-to-analog converter. Accumulator A determines whether its output voltage increases, decreases, or remains constant based on the output of the isolated communication interface module. The phase splitter performs N-phase splitting based on the pulse repetition period corresponding to the output of the isolated communication interface module, generating corresponding N-phase pulses and levels. A more detailed implementation diagram is shown below. Figure 6 As shown.

[0111] exist Figure 6 In the block diagram shown, the output level Vref of accumulator A is... A via A phase comparator UA The output voltage Cs of the primary current detection voltage circuit of phase A A Comparison; the phase splitter outputs phase A pulses to phase D A When the Q and QB terminals of the flip-flop are set to "1" and "0" respectively, the comparator U... A The output of D A The Q and QB terminals of the flip-flop are reset to "0" and "1" respectively. A The rising edges of the Q and QB terminals of the flip-flop respectively activate two resettable integrator circuits with fixed integration slopes k (the slope k of these integrator circuits is related to...). Figure 5 The integrator circuits with the fixed integral slope k are identical. The output voltage of both integrator circuits with the fixed integral slope k increases linearly from zero. D A The rising edge of the Q input of the trigger starts the integrator circuit with a fixed integration slope k; the output voltage V of this integrator circuit INT_DRA (t) The voltage increases linearly from zero; the output voltage V of this integrator circuit. INT_DRA (t) and the I-phase level output from the phase splitter are compared by comparator U IUP Continuous comparison; similarly, D A The rising edge of the QB terminal of the trigger starts another integrator circuit with a fixed integration slope k; the output voltage V of this integrator circuit INT_DRAB (t) The voltage increases linearly from zero; the output voltage V of this integrator circuit. INT_DRAB (t) is also related to the I-phase level output from the phase splitter via comparator U. Idown Continuous comparison; when D A The rising edge of the Q terminal of the flip-flop triggers the output voltage V of the integrator circuit. INT_DRA (t) is equal to or greater than the I-phase output level of the phase splitter, and the comparator U IUP Output high level via D I The ck terminal of the flip-flop makes D I The flip-flop outputs Q at a "1" level; when D A The rising edge of the QB terminal of the flip-flop triggers the output voltage V of the integrator circuit. INT_DRAB (t) is equal to or greater than the I-phase output level of the phase splitter, and the comparator U Idown Output high level via D I The Reset terminal of the trigger makes D I The flip-flop output Q is set to "0". This sets D to a level that is 0. I The Q output of the trigger is driven by the corresponding driver module to output Dr. I And drive the primary-side power switch Q I The reset signals for these two integrator circuits with fixed integration slopes k that can be reset are D, respectively. N The trigger outputs Q and QB.

[0112] The phase splitter outputs a trigger pulse for phase A, which is then transmitted via D...A The Set input of the flip-flop makes the D phase of phase A... A The trigger outputs logic "1", meaning the primary-side power switch Q of phase A channel is 1. A Dr. A The primary-side power switch Q is set to a high level. A On. Primary-side power switch Q A The cutoff time is determined by the output inductor L. A The timing of when the current reaches its peak value is determined by this.

[0113] Based on the output inductance L A The time of current zero crossing and the required output inductance L A The average current is used in the primary-side control circuit accumulator A circuit (this accumulator can be composed of an up / down counter + analog-to-digital converter DAC, or it can be composed of a switched capacitor circuit) to maintain and adjust the primary-side power switch Q. A Reference level Vref for the maximum current required to flow A That is, the corresponding output inductance L A The current is reflected to the primary side detection voltage Vcs A With reference level Vref A Continuous comparison; after passing through the primary-side power switch Q A On-time Ton A When the primary power switch Q A The current flowing through it increases from zero to the corresponding reference level Vref A When the peak current of the output inductor is corresponding to the comparator U A The output logic high level jumps up via the Ck clock, causing D to... A The trigger outputs logic "0", which makes the output drive Dr A The down-step is at zero level, that is, a conduction pulse is generated that dominates phase A, and its pulse width corresponds to the conduction time Ton. A .

[0114] For the rising edge of the conduction pulse that dominates phase A, Dr A and falling edge Dr AB Two integrator circuits with the same integration slope k are started respectively. The voltage of both integrator circuits increases from zero until the rising edge of the N-phase conduction pulse disappears, and the rising edge Dr... A The integrator circuit that starts is Dr N Clear to zero; until the falling edge of the N-phase conduction pulse disappears, then the falling edge Dr... AB The integrator circuit that starts is Dr NB Clear to zero. Due to the rising edge Dr A The integrator circuit that starts up is compared to the falling edge Dr AB The integrator circuit starts early, with the rising edge Dr AThe output voltage of the integrator circuit at startup will always be greater than the falling edge Dr. AB The output voltage of the integrator circuit upon startup. The rising slope of the output voltage of these two integrator circuits is the same as the rising slope of the output voltage of the integrator circuit during the switching cycle, and the slope is k.

[0115] The process of generating the I-phase conduction pulse is as follows: when the rising edge Dr... A The output voltage V of the integrator circuit at startup INT_DRA (t) is equal to or greater than the I-phase output trigger level V I After comparator U IUP Output jump logic via D I The clock ck of the flip-flop makes D I The flip-flop outputs logic "1"; while when the falling edge Dr... AB The output voltage V of the integrator circuit at startup INT_DRAB (t) is equal to or greater than the trigger level V I After comparator U IDOWN Output jump logic via D I The trigger's Reset makes D I When the trigger outputs logic "0", it generates a conduction pulse for phase I. The pulse width of this conduction pulse is Ton. I The conduction time Ton of the conduction pulse of phase A A Same; similarly, when the rising edge Dr A The output voltage V of the integrator circuit at startup INT_DRA (t) is equal to or greater than the C-phase trigger level V C After comparator U CUP Output jump logic via D C The clock ck of the flip-flop makes D C The flip-flop outputs logic "1"; while when the falling edge Dr... AB The output voltage V of the integrator circuit at startup INT_DRAB (t) is equal to or greater than the trigger level V C After comparator U CDOWN Output jump logic via D C The trigger's Reset makes D C When the trigger outputs logic "0", it generates a conduction pulse for phase C. The pulse width of this conduction pulse is Ton. C The conduction time Ton of the conduction pulse of phase A A The same principle is used to generate conduction pulses for phases I and N, corresponding to the conduction time Ton of the conduction pulse. I =Ton C =.....=Ton N =Ton A =Ton BThe implementation result of this embodiment is the same as that of Embodiment 1, where the conduction pulse width time of the output conduction pulse of all N-1 phases is the same as the conduction pulse width time of the conduction pulse of the dominant power channel of phase A.

[0116] In this embodiment, the primary-side control circuit of the dominant A-phase power channel includes an accumulator A circuit to maintain and adjust the reference level Vref of the maximum current required to flow through the primary-side power switch. A That is, the corresponding output inductance L A The peak current; due to the reference level Vref of this maximum current. A The function of the primary input voltage V IN The change will not change the peak current of the output inductor, but will change the on-time Ton of the dominant phase A. A The change occurs, that is, with the change in the primary input voltage V IN The increase in the conduction time Ton of the dominant A phase A Decrease, and vice versa; that is, due to the reference level Vref of this maximum current. A This loop control exhibits feedforward control characteristics due to the on-time Ton of the primary-side power switch in phase I. I It is equal to and follows the conduction time Ton of the dominant A phase. A The on-time Ton of the primary-side power switch of phase I I The control also has feedforward control characteristics.

[0117] In Example 1, the pulse width of the conduction pulse of the dominant power channel of phase A is converted into an analog voltage, and this analog voltage is used to reconstruct the conduction pulse widths of phases B, C, ... J, ... and N. Example 3 uses the rising and falling edges of the conduction pulse of the dominant power channel of phase A to reconstruct the conduction pulse widths of phases B, C, ... J, ... and N; this eliminates the need for the time-voltage converter and hold (TV-Holder) in Example 1, but requires the addition of two integrator circuits with a resettable fixed integration slope k.

[0118] Finally, it should be noted that the above examples are merely some specific embodiments of the present invention. Obviously, the present invention is not limited to the above embodiments and many variations are possible. All variations that can be directly derived or conceived by those skilled in the art from the disclosure of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A method for controlling the N-phase misalignment of a primary-secondary-side isolated DC-DC converter, characterized in that: This includes the dominant A-phase power channel and the N-1 phase auxiliary power channel; the isolation feedback communication between the primary and secondary sides of the N-phase is completed solely through the isolation feedback communication between the primary and secondary sides of the dominant A-phase power channel; the control condition for implementing critical discontinuity and discontinuity staggered control of the N-phase inductor current is the duration Ton of each N-phase inductor current from zero to its respective peak value. N same; The forward N-phase misalignment control power circuit includes a primary-side control module, an isolation communication module, a secondary-side control module, a dominant A-phase power channel, and several parallel power channels I. The primary control module has a corresponding output Dr A and Dr Ⅰ The Dr Ⅰ Including Dr B Dr N ; The primary-side control module is equipped with a corresponding primary-side current detection input terminal Vcsp. A and Vcsp Ⅰ The Vcsp Ⅰ Including Vcsp B ...,Vcsp N ; The secondary control module has corresponding output Dr A1 and Dr I1 The Dr I1 Including Dr B1 Dr N1 ; The secondary control module has corresponding output Dr A2 and Dr I2 The Dr I2 Including Dr B2 Dr N2 ; Regarding the dominant single-phase power channel A, including the primary-side power switch Q A Secondary-side power switch MOSFET A1 Secondary-side power switch MOSFET A2 Primary winding Np A Secondary winding Ns A And the primary-side current detection voltage circuit, the corresponding output voltage is Vcsp. A Primary power switch Q A The output Dr on the gate and primary-side control module A Connected, primary-side power switch Q A The drain and primary winding Np A Connect the non-identical terminals; primary-side power switch Q A The source electrode is connected to ground via a current detection circuit; one end of the primary voltage source Vin is connected to the primary winding Np. A The same-named terminal is connected; the other terminal is grounded; the connection between the primary-side voltage source Vin and the primary-side control module provides feedback for the primary-side voltage; the secondary-side power switch MOS... A1 Output Dr on the gate and secondary side control module A1 Connected, secondary power switch MOS A1 The drain and secondary winding Ns A Non-identical terminals are connected; secondary power switch MOS A1 The source is connected to the secondary side ground; the secondary side power switch MOS A2 Output Dr on the gate and secondary side control module A2 Connected, secondary power switch MOS A2 The drain and secondary winding Ns A The same name terminal and inductor L A One end is connected; secondary power switch MOS A2 The source and secondary side are connected to ground; inductor L A The other end is connected to the secondary voltage Vo; the connection between the secondary voltage Vo and the secondary control module is to provide feedback for the output voltage Vo. Regarding the parallel power channel I, its connection relationship is equivalent to that of the dominant single-phase power channel A.

2. The N-phase misalignment control method for a primary-secondary-side isolated DC-DC converter according to claim 1, characterized in that: The dominant single-phase power channel is phase A, and the N-1 phase auxiliary power channel is phase I. The inductor current I that dominates the single-phase power channel A LA From zero to its peak Duration Ton A The inductor currents I of each phase auxiliary power channel LI From zero to their respective peak values Duration Ton I Same, that is, Ton A =Ton I .

3. The N-phase misalignment control method for a primary-secondary-side isolated DC-DC converter according to claim 2, characterized in that: Since the energy storage volt-seconds of each phase inductor are equal, the inductor current I corresponding to each phase power channel is... LI From its peak The duration Toff that decays to zero I They are equal.

4. The N-phase misalignment control method for a primary-secondary-side isolated DC-DC converter according to claim 2, characterized in that: In a forward N-phase misaligned control power circuit, the primary and secondary power switches Q of the main A-phase isolation power circuit are... A MOS A1 and MOS A2 The on / off control is influenced by the input / output voltage and the output inductance L. A Medium current magnitude control; secondary side control circuit module based on output inductance L A The change in current generates a corresponding control signal to control the power switch MOS. A1 and MOS A2 ; And set the corresponding primary-side power switch Q A The relevant control information is transmitted from the isolated communication module to the primary control module via the self-side transmission. The primary control module then adjusts the primary power switch Q based on the received information. A Perform conduction time control; The primary-side power switch Q of phase I in a forward N-phase misalignment control power circuit I The conduction time Ton is controlled by this primary control module. I That is, the primary-side power switch Q of phase I. I On-time Ton I Equal to the primary-side power switch Q of phase A A On-time Ton A Similarly, the secondary power switch MOS of phase I in this forward N-phase misalignment control power circuit I1 and MOS I2 All of these are controlled by this edge control module; Ultimately, the switching on-time Ton of each phase's main power switch is controlled. I same.

5. The N-phase misalignment control method for a primary-secondary-side isolated DC-DC converter according to any one of claims 1 to 4, characterized in that: Phase A is the dominant single-phase power channel; the secondary control module of phase A sends corresponding pulses to the primary control module of phase A, which are received by the isolated communication interface module; the output of the isolated communication interface module is given to the accumulator and phase splitter modules of the phase A control section respectively; Since the primary-side power switches of phase A and phase I have the same on-time, it can be ensured that the switching cycles corresponding to the inductor currents in each phase are equal. Therefore, only one communication path from the secondary side to the primary side is needed to ensure that the isolated N-phase output inductor currents all operate at critical discontinuous or intermittent conditions.

6. The N-phase misalignment control method for a primary-secondary-side isolated DC-DC converter according to any one of claims 1 to 4, characterized in that: The secondary control module sends corresponding pulses to the primary control module, which are received by the isolation communication interface module. The output of the isolation communication interface module is sent to accumulator A and phase splitter module respectively. Accumulator A determines whether to increase, decrease or maintain the output voltage of the accumulator based on the output of the isolation communication interface module. The phase splitter performs N-phase phase splitting according to the pulse repetition period corresponding to the output of the isolation communication interface module, generating corresponding N-phase pulses and levels.

7. The N-phase misalignment control method for a primary-secondary-side isolated DC-DC converter according to claim 6, characterized in that: Make the power switch on-time Ton in the I-phase power channel I Equal to and following the on-time Ton of the A-phase power switch A It is necessary to change the value Vref of the accumulator in the I-phase power channel. I This is achieved indirectly by reducing the on-time Ton of the power switch within the I-phase power channel. I Equal to and following the on-time Ton of the A-phase power switch A .

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