logic control circuit, flip-flop, and pulse generator circuit

Abstract

The application provides a logic control circuit, a flip-flop and a pulse generation circuit. The logic control circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and an output circuit. The first end of the first MOS transistor is connected to a power supply, and the second end of the first MOS transistor is connected to the first end of the second MOS transistor. The second end of the second MOS transistor is connected to the first end of the third MOS transistor, and the second end of the third MOS transistor is grounded. The second end of the first MOS transistor is also used for connecting the first end of the output circuit. The second end of the output circuit is used as the output end of the logic control circuit and is also used for connecting the control end of the first MOS transistor. The control end of the second MOS transistor is used for receiving a first clock signal, and the control end of the third MOS transistor is used for receiving a second clock signal. The second clock signal has the same waveform as the first clock signal and is delayed from the first clock signal by a preset time length. The application simplifies the design of the circuit, reduces energy consumption and reduces the time delay from receiving the clock signal to generating the pulse signal.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a logic control circuit, a flip-flop, and a pulse generation circuit. Background Technology

[0002] Currently in the field of integrated circuit technology, when the circuit containing the trigger implements high-speed pulses or very narrow pulses, the output response signal has a long delay. Increasing the size of the transmission gate or inverter in the circuit can effectively reduce the delay, but increasing the size of the transmission gate or inverter will lead to an increase in circuit power consumption, and the response delay will be more serious in the case of low-voltage circuits. Summary of the Invention

[0003] The main purpose of this application is to provide a variety of logic control circuits, flip-flops and pulse generation circuits, which aim to reduce the time delay of the pulse signals output by the circuit.

[0004] In a first aspect, this application provides a logic control circuit, the logic control circuit comprising:

[0005] A first MOSFET, a second MOSFET, a third MOSFET, and an output circuit; the first terminal of the first MOSFET is connected to a power supply, and the second terminal of the first MOSFET is connected to the first terminal of the second MOSFET; the second terminal of the second MOSFET is connected to the first terminal of the third MOSFET, and the second terminal of the third MOSFET is grounded;

[0006] The second terminal of the first MOS transistor is also used to connect to the first terminal of the output circuit. The second terminal of the output circuit serves as the output terminal of the logic control circuit, and the second terminal of the output circuit is also used to connect to the control terminal of the first MOS transistor, so as to control the on / off state of the first MOS transistor through the pulse signal of the second terminal of the output circuit.

[0007] The control terminal of the second MOS transistor is used to receive the first clock signal, and the control terminal of the third MOS transistor is used to receive the second clock signal. The second clock signal has the same waveform as the first clock signal, but is delayed by a preset time.

[0008] When the first MOSFET is turned on, the voltage signal at the second terminal of the first MOSFET is high; and when the level of the first clock signal is different from the level of the second clock signal, the second MOSFET or the third MOSFET is turned off so that the second terminal of the first MOSFET remains high.

[0009] When the first MOSFET is turned off, and when the level of the first clock signal is the same as the level of the second clock signal, both the second MOSFET and the third MOSFET are turned on to set the voltage at the second terminal of the first MOSFET to a low level.

[0010] Secondly, this application also provides another logic control circuit, the logic control circuit comprising:

[0011] A first MOSFET, a second MOSFET, a third MOSFET, and an output circuit; the first terminal of the first MOSFET is connected to a power supply, and the second terminal of the first MOSFET is connected to the first terminal of the second MOSFET; the second terminal of the second MOSFET is connected to the first terminal of the third MOSFET, and the second terminal of the third MOSFET is grounded;

[0012] The second terminal of the second MOS transistor is also connected to the first terminal of the output circuit. The second terminal of the output circuit serves as the output terminal of the logic control circuit. The second terminal of the output circuit is also connected to the control terminal of the third MOS transistor so as to control the on / off state of the third MOS transistor through the pulse signal of the second terminal of the output circuit.

[0013] The first MOSFET further includes a control terminal for receiving a first clock signal, and the second MOSFET further includes a control terminal for receiving a second clock signal. The second clock signal has the same waveform as the first clock signal, but is delayed by a preset time compared to the first clock signal.

[0014] When the third MOS transistor is turned off, and when the level of the first clock signal is the same as the level of the second clock signal, both the first MOS transistor and the second MOS transistor are turned on to set the second terminal of the first MOS transistor to a high level.

[0015] When the level of the first clock signal is different from the level of the second clock signal, the first MOSFET or the second MOSFET is turned off; and when the third MOSFET is turned on, the second terminal of the first MOSFET is set to a low level.

[0016] Thirdly, this application also provides a trigger, the trigger comprising:

[0017] The logic control circuit as described in the first aspect above; or the logic control circuit as described in the second aspect above.

[0018] Fourthly, this application also provides a pulse generating circuit, the pulse generating circuit comprising:

[0019] The logic control circuit described in the first aspect above;

[0020] A first time-delay inverting circuit is provided, with one end receiving the first clock signal and the other end connected to the control terminal of the third MOS transistor to input the generated second clock signal into the control terminal of the third MOS transistor, so that the second clock signal is delayed by a first preset time compared to the first clock signal.

[0021] Fifthly, this application also provides a pulse generating circuit, the pulse generating circuit comprising:

[0022] The logic control circuit as described in the second aspect above;

[0023] A first time delay inverting circuit, one end of which is used to receive the first clock signal, and the other end is connected to the control terminal of the second MOS transistor;

[0024] The second delay inverting circuit is connected between the second terminal of the second MOS transistor and the control terminal of the third MOS transistor. The second delay inverting circuit is used to invert and delay the pulse signal at the second terminal of the second MOS transistor so that the pulse signal received by the control terminal of the third MOS transistor is delayed by a preset time compared with the pulse signal at the second terminal of the second MOS transistor.

[0025] Sixthly, this application also provides a pulse generating circuit, the pulse generating circuit comprising:

[0026] The logic control circuit as described in the second aspect above;

[0027] A time delay inverting circuit, one end of which is used to receive the first clock signal, and the other end is connected to the control terminal of the second MOS transistor;

[0028] A delay circuit is connected between the second terminal of the second MOS transistor and the control terminal of the third MOS transistor. The delay circuit is used to delay the voltage signal output from the second terminal of the second MOS transistor so that the pulse signal received by the control terminal of the third MOS transistor is delayed by a preset time compared with the pulse signal from the second terminal of the second MOS transistor.

[0029] This application provides a logic control circuit, a flip-flop, and a pulse generation signal. This application reduces the number of electronic components in the circuit by having multiple MOS transistors work together to simplify circuit design, and can reduce the delay of the response signal under low voltage operating conditions. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram of a logic control circuit provided in an embodiment of this application;

[0032] Figure 2 A schematic diagram of a clock signal for a logic control circuit provided in an embodiment of this application;

[0033] Figure 3 A schematic diagram of a logic control circuit provided for another embodiment of this application;

[0034] Figure 4 A schematic diagram of a logic control circuit provided in an embodiment of this application;

[0035] Figure 5 A schematic diagram of a logic control circuit provided for another embodiment of this application;

[0036] Figure 6 A schematic diagram of a logic control circuit provided for another embodiment of this application;

[0037] Figure 7 A schematic diagram of a logic control circuit provided in yet another embodiment of this application;

[0038] Figure 8 A schematic diagram of a logic control circuit provided for another embodiment of this application;

[0039] Figure 9 A schematic diagram of a logic control circuit provided in yet another embodiment of this application;

[0040] Figure 10 A schematic diagram of a logic control circuit provided in another embodiment of this application;

[0041] Figure 11 A schematic diagram of a logic control circuit provided in an embodiment of this application;

[0042] Figure 12 A schematic diagram of a pulse generation circuit provided in an embodiment of this application;

[0043] Figure 13 A schematic diagram of a pulse generation circuit provided for another embodiment of this application;

[0044] Figure 14 for Figure 13Timing diagrams corresponding to the embodiments;

[0045] Figure 15 A pulse generation circuit is provided as another embodiment of this application.

[0046] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0047] Figure label:

[0048] Q1, first MOSFET; Q2, second MOSFET; Q3, third MOSFET;

[0049] 10. Output circuit; Q4, fourth MOSFET; M1, first inverter;

[0050] M2, NAND gate; Q5, fifth MOSFET; M3, second inverter;

[0051] M4, inverter; Q6, sixth MOSFET; Q7, seventh MOSFET;

[0052] Q8, the eighth MOSFET; T1, the first time-delay inverting circuit; T2, the second time-delay inverting circuit;

[0053] T3, delay inverting circuit; T4, delay circuit; CLK, first clock signal;

[0054] CLKND, the second clock signal. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0057] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0058] In existing technologies, some pulse generation circuits may include D-type flip-flops. By inputting a clock signal into the D-type flip-flop, the flip-flop responds to the input clock signal and generates a corresponding pulse signal for output. However, since D-type flip-flops contain a large number of logic gate electronic components, there will be a certain time delay in generating the pulse signal in response to the clock signal. Increasing the size or area of ​​the logic gate electronic components in the D-type flip-flop can alleviate the time delay to some extent, but it also increases the power consumption of the circuit and is not convenient for integrated circuit design. Furthermore, under low-voltage operating conditions, the losses and time delays in the circuit will become more prominent.

[0059] To simplify circuit design and enable operation in low-voltage environments, this application proposes a logic control circuit, a flip-flop, and a pulse generation circuit.

[0060] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a logic control circuit provided in an embodiment of this application.

[0061] like Figure 1 As shown, the logic control circuit includes: a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, and an output circuit 10. The first terminal of the first MOSFET Q1 is connected to the power supply, and the second terminal of the first MOSFET Q1 is connected to the first terminal of the second MOSFET Q2; the second terminal of the second MOSFET Q2 is connected to the first terminal of the third MOSFET Q3, and the second terminal of the third MOSFET Q3 is grounded.

[0062] The second terminal of the first MOSFET Q1 is also used to connect to the first terminal of the output circuit 10. The second terminal of the output circuit 10 serves as the output terminal of the logic control circuit, and it is also used to connect to the control terminal of the first MOSFET Q1. It can be understood that the second terminal of the output circuit 10 outputs a pulse signal, thereby controlling the on / off state of the first MOSFET Q1 through the pulse signal output from the second terminal of the output circuit 10. For ease of explanation, the pulse signal received by the first MOSFET Q1 will be referred to as the CDN signal below. It can be understood that the CDN signal can be the same as the pulse signal output from the second terminal of the output circuit 10, or the pulse signal output from the second terminal of the output circuit 10 can be pre-processed to obtain the CDN signal.

[0063] The control terminal of the second MOSFET Q2 is used to receive the first clock signal CLK, and the control terminal of the third MOSFET Q3 is used to receive the second clock signal CLKND. Figure 2 As shown, Figure 2 This is a schematic diagram of a clock signal for a logic control circuit provided in an embodiment of this application. It can be understood that the second clock signal CLKND has the same waveform as the first clock signal CLK, but is delayed by a preset time compared to the first clock signal CLK.

[0064] The first clock signal CLK and the second clock signal CLKND exist in both in-phase and out-of-phase states. The in-phase state indicates that the levels of the first clock signal CLK and the second clock signal CLKND are the same, meaning both are either high or low. The out-of-phase state indicates that the levels of the first clock signal CLK and the second clock signal CLKND are opposite. Understandably, there are two in-phase states in each cycle, and the duration of each in-phase state is a preset duration.

[0065] For example, the first clock signal CLK and the second clock signal CLKND may be provided by a clock circuit connected to the logic control circuit. It is understood that in some embodiments, the logic control circuit may be connected to both the first clock circuit and the second clock circuit to receive the first clock signal CLK transmitted by the first clock circuit and the second clock signal CLKND transmitted by the second clock circuit; in other embodiments, the logic control circuit is connected to a clock circuit to receive clock signals transmitted by the same clock circuit.

[0066] In some embodiments, such as Figure 1 As shown, the first MOS transistor Q1 is a PMOS transistor, and the second MOS transistor Q2 and the third MOS transistor Q3 are both NMOS transistors. The pulse signal output from the second terminal of the output circuit 10 is the same as the voltage signal at the second terminal of the first MOS transistor Q1. For ease of description, a data node DYN is introduced. The data node DYN is located at the second terminal of the first MOS transistor Q1 and is used to indicate the level signal at the second terminal of the first MOS transistor Q1.

[0067] Understandably, in a logic control circuit, the initial state can be defined as the low level of the data node DYN. Understandably, at this moment, the pulse signal output from the second terminal of the output circuit 10 is a low-level pulse signal, which is transmitted to the control terminal of the first MOSFET Q1 to turn on the first MOSFET Q1. Thus, the power supply connected to the first terminal of the first MOSFET Q1 can apply voltage to the second terminal of the first MOSFET Q1 to set the data node DYN to a high level. Furthermore, when the level of the first clock signal CLK is different from the level of the second clock signal CLKND, the second MOSFET Q2 or the third MOSFET Q3 is turned off so that the data node DYN can remain in a high-level state.

[0068] At this time, the data node DYN of the logic control circuit is in a high-level state. When the pulse signal at the second terminal of the output circuit 10 is also a high-level signal and is transmitted to the control terminal of the first MOS transistor Q1, the first MOS transistor Q1 is turned off, and the data node DYN is still in a high-level state. However, when the level of the first clock signal CLK is the same as the level of the second clock signal CLKND, the second MOS transistor Q2 and the third MOS transistor Q3 are both turned on, and the data node DYN is set to a low level.

[0069] Specifically, when the second and third MOSFETs Q3 are NMOS transistors and the first clock signal CLK is low, the second clock signal CLKND is high. At this time, the second MOSFET Q2 is off, the third MOSFET Q3 is on, and the data node DYN remains high. When the rising edge of the first clock signal CLK arrives and sets it to high, since the second clock signal CLKND is delayed by a preset time compared to the first clock signal CLK, the first clock signal CLK and the second clock signal CLKND enter the same phase state. In this state, both the second MOSFET Q2 and the third MOSFET Q3 are on, and the data node DYN can be considered to be grounded through the second MOSFET Q2 and the third MOSFET Q3, so that the data node DYN is set to low. This causes the second terminal of the output circuit 10 to output a low-level pulse signal. After a preset time, the first clock signal CLK and the second clock signal CLKND enter the inverted state, the logic control circuit returns to the initial state, and repeats the step of transmitting the low-level pulse signal to the control terminal of the first MOSFET Q1. This will not be described further here.

[0070] Understandably, by controlling the on / off state of the second and third MOSFETs Q3 and the first MOSFET Q1 through a periodic clock signal, the level state of the data node DYN in the logic control circuit can be controlled, thereby outputting a corresponding pulse signal at the second terminal of the output circuit 10 to achieve the purpose of generating a pulse signal.

[0071] Please see Figure 3 , Figure 3 This is a schematic diagram of a logic control circuit provided for another embodiment of this application. In other embodiments, such as... Figure 3 As shown, the first MOSFET Q1 is an NMOS transistor, while the second MOSFET Q2 and the third MOSFET Q3 are both PMOS transistors.

[0072] For example, since the first MOSFET Q1 is an NMOS transistor, when the data node DYN is at a low level, if the second terminal of the output circuit 10 outputs a low-level pulse signal and transmits it to the control terminal of the first MOSFET Q1, the first MOSFET Q1 will not conduct, thus failing to set the data node DYN to a high level. Therefore, it is necessary to invert the level of the data node DYN or invert the pulse signal output from the second terminal of the output circuit 10 to ensure that the CDN signal received by the control terminal of the first MOSFET Q1 is inverted with the level signal of the data node DYN.

[0073] It can be assumed that in the output circuit 10, the signal of the data node DYN is inverted so that the pulse signal output from the second terminal of the output circuit 10 is inverted with the level signal of the data node DYN.

[0074] Similarly, when the data node DYN of the logic control circuit is at a low level, it is taken as the initial state. At this moment, the pulse signal output by the second terminal of the output circuit 10 is a high-level pulse signal, and the pulse signal is transmitted to the control terminal of the first MOSFET Q1 to turn on the first MOSFET Q1. Thus, the power supply connected to the first terminal of the first MOSFET Q1 can apply voltage to the second terminal of the first MOSFET Q1 through the first MOSFET Q1 to set the data node DYN to a high level. When the level of the first clock signal CLK is different from the level of the second clock signal CLKND, the second MOSFET Q2 or the third MOSFET Q3 is turned off so that the data node DYN can maintain a high-level state.

[0075] At this time, the data node DYN of the logic control circuit is in a high-level state. When the pulse signal of the output circuit 10 becomes a low-level signal and is transmitted to the control terminal of the first MOSFET Q1, the first MOSFET Q1 is turned off. The data node DYN is still in a high-level state. However, when the level of the first clock signal CLK is the same as the level of the second clock signal CLKND, the second MOSFET Q2 and the third MOSFET Q3 are both turned on, and the data node DYN is set to a low level.

[0076] Specifically, the second and third MOSFETs Q3 are PMOS transistors. When the first clock signal CLK is high and the second clock signal CLKND is low, the second MOSFET Q2 is off, the third MOSFET Q3 is on, and the data node DYN remains high. When the falling edge of the first clock signal CLK arrives and sets it low, the first clock signal CLK and the second clock signal CLKND enter a state of in-phase operation. In this state, both the second MOSFET Q2 and the third MOSFET Q3 are on, and the data node DYN can be considered to be grounded through the second MOSFET Q2 and the third MOSFET Q3, thus setting the data node DYN to low. After a preset time, the first clock signal CLK and the second clock signal CLKND enter a state of inversion. The logic control circuit returns to its initial state and repeats the step of transmitting the high-level pulse signal to the control terminal of the first MOSFET Q1, which will not be described further here.

[0077] Please combine Figure 1 See Figure 4 , Figure 4 This is a schematic diagram of a logic control circuit provided in an embodiment of this application.

[0078] In some implementations, such as Figure 4 As shown, the output circuit 10 includes a fourth MOSFET Q4. The control terminal of the fourth MOSFET Q4 serves as the control terminal of the output circuit 10 and is used to receive the enable signal EN. The first terminal of the fourth MOSFET Q4 is connected to the power supply, and the second terminal of the fourth MOSFET Q4 is connected to the second terminal of the first MOSFET Q1.

[0079] Understandably, the fourth MOSFET Q4 can be connected to the same power supply as the first MOSFET Q1.

[0080] The fourth MOSFET Q4 is used to control the pulse signal output from the second terminal of the output circuit 10 according to the enable signal. It can be understood that when the enable signal EN is used to indicate signal output, the output circuit 10 can generate a corresponding pulse signal based on the state of the data node DYN. When the enable signal is used to indicate no signal output, the fourth MOSFET Q4 controls the second terminal of the output circuit 10 to have no pulse signal output. At this time, the second and third MOSFETs Q3 can still receive the clock signal, but the second terminal of the output circuit 10 has no pulse signal output. For example, when the enable signal EN is high, an indicator signal is output; when the enable signal EN is low, it indicates no signal output.

[0081] Please combine Figure 1 See Figure 5 , Figure 5 This is a schematic diagram of a logic control circuit provided for another embodiment of this application.

[0082] In some implementations, such as Figure 5 As shown, when the first MOS transistor Q1 is a PMOS transistor, the second MOS transistor Q2 and the third MOS transistor Q3 are NMOS transistors, the output circuit 10 also includes a first inverter M1. The input terminal of the first inverter M1 is connected to the second terminal of the first MOS transistor Q1, and the output terminal of the first inverter M1 serves as the second terminal of the output circuit 10.

[0083] Understandably, by setting a first inverter M1 in the output circuit 10, the level signal of the data node DYN connected to the input terminal of the first inverter M1 can be inverted, so that the pulse signal output from the second terminal of the output circuit 10 is inverted with the level signal of the data node DYN.

[0084] When the first MOSFET Q1 is a PMOS transistor and the second and third MOSFETs Q3 are NMOS transistors, the control terminal of the first MOSFET Q1 needs to receive a low-level signal to turn on the first MOSFET Q1. If the data node DYN is low and the pulse signal output from the second terminal of the output circuit 10 is high, the first MOSFET Q1 will not turn on, the data node DYN will remain low, and the circuit will not operate. Therefore, it is necessary to invert the pulse signal output from the second terminal of the output circuit 10 to obtain the inverted signal of the pulse signal output from the second terminal of the output circuit 10, so as to perform two inversions on the signal of the data node DYN, thereby ensuring that the signal received by the control terminal of the first MOSFET Q1 is in phase with the signal of the data node DYN, so that when the data node DYN is low, the first MOSFET Q1 can turn on and set the data node DYN to a high level, and perform the steps described above. These will not be repeated here.

[0085] Understandably, a stable pulse signal can be obtained after two inversion processes to avoid logic errors in the first MOS transistor Q1 or data node DYN in the circuit.

[0086] Understandably, the inversion of the pulse signal output from the second terminal of the output circuit 10 can be performed in a circuit connected to the logic control circuit. An inverter or other device capable of inversion can be used to make the pulse signal received by the control terminal of the first MOS transistor Q1 inverted with the pulse signal output from the second terminal of the output circuit 10.

[0087] For example, Figure 5 The provided embodiments can be compared with Figure 4 The provided embodiments are combined.

[0088] Please combine Figure 3 See Figure 6 , Figure 6 This is a schematic diagram of a logic control circuit provided for another embodiment of this application.

[0089] In other implementations, such as Figure 6 As shown, when the first MOS transistor Q1 is an NMOS transistor and the second and third MOS transistors Q3 are PMOS transistors, the output circuit 10 also includes a first inverter M1. The input terminal of the first inverter M1 is connected to the second terminal of the first MOS transistor Q1, and the output terminal of the first inverter M1 serves as the second terminal of the output circuit 10.

[0090] Understandably, when the first MOSFET Q1 is an NMOS transistor and the second and third MOSFETs Q3 are PMOS transistors, the control terminal of the first MOSFET Q1 needs to receive a high-level signal to turn on the first MOSFET Q1. If the data node DYN is low and the first inverter M1 in the output circuit 10 performs inversion processing, a high-level pulse signal is output at the second terminal of the output circuit 10. The first MOSFET Q1 receives the high-level pulse signal and turns on, the data node DYN is set to high, and the aforementioned steps are repeated, which will not be described here.

[0091] For example, Figure 6 The provided embodiments can be compared with Figure 4 The provided embodiments are combined.

[0092] Please combine Figure 4 See Figure 7 , Figure 7 This is a schematic diagram of a logic control circuit provided in another embodiment of this application.

[0093] In some implementations, the first MOS transistor Q1 is an NMOS transistor, and the second, third, and fourth MOS transistors Q4 are PMOS transistors. The output circuit 10 also includes a NAND gate M2. The first signal input terminal of the NAND gate M2 is connected to the control terminal of the fourth MOS transistor Q4, the second signal input terminal of the NAND gate M2 is connected to the second terminal of the fourth MOS transistor Q4, and the output terminal of the NAND gate M2 serves as the second terminal of the output circuit 10.

[0094] Understandably, when the data node DYN or the enable signal EN is low, the second terminal of the output circuit 10 outputs a high-level pulse signal to turn on the first MOSFET Q1, setting the data node DYN to a high level. When both the data node DYN and the enable signal EN are high, the second terminal of the output circuit 10 outputs a low-level pulse signal to turn off the first MOSFET Q1, keeping the data node DYN in a high-level state.

[0095] When both the second MOSFET Q2 and the third MOSFET Q3 are turned on, the data node DYN is set to low level again. For detailed circuit operation steps, please refer to [link / reference needed]. Figure 3 The corresponding logic control circuit will not be described here.

[0096] In some other embodiments, the first MOS transistor Q1 is a PMOS transistor, the second, third and fourth MOS transistors Q4 are NMOS transistors, and the output circuit 10 further includes a NAND gate M2. The first signal input terminal of the NAND gate M2 is connected to the control terminal of the fourth MOS transistor Q4, the second signal input terminal of the NAND gate M2 is connected to the second terminal of the fourth MOS transistor Q4, and the output terminal of the NAND gate M2 serves as the second terminal of the output circuit 10.

[0097] For example, when the data node DYN or the enable signal is low, the second terminal of the output circuit 10 outputs a high-level pulse signal. The pulse signal output from the second terminal of the output circuit 10 needs to be inverted in order to turn on the first MOS transistor Q1 and set the data node DYN to a high level.

[0098] When both the data node DYN and the enable signal are high, the second terminal of the output circuit 10 outputs a low-level pulse signal, the first MOS transistor Q1 is turned off, and the data node DYN remains high.

[0099] When both the second MOSFET Q2 and the third MOSFET Q3 are turned on, the data node DYN is set to low. Please refer to [link / reference needed] for detailed circuit operation steps. Figure 1 The corresponding logic control circuit will not be described here.

[0100] Please combine Figure 5 See Figure 8 , Figure 8 This is a schematic diagram of a logic control circuit provided for another embodiment of this application.

[0101] In some embodiments, the logic control circuit further includes a fifth MOSFET Q5, the control terminal of the fifth MOSFET Q5 is connected to the output terminal of the first inverter M1, the first terminal of the fifth MOSFET Q5 is used to connect to the power supply, and the second terminal of the fifth MOSFET Q5 is connected to the input terminal of the first inverter M1.

[0102] For example, by connecting the fifth MOS transistor Q5, the signal in the logic control circuit can be kept stable. The specific operation steps of the logic control circuit are as provided in the previous embodiment, and will not be described again here.

[0103] Please combine Figure 1 See Figure 9 , Figure 9 This is a schematic diagram of a logic control circuit provided in another embodiment of this application.

[0104] In some embodiments, the logic control circuit further includes: a second inverter M3, a sixth MOSFET Q6, a seventh MOSFET Q7, and an eighth MOSFET Q8, wherein the sixth MOSFET Q6 is a PMOS transistor, and the seventh and eighth MOSFETs Q8 are NMOS transistors. The first terminal of the sixth MOSFET Q6 is connected to the power supply, and the second terminal of the sixth MOSFET Q6 is connected to the first terminal of the seventh MOSFET Q7; the second terminal of the seventh MOSFET Q7 is connected to the first terminal of the eighth MOSFET Q8, and the second terminal of the eighth MOSFET Q8 is grounded.

[0105] The control terminals of the sixth MOSFET Q6 and the seventh MOSFET Q7 are both connected to the output terminal of the second inverter M3. The input terminal of the second inverter M3 is connected to the first terminal of the output circuit 10, and the input terminal of the second inverter M3 is also connected to the second terminal of the sixth MOSFET Q6. The control terminal of the eighth MOSFET Q8 is connected to the control terminal of the first MOSFET Q1.

[0106] Understandably, when the data node DYN is low, it is inverted by the second inverter M3, and a high-level signal is output at the output of the second inverter M3 to control the sixth MOSFET Q6 to turn off and the seventh MOSFET Q7 to turn on. When the control terminal of the first MOSFET Q1 receives a high-level pulse signal, the eighth MOSFET Q8 turns on, and the second terminal of the sixth MOSFET Q6 can be regarded as grounded and set to low level.

[0107] When the control terminal of the first MOSFET Q1 receives a low-level pulse signal, the first MOSFET Q1 turns on, the eighth MOSFET Q8 turns off, and the data node DYN is set to a high level. The signal is then inverted by the second inverter M3, which outputs a low-level signal to turn on the sixth MOSFET Q6, turn off the seventh MOSFET Q7, and set the second terminal of the sixth MOSFET Q6 to a high level. This allows data to be latched into the second terminal of the sixth MOSFET Q6. When the data node DYN is set to a low level, the second terminal of the sixth MOSFET Q6 is also set to a low level, thus clearing the data.

[0108] Understandably, the second inverter M3 and the sixth, seventh, and eighth MOSFETs Q8 can latch the data and maintain signal stability.

[0109] Please see Figure 10 , Figure 10 This is a schematic diagram of a logic control circuit provided in another embodiment of this application.

[0110] like Figure 10As shown, the logic control circuit includes: a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, and an output circuit 10; the first terminal of the first MOSFET Q1 is connected to the power supply, and the second terminal of the first MOSFET Q1 is connected to the first terminal of the second MOSFET Q2; the second terminal of the second MOSFET Q2 is connected to the first terminal of the third MOSFET Q3, and the second terminal of the third MOSFET Q3 is grounded.

[0111] The second terminal of the second MOSFET Q2 is also connected to the first terminal of the output circuit 10. The second terminal of the output circuit 10 serves as the output terminal of the logic control circuit. The second terminal of the output circuit 10 is also connected to the control terminal of the third MOSFET Q3, so as to control the on / off state of the third MOSFET Q3 through the pulse signal of the second terminal of the output circuit 10.

[0112] The first MOSFET Q1 also includes a control terminal for receiving the first clock signal CLK, and the second MOSFET Q2 also includes a control terminal for receiving the second clock signal CLKND. The second clock signal CLKND has the same waveform as the first clock signal CLK, but is delayed by a preset time compared to the first clock signal CLK.

[0113] When the third MOSFET Q3 is turned off, and when the level of the first clock signal CLK is the same as the level of the second clock signal CLKND, both the first MOSFET Q1 and the second MOSFET Q2 are turned on to set the second terminal of the first MOSFET Q1 to a high level; when the level of the first clock signal CLK is different from the level of the second clock signal CLKND, either the first MOSFET Q1 or the second MOSFET Q2 is turned off; and when the third MOSFET Q3 is turned on, the second terminal of the first MOSFET Q1 is set to a low level.

[0114] For example, the second terminal of the second MOSFET Q2 serves as the data node DYN, and when the data node DYN is at a low level, the first MOSFET Q1 and the second MOSFET Q2 must be turned on simultaneously to set the data node DYN to a high level.

[0115] For example, the control terminal of the first MOSFET Q1 receives the first clock signal CLK, and the control terminal of the second MOSFET Q2 receives the second clock signal CLKND. The first clock signal CLK and the second clock signal CLKND exist in both in-phase and out-of-phase states. The in-phase state indicates that the level of the first clock signal CLK is the same as the level of the second clock signal CLKND, i.e., both the first clock signal CLK and the second clock signal CLKND are either high or low level signals. The out-of-phase state indicates that the level of the first clock signal CLK is opposite to the level of the second clock signal CLKND. It can be understood that there are two in-phase states in each cycle, and the duration of each in-phase state is a preset duration.

[0116] For example, when the third MOSFET Q3 is turned on, the data node DYN can be set to a low level.

[0117] In some implementations, the first and second MOSFETs Q2 are PMOS transistors, and the third MOSFET Q3 is an NMOS transistor. When the data node DYN is low, and the falling edge of the first clock signal CLK arrives and sets the first clock signal CLK to a low level, the first clock signal CLK and the second clock signal CLKND are in phase. The first MOSFET Q1 and the second MOSFET Q2 are both turned on, setting the data node DYN to a high level. After a preset time, the first clock signal CLK and the second clock signal CLKND are out of phase, the first MOSFET Q1 or the second MOSFET Q2 is turned off, and the data node DYN remains high.

[0118] When the control terminal of the third MOSFET Q3 receives a high-level pulse signal, it controls the third MOSFET Q3 to turn on, so as to set the data node DYN to a low level, and repeats the above steps after the next falling edge of the first clock signal CLK arrives.

[0119] Understandably, the data node DYN is connected to the first terminal of the output circuit 10, and the second terminal of the output circuit 10 is connected to the control terminal of the third MOS transistor Q3. The pulse signal at the output terminal of the output circuit 10 can control the on / off state of the third MOS transistor Q3. Therefore, in order to avoid the data node DYN level changing too quickly, the pulse signal at the output terminal of the output circuit 10 can be delayed so that the third MOS transistor Q3 receives the pulse signal at the output terminal of the output circuit 10 after a second preset time.

[0120] In other embodiments, the first and second MOSFETs Q2 are NMOS transistors, and the third MOSFET Q3 is a PMOS transistor. When the data node DYN is low and the rising edge of the first clock signal CLK arrives and sets the first clock signal CLK to a high level, the first clock signal CLK and the second clock signal CLKND are in phase. The first MOSFET Q1 and the second MOSFET Q2 are both turned on, setting the data node DYN to a high level. After a preset time, the first clock signal CLK and the second clock signal CLKND are out of phase, the first MOSFET Q1 or the second MOSFET Q2 is turned off, and the data node DYN remains high.

[0121] When the control terminal of the third MOSFET Q3 receives a low-level pulse signal, it controls the third MOSFET Q3 to turn on, so as to set the data node DYN to a low level, and repeats the above steps after the next rising edge of the first clock signal CLK arrives.

[0122] Understandably, in this situation, if the pulse signal output from the second terminal of output circuit 10 is in phase with the level signal of data node DYN, when data node DYN is at a high level, the third MOSFET Q3 receives the high-level pulse signal and is in a turned-off state, thus failing to set data node DYN to a low level. Therefore, it is necessary to invert the level signal of data node DYN to make it out of phase with the pulse signal received by the control terminal of the third MOSFET Q3. For example, the inversion can be performed in output circuit 10, or an electronic component for inversion, such as an inverter, can be connected between the control terminal of the third MOSFET Q3 and the second terminal of output circuit 10.

[0123] Please combine Figure 10 See Figure 11 , Figure 11 This is a schematic diagram of a logic control circuit provided in an embodiment of this application. The output circuit 10 includes an inverter M4, the input terminal of which is connected to the second terminal of the second MOS transistor Q2, and the output terminal of the inverter M4 serves as the second terminal of the output circuit 10.

[0124] Understandably, when the first and second MOSFETs Q2 are NMOS transistors and the third MOSFET Q3 is a PMOS transistor, the second terminal of the output circuit 10 is connected to the control terminal of the third MOSFET Q3. When the data node DYN is high, the output terminal of the output circuit 10 outputs a low-level pulse signal and transmits the low-level pulse signal to the control terminal of the third MOSFET Q3 to turn on the third MOSFET Q3, thereby setting the data node DYN to low. The remaining steps are as described in the previous embodiment and will not be repeated here.

[0125] When the first and second MOS transistors Q2 are PMOS transistors and the third MOS transistor Q3 is an NMOS transistor, if the data node DYN is high, the second terminal of the output circuit 10 outputs a low-level pulse signal. Therefore, the pulse signal needs to be inverted and the processed pulse signal is transmitted to the control terminal of the third MOS transistor Q3 to turn on the third MOS transistor Q3 and set the data node DYN to low. The remaining steps are as described in the previous embodiment and will not be repeated here.

[0126] This application also provides a trigger, wherein the trigger includes the logic control circuit provided in any of the foregoing embodiments.

[0127] Please combine Figure 1 See Figure 12 This application also provides a pulse generating circuit, which includes, for example, a pulse generating circuit. Figures 1-9 The logic control circuit provided in any of the corresponding embodiments.

[0128] Specifically, the second MOSFET Q2 and the third MOSFET Q3 can be connected to the same clock circuit, and a first time-delay inverter circuit T1 is connected between the output of the clock circuit and the control terminal of the third MOSFET Q3. The first time-delay inverter circuit T1 generates a second clock signal CLKND based on the first clock signal CLK, such that the second clock signal CLKND is delayed by a first preset time compared to the first clock signal CLK, and the first clock signal CLK and the second clock signal CLKND have periods of in-phase and periods of out-of-phase. The second clock signal CLKND is transmitted to the control terminal of the third MOSFET Q3 through the first time-delay inverter circuit T1 to control the on / off state of the third MOSFET Q3.

[0129] For example, the first time-delay inverting circuit T1 may include multiple buffers and an inverter to delay and invert the first clock signal CLK to generate a second clock signal CLKND.

[0130] Please combine Figure 12 See Figure 13 , Figure 13 This is a schematic diagram of a pulse generation circuit according to another embodiment of this application. In this pulse generation circuit, the first MOS transistor Q1 is a PMOS transistor, and the second and third MOS transistors Q3 are NMOS transistors. The pulse generation circuit also includes a second time-delay inverting circuit T2. The input terminal of the second time-delay inverting circuit T2 is connected to the output terminal of the logic control circuit. The inverted output terminal output1 of the second time-delay inverting circuit T2 is connected to the control terminal of the first MOS transistor Q1. The non-inverted output terminal output2 of the second time-delay inverting circuit T2 serves as the output terminal of the pulse generation circuit.

[0131] Understandably, the signal output from the inverting output terminal (output1) of the second time-delay inverting circuit T2 is inverted compared to the signal received from the input terminal of the second time-delay inverting circuit T2. By delaying and inverting the pulse signal output from the first inverter M1 of the logic control circuit, the pulse signal received by the control terminal of the first MOS transistor Q1 from the second terminal of the output circuit 10 is delayed. This ensures that the level signal of the data node DYN is in phase with the pulse signal received by the control terminal of the first MOS transistor Q1.

[0132] In other embodiments, the first MOS transistor Q1 is an NMOS transistor, and the second and third MOS transistors Q3 are PMOS transistors. Since the level signal of the data node DYN is out of phase with the pulse signal received by the control terminal of the first MOS transistor Q1, it is not necessary to perform inversion processing in the pulse generation circuit. Only time delay processing is required. The time delay circuit is connected between the output terminal of the logic control circuit and the control terminal of the first MOS transistor Q1 to perform time delay processing on the pulse signal output by the second terminal of the output circuit 10.

[0133] Please see Figure 14 , Figure 14 for Figure 13 The timing diagram corresponding to the embodiment is shown in the figure. The first clock signal CLK and the second clock signal CLKND can control the on and off of the second MOSFET Q2 and the third MOSFET Q3. The pulse signal at the second terminal of the output circuit 10 can control the on and off of the first MOSFET Q1, so that the pulse generation circuit generates a periodically changing pulse signal.

[0134] Please combine Figure 10 See Figure 15 , Figure 15 A pulse generation circuit is provided in another embodiment of this application. The pulse generation circuit includes, as follows: Figures 10-11 The logic control circuit provided in any of the corresponding embodiments.

[0135] When the first and second MOSFETs Q2 are NMOS transistors and the third MOSFET Q3 is a PMOS transistor (not shown in the figure), the pulse generation circuit includes a first delay inverting circuit and a second delay inverting circuit. One end of the first delay inverting circuit is used to receive the first clock signal CLK, and the other end is connected to the control terminal of the second MOSFET Q2. The second delay inverting circuit is connected between the second terminal of the second MOSFET Q2 and the control terminal of the third MOSFET Q3. The second delay inverting circuit is used to invert and delay the pulse signal at the second terminal of the output circuit 10 so that the pulse signal received by the control terminal of the third MOSFET Q3 is delayed by a preset time compared with the pulse signal at the second terminal of the second MOSFET Q2. The specific circuit operation steps are as described in the previous embodiment and will not be repeated here.

[0136] In other implementations, such as Figure 15 As shown, when the first and second MOS transistors Q2 are PMOS transistors and the third MOS transistor Q3 is an NMOS transistor, the pulse generation circuit includes a time-delay inverting circuit T3 and a time-delay circuit T4. One end of the time-delay inverting circuit T3 is used to receive the first clock signal CLK, and the other end is connected to the control terminal of the second MOS transistor Q2. The time-delay circuit T4 is connected between the second terminal of the second MOS transistor Q2 and the control terminal of the third MOS transistor Q3. The time-delay circuit T4 is used to delay the pulse signal output from the second terminal of the output circuit 10 so that the pulse signal received by the control terminal of the third MOS transistor Q3 is delayed by a preset time compared with the pulse signal from the second terminal of the second MOS transistor Q2. The specific circuit operation steps are as described in the previous embodiment and will not be repeated here.

[0137] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0138] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, herein, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0139] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above descriptions are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A logic control circuit, characterized in that, include: A first MOSFET, a second MOSFET, a third MOSFET, and an output circuit; the first terminal of the first MOSFET is connected to a power supply, and the second terminal of the first MOSFET is connected to the first terminal of the second MOSFET; the second terminal of the second MOSFET is connected to the first terminal of the third MOSFET, and the second terminal of the third MOSFET is grounded; The second terminal of the first MOS transistor is also used to connect to the first terminal of the output circuit. The second terminal of the output circuit serves as the output terminal of the logic control circuit, and the second terminal of the output circuit is also used to connect to the control terminal of the first MOS transistor, so as to control the on / off state of the first MOS transistor through the pulse signal of the second terminal of the output circuit. The control terminal of the second MOS transistor is used to receive the first clock signal, and the control terminal of the third MOS transistor is used to receive the second clock signal. The second clock signal has the same waveform as the first clock signal, but is delayed by a preset time. When the first MOSFET is turned on, the second terminal of the first MOSFET is at a high level; and when the level of the first clock signal is different from the level of the second clock signal, the second MOSFET or the third MOSFET is turned off so that the second terminal of the first MOSFET remains at a high level. When the first MOSFET is turned off, and when the level of the first clock signal is the same as the level of the second clock signal, both the second MOSFET and the third MOSFET are turned on to set the second terminal of the first MOSFET to a low level. The output circuit includes a fourth MOSFET; the first terminal of the fourth MOSFET is connected to the power supply, and the second terminal of the fourth MOSFET is connected to the second terminal of the first MOSFET; the control terminal of the fourth MOSFET serves as the control terminal of the output circuit and is used to receive an enable signal. When the enable signal indicates signal output, the output circuit can generate a corresponding pulse signal based on the state of the data node; when the enable signal indicates no signal output, the second MOSFET and the third MOSFET can still receive the corresponding clock signal, but the second terminal of the output circuit has no pulse signal output. The data node is located at the second end of the first MOS transistor and is used to indicate the level signal at the second end of the first MOS transistor.

2. The logic control circuit as described in claim 1, characterized in that, The first MOS transistor is an NMOS transistor, and the second and third MOS transistors are PMOS transistors. The output circuit further includes a first inverter, the input terminal of which is connected to the second terminal of the first MOS transistor, and the output terminal of which serves as the second terminal of the output circuit.

3. The logic control circuit as described in claim 1, characterized in that, The first MOS transistor is an NMOS transistor, and the second, third, and fourth MOS transistors are PMOS transistors. The output circuit further includes a NAND gate, the first signal input terminal of which is connected to the control terminal of the fourth MOS transistor, the second signal input terminal of which is connected to the second terminal of the fourth MOS transistor, and the output terminal of which serves as the second terminal of the output circuit.

4. The logic control circuit as described in claim 2, characterized in that, The logic control circuit further includes a fifth MOS transistor, the control terminal of which is connected to the output terminal of the first inverter, the first terminal of which is connected to the power supply, and the second terminal of which is connected to the input terminal of the first inverter.

5. The logic control circuit as described in claim 1, characterized in that, The first MOS transistor is a PMOS transistor, and the second and third MOS transistors are NMOS transistors; the output circuit further includes: a first inverter, the input terminal of the first inverter is connected to the second terminal of the first MOS transistor, and the output terminal of the first inverter serves as the second terminal of the output circuit. The second terminal of the output circuit is also used to connect to the control terminal of the first MOS transistor, so as to control the on / off state of the first MOS transistor through the pulse signal of the second terminal of the output circuit, including: the control terminal of the first MOS transistor receives the inverted signal of the pulse signal of the second terminal of the output circuit, so as to control the on / off state of the first MOS transistor through the inverted signal of the pulse signal of the second terminal of the output circuit.

6. The logic control circuit as described in claim 5, characterized in that, The logic control circuit further includes: a second inverter, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor, wherein the sixth MOS transistor is a PMOS transistor, and the seventh and eighth MOS transistors are NMOS transistors; the first terminal of the sixth MOS transistor is connected to the power supply, the second terminal of the sixth MOS transistor is connected to the first terminal of the seventh MOS transistor; the second terminal of the seventh MOS transistor is connected to the first terminal of the eighth MOS transistor, and the second terminal of the eighth MOS transistor is grounded; The control terminals of the sixth MOS transistor and the seventh MOS transistor are both connected to the output terminal of the second inverter. The input terminal of the second inverter is connected to the first terminal of the output circuit, and the input terminal of the second inverter is also connected to the second terminal of the sixth MOS transistor. The control terminal of the eighth MOS transistor is connected to the control terminal of the first MOS transistor.

7. A logic control circuit, characterized in that, include: A first MOSFET, a second MOSFET, a third MOSFET, and an output circuit; the first terminal of the first MOSFET is connected to a power supply, and the second terminal of the first MOSFET is connected to the first terminal of the second MOSFET; the second terminal of the second MOSFET is connected to the first terminal of the third MOSFET, and the second terminal of the third MOSFET is grounded; The second terminal of the second MOS transistor is also connected to the first terminal of the output circuit. The second terminal of the output circuit serves as the output terminal of the logic control circuit. The second terminal of the output circuit is also connected to the control terminal of the third MOS transistor so as to control the on / off state of the third MOS transistor through the pulse signal of the second terminal of the output circuit. The first MOSFET further includes a control terminal for receiving a first clock signal, and the second MOSFET further includes a control terminal for receiving a second clock signal. The second clock signal has the same waveform as the first clock signal, but is delayed by a preset time compared to the first clock signal. When the third MOS transistor is turned off, and when the level of the first clock signal is the same as the level of the second clock signal, both the first MOS transistor and the second MOS transistor are turned on to set the second terminal of the first MOS transistor to a high level. When the level of the first clock signal is different from the level of the second clock signal, the first MOSFET or the second MOSFET is turned off; and when the third MOSFET is turned on, the second terminal of the first MOSFET is set to a low level.

8. The logic control circuit as described in claim 7, characterized in that, The first and second MOS transistors are NMOS transistors, and the third MOS transistor is a PMOS transistor; the output circuit includes an inverter, the input terminal of which is connected to the second terminal of the second MOS transistor, and the output terminal of which serves as the second terminal of the output circuit.

9. The logic control circuit as described in claim 7, characterized in that, The first and second MOS transistors are PMOS transistors, and the third MOS transistor is an NMOS transistor; the output circuit includes an inverter, the input terminal of which is connected to the second terminal of the second MOS transistor, and the output terminal of which serves as the second terminal of the output circuit. The second terminal of the output circuit is also connected to the control terminal of the third MOS transistor, so as to control the on / off state of the third MOS transistor through the pulse signal output from the second terminal of the output circuit, including: the control terminal of the third MOS transistor is used to receive the inverted signal of the pulse signal from the second terminal of the output circuit, so as to control the on / off state of the third MOS transistor through the inverted signal of the pulse signal from the second terminal of the output circuit.

10. A trigger, characterized in that, include: The logic control circuit as described in any one of claims 1-6; or The logic control circuit as described in any one of claims 7-9.

11. A pulse generation circuit, characterized in that, The pulse generation circuit includes: The logic control circuit as described in any one of claims 1-4 or the logic control circuit as described in any one of claims 1, 5-6; A first time-delay inverting circuit is provided, with one end receiving the first clock signal and the other end connected to the control terminal of the third MOS transistor to input the generated second clock signal into the control terminal of the third MOS transistor, so that the second clock signal is delayed by a first preset time compared to the first clock signal.

12. The pulse generation circuit as described in claim 11, characterized in that, When the pulse generating circuit includes the logic control circuit as described in any one of claims 1-4, the pulse generating circuit further includes: a delay circuit, the delay circuit being connected between the output terminal of the logic control circuit and the control terminal of the first MOS transistor, the output terminal of the delay circuit also serving as the output terminal of the pulse generating circuit; the delay circuit is used to perform delay processing on the pulse signal at the second terminal of the output circuit, so that the pulse signal received by the control terminal of the first MOS transistor is delayed by a second preset time compared to the pulse signal at the second terminal of the output circuit.

13. The pulse generation circuit as described in claim 11, characterized in that, When the pulse generation circuit includes the logic control circuit as described in any one of claims 1, 5-6, the pulse generation circuit further includes: a second time-delay inverting circuit, wherein the input terminal of the second time-delay inverting circuit is connected to the output terminal of the logic control circuit, and the inverted output terminal of the second time-delay inverting circuit is connected to the control terminal of the first MOS transistor; the non-inverting output terminal of the second time-delay inverting circuit serves as the output terminal of the pulse generation circuit; the second time-delay inverting circuit is used to perform time-delay processing and inversion processing on the pulse signal output from the second terminal of the output circuit, so that the pulse signal received by the control terminal of the first MOS transistor is delayed by a second preset time compared with the pulse signal at the second terminal of the output circuit.

14. A pulse generation circuit, characterized in that, The pulse generation circuit includes: The logic control circuit as described in claim 7 or 8; A first time delay inverter circuit, one end of which is used to receive the first clock signal, and the other end is connected to the control terminal of the second MOS transistor; The second delay inverting circuit is connected between the second terminal of the output circuit and the control terminal of the third MOS transistor. The second delay inverting circuit is used to invert and delay the pulse signal at the second terminal of the output circuit so that the pulse signal received by the control terminal of the third MOS transistor is delayed by a preset time compared with the pulse signal at the second terminal of the second MOS transistor.

15. A pulse generation circuit, characterized in that, The pulse generation circuit includes: The logic control circuit as described in claim 7 or 9; A time delay inverting circuit, one end of which is used to receive the first clock signal, and the other end is connected to the control terminal of the second MOS transistor; A delay circuit is provided, which is connected between the second terminal of the output circuit and the control terminal of the third MOS transistor. The delay circuit is used to delay the pulse signal output from the second terminal of the output circuit so that the pulse signal received by the control terminal of the third MOS transistor is delayed by a preset time compared with the pulse signal from the second terminal of the second MOS transistor.

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