Clock detection circuit, control system and electronic device

Abstract

Embodiments of the present application provide a clock detection circuit, a control system and an electronic device, wherein the clock detection circuit is used for receiving and detecting a clock signal, and comprises a frequency division module, a first detection module and a counting module; the frequency division module is used for frequency dividing the clock signal to generate a logic signal, and sending the logic signal to the first detection module; the first detection module is used for determining whether to send a reset signal to the counting module according to a change of the logic signal and a change of the clock signal after being enabled, the reset signal being used for controlling the counting module to reset and re-count the clock; the counting module is used for counting the clock signal, and judging whether the clock signal is continuous according to whether a counting quantity reaches a preset threshold; wherein the clock signal and / or the logic signal is an enable signal for enabling the first detection module. The clock detection circuit provided by the present application can reduce power consumption generated by clock detection.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to a clock detection circuit, processor, and electronic device. Background Technology

[0002] With the development of technology, people have higher requirements for the battery life of electronic devices such as mobile phones and tablets, thus needing to minimize the power consumption of these devices. However, even when the audio function is not in use, the audio system of mobile phones and tablets still generates a significant amount of power consumption. To address this issue, a clock signal input is generated when the audio system plays music. By detecting changes in this clock signal, the system can determine whether the audio function is being used and shut down promptly when the audio function is not in use. However, existing clock detection circuits also generate considerable power consumption during clock signal detection, resulting in additional power loss. Summary of the Invention

[0003] In view of this, embodiments of this application provide a clock detection circuit, a control system, and an electronic device, wherein the clock detection circuit reduces the power consumption of clock detection.

[0004] According to a first aspect of the present application, a clock detection circuit is provided for receiving and detecting a clock signal, comprising: a frequency division module, a first detection module, and a counting module; the frequency division module is used to divide the clock signal to generate a logic signal and send the logic signal to the first detection module; the first detection module is used, after being enabled, to determine whether to send a reset signal to the counting module based on changes in the logic signal and changes in the clock signal, the reset signal being used to control the counting module to reset and restart clock counting; the counting module is used to count the clock signal and determine whether the clock signal is continuous based on whether the count reaches a preset threshold; wherein, the clock signal and / or the logic signal is an enable signal that enables the first detection module.

[0005] In one possible implementation, the first detection module includes a first timing detection module and a second timing detection module. The first timing detection module, upon being enabled by a first enable signal, enters a first delay period for timing. If, within the first delay period, the logic signal remains unchanged, the module controls the counting module to reset and restart clock counting. The second timing detection module, upon being enabled by a second enable signal, enters a second delay period for timing. If, within the second delay period, the clock signal remains unchanged, the module controls the counting module to reset and restart clock counting. The first enable signal is a signal where the logic signal is at a high level; the second enable signal is a signal where both the logic signal and the clock signal are at a low level.

[0006] In one possible implementation, the first timing detection module is further configured to generate a first timing signal, and after being enabled by a first enable signal, adjust the changes in the first timing signal based on the first enable signal, and enter the timing of a first delay period according to the changes in the first timing signal; the second timing detection module is further configured to generate a second timing signal, and after being enabled by a second enable signal, adjust the changes in the second timing signal based on the second enable signal, and enter the timing of a second delay period according to the changes in the second timing signal.

[0007] In one possible implementation, the clock detection circuit further includes a receiving module and a second detection module. The counting module is further configured to output an indication signal indicating whether the clock signal is continuous or discontinuous after determining whether the clock signal is continuous. The receiving module receives the clock signal and the indication signal, generates a first clock synchronization signal and a second clock synchronization signal based on the clock signal and the indication signal, and sends the first clock synchronization signal to the frequency division module, the first detection module, and the counting module respectively, and sends the second clock synchronization signal to the second detection module. Wherein, when the indication signal indicates that the clock is discontinuous, the first clock synchronization signal is the clock signal; when the indication signal indicates that the clock signal is continuous, the second clock synchronization signal is the clock signal. The second detection module, after being enabled by a third enable signal, determines whether to send an interrupt signal CLK_OFF to the counting module based on the change in the second clock synchronization signal. The interrupt signal CLK_OFF controls the counting module to adjust the indication signal indicating that the clock signal is continuous to the indication signal indicating that the clock signal is discontinuous. Wherein, the third enable signal is the indication signal indicating that the clock signal is continuous.

[0008] In one possible implementation, the second detection module includes a third timing detection module; the third timing detection module is used to enter a third delay period for timing after being enabled by the third enable signal, and if the second clock synchronization signal is detected to remain unchanged during the third delay period, the interrupt signal CLK_OFF is sent to the counting module.

[0009] In one possible implementation, the third timing detection module is specifically used to generate a third timing signal, adjust the changes in the third timing signal based on the third enable signal, and enter the timing of the third delay period according to the changes in the third timing signal.

[0010] In one possible implementation, the receiving module includes a first sub-receiving module and a second sub-receiving module; the first sub-receiving module includes a first signal input terminal and a second signal input terminal, the first signal input terminal being used to receive the clock signal, and the second signal input terminal being used to receive the indication signal; the first sub-receiving module is used to send a first clock synchronization signal to the frequency division module, the first detection module, and the counting module when the indication signal indicates that the clock signal is discontinuous; the second sub-receiving module includes a third signal input terminal and a fourth signal input terminal, the third signal input terminal being used to receive the clock signal, and the fourth signal input terminal being used to receive the indication signal; the second sub-receiving module is used to send a second clock synchronization signal to the second detection module when the indication signal indicates that the clock signal is continuous.

[0011] In one possible implementation, the first sub-receiving module includes a NOT gate and a NOR gate, wherein the input terminal of the NOT gate serves as the first signal input terminal, and the first sub-input terminal of the NOR gate serves as the second signal input terminal; the output terminal of the NOT gate is connected to the second sub-input terminal of the NOR gate; the output terminal of the NOR gate serves as the output terminal of the first sub-receiving module and is connected to the input terminal of the first detection module and the input terminal of the counting module; the second sub-receiving module includes an AND gate, wherein the AND gate includes a third sub-input terminal and a fourth sub-input terminal; the third sub-input terminal serves as the third signal input terminal, and the fourth sub-input terminal serves as the fourth signal input terminal; the output terminal of the AND gate serves as the output terminal of the second sub-receiving module and is connected to the input terminal of the second detection module.

[0012] According to a second aspect of the embodiments of this application, a control system is provided, including the clock detection circuit described in any of the above embodiments; the clock detection circuit is used to detect a clock signal generated during the operation of the controlled system, and send an indication signal to the controlled system indicating that the clock signal is continuous and / or discontinuous, thereby turning on the controlled system by the indication signal indicating that the clock signal is continuous, and / or turning off the controlled system by the indication signal indicating that the clock signal is discontinuous; wherein, the controlled system includes an audio system and / or a video system.

[0013] According to a third aspect of the present application, an electronic device is provided, including a control system as described in the second aspect of the present application.

[0014] In the clock detection circuit provided in this application embodiment, the frequency divider module can divide the clock signal to generate a logic signal. The first detection module, after being enabled, determines whether to send a reset signal to the counting module based on changes in both the logic signal and the clock signal. This allows the first detection module to remain in a closed state when no clock signal is received, thereby reducing the power consumption of the clock detection circuit. The counting module can be reset and restart clock counting based on the reset signal. Therefore, the clock counting by the counting module integrates changes in both the logic signal and the clock signal, effectively improving the accuracy of clock signal detection. In summary, this application embodiment can reduce the power consumption of the clock detection circuit while ensuring clock detection accuracy, thereby increasing the battery life of electronic devices using this clock detection circuit. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0016] Figure 1 This is a structural block diagram of a clock detection circuit provided in an embodiment of this application;

[0017] Figure 2 This is a signal timing diagram provided in an embodiment of this application;

[0018] Figure 3 This is another signal timing diagram provided in an embodiment of this application;

[0019] Figure 4 This is yet another signal timing diagram provided in the embodiments of this application;

[0020] Figure 5This is a structural block diagram of another clock detection circuit provided in an embodiment of this application;

[0021] Figure 6 This is yet another signal timing diagram provided in the embodiments of this application;

[0022] Figure 7 This is a structural block diagram of another clock detection circuit provided in the embodiments of this application;

[0023] Figure 8 This is a schematic diagram of the circuit structure of another clock detection circuit provided in the embodiments of this application;

[0024] Figure 9 This is a structural block diagram of a control system provided in an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0026] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0027] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0028] As mentioned earlier, existing audio systems in mobile phones, tablets, and other electronic devices generate significant power consumption even when the audio function is not in use. To address this, a clock signal input during music playback could be used to detect changes in the clock signal and determine if the audio function is being used, allowing the audio system to be shut down promptly when not in use. However, existing clock detection circuits also consume considerable power during clock signal detection, resulting in additional power loss.

[0029] The first aspect of this application provides a clock detection circuit applicable to audio system control, such as the control system provided in the second aspect of this application, to solve the above-mentioned problems.

[0030] In the clock detection circuit provided in this application embodiment, the frequency divider module can divide the clock signal to generate a logic signal. The first detection module, after being enabled, determines whether to send a reset signal to the counting module based on changes in both the logic signal and the clock signal. This allows the first detection module to remain in a closed state when no clock signal is received, thereby reducing the power consumption of the clock detection circuit. The counting module can be reset and restart clock counting based on the reset signal. Therefore, the clock counting by the counting module integrates changes in both the logic signal and the clock signal, effectively improving the accuracy of clock signal detection. In summary, this application embodiment can reduce the power consumption of the clock detection circuit while ensuring clock detection accuracy, thereby increasing the battery life of electronic devices using this clock detection circuit.

[0031] The following is a reference to the appendix. Figure 1-8 The clock detection circuit provided in the embodiments of this application will be described in detail.

[0032] like Figure 1 As shown, this application embodiment provides a clock detection circuit 100 for receiving and detecting clock signals, including: a frequency division module 110, a first detection module 120, and a counting module 130.

[0033] Frequency divider module 110 is used to divide the clock signal to generate a logic signal and send the logic signal to the first detection module 120. Preferably, the frequency of the logic signal is half that of the clock signal, so that one cycle of the clock signal can be detected during the high-level or low-level phase of the logic signal, thereby achieving higher detection accuracy. Frequency divider module 110 may include a D flip-flop or other suitable frequency divider for dividing the clock signal. The specific structure of frequency divider module 110 can be found in related technologies, and will not be elaborated here, all of which are within the protection scope of the embodiments of this application.

[0034] The first detection module 120, after being enabled, determines whether to send a reset signal to the counting module 130 based on changes in the logic signal and the clock signal. It can detect clock changes by combining both logic and clock signal data, improving the accuracy of clock detection. The reset signal controls the counting module 130 to reset and restart clock counting. It should be noted that the first detection module 120 includes a detection circuit for detecting clock changes, which only begins detecting clock signal changes after being enabled by a clock signal or logic signal. Therefore, the first detection module 120 can be in a closed state when not enabled, thus saving power.

[0035] Optionally, the clock signal and / or logic signal is an enable signal for enabling the first detection module 120. In this embodiment, the enable signal for the first detection module 120 is preferably a positive level clock signal, so that when the clock signal appears, the first detection module 120 can quickly respond to changes in the clock signal and thus detect the clock signal in a timely manner.

[0036] The counting module 130 is used to count the clock signal and determine whether the clock signal is continuous based on whether the count reaches a preset threshold. The counting module 130 can use a counter or other suitable electronic components for counting. The preset threshold can be set to values ​​such as 128, 256, 512, or other suitable values, all of which are within the protection scope of the embodiments of this application.

[0037] In the clock detection circuit 100 provided in this application embodiment, the frequency divider module 110 can divide the clock signal to generate a logic signal. The first detection module 120, after being enabled, determines whether to send a reset signal to the counting module 130 based on changes in the logic signal and the clock signal. This allows the first detection module 120 to remain in a closed state when no clock signal is received, thereby reducing the power consumption of the clock detection circuit 100. The counting module 130 can be reset according to the reset signal and restart clock counting. Therefore, the clock counting by the counting module 130 integrates changes in both the logic signal and the clock signal, effectively improving the accuracy of clock signal detection. In summary, this application embodiment can reduce the power consumption of the clock detection circuit while ensuring clock detection accuracy, thereby increasing the battery life of electronic devices using this clock detection circuit 100.

[0038] In some optional embodiments, the first detection module 120 includes a first timing detection module and a second timing detection module.

[0039] The first timing detection module is used to enter the first delay period for timing after being enabled by the first enable signal. If no change in the logic signal is detected within the first delay period, the module can send a reset signal to the counting module 130 to control the counting module 130 to reset and restart the clock counting. The first enable signal is a logic signal with a high level.

[0040] The second timing detection module, after being enabled by the second enable signal, enters the second delay period for timing. If no change in the clock signal is detected within the second delay period, a reset signal can be sent to the counting module 130 to control the counting module 130 to reset and restart clock counting. The second enable signal is a signal where both the logic signal and the clock signal are low. That is, the second delay period and the first delay period begin at different stages of a logic signal cycle, complementing each other. This allows the second and first timing detection modules to perform clock detection at different stages of a logic signal cycle, thus avoiding missing changes in the clock signal. Furthermore, by setting the first and second delay periods, continuous clock detection by the first and second timing detection modules can be avoided, thereby reducing the power consumption of the first detection module 120.

[0041] In this embodiment, the first delay period should be set to be greater than half the period of the logic signal to avoid the first timing detection module missing changes in the logic signal. Furthermore, the first delay period can be set to be less than or equal to the period of the logic signal, for example, the frequency of the logic signal being half the clock signal frequency, to avoid excessive repeated detection of the clock signal and reduce the power consumption of the first detection module 120. Alternatively, the first delay period can be greater than the period of the logic signal to detect at least one complete cycle of the logic signal within the first delay period. Similarly, the second delay period should be greater than half the period of the clock signal to avoid the second timing detection module missing changes in the clock signal. Furthermore, the second delay period can be set to be less than or equal to the period of the clock signal to avoid excessive repeated detection of the clock signal and reduce the power consumption of the first detection module 120. It should be understood that the second delay period can also be greater than the period of the clock signal to detect at least one complete cycle of the clock signal within the second delay period.

[0042] In some optional embodiments, the first timing detection module is further configured to generate a first timing signal, and after being enabled by a first enable signal, adjust the changes in the first timing signal based on the first enable signal, and enter the timing of the first delay period according to the changes in the first timing signal.

[0043] For example, such as Figure 2 and Figure 3 As shown, when the logic signal CLK_PULSE is high (forming the first enable signal), the first timing detection module is enabled. Simultaneously, the first timing detection module sets the first timing signal EN_DLY1 to high and begins timing for the first delay period DT1. If, within the first delay period DT1, the logic signal CLK_PULSE changes from high to low, the first timing signal EN_DLY1 is set low, and timing for the first delay period DT1 ends. If, within the complete first delay period DT1, the logic signal CLK_PULSE does not change from high to low, a reset signal CLK_RESET is sent to the counting module 130 simultaneously with the completion of the first delay period DT1 (when the first timing signal EN_DLY1 changes to low), controlling the counting module 130 to reset and restart clock counting. See details... Figure 3 The first delay period DT1 corresponds to time T1. It should be understood that sending the reset signal CLK_RESET to the counting module 130 corresponds to... Figure 3 During the phase when the reset signal CLK_RESET changes from low to high, Figure 2 The reset signal CLK_RESET remains low throughout the process. Figure 2 During the corresponding period, no reset signal CLK_RESET was sent to the counting module 130. As a possible implementation, when the clock signal CLK is determined to be discontinuous, the logic signal CLK_PULSE can also be set to low level at the same time, so as to prevent the first detection module 120 from being enabled when the logic signal CLK_PULSE is used as the enable signal of the first detection module 120.

[0044] The second timing detection module is also used to generate a second timing signal EN_DLY2, and after being enabled by a second enable signal, it adjusts the changes in the second timing signal EN_DLY2 based on the second enable signal, and enters the timing of the second delay period DT2 according to the changes in the second timing signal EN_DLY2.

[0045] For example, such as Figure 2 and Figure 4As shown, when both the logic signal CLK_PULSE and the clock signal CLK are low (forming the second enable signal), the second timing detection module is enabled. Simultaneously, the second timing detection module sets the second timing signal EN_DLY2 to high and begins timing for the second delay period DT2. If, within the complete second delay period DT2, the clock signal CLK changes from low to high, the second timing signal EN_DLY2 is set low, and timing for the second delay period DT2 ends. If, within the second delay period DT2, the clock signal CLK does not change from low to high, a reset signal CLK_RESET is sent to the counting module 130 simultaneously with the completion of the second delay period DT2 (when the second timing signal EN_DLY2 becomes low), controlling the counting module 130 to reset and restart clock counting. See details... Figure 4 The second delay period DT2 corresponds to time T2.

[0046] It should be understood that the first timing detection module and the second timing detection module respectively include corresponding circuits for generating and adjusting the first timing signal EN_DLY1 and the second timing signal EN_DLY2. The specific structure of the corresponding circuits can be referred to in related technologies, and will not be repeated here. All of them are within the protection scope of the embodiments of this application.

[0047] In this embodiment, the first timing signal EN_DLY1 is adjusted according to the first enable signal, and the first delay period DT1 is timed by the change of the first timing signal EN_DLY1. The second timing signal EN_DLY2 is adjusted according to the second enable signal, and the second delay period DT2 is timed by the change of the second timing signal EN_DLY2. This can easily distinguish the first delay period DT1 and the second delay period DT2, so that the first timing detection module and the second timing detection module do not interfere with each other, thereby ensuring the accuracy of the final detection result as much as possible.

[0048] like Figure 5As shown, in some optional embodiments, the clock detection circuit 100 further includes a receiving module 140 and a second detection module 150. The counting module 130 is also used to output an indication signal CLK_IND indicating whether the clock signal CLK is continuous or discontinuous after determining whether the clock signal CLK is continuous. In this embodiment, the indication signal CLK_IND can be set to use a high level to indicate that the clock signal CLK is continuous and a low level to indicate that the clock signal CLK is discontinuous. Thus, the state of the clock signal CLK indicated by the indication signal CLK_IND can be adjusted simply by adjusting the level of the indication signal CLK_IND. The following description assumes that the high level of the indication signal CLK_IND indicates that the clock signal CLK is continuous and the low level of the indication signal CLK_IND indicates that the clock signal CLK is discontinuous.

[0049] The receiving module 140 receives the clock signal CLK and the indication signal CLK_IND. Based on the clock signal CLK and the indication signal CLK_IND, it generates a first clock synchronization signal and a second clock synchronization signal. The first clock synchronization signal is sent to the frequency divider module 110, the first detection module 120, and the counting module 130, respectively, while the second clock synchronization signal is sent to the second detection module 150. When the indication signal CLK_IND indicates that the clock is discontinuous, the first clock synchronization signal is the clock signal CLK; when the indication signal CLK_IND indicates that the clock signal CLK is continuous, the second clock synchronization signal is the clock signal CLK. The receiving module 140 can be constructed using a combination of logic gate circuits or other suitable electronic components. Specific details can be found in related technologies, which will not be elaborated here, and are all within the protection scope of this application.

[0050] The second detection module 150, after being enabled by the third enable signal, determines whether to send an interrupt signal CLK_OFF to the counting module 130 based on changes in the second clock synchronization signal. The interrupt signal CLK_OFF controls the counting module 130 to adjust the indicator signal CLK_IND, which indicates continuous clock signal CLK, to an indicator signal CLK_IND, which indicates discontinuous clock signal CLK. The third enable signal is CLK_IND, meaning the second detection module 150 is only enabled when the clock signal CLK is continuous. Therefore, when the clock detection circuit 100 does not receive the clock signal CLK or the clock signal CLK is discontinuous, the second detection module 150 is in a closed state.

[0051] In this embodiment, the first detection module 120 can be used to detect the clock signal CLK when it is discontinuous, that is, the first detection module 120 can be used to detect the clock signal CLK from non-existence to presence; and the second detection module 150 is turned off when the clock signal CLK is continuous, that is, the second detection module 150 can be used to detect the clock signal CLK from presence to absence. Through the division of labor between the first detection module 120 and the second detection module 150, different detection strategies can be adopted for different changing states of the clock signal CLK, thereby improving the accuracy or efficiency of clock signal CLK detection, making the application of the clock detection circuit 100 more flexible. In addition, when the first detection module 120 is enabled, the second detection module 150 can be in a closed state, and when the second detection module 150 is enabled, the first detection module 120 can be in a closed state. This ensures that only one of the first detection module 120 and the second detection module 150 generates power consumption at any given time. This allows for more targeted detection of the clock signal CLK without generating additional power consumption, thus achieving better detection results under similar power consumption conditions.

[0052] In some optional embodiments, the second detection module 150 includes a third timing detection module. The third timing detection module, after being enabled by a third enable signal, enters a third delay period for timing. If, within the third delay period, the second clock synchronization signal remains unchanged, an interrupt signal CLK_OFF is sent to the counting module 130. The third delay period should be greater than the period of the clock signal CLK. For example, the third delay period can be set to 64 times, 128 times, 256 times, or 512 times the clock period, etc. Except for the third delay period being greater than the period of the clock signal CLK, this application does not impose excessive limitations on the third delay period. It should be understood that a larger third delay period makes it easier to detect changes in the second clock synchronization signal, i.e., the higher the sensitivity of the third timing detection module. Furthermore, a larger third delay period results in a longer operating time and higher power consumption for the third timing detection module. Therefore, by setting the size of the third delay period, the sensitivity and power consumption of the third timing detection module can be controlled.

[0053] Since the second clock synchronization signal is the clock signal CLK when the indication signal CLK is continuous, and the third enable signal for enabling the third timing detection module is the indication signal CLK_IND that indicates the continuous clock signal CLK, in this embodiment, after the third timing detection module is enabled, the clock signal CLK can be detected within the third delay period, and the sensitivity and power consumption of the third timing detection module can be controlled by setting the size of the third delay period, making the setting of the second detection module 150 more flexible.

[0054] In some optional embodiments, the third timing detection module is specifically used to generate a third timing signal, adjust the changes of the third timing signal according to a third enable signal, and perform timing of the third delay period DT3 according to the changes of the third timing signal.

[0055] For example, such as Figure 6 As shown, when the indicator signal CLK_IND is high to indicate that the clock signal CLK is continuous (i.e., the third enable signal), the third timing detection module is enabled. At this time, the second clock synchronization signal is the clock signal CLK, and the third timing detection module can detect the clock signal CLK through the second clock synchronization signal. When the third timing detection module detects that the clock signal CLK changes from high to low, it sets the third timing signal to high and begins timing the third delay period DT3. If the clock signal CLK changes from low to high within the third delay period DT3, the third timing signal is set to low, and timing of the third delay period DT3 ends. If the clock signal CLK does not change from low to high within the complete third delay period DT3, an interrupt signal CLK_OFF is sent to the counting module 130 upon completion of the third delay period DT3 (when the third timing signal EN_DLY3 becomes low). This interrupts the counting module 130 to adjust the indicator signal CLK_IND to low to indicate that the clock signal CLK is discontinuous, specifically referring to the third delay period DT3 corresponding to time T3.

[0056] As a feasible implementation, a feedback line for the indicator signal CLK_IND is set between the counting module 130 and the third timing detection module, so that the third timing detection module can react to the changes in the indicator signal CLK_IND in a timely manner. For example, after the indicator signal CLK_IND changes from the continuous indication clock signal CLK to the discontinuous indication clock signal CLK, the third timing detection module immediately stops sending the interrupt signal CLK_OFF to reduce power consumption.

[0057] In this embodiment, when the third enable signal is the indication signal CLK_IND indicating the continuous operation of the clock signal CLK, the change of the third timing signal can be adjusted according to the change of the third enable signal, and the timing of the third delay period DT3 can be performed by the change of the third timing signal. The timing of detecting the clock signal CLK can be determined solely based on the level changes of the third enable signal and the third timing signal, making the detection logic of the clock signal CLK clear and easy to implement, and greatly improving the practicality of the clock detection circuit 100.

[0058] As a feasible implementation method, such as Figure 7 As shown, the receiving module 140 includes a first sub-receiving module 141 and a second sub-receiving module 142.

[0059] The first sub-receiving module 141 includes a first signal input terminal and a second signal input terminal. The first signal input terminal is used to receive the clock signal CLK, and the second signal input terminal is used to receive the indication signal CLK_IND. The first sub-receiving module 141 is used to send a first clock synchronization signal to the frequency divider module 110, the first detection module 120, and the counting module 130 when the indication signal CLK_IND indicates that the clock signal CLK is discontinuous. It should be noted that when the indication signal CLK_IND indicates that the clock signal CLK is discontinuous, the first clock synchronization signal is the clock signal CLK. When the indication signal CLK_IND indicates that the clock signal CLK is continuous, the first clock synchronization signal is preferably a signal other than the clock signal CLK, such as a continuous low-level signal. This allows the first detection module 120 to be disabled when the indication signal CLK_IND indicates that the clock signal CLK is continuous, thereby reducing power consumption. Of course, when the indication signal CLK_IND indicates that the clock signal CLK is continuous, the first clock synchronization signal can also be the clock signal CLK. In this case, the first detection module 120 will be enabled, thus operating even when the clock signal CLK is continuous.

[0060] The second sub-receiving module 142 includes a third signal input terminal and a fourth signal input terminal. The third signal input terminal is used to receive the clock signal CLK, and the fourth signal input terminal is used to receive the indication signal CLK_IND. The second sub-receiving module 142 is used to send a second clock synchronization signal to the second detection module 150 when the indication signal CLK_IND indicates that the clock signal CLK is continuous. Similar to the first clock synchronization signal, when the indication signal CLK_IND indicates that the clock signal CLK is continuous, the second clock synchronization signal is the clock signal CLK. When the indication signal CLK_IND indicates that the clock signal CLK is discontinuous, the second clock synchronization signal is preferably a signal other than the clock signal CLK, such as a continuous low-level signal. This allows the second detection module 150 to be disabled when the indication signal CLK_IND indicates that the clock signal CLK is continuous, thereby reducing power consumption.

[0061] In this embodiment, when the indication signal CLK_IND indicates that the clock signal CLK is discontinuous, the first sub-receiving module 141 can send the clock signal CLK to the frequency division module 110, the first detection module 120, and the counting module 130 via the first clock synchronization signal. When the indication signal CLK_IND indicates that the clock signal CLK is continuous, the second sub-receiving module 142 can send the clock signal CLK to the second detection module 150 via the second clock synchronization signal. This allows the first detection module 120 and the second detection module 150 to detect the clock signal CLK individually. The combination of the first detection module 120 and the second detection module 150 enables comprehensive detection of the clock signal CLK, thereby ensuring the accuracy of the clock signal CLK detection.

[0062] like Figure 8 As shown, in some optional embodiments, the first sub-receiving module 141 includes a NOT gate and a NOR gate. The input terminal of the NOT gate serves as the first signal input terminal of the first sub-receiving module 141, receiving the clock signal CLK to be detected. The first sub-input terminal of the NOR gate serves as the second signal input terminal of the first sub-receiving module 141, receiving the indication signal CLK_IND output by the counting module 130. The output terminal of the NOT gate is connected to the second sub-input terminal of the NOR gate. The output terminal of the NOR gate serves as the output terminal of the first sub-receiving module 141, connected to the input terminals of the first detection module 120 and the counting module 130.

[0063] The second sub-receiving module 142 includes an AND gate, which has a third sub-input, a fourth sub-input, and an output. The third sub-input serves as the third signal input of the second sub-receiving module 142, and the fourth sub-input serves as the fourth signal input. The third sub-input of the AND gate receives the clock signal CLK to be detected, and the fourth sub-input receives the indication signal CLK_IND. The output of the AND gate serves as the output of the second sub-receiving module 142 and is connected to the input of the second detection module 150.

[0064] The first sub-receiving module 141, through a combination of NOT and NOR gates, can output a first clock synchronization signal identical to the clock signal CLK when the indicator signal CLK_IND is low, and output a first clock synchronization signal that remains low when the indicator signal CLK_IND is high. The second sub-receiving module 142, through an AND gate, can output a second clock synchronization signal identical to the clock signal CLK when the indicator signal CLK_IND is high, and output a first clock synchronization signal that remains low when the indicator signal CLK_IND is low.

[0065] As in the above embodiment, the indicator signal CLK_IND can be set to indicate continuous clock signal CLK with a high level and discontinuous clock signal CLK with a low level. Therefore, in this embodiment, the first sub-receiving module 141 can output a first clock synchronization signal identical to the clock signal CLK when the indicator signal CLK_IND indicates discontinuous clock signal CLK, and output a first clock synchronization signal that is always low when the indicator signal CLK_IND indicates continuous clock signal CLK; the second sub-receiving module 142 can output a second clock synchronization signal identical to the clock signal CLK when the indicator signal CLK_IND indicates continuous clock signal CLK, and output a second clock synchronization signal that is always low when the indicator signal CLK_IND indicates discontinuous clock signal CLK. Thus, the function of the receiving module 140 can be perfectly implemented through simple logic circuits, making the receiving module 140 more practical. In addition, since the receiving module 140 is composed of logic circuits, the receiving module 140 hardly generates power consumption when it does not receive the clock signal CLK, enabling the clock detection circuit to better achieve the goal of reducing power consumption.

[0066] like Figure 9As shown, according to a second aspect of the embodiments of this application, a control system 200 is provided, including a clock detection circuit 100 provided in any of the above embodiments. The clock detection circuit 100 is used to receive and detect a clock signal CLK generated during the operation of the controlled system 300, and to send an indication signal CLK_IND to the controlled system 300 indicating whether the clock signal CLK is continuous or discontinuous. The controlled system 300 is turned on by the indication signal CLK_IND indicating continuous clock signal CLK, and / or turned off by the indication signal CLK_IND indicating discontinuous clock signal CLK, thereby realizing automatic control of the switching on and off of the controlled system 300. This allows the controlled system 300 to be turned on in a timely manner to better meet user needs, and also allows the controlled system 300 to be turned off in a timely manner to reduce power consumption generated by the controlled system 300.

[0067] In this application embodiment, the controlled system 300 can be an audio system, a video system, or other similar systems.

[0068] It should be understood that the control system provided in this application embodiment is based on the same inventive concept as the aforementioned clock detection circuit 100 embodiment and can achieve the same effect. For the specific implementation process, please refer to the description in the aforementioned clock detection circuit 100 embodiment, which will not be repeated here.

[0069] A third aspect of this application also provides an electronic device, including the control system described in the above embodiments.

[0070] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0071] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0072] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A clock detection circuit for receiving a clock signal and detecting the clock signal, characterized in that, include: The module consists of a frequency division module, a first detection module, and a counting module. The frequency division module is used to divide the clock signal to generate a logic signal, and send the logic signal to the first detection module. The first detection module is used to determine whether to send a reset signal to the counting module based on the changes in the logic signal and the clock signal after being enabled. The reset signal is used to control the counting module to reset and start clock counting again. The counting module is used to count the clock signal and determine whether the clock signal is continuous based on whether the count reaches a preset threshold. Wherein, the clock signal and / or the logic signal are enable signals that enable the first detection module; the first detection module includes a first timing detection module and a second timing detection module; The first timing detection module is used to enter the timing of the first delay period after being enabled by the first enable signal, and if the logic signal is not changed within the first delay period, it controls the counting module to be reset and start clock counting again. The second timing detection module is used to enter the second delay period for timing after being enabled by the second enable signal, and if the clock signal is not changed within the second delay period, it controls the counting module to reset and start counting the clock again. Wherein, the first enable signal is a signal in which the logic signal is high; the second enable signal is a signal in which both the logic signal and the clock signal are low.

2. The clock detection circuit according to claim 1, characterized in that, The first timing detection module is also used to generate a first timing signal, and after being enabled by a first enable signal, adjust the changes in the first timing signal based on the first enable signal, and enter the timing of the first delay period according to the changes in the first timing signal; The second timing detection module is also used to generate a second timing signal, and after being enabled by a second enable signal, adjust the changes in the second timing signal based on the second enable signal, and enter the timing of the second delay period according to the changes in the second timing signal.

3. The clock detection circuit according to claim 1 or 2, characterized in that, The clock detection circuit further includes a receiving module and a second detection module, and the counting module is also used to output an indication signal indicating whether the clock signal is continuous or discontinuous after determining whether the clock signal is continuous. The receiving module is used to receive the clock signal and the indication signal, generate a first clock synchronization signal and a second clock synchronization signal based on the clock signal and the indication signal, and send the first clock synchronization signal to the frequency division module, the first detection module and the counting module respectively, and send the second clock synchronization signal to the second detection module; wherein, when the indication signal indicates that the clock signal is discontinuous, the first clock synchronization signal is the clock signal, and when the indication signal indicates that the clock signal is continuous, the second clock synchronization signal is the clock signal; The second detection module is used to determine whether to send an interrupt signal CLK_OFF to the counting module based on the change of the second clock synchronization signal after being enabled by the third enable signal. The interrupt signal CLK_OFF is used to control the counting module to adjust the indicator signal that indicates the clock signal is continuous to the indicator signal that indicates the clock signal is discontinuous. The third enable signal is an indication signal that indicates the clock signal is continuous.

4. The clock detection circuit according to claim 3, characterized in that, The second detection module includes a third timing detection module; The third timing detection module is used to enter the third delay period for timing after being enabled by the third enable signal, and if the second clock synchronization signal is not changed during the third delay period, the interrupt signal CLK_OFF is sent to the counting module.

5. The clock detection circuit according to claim 4, characterized in that, The third timing detection module is specifically used to generate a third timing signal, adjust the changes in the third timing signal based on the third enable signal, and enter the timing of the third delay period according to the changes in the third timing signal.

6. The clock detection circuit according to claim 5, characterized in that, The receiving module includes a first sub-receiving module and a second sub-receiving module; The first sub-receiving module includes a first signal input terminal and a second signal input terminal. The first signal input terminal is used to receive the clock signal, and the second signal input terminal is used to receive the indication signal. The first sub-receiving module is used to send the first clock synchronization signal to the frequency division module, the first detection module, and the counting module when the indication signal indicates that the clock signal is discontinuous; The second sub-receiving module includes a third signal input terminal and a fourth signal input terminal. The third signal input terminal is used to receive the clock signal, and the fourth signal input terminal is used to receive the indication signal. The second sub-receiving module is used to send the second clock synchronization signal to the second detection module when the indication signal indicates that the clock signal is continuous.

7. The clock detection circuit according to claim 6, characterized in that, The first sub-receiving module includes a NOT gate and a NOR gate, wherein the input terminal of the NOT gate serves as the first signal input terminal, and the first sub-input terminal of the NOR gate serves as the second signal input terminal; The output of the NOT gate is connected to the second sub-input of the NOR gate; the output of the NOR gate serves as the output of the first sub-receiving module and is connected to the input of the first detection module and the input of the counting module. The second sub-receiving module includes an AND gate, which includes a third sub-input terminal and a fourth sub-input terminal; The third sub-input terminal serves as the third signal input terminal, and the fourth sub-input terminal serves as the fourth signal input terminal; the output terminal of the AND gate serves as the output terminal of the second sub-receiving module and is connected to the input terminal of the second detection module.

8. A control system, characterized in that, include: The clock detection circuit as described in any one of claims 1-7; The clock detection circuit is used to detect the clock signal generated during the operation of the controlled system, and send an indication signal to the controlled system indicating that the clock signal is continuous and / or discontinuous. The controlled system is turned on by the indication signal indicating that the clock signal is continuous, and / or the controlled system is turned off by the indication signal indicating that the clock signal is discontinuous. The controlled system includes an audio system and / or a video system.

9. An electronic device, characterized in that, Includes the control system as described in claim 8.

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