A low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation

Abstract

This invention relates to a low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation. Building upon traditional passive summation schemes, it aims to achieve multiplication of the summation coefficients through bidirectional sampling and charge sharing techniques, thereby offsetting the attenuation caused by summation. This scheme successfully solves the attenuation drawback of traditional passive summation schemes without sacrificing the overhead of active summation circuitry, and has broad market application prospects.

Description

Technical Field

[0001] This invention relates to a low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation. Background Technology

[0002] With the continuous development of the Internet of Things (IoT) industry, the connection between the analog and digital worlds is becoming increasingly close. As the sole interface connecting analog reality and digital, analog-to-digital (ADC) circuits face ever-increasing demands for precision due to advancements in digital technology. Delta-Sigma ADCs emerged in this context. In portable devices, in addition to high precision, low power consumption is also a crucial requirement. Therefore, finding a balance between high precision and low power consumption has become a focal point of exploration in modern industry and academia.

[0003] As a crucial component of multi-bit Delta-Sigma modulators, traditional summing circuits utilize active over-the-air (OTA) capacitors as the core to sum the signals at each node, consuming significant amounts of active power. To reduce this power consumption, passive summing schemes have gained popularity in recent years. While passive summing circuits reduce power consumption by directly connecting the summing capacitors carrying the signals from each branch in parallel, they introduce attenuation to the summation result. This makes the design requirements for multi-bit quantizers more stringent, which is undesirable. Summary of the Invention

[0004] The purpose of this invention is to provide a low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation. Building upon traditional passive summation schemes, it aims to achieve multiplication of the summation coefficients through bidirectional sampling and charge sharing techniques, thereby offsetting the attenuation caused by summation. This scheme successfully solves the attenuation drawback of traditional passive summation schemes without sacrificing the overhead of active summation circuitry, and has broad market application prospects.

[0005] To achieve the above objectives, the technical solution of the present invention is: a low-power multi-bit Delta-Sigma modulator based on passive and attenuation-free summation, which uses bidirectional sampling technology to perform passive summation to compensate for coefficient attenuation.

[0006] In one embodiment of the present invention, charge sharing technology is further adopted in the bidirectional sampling technology to achieve a higher summation factor multiplication, so as to offset the attenuation caused by summation.

[0007] In one embodiment of the present invention, the low-power multi-bit Delta-Sigma modulator includes a switch SW. 1a SW 1b SW 1c SW 1d SW2a SW 2b SW 2c SW 2d Capacitor C f1 C f2 SW 1a One end is connected to GND, SW 1a The other end is with SW 2b one end, C f1 One end is connected to SW 1b One end is with SW 2a one end, C f1 The other end is connected to SW 1b The other end is with SW 1d Connect one end and use it as the summation node V. DACp SW 1d The other end is with SW 2c one end, C f2 One end is connected to SW 1c One end is connected to GND, SW 1c The other end is with SW 2d one end, C f2 The other end is connected to SW 2a The other end, SW 2b The other end, SW 2c The other end, SW 2d The other end is connected to the summation signal V. ip1 Summation signal V ip1 The inverse signal V in1 Summation signal V ip2 Summation signal V ip2 The inverse signal V in2 SW 1a SW 1b SW 1c SW 1d Both are controlled by the switch control signal Φ1 for opening and closing, SW 2a SW 2b SW 2c SW 2d Both are controlled by the switch control signal Φ2 for opening and closing.

[0008] In one embodiment of the present invention, the low-power multi-bit Delta-Sigma modulator operates as follows:

[0009] When Φ2 is high, SW 2a SW 2b SW 2c SW 2d Closed circuit, capacitor C f1 and C f2 Charging, at this time Cf1 and C f2 The lower electrode plate is connected to V in1 and V in2 via V ip1 With V in1 Bidirectional sampling, at this time C f1 The voltage difference carried is V ip1 -V in1 Because of V ip1 With V in1 Since it is a set of differential voltages, there exists V ip1 -V in1 =2·V ip1 Therefore, it is equivalent to C. f1 The carried voltage signal is twice V ip1 C f2 Similarly, the carried voltage signal is twice V. ip2 That is, to complete C f1 and C f2 The carried voltage signal is multiplied by 2; at this time, when Φ1 is high, SW 2a SW 2b SW 2c SW 2d Disconnect, SW 1a SW 1b SW 1c SW 1d Closed, C f1 and C f2 Each carrying twice the V ip1 and V ip2 The voltage signal is transmitted to the summing node V. DACp Summation is performed; since C f1 and C f2 The parallel connection, finally summing the nodes V DACp The voltage is:

[0010]

[0011] By setting the coefficients, C f1 =C f2 Then at the summation node V DACp Transmit 1 times V ip1 With V ip2 Thus, through bidirectional sampling technology, C f1 and C f2 The carried voltage signal achieves a 2x multiplication, successfully compensating for the attenuation caused by the direct parallel connection of the summing capacitors.

[0012] In one embodiment of the present invention, the low-power multi-bit Delta-Sigma modulator includes a switch SW. 1a SW 1bSW 1c SW 1d SW 1e SW 1f SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h Capacitor C f1a C f1b C f2a C f2b SW 1a One end is connected to GND, SW 1a The other end is with SW 2b one end, C f1a One end is connected to SW 1b One end is with SW 2c one end, C f1b One end is connected, C f1a The other end is with SW 2a One end is connected, and via SW 1c With SW 2d one end, C f1b The other end is connected to SW 1b The other end is with SW 1e Connect one end and use it as the summation node V. DACp SW 1e The other end is with SW 2g one end, C f2a One end is connected, C f2a The other end is with SW 2h One end is connected, and via SW 1f With SW 2e one end, C f2b One end is connected, C f2b The other end is with SW 2f One end is connected, and via SW 1d Connect to GND, SW 2a The other end, SW 2c The other end summing signal V ip1 SW 2b The other end, SW 2d The other end summing signal V ip1 The inverse signal V in1 SW 2g The other end, SW 2e The other end summing signal V ip2 SW 2h The other end, SW 2fThe other end summing signal V ip2 The inverse signal V in2 SW 1a SW 1b SW 1c SW 1d SW 1e SW 1f Both are controlled by the switch control signal Φ1 for opening and closing, SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h Both are controlled by the switch control signal Φ2 for opening and closing.

[0013] In one embodiment of the present invention, the low-power multi-bit Delta-Sigma modulator operates as follows:

[0014] When Φ2 is high, SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h Closed, circuit node V ip1 V in1 and V ip2 V in2 Capacitor C f1a C f1b and C f2a C f2b Charging, at this time C f1a C f1b and C f2a C f2b The voltage signal carried by the capacitor is equivalent to twice V. ip1 and V ip2 When Φ1 is high, SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h Disconnect, SW 1a SW 1b SW 1c SW 1d SW 1e SW 1f Closed, because C is closed at this timef1a With C f1b In series, the voltages carried are superimposed, C f1a With C f1b The series circuit formed is equivalent to carrying 4 times V ip1 Similarly, C f2a With C f2b The series circuit formed is equivalent to carrying 4 times V ip2 This means multiplying the voltage signal carried by the summing capacitor by four times; this four-fold voltage signal is then transmitted to the summing node V. DACp Summing at point C, if C f1a =C f1b =C f1 C f2a =C f2b =C f2 Due to the parallel connection of the summing capacitor bank, the final summing node V DACp The voltage is:

[0015]

[0016] By setting the coefficients, C f1 =C f2 Then at the summation node V DACp Upload 2 times V ip1 and 2 times V ip2 Thus, by combining bidirectional sampling technology with charge sharing technology, C f1 and C f2 The carried voltage signal achieves a 4-fold multiplication, successfully compensating for the attenuation caused by the direct parallel connection of the summing capacitors.

[0017] Compared to existing technologies, this invention offers the following advantages: It achieves multiplication of the summation coefficient through bidirectional sampling and charge sharing techniques, thereby offsetting the attenuation caused by the summation. This solution successfully overcomes the attenuation drawbacks of traditional passive summation schemes without sacrificing the overhead of active summing circuits, and has broad market application prospects. Attached Figure Description

[0018] Figure 1 This is a traditional sourceless summation method.

[0019] Figure 2 This is a passive summation method for bidirectional sampling.

[0020] Figure 3 This is a bidirectional sampling + charge-sharing passive summation.

[0021] Figure 4 This is an application case of a passive, non-summary solution.

[0022] Figure 5 This is the output spectrum of the modulator. Detailed Implementation

[0023] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] This invention provides a low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation. Passive summation is performed using bidirectional sampling technology to compensate for coefficient attenuation. Furthermore, charge sharing technology is employed on top of the bidirectional sampling technology to achieve a higher summation coefficient multiplication, thus offsetting the attenuation caused by the summation.

[0025] The following is a detailed implementation process of the present invention.

[0026] To simplify the description, V is implemented using a passive summing circuit. ip1 and V ip2 For example, summation. Figure 1 The diagram shows a traditional passive summation scheme. When Φ2 is high, SW 2a SW 2b SW 2c SW 2d When closed, circuit node V ip1 and V ip2 Capacitor C f1 and C f2 Charging, at this time C f1 and C f2 The voltage signal carried by the capacitor is 1 times V. ip1 and V ip2 When Φ1 is high, SW 2a SW 2b SW 2c SW 2d Disconnect, SW 1a SW 1b SW 1c SW 1d Closed, C f1 and C f2 Each carrying 1 times V ip1 and V ip2 Voltage is transferred to V DACp Perform summation. Since C... f1 and C f2 The parallel connection, finally summing the nodes V DACp The voltage is:

[0027]

[0028] If C f1 =C f2 Then at the signal summation node V DACp Only 0.5 times V was passed up. ip1 and 0.5 times V ip2This causes a decrease in the summation coefficient. If we want to compensate for this decrease, a simple and effective method is obviously to increase the signal multiplier carried by the capacitor, thus multiplying the signal.

[0029] Figure 2 The diagram shows the proposed solution, which uses bidirectional sampling technology for passive summation to compensate for coefficient attenuation. Since the summation circuit of Delta-Sigma modulators is mostly performed in differential circuits, Figure 2 China V ip1 V in1 and V ip2 V in2 This represents the positive and negative terminal voltages of two sets of differential circuits, and there exists a relationship V. ip1 =-V in1 V ip2 =-V in2 When Φ2 is high, SW 2a SW 2b SW 2c SW 2d When closed, the circuit is capacitor C. f1 and C f2 Charging, and Figure 1 The difference is that C at this time f1 and C f2 The lower electrode plate was connected to V in1 and V in2 Through V ip1 With V in1 Bidirectional sampling, at this time C f1 The voltage difference carried is V ip1 -V in1 Because of V ip1 With V in1 Since it is a set of differential voltages, there exists V ip1 -V in1 =2·V ip1 Therefore, it is equivalent to C. f1 The carried voltage signal is twice V ip1 C f2 Similarly, the carried voltage signal is twice V. ip2 Thus, C was completed through bidirectional sampling technology. f1 and C f2 The carried voltage signal achieves a 2x multiplication. At this time, when Φ1 is high, SW... 2a SW 2b SW 2c SW 2d Disconnect, SW 1a SW 1b SW 1c SW 1d Closed, C f1 and Cf2 Each carrying twice the V ip1 and V ip2 The voltage signal is transmitted to V DACp Perform summation. Since C... f1 and C f2 The parallel connection, finally summing the nodes V DACp The voltage is:

[0030]

[0031] If C is made possible by setting the coefficients f1 =C f2 So exactly one times V was passed at the summation node. ip1 With V ip2 Thus, we have achieved C through bidirectional sampling technology. f1 and C f2 The carried voltage signal achieved a 2x multiplication, successfully compensating for the attenuation caused by the direct parallel connection of the summing capacitors. For even larger signal multiplication, a more aggressive expansion scheme can be employed.

[0032] Figure 3 As shown Figure 2 The extension, through bidirectional sampling technology combined with charge sharing technology, can achieve a higher coefficient multiplication. When Φ2 is high, SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h When closed, circuit node V ip1 V in1 and V ip2 V in2 Capacitor C f1a C f1b and C f2a C f2b Charging, and Figure 2 Similar to the case, C at this time f1a C f1b and C f2a C f2b The voltage signal carried by the capacitor is equivalent to twice V. ip1 and V ip2 When Φ1 is high, SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW2h Disconnect, SW 1a SW 1b SW 1c SW 1d SW 1e SW 1f Closed, because C is closed at this time f1a With C f1b In series, the voltages carried are superimposed, C f1a With C f1b The series circuit formed by it effectively carries 4 times the V ip1 Similarly, C f2a With C f2b The series circuit formed by it effectively carries 4 times the V ip2 Thus, through bidirectional sampling and charge-sharing techniques, the voltage signal carried by the summing capacitor was multiplied by 4. This 4-fold voltage signal was then transmitted to V. DACp Summing at nodes, if C f1a =C f1b =C f1 C f2a =C f2b =C f2 Due to the parallel connection of the summing capacitor bank, the final summing node V DACp The voltage is:

[0033]

[0034] If C f1 =C f2 Then at the signal summation node V DACp Uploaded 2 times V ip1 and 2 times V ip2 This makes it possible to compensate for higher attenuation, thus improving the applicability and degree of freedom of passive attenuation-free summation.

[0035] Figure 4 The illustration shows an example of a low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation proposed in this invention. In this example, the signals to be summed by the summing circuit are V... ip -V in V o1p -V o1n V o2p -V o2n The summation coefficients are required to be 1:0.25:0.25. When Φ2d is high, SW 3a and SW 3b When closed, the positive and negative output terminals of the input signal are fed to capacitor C through bidirectional sampling technology. f1a Charging allows C f1a The pressure difference carried is V ip -Vin Equivalent to twice the V ip This achieves a 2x coefficient multiplication. Meanwhile, SW 11a and SW 11b It is also closed, and OTA1 also sends bidirectional sampling to C. f2a Charging makes its voltage difference equivalent to twice the voltage of V. o1p This also achieves a 2x coefficient multiplication. Meanwhile, SW 16a and SW 17b Also close, making C f3a The differential pressure is zeroed. When Φ1d is high, SW... 4a and SW 4b Close, SW 12a and SW 12b Also close, making C f1a With C f2a Each carrying twice the V ip With 2 times V op1 Pressure difference pushes towards summation node V DACp Perform summation. Meanwhile, SW... 3a It is also closed; OTA2 only has the positive output terminal V. o2p Give C f3a Charging is equivalent to C f3a Carrying a pressure difference of 1 times V o2p To perform the summation, the final summation node V is... DACp The final voltage at the terminal is:

[0036]

[0037] Where C pa Let C be the expected parasitic capacitance. f1a :C f2a :C f3a :C pa =4:1:2:1, then the final V DACp for:

[0038] 1·V ip +0.25·V o1p +0.25·V o2p

[0039] negative end V DACn Similarly, the final summation result is V. DACp -V DACn for:

[0040] 1·(V ip -V in )+0.25·(V o1p -V o1n )+0.25·(V o2p -Vo2n )

[0041] Thus by C f1a C f2a The carried signal achieves a 2x coefficient multiplication through bidirectional sampling technology, thus realizing a passive and attenuation-free summation method.

[0042] Figure 5 The image shows the output data spectrum analysis of this low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation. At a bandwidth of 20kHz, the modulator achieved an SNDR performance of 102.62dB, indicating good modulator performance.

[0043] It can be seen that the proposed passive and attenuation-free summing scheme can successfully solve the attenuation drawback of traditional passive summing schemes without sacrificing the overhead of active summing circuits. Furthermore, it is very suitable for the design of low-power Delta-Sigma modulators and has broad market application prospects.

[0044] The above are preferred embodiments of the present invention. Any changes made to the technical solution of the present invention that do not exceed the scope of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation, characterized in that, Passive summation is performed using bidirectional sampling technology to compensate for coefficient attenuation; further, charge sharing technology is employed on top of bidirectional sampling to achieve a higher summation coefficient multiplication, thus offsetting the attenuation caused by summation; the low-power multi-bit Delta-Sigma modulator includes a switch SW. 1a SW 1b SW 1c SW 1d SW 2a SW 2b SW 2c SW 2d Capacitor C f1 C f2 SW 1a One end is connected to GND, SW 1a The other end is with SW 2b one end, C f1 One end is connected to SW 1b One end is with SW 2a one end, C f1 The other end is connected to SW 1b The other end is with SW 1d Connect one end and use it as the summation node V. DACp SW 1d The other end is with SW 2c one end, C f2 One end is connected to SW 1c One end is connected to GND, SW 1c The other end is with SW 2d one end, C f2 The other end is connected to SW 2a The other end, SW 2b The other end, SW 2c The other end, SW 2d The other end is connected to the summation signal V. ip1 Summation signal V ip1 The inverse signal V in1 Summation signal V ip2 Summation signal V ip2 The inverse signal V in2 SW 1a SW 1b SW 1c SW 1d Both are controlled by the switch control signal Φ1 for opening and closing, SW 2a SW 2b SW 2c SW 2d Both are controlled by the switch control signal Φ2 for opening and closing.

2. The low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation according to claim 1, characterized in that, The low-power multi-bit Delta-Sigma modulator operates as follows: When Φ2 is high, SW 2a SW 2b SW 2c SW 2d Closed circuit, capacitor C f1 and C f2 Charging, at this time C f1 and C f2 The lower electrode plate is connected to V in1 and V in2 via V ip1 With V in1 Bidirectional sampling, at this time C f1 The voltage difference carried is V ip1 -V in1 Because of V ip1 With V in1 Since it is a set of differential voltages, there exists V ip1 -V in1 =2·V ip1 Therefore, it is equivalent to C. f1 The carried voltage signal is twice V. ip1 C f2 Similarly, the carried voltage signal is twice V. ip2 That is, to complete C f1 and C f2 The carried voltage signal is multiplied by 2; at this time, when Φ1 is high, SW 2a SW 2b SW 2c SW 2d Disconnect, SW 1a SW 1b SW 1c SW 1d Closed, C f1 and C f2 Each carrying 2 times the V ip1 and V ip2 The voltage signal is transmitted to the summing node V. DACp Summation is performed; since C f1 and C f2 The parallel connection, finally summing the nodes V DACp The voltage is: By setting the coefficients, C f1 =C f2 Then at the summation node V DACp Transmit 1 times V ip1 With V ip2 Thus, through bidirectional sampling technology, C f1 and C f2 The carried voltage signal achieves a 2x multiplication, successfully compensating for the attenuation caused by the direct parallel connection of the summing capacitors.

3. A low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation, characterized in that, Passive summation is performed using bidirectional sampling technology to compensate for coefficient attenuation; further, charge sharing technology is employed on top of bidirectional sampling to achieve a higher summation coefficient multiplication, thus offsetting the attenuation caused by summation; the low-power multi-bit Delta-Sigma modulator includes a switch SW. 1a SW 1b SW 1c SW 1d SW 1e SW 1f SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h Capacitor C f1a C f1b C f2a C f2b SW 1a One end is connected to GND, SW 1a The other end is with SW 2b one end, C f1a One end is connected to SW 1b One end is with SW 2c one end, C f1b One end is connected, C f1a The other end is with SW 2a One end is connected, and via SW 1c With SW 2d one end, C f1b The other end is connected to SW 1b The other end is with SW 1e Connect one end and use it as the summation node V. DACp SW 1e The other end is with SW 2g one end, C f2a One end is connected, C f2a The other end is with SW 2h One end is connected, and via SW 1f With SW 2e one end, C f2b One end is connected, C f2b The other end is with SW 2f One end is connected, and via SW 1d Connect to GND, SW 2a The other end, SW 2c The other end summing signal V ip1 SW 2b The other end, SW 2d The other end summing signal V ip1 The inverse signal V in1 SW 2g The other end, SW 2e The other end summing signal V ip2 SW 2h The other end, SW 2f The other end summing signal V ip2 The inverse signal V in2 SW 1a SW 1b SW 1c SW 1d SW 1e SW 1f Both are controlled by the switch control signal Φ1 for opening and closing, SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h Both are controlled by the switch control signal Φ2 for opening and closing.

4. A low-power multi-bit Delta-Sigma modulator based on passive, attenuation-free summation according to claim 3, characterized in that, The low-power multi-bit Delta-Sigma modulator operates as follows: When Φ2 is high, SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h Closed, circuit node V ip1 V in1 and V ip2 V in2 Capacitor C f1a C f1b and C f2a C f2b Charging, at this time C f1a C f1b and C f2a C f2b The voltage signal carried by the capacitor is equivalent to twice V. ip1 and V ip2 When Φ1 is high, SW 2a SW 2b SW 2c SW 2d SW 2e SW 2f SW 2g SW 2h Disconnect, SW 1a SW 1b SW 1c SW 1d SW 1e SW 1f Closed, because C is closed at this time f1a With C f1b In series, the voltages carried are superimposed, C f1a With C f1b The series circuit formed is equivalent to carrying 4 times V ip1 Similarly, C f2a With C f2b The series circuit formed is equivalent to carrying 4 times V ip2 This means multiplying the voltage signal carried by the summing capacitor by four times; this four-fold voltage signal is then transmitted to the summing node V. DACp Summing at point C, if C f1a =C f1b =C f1 C f2a =C f2b =C f2 Due to the parallel connection of the summing capacitor bank, the final summing node V DACp The voltage is: By setting the coefficients, C f1 =C f2 Then at the summation node V DACp Upload 2 times V ip1 and 2 times V ip2 Thus, by combining bidirectional sampling technology with charge sharing technology, C f1 and C f2 The carried voltage signal achieves a 4-fold multiplication, successfully compensating for the attenuation caused by the direct parallel connection of the summing capacitors.

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