Method and apparatus for channel coding

Abstract

The application provides a method and device for convolutional encoding, comprising: a terminal device generating a first bit sequence, determining a second bit sequence according to the first bit sequence. The second bit sequence comprises M bits, and any one bit in the last N bits of the second bit sequence is identical to the value of any one bit in the first N bits of the first bit sequence. M and N are positive integers, and M is greater than N. The second bit sequence is subjected to convolutional encoding by a convolutional encoder to obtain a third bit sequence. The initial value of a shift register of the convolutional encoder is equal to the value of the last N bits of the second bit sequence. The convolutional encoder comprises N shift registers, and the third bit sequence is transmitted. The technical solution disclosed by the application helps to reduce the complexity of convolutional encoding while ensuring the performance of convolutional encoding.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to methods and apparatus for channel coding. Background Technology

[0002] With the fifth generation of new wireless access technology (5G) th With the increasing prevalence of Generation New Radio (5G NR) and machine-type communication (MTC) and Internet of Things (IoT) communication, the number of connected IoT devices is growing daily, and the industry's demand for reduced cost and power consumption of IoT devices is becoming increasingly strong. Therefore, research is focusing on Passive IoT or Backscatter communication. However, due to the power consumption and complexity limitations of passive IoT / backscatter communication terminal devices, the power consumption of these terminals may be limited to less than 1 microwatt (μW) or less than 100 μW. Under this target, it is difficult for passive IoT terminal devices to implement complex channel coding, such as computationally complex coding or requiring large amounts of memory to store information. Therefore, it is necessary to consider implementing simple channel coding to improve the coverage of passive IoT terminal devices.

[0003] In current Long Term Evolution (LTE) systems, convolutional coding methods typically employ two approaches to ensure channel coding performance: (1) channel coding can only begin after all information bits have been added with a cyclic redundancy check (CRC) code; and (2) rate matching is performed after coding, including processes such as block interleaving, bit collection, and bit selection. However, for passive IoT terminal devices, both starting channel coding after CRC addition and performing rate matching after coding are generally difficult to implement due to their limited energy consumption. Furthermore, failing to perform rate matching after coding leads to poor channel coding performance.

[0004] Therefore, there is an urgent need for a convolutional coding method that can reduce the power consumption and complexity of convolutional coding while ensuring a certain level of performance. Summary of the Invention

[0005] This application provides a method and apparatus for convolutional coding, which helps to reduce the complexity of convolutional coding while ensuring its performance.

[0006] Firstly, a convolutional coding method is provided, comprising: a terminal device generating a first bit sequence, which is an original bit sequence; the terminal device determining a second bit sequence based on the first bit sequence, which is a bit sequence to be encoded, comprising M bits, wherein the last N bits of the second bit sequence correspond one-to-one with the first N bits of the first bit sequence, and any bit in the last N bits of the second bit sequence has the same value as the bit corresponding to any bit in the first N bits of the first bit sequence, wherein M and N are positive integers, and M is greater than N; the terminal device performing convolutional coding on the second bit sequence using a convolutional encoder to obtain a third bit sequence, which is the encoded bit sequence, wherein the initial value of the shift register of the convolutional encoder is equal to the value of the last N bits of the second bit sequence, and the convolutional encoder comprises N shift registers; and the terminal device transmitting the third bit sequence.

[0007] The first bit sequence is the original bit sequence. Optionally, the first bit sequence can also be generated by other chips or devices. The terminal device mentioned above only processes the first bit sequence to obtain the third bit sequence.

[0008] According to the technical solution of this application, there is no need to wait for the original information bits to be added with CRC bits to obtain the complete first bit sequence before starting the convolutional encoder for encoding. This effectively reduces the cache / storage overhead of low-power terminal devices using convolutional encoding, which helps to further reduce the power consumption of low-power terminal devices using convolutional encoding. In addition, convolutional encoding has the characteristic of keeping the register end state consistent with the initial state, which ensures the performance of convolutional encoding in certain low-power terminal devices and effectively improves the coverage performance of communication between low-power terminal devices and network devices.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the first MN bits of the second bit sequence are the (N+1)th to (M)th bits of the first bit sequence. This approach does not disrupt the order of bits other than the first N bits in the original bit sequence and does not increase the complexity of convolutional coding in low-power terminal devices.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the initial value of the shift register of the convolutional encoder includes the values ​​of N shift registers, where the value of the i-th shift register is s. i Let i be a natural number less than N, and let the last N bits of the second bit sequence be x. M-N+i The first N bits of the first bit sequence have a value of c. i , where s i equals c i And x M-N+i equals c N-1-i Or, s iequals c N-1-i And x M-N+i equals c i This method moves the first N bits of the first bit sequence to the end of the second bit sequence and sends them last, arranging them in ascending or descending order of sequence number. Convolutional coding has the characteristic of maintaining consistency between the end state and the initial state of the register, ensuring the performance of convolutional coding in certain low-power terminal devices and effectively improving the coverage performance of communication between low-power terminal devices and network devices.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, N equals 6.

[0012] In conjunction with the first aspect, in certain implementations of the first aspect, the terminal device transmits a third bit sequence, including: the terminal device transmits the third bit sequence without performing any first processing on the third bit sequence, whereby the first processing includes block interleaving and / or rate matching, and rate matching includes at least one of bit collection, bit selection, and bit pruning. By transmitting the third bit sequence without performing any processing, the cache / storage overhead of the low-power terminal device using convolutional coding is effectively reduced, without additionally increasing the power consumption of the low-power terminal device using convolutional coding.

[0013] In conjunction with the first aspect, in some other implementations of the first aspect, the terminal device transmits the third bit sequence, including: the terminal device performs a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes block interleaving, where the number of rows multiplied by the number of columns of the matrix is ​​less than the length of the third bit sequence. The number of columns in the block-interleaved matrix is ​​less than 32, wherein the number of columns in the block-interleaved matrix is ​​4, 8, or 16. The terminal device then transmits the processed third bit sequence. Block interleaving can also be called sub-block interleaving. This approach, by processing the third bit to a certain extent before transmitting the third bit sequence, slightly increases the buffer / storage overhead of convolutional coding in the low-power terminal device, which helps to improve the performance of convolutional coding to a certain extent and effectively improves the coverage performance of communication between the low-power terminal device and network equipment.

[0014] In conjunction with the first aspect, in certain implementations of the first aspect, the terminal device sends first information, which indicates that the terminal device is a terminal device with a first capability. The first capability includes at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence. The first bit sequence is convolutionally encoded using a convolutional encoder. By doing so, the network device can obtain the channel coding capability associated with the type of the terminal device and decode the information bits sent by the terminal device according to the different channel coding methods for different types of terminal devices. This enables terminal devices and network devices with different capabilities to complete effective channel coding transmission and reception, effectively improving the coverage performance of communication between different terminal devices and network devices.

[0015] Secondly, a convolutional coding method is provided. It includes: a network device receiving a third bit sequence, which is the bit sequence to be decoded; the network device determining the last N bits of a second bit sequence based on the third bit sequence; and the network device decoding the third bit sequence using the last N bits of the second bit sequence to obtain the second bit sequence, which is the decoded bit sequence. The second bit sequence includes M bits, with the N bits being the last N bits of the second bit sequence. The network device determining a first bit sequence based on the second bit sequence, which is the original bit sequence. The first N bits of the first bit sequence correspond one-to-one with the last N bits of the second bit sequence, and any bit in the first N bits of the first bit sequence has the same value as the bit corresponding to any bit in the last N bits of the second bit sequence, where M and N are positive integers, and M is greater than N.

[0016] According to the technical solution of this application, there is no need to wait for the original information bits to be added with CRC bits to obtain the complete first bit sequence before starting the convolutional encoder for encoding. This effectively reduces the cache / storage overhead of low-power terminal devices using convolutional encoding, which helps to further reduce the power consumption of low-power terminal devices using convolutional encoding. In addition, convolutional encoding has the characteristic of keeping the register end state consistent with the initial state, which ensures the performance of convolutional encoding in certain low-power terminal devices and effectively improves the coverage performance of communication between low-power terminal devices and network devices.

[0017] In conjunction with the second aspect, in some implementations of the second aspect, the N+1 to Mth bits of the first bit sequence are the first MN bits of the second bit sequence.

[0018] In conjunction with the second aspect, in some implementations of the second aspect, N equals 6.

[0019] In conjunction with the second aspect, in some implementations of the second aspect, the network device determines the last N bits of the second bit sequence based on the third bit sequence, including: the network device does not perform the first processing on the third bit sequence, and obtains the last N bits of the second bit sequence based on the third bit sequence, wherein the first processing includes deblocking and / or derate matching, and rate matching includes at least one of bit collection, bit selection, and bit pruning.

[0020] In conjunction with the second aspect, in some other implementations of the second aspect, the network device determines the last N bits of the second bit sequence based on the third bit sequence, including: the network device performs a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes block interleaving where the number of rows multiplied by the number of columns of the solution matrix is ​​less than the length of the third bit sequence. The number of columns in the block interleaving matrix is ​​less than 32, wherein the number of columns in the block interleaving matrix is ​​4, 8, or 16. The network device determines the last N bits of the second bit sequence based on the processed third bit sequence.

[0021] In conjunction with the second aspect, in some implementations of the second aspect, the above method further includes: a network device receiving first information, the first information being used to indicate that a terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0022] Thirdly, a convolutional coding method is provided. This includes: a terminal device generating a first bit sequence, which is the original bit sequence and includes M bits. The terminal device determines a second bit sequence based on the first bit sequence, which is the bit sequence to be encoded. The second bit sequence includes M+N bits, where N bits are predefined bits, and the values ​​of the N bits are not all equal to 0. The last N bits of the second bit sequence are also predefined bits, and M and N are positive integers. The terminal device performs convolutional coding on the second bit sequence using a convolutional encoder to obtain a third bit sequence, which is the encoded bit sequence. The initial value of the shift registers of the convolutional encoder is equal to the values ​​of the last N bits of the second bit sequence, and the convolutional encoder includes N shift registers. The terminal device then transmits the third bit sequence.

[0023] According to the technical solution of this application, there is no need to wait for the original information bits to be added with CRC bits to obtain the complete first bit sequence before starting the convolutional encoder for encoding. This effectively reduces the cache / storage overhead of low-power terminal devices using convolutional encoding, which helps to further reduce the power consumption of low-power terminal devices using convolutional encoding. In addition, convolutional encoding has the characteristic of keeping the register end state consistent with the initial state, which ensures the performance of convolutional encoding in certain low-power terminal devices and effectively improves the coverage performance of communication between low-power terminal devices and network devices.

[0024] In conjunction with the third aspect, in some implementations of the third aspect, the first M bits of the second bit sequence are the M bits of the first bit sequence. This does not disrupt the bit order in the original bit sequence, helping to reduce the encoding complexity of the terminal device while ensuring the accuracy of information transmission.

[0025] In conjunction with the third aspect, in some implementations of the third aspect, predefined N bits carry second information, which includes payload type information, service type information, or channel type information. This allows information to be carried on predefined bits, avoiding the bit rate loss caused by adding an extra N bits during actual information transmission due to convolutional coding.

[0026] In conjunction with the third aspect, in some implementations of the third aspect, N equals 6.

[0027] In conjunction with the third aspect, in some implementations of the third aspect, the terminal device transmits a third bit sequence, including: the terminal device transmits the third bit sequence without performing any first processing on the third bit sequence, where the first processing includes block interleaving and / or rate matching, and rate matching includes at least one of bit collection, bit selection, and bit pruning. By transmitting the third bit sequence without performing any processing, the cache / storage overhead of the low-power terminal device using convolutional coding is effectively reduced, without additionally increasing the power consumption of the low-power terminal device using convolutional coding.

[0028] In conjunction with the third aspect, in some other implementations of the third aspect, the terminal device transmits the third bit sequence, including: the terminal device performs a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes block interleaving where the number of rows multiplied by the number of columns of the matrix is ​​less than the length of the third bit sequence. The number of columns in the block-interleaved matrix is ​​less than 32, wherein the number of columns in the block-interleaved matrix is ​​4, 8, or 16. The terminal device then transmits the processed third bit sequence. This approach, by processing the third bit to a certain extent before transmitting it, slightly increases the buffering / storage overhead of convolutional coding in the low-power terminal device, which helps to improve the performance of convolutional coding to a certain extent and effectively improves the coverage performance of communication between the low-power terminal device and network equipment.

[0029] In conjunction with the third aspect, in some implementations of the third aspect, the method further includes: the terminal device sending first information, the first information indicating that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence using a convolutional encoder. In this way, the network device can obtain the channel coding capability associated with the type of the terminal device, and decode the information bits sent by the terminal device according to the different channel coding methods for different types of terminal devices, enabling terminal devices and network devices with different capabilities to complete effective channel coding transmission and reception, effectively improving the coverage performance of communication between different terminal devices and network devices.

[0030] Fourthly, a convolutional coding method is provided. This includes: a network device receiving a third bit sequence, which is the bit sequence to be decoded; the network device determining the last N bits of a second bit sequence based on the third bit sequence; and decoding the third bit sequence using the last N bits of the second bit sequence to obtain the second bit sequence, which is the decoded bit sequence. The second bit sequence includes M+N bits, where N bits are predefined bits, and the values ​​of the N bits are not all equal to 0. The last N bits of the second bit sequence are predefined bits, and M and N are positive integers. The network device determining a first bit sequence based on the second bit sequence, which is the original bit sequence and includes M bits.

[0031] According to the technical solution of this application, there is no need to wait for the original information bits to be added with CRC bits to obtain the complete first bit sequence before starting the convolutional encoder for encoding. This effectively reduces the cache / storage overhead of low-power terminal devices using convolutional encoding, which helps to further reduce the power consumption of low-power terminal devices using convolutional encoding. In addition, convolutional encoding has the characteristic of keeping the register end state consistent with the initial state, which ensures the performance of convolutional encoding in certain low-power terminal devices and effectively improves the coverage performance of communication between low-power terminal devices and network devices.

[0032] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first M bits of the second bit sequence are the M bits of the first bit sequence.

[0033] In conjunction with the fourth aspect, in some implementations of the fourth aspect, predefined N bits carry second information, which includes information about the load type, service type, or channel type.

[0034] In conjunction with the fourth aspect, in some implementations of the fourth aspect, N equals 6.

[0035] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the network device determines the last N bits of the second bit sequence based on the third bit sequence, including: the network device does not perform the first processing on the third bit sequence, and obtains N bits based on the third bit sequence, wherein the first processing includes deblocking and / or derate matching, and rate matching includes at least one of bit collection, bit selection, and bit pruning.

[0036] In conjunction with the fourth aspect, in some other implementations of the fourth aspect, the network device determines the last N bits of the second bit sequence based on the third bit sequence, including: the network device performs a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes block interleaving where the number of rows multiplied by the number of columns of the solution matrix is ​​less than the length of the third bit sequence. The number of columns in the block interleaving matrix is ​​less than 32, wherein the number of columns in the block interleaving matrix is ​​4, 8, or 16. The network device determines the last N bits of the second bit sequence based on the processed third bit sequence.

[0037] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the above method further includes: a network device receiving first information, the first information being used to indicate that a terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0038] Fifthly, a convolutional coding apparatus is provided. It includes: a processing unit for generating a first bit sequence, which is the original bit sequence; determining a second bit sequence based on the first bit sequence, the second bit sequence being the bit sequence to be encoded, the second bit sequence comprising M bits, wherein the last N bits of the second bit sequence correspond one-to-one with the first N bits of the first bit sequence, and any bit in the last N bits of the second bit sequence has the same value as the bit corresponding to any bit in the first N bits of the first bit sequence, wherein M and N are positive integers, and M is greater than N; performing convolutional coding on the second bit sequence using a convolutional encoder to obtain a third bit sequence, the third bit sequence being the encoded bit sequence, the initial value of the shift registers of the convolutional encoder being equal to the values ​​of the last N bits of the second bit sequence, and the convolutional encoder including N shift registers; and a transceiver unit for transmitting the third bit sequence.

[0039] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the first MN bits of the second bit sequence are the N+1 to M bits of the first bit sequence.

[0040] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the initial value of the shift register of the convolutional encoder includes the values ​​of N shift registers, where the value of the i-th shift register is s. i Let i be a natural number less than N. The last N bits of the second bit sequence are x. M-N+i The first N bits of the first bit sequence have a value of c. i , where s i equals c i And x M-N+i equals G N-1-i Or, s i equals c N-1-i And x M-N+i equals c i .

[0041] In conjunction with the fifth aspect, in some implementations of the fifth aspect, N equals 6.

[0042] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the processing unit is further configured to not perform the first processing on the third bit sequence, the first processing including block interleaving and / or rate matching, the rate matching including at least one of bit collection, bit selection, and bit trimming. The transceiver unit is configured to transmit the third bit sequence.

[0043] In conjunction with the fifth aspect, in some other implementations of the fifth aspect, the processing unit is further configured to perform a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes block interleaving where the number of rows multiplied by the number of columns of the matrix is ​​less than the length of the third bit sequence. The number of columns in the block interleaving matrix is ​​less than 32, wherein the number of columns in the block interleaving matrix is ​​4, 8, or 16. The transceiver unit is further configured to transmit the processed third bit sequence.

[0044] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the transceiver unit is further configured to transmit first information, which is used to indicate that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0045] Sixthly, a convolutional coding apparatus is provided. It includes: a transceiver unit for receiving a third bit sequence, which is a bit sequence to be decoded; and a processing unit for decoding the third bit sequence based on the last N bits of a second bit sequence to obtain a second bit sequence, which is the decoded bit sequence. The second bit sequence includes M bits, and the N bits are the last N bits of the second bit sequence. A network device determines a first bit sequence based on the second bit sequence, which is the original bit sequence. The first N bits of the first bit sequence correspond one-to-one with the last N bits of the second bit sequence, and any bit in the first N bits of the first bit sequence has the same value as the bit corresponding to any bit in the last N bits of the second bit sequence, where M and N are positive integers, and M is greater than N.

[0046] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the N+1 to Mth bits of the first bit sequence are the first MN bits of the second bit sequence.

[0047] In conjunction with the sixth aspect, in some implementations of the sixth aspect, N equals 6.

[0048] In conjunction with the sixth aspect, in some implementations of the sixth aspect, a processing unit is used to obtain the last N bits of the second bit sequence without performing the first processing on the third bit sequence. The first processing includes deblocking and / or derate matching, and the rate matching includes at least one of bit collection, bit selection, and bit pruning.

[0049] In conjunction with the sixth aspect, in some other implementations of the sixth aspect, a second processing is performed on the third bit sequence to obtain a processed third bit sequence. This second processing includes block interleaving where the number of rows multiplied by the number of columns of the solution matrix is ​​less than the length of the third bit sequence. The number of columns in the block interleaving matrix is ​​less than 32, and the number of columns in the block interleaving matrix can be 4, 8, or 16. The last N bits of the second bit sequence are determined based on the processed third bit sequence.

[0050] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the transceiver unit is further configured to receive first information, which indicates that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; and performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0051] A seventh aspect provides a convolutional coding apparatus. It includes: a processing unit for generating a first bit sequence, which is an original bit sequence comprising M bits; determining a second bit sequence based on the first bit sequence, which is a bit sequence to be encoded; the second bit sequence comprising M+N bits, wherein N bits are predefined bits, and the values ​​of the N bits are not all equal to 0, and the last N bits of the second bit sequence are predefined bits, where M and N are positive integers; performing convolutional coding on the second bit sequence using a convolutional encoder to obtain a third bit sequence, which is the encoded bit sequence; the initial value of the shift register of the convolutional encoder is equal to the value of the last N bits of the second bit sequence, and the convolutional encoder includes N shift registers; and a transceiver unit for transmitting the third bit sequence.

[0052] In conjunction with the seventh aspect, in some implementations of the seventh aspect, the first M bits of the second bit sequence are the M bits of the first bit sequence.

[0053] In conjunction with the seventh aspect, in some implementations of the seventh aspect, a predefined N bits carry second information, which includes information about the load type, service type, or channel type.

[0054] In conjunction with the seventh aspect, in some implementations of the seventh aspect, N equals 6.

[0055] In conjunction with the seventh aspect, in some implementations of the seventh aspect, the processing unit is further configured to not perform the first processing on the third bit sequence, the first processing including block interleaving and / or rate matching, the rate matching including at least one of bit collection, bit selection, and bit trimming; the transceiver unit is configured to transmit the third bit sequence.

[0056] In conjunction with the seventh aspect, in some other implementations of the seventh aspect, the processing unit is further configured to perform a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes block interleaving where the number of rows multiplied by the number of columns of the matrix is ​​less than the length of the third bit sequence. The number of columns in the block-interleaved matrix is ​​less than 32, wherein the number of columns in the block-interleaved matrix is ​​4, 8, or 16. The transceiver unit is configured to transmit the processed third bit sequence.

[0057] In conjunction with the seventh aspect, in some implementations of the seventh aspect, the transceiver unit is further configured to transmit first information, which indicates that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0058] Eighthly, a convolutional coding apparatus is provided. It includes: a transceiver unit for receiving a third bit sequence, which is a bit sequence to be decoded; a processing unit for determining the last N bits of a second bit sequence based on the third bit sequence; decoding the third bit sequence based on the last N bits of the second bit sequence to obtain a second bit sequence, which is the decoded bit sequence. The second bit sequence includes M+N bits, where N bits are predefined bits, and the values ​​of the N bits are not all equal to 0. The last N bits of the second bit sequence are predefined bits, and M and N are positive integers; and determining a first bit sequence based on the second bit sequence, which is the original bit sequence and includes M bits.

[0059] In conjunction with the eighth aspect, in some implementations of the eighth aspect, the first M bits of the second bit sequence are the M bits of the first bit sequence.

[0060] In conjunction with the eighth aspect, in some implementations of the eighth aspect, a predefined N bits carry second information, which includes information about the load type, information about the service type, or information about the channel type.

[0061] In conjunction with the eighth aspect, in some implementations of the eighth aspect, N equals 6.

[0062] In conjunction with the eighth aspect, in some implementations of the eighth aspect, a processing unit is used to obtain N bits from the third bit sequence without performing the first processing. The first processing includes deblocking and / or derate matching, and the rate matching includes at least one of bit collection, bit selection, and bit pruning.

[0063] In conjunction with the eighth aspect, in some implementations of the eighth aspect, a processing unit is used to perform a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes block interleaving where the number of rows multiplied by the number of columns of the solution matrix is ​​less than the length of the third bit sequence. The number of columns in the block interleaving matrix is ​​less than 32, wherein the number of columns in the block interleaving matrix is ​​4, 8, or 16. The last N bits of the second bit sequence are determined based on the processed third bit sequence.

[0064] In conjunction with the eighth aspect, in some implementations of the eighth aspect, the transceiver unit is further configured to receive first information, which indicates that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; and performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0065] A ninth aspect provides a communication device including a processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices outside the communication device and transmit them to the processor, or to send signals from the processor to other communication devices outside the communication device, the processor being configured to implement the methods in any possible implementation of the first to fourth aspects via logic circuits or execution code instructions.

[0066] In a tenth aspect, a computer-readable storage medium is provided, which stores a computer program or instructions that, when executed, implement the methods in any possible implementations of the first to fourth aspects described above.

[0067] In the eleventh aspect, a computer program product containing instructions is provided, which, when executed, implements the methods in any possible implementations of the first to fourth aspects described above.

[0068] In a twelfth aspect, a computer program is provided, comprising code or instructions that, when executed, implement the methods of any possible implementations of the first to fourth aspects described above.

[0069] In a thirteenth aspect, a chip system is provided, comprising a processor and a memory for implementing the methods of any possible implementations of the first to fourth aspects described above. The chip system is composed of chips and also includes chips and other discrete devices.

[0070] In a fourteenth aspect, a communication system is provided, including the terminal equipment and network equipment described above.

[0071] The terminal device is used to implement the methods of each implementation mode in the first and third aspects mentioned above, and the network device is used to implement the methods of each implementation mode in the second and fourth aspects mentioned above.

[0072] In one possible design, the communication system also includes other devices that interact with the terminal device or network device as provided in the embodiments of this application. Attached Figure Description

[0073] Figure 1 This is a schematic diagram of the communication system 100 to which this application applies.

[0074] Figure 2 This is a schematic diagram of the convolutional code encoder circuit in an LTE system.

[0075] Figure 3 This is a schematic diagram of the process of block interleaving and rate matching after encoding.

[0076] Figure 4 This is an example of a schematic flowchart of the convolutional coding method in this application.

[0077] Figure 5 This is the first schematic diagram of the initial value of the shift register of the convolution encoder provided in the embodiments of this application.

[0078] Figure 6 This is a second schematic diagram showing the initial value of the shift register of the convolution encoder provided in this application embodiment.

[0079] Figure 7 This is a third schematic diagram showing the initial value of the shift register of the convolution encoder provided in this application embodiment.

[0080] Figure 8 This is the fourth schematic diagram of the initial value of the shift register of the convolution encoder provided in the embodiments of this application.

[0081] Figure 9 This is another illustrative flowchart of the convolutional coding method in this application.

[0082] Figure 10 This is the fifth schematic diagram of the initial value of the shift register of the convolution encoder provided in the embodiments of this application.

[0083] Figure 11 This is a schematic diagram of an example of the convolutional coding device provided in this application.

[0084] Figure 12 This is a schematic diagram of an example of the convolutional coding device provided in this application. Detailed Implementation

[0085] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0086] Figure 1 This is a schematic diagram of a communication system 100 applicable to embodiments of this application.

[0087] like Figure 1 As shown, the communication system 100 may include one or more network devices, for example, Figure 1 The network device 101 shown. The communication system 100 may also include one or more terminal devices (also referred to as user equipment (UE)), for example, Figure 1 The terminal devices 102, 103, and 104 shown are examples of such devices. The communication system 100 can support sidelink communication technology, such as sidelink communication between terminal devices 102 and 103, and sidelink communication between terminal devices 102 and 104.

[0088] It should be understood that Figure 1 This is just an illustration; the communication system may also include other network devices, such as core network device 105 and others. Figure 1 The wireless relay equipment and wireless backhaul equipment are not shown in the diagram. The embodiments of this application do not limit the number of network devices and terminal devices included in the mobile communication system.

[0089] The terminal device in this application embodiment can be a passive tag, a semi-passive tag, an active tag, a passive IoT terminal device, a semi-passive terminal device, a semi-passive IoT terminal device, an active IoT terminal device, a terminal device with backscatter capability, an NR terminal device, an NR base station / pole station / micro station / small station, a reader / writer terminal device, etc. The terminal device can also refer to user equipment, access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, wireless communication equipment, user agent, or user device. The terminals in the embodiments of this application may be mobile phones, tablets, computers with wireless transceiver capabilities, virtual reality (VR) terminals, augmented reality (AR) terminals, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical care, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, wearable devices, terminals in 5G networks, or terminals in future evolved networks, etc.

[0090] Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices; they achieve powerful functions through software support, data interaction, and cloud interaction. Broadly defined, wearable smart devices include those with comprehensive functions, large sizes, and the ability to perform complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses. They also include devices focused on a specific application function that require the use of other devices, such as smart bracelets and smart jewelry for vital sign monitoring.

[0091] Furthermore, the terminal device can also be a terminal device in an Internet of Things (IoT) system. The technical characteristic of IoT is connecting objects to networks via communication technology, thereby realizing an intelligent network that enables human-machine interaction and machine-to-machine interaction. This application does not limit the specific form of the terminal device.

[0092] It should be understood that in the embodiments of this application, the terminal device can be a means for implementing the functions of the terminal device, or a means for supporting the terminal device in implementing the functions, such as a chip system, which can be installed in the terminal. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0093] The network device in this application embodiment can be any device with wireless transceiver capabilities. This device includes, but is not limited to: evolved Node B (eNB), home base station (e.g., home evolved node B, or home node B, HNB), base band unit (BBU), access point (AP), wireless relay node, wireless backhaul node, transmission point (TP), or transmission and reception point (TRP) in a wireless fidelity (WIFI) system. It can also be a 5th generation (5G) network device, such as a next-generation node B (gNB) in a new radio (NR) wireless communication system, or a transmission point (TRP or TP), one or a group of antenna panels (including multiple antenna panels) of a base station in a 5G system, or a network node constituting a gNB or transmission point, such as a base band unit (BBU) or a distributed unit (DU).

[0094] In some deployments, a gNB may include a centralized unit (CU) and a dedicated unit (DU). The CU implements some of the gNB's functions, and the DU implements others. For example, the CU handles non-real-time protocols and services, implementing radio resource control (RRC) and packet data convergence protocol (PDCP) layer functions. The DU handles physical layer protocols and real-time services, implementing radio link control (RLC), media access control (MAC), and physical (PHY) layer functions. A gNB may also include an active antenna unit (AAU). The AAU implements some physical layer processing functions, radio frequency processing, and related active antenna functions. Since RRC layer information ultimately becomes PHY layer information, or is derived from PHY layer information, in this architecture, higher-layer signaling, such as RRC layer signaling, can be considered to be sent by the DU, or by the DU+AAU. It is understood that network devices can be one or more of the following: CU nodes, DU nodes, and AAU nodes. Furthermore, a CU can be classified as a network device in the radio access network (RAN) or as a network device in the core network (CN); this application does not impose any limitations on this.

[0095] It should be understood that in the embodiments of this application, the network device can be a means for implementing the functions of the network device, or a means that enables the network device to implement the functions, such as a chip system, which can be installed in the network device.

[0096] The technical solutions of this application can be applied to service scenarios such as backscatter communication and passive IoT communication in NR communication systems, as well as various communication systems, such as: LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, 5G systems, vehicle-to-X (V2X) systems, where V2X can include vehicle-to-network (V2N), vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), vehicle-to-pedestrian (V2P), long-term evolution-vehicle (LTE-V) technology for vehicle-to-everything (V2V) communication, vehicle-to-everything (V2V) communication, machine-type communication (MTC), Internet of Things (IoT), long-term evolution-machine (LTE-M) technology for machine-to-machine (M2M) communication, and device-to-device (D2M) communication. Device-to-device (D2D) and other or future evolutionary communication systems, such as the 6th generation (6G) system.

[0097] In this process, the downlink transmits information from NR base stations / pole stations / micro stations / small stations or NR terminal devices or readers to passive terminal devices / passive IoT terminal devices / semi-passive terminal devices / semi-passive IoT terminal devices / terminal devices with backscatter capability, while the uplink transmits information from passive terminal devices / passive IoT terminal devices / semi-passive terminal devices / semi-passive IoT terminal devices / terminal devices with backscatter capability to NR base stations / pole stations / micro stations / small stations or NR terminal devices or readers.

[0098] With the increasing application of 5G NR MTC and IoT communication, the number of connected IoT devices is growing daily. Therefore, the industry's demand for reduced cost and power consumption of IoT devices is becoming increasingly strong. During the 4G era, 3GPP introduced the NB-IoT system, but NB-IoT terminals still require external power (e.g., batteries) and have the ability to generate local high-frequency local oscillator carriers. Therefore, these terminals can only achieve milliwatt-level power consumption. For the goal of 5G IoT (Internet of Everything), enabling terminal devices to access the 5G network and communicate effectively without continuous external power supply, passively accepting external radio frequency signals as local energy, or using other energy harvesting methods—such as passive / semi-passive terminal power supply methods—is a key focus of current 5G research. This can also be defined as passive IoT or backscatter communication research. In passive IoT systems, there are terminals capable of backscatter communication, which can be traditionally defined as tags, and further classified as passive tags and semi-passive tags. Passive tags or passive reverse communication terminal devices have no power supply equipment / circuit. The terminal device relies solely on receiving the radio frequency signal transmitted downlink from the network device, and obtains a DC voltage through a series of circuits such as filtering circuits to supply power, enabling further demodulation of the downlink signal and reflection of the uplink (modulation) signal. The network device providing the downlink signal can be a base station device (including a series of base station devices such as macro stations / small stations / micro stations / pole stations), or a reader device, a helper device, or a series of network devices that can excite passive / semi-passive terminal devices.

[0099] Due to power consumption and complexity limitations of passive IoT terminal devices / reverse communication terminal devices, the power consumption of these terminals may be limited to a target power consumption of less than 1μW or less than 100μW. Under this target, it is difficult for passive IoT terminal devices to implement complex channel coding, such as computationally complex coding or coding requiring large amounts of memory storage. Therefore, it is necessary to consider implementing simpler channel coding to improve the coverage of passive IoT terminal devices.

[0100] Figure 2 An example of a convolutional code encoder circuit in an LTE system is shown.

[0101] The classic channel coding principle in communication is convolutional coding (CC). In LTE systems, convolutional codes are used for both the physical downlink shared channel (PDCCH) and the NB-IoT downlink control channel (PDSCH). The convolutional codes used in LTE systems are limited to a length of 7 bits, have 6 registers, and a code rate of 1 / 3, meaning 1 bit is encoded into 3 bits. The encoding circuit is as follows... Figure 1 As shown, each path corresponds to a generator polynomial, where the encoded bit value is obtained by XORing several bit values ​​in the six registers with the input bit value. Furthermore, LTE systems use tail-biting convolutional coding (TBCC). The initial state of the TBCC registers is set to the last 6 bits of the bit to be transmitted; thus, the register state returns to the last 6 bits of the bit to be transmitted after encoding, resembling a snake biting its own tail, hence the name tail-biting convolutional code. The number of input bits is defined as K, and the input bit sequence is c0, c1, c2, ..., c K-1 Define the initial state of the register as register s. i If i = 0, 1, ..., 5, then for the tail-biting convolutional code, the initial state s i The value is s i =c K-1-i During convolutional coding, when a new bit is input, the register value is shifted to the right (the value of the last register is discarded), and the previous input bit value is shifted to the right and placed into the first register as its value. As previously defined, the initial state of the register is c. K-1 c K-2 c K-3 c K-6 The first bit c0 of the input bit sequence enters the encoder, and the output encoded bit is d0. (0) d0 (1) and d0 (2) When the second bit c1 of the input bit sequence enters the encoder, the register state is updated to c0, c K-1 c K-2 c K-5 The output encoded bits are d1 (0) d1 (1) and d1 (2) .

[0102] Figure 3 A schematic diagram illustrates the process of block interleaving and rate matching after encoding.

[0103] In existing LTE systems, after generating three output bit sequences using three generator polynomial coding methods, block interleaving and rate matching are required. Rate matching includes bit collection, bit selection, and bit pruning. First, each output bit sequence is interleaved using a block interleaver matrix. Each block interleaver matrix is ​​set to R rows and C columns, where C defaults to 32. The number of bits in the output bit sequence is defined as D. If D is less than R×C, padding (R×CD) bits are added before the output bit sequence, with values ​​set to null. <null>(This can be simply understood as NULL being 0.) This satisfies the requirement for the bit sequence to enter the R×C interleaver for interleaving. After the bit sequence is input row by row into the R×C interleaver, in the LTE system, the block interleaver matrix needs to perform column permutations on the 32 columns of bits. The column permutation pattern is given in Table 5.1.4-2 of the 3rd Generation Partnership Project (3GPP) protocol 36.212, as shown in Table 1 below:

[0104] Table 1 shows the permutation patterns.

[0105]

[0106] After column permutation, the R×C bits are output column-wise. Each output bit sequence undergoes the block interleaving operation described above, resulting in an output bit sequence v after each block interleaving. k (0) v k (1) v k (2) ,like Figure 3 As shown. The bit sequence after output interleaving needs to collect the bits from the three outputs into memory. The bits in the output bit sequence after bit collection are defined as W. k Among them, W k =v k (0) W D+k =v k (1) W 2D+k =v k (2) k = 0, 1, ..., (R × C - 1). This involves concatenating the bit sequences output after the three-way block interleaving. The collected bit sequences are then output to the bit selection and trimming module. When encountering padding before interleaving... <null>, then <null>Bit pruning (also known as puncturing). Specifically, the bits in the output bit sequence after bit selection are defined as e. k If we define the number of output bits after bit selection as E, then the mathematical representation of the bit selection process is as follows:

[0107]

[0108] exist Figure 3 In the coding scheme shown, the convolutional coding used in LTE requires block interleaving and rate matching operations. The interleaving in block interleaving requires three interleavers, each storing R×C bits, and also requires additional matrix column permutation operations. Bit collection requires storing all 3×R×C bits output by the interleavers and performing bit selection of valid bits. <null>Bit pruning operations; for passive terminal devices, rate matching in LTE technology requires significant memory overhead, which low-power, low-complexity passive terminal devices (<1μW) cannot handle. Even if rate matching is not performed after encoding, the following methods can be used... Figure 2 The aforementioned tail-biting convolutional code encoding technique requires that encoding wait until the original information bits have been completely updated with cyclic redundancy check (CRC) bits to obtain a complete bit sequence. Only then can the last 6 bits of the bit sequence be used as the initial state of the shift register in the convolutional encoder before encoding can begin. This makes it difficult to start channel coding quickly, resulting in significant overhead for buffering / storage in low-power passive terminal devices. Consequently, implementing tail-biting convolutional codes, block interleaving, and rate matching in low-power passive terminal devices for LTE presents considerable challenges.

[0109] To address the aforementioned issues, a traditional convolutional coding scheme exists in academia. This scheme eliminates the need for rate matching after convolutional coding. The register is initially set to six specific state values. One bit from the input bit sequence enters the encoder's three generator polynomials, simultaneously outputting three bits. There's no need to collect all the bits from one encoded path for interleaving; the encoded three bits can be sent directly. Then, one bit from the next input bit sequence enters the encoder, and the process repeats. Let w be the number of bits in the output bit sequence. k The bits in the output bit sequence can be represented as: w 3k =d k (0) w 3k+1 =d k (1) w 3k+2 =d k (2) Where k = 0, 1, ..., (k-1). This "encode-as-you-go" approach effectively simplifies the caching / storage overhead of the terminal device. However, because the final state of the register is inconsistent with its initial state, this encoding method is a "non-convergent" encoding method. The code distance between the final encoded codewords is smaller than the code distance between codewords whose final and initial states are consistent, thus significantly reducing the performance of convolutional coding.

[0110] Therefore, this application proposes a convolutional coding method, which aims to reduce the power consumption and complexity of convolutional coding in terminal devices while ensuring certain convolutional coding performance.

[0111] The technical solution of this application will be described in detail below using the interaction between a terminal device and a network device as an example. The terminal device can be... Figure 1 The terminal devices (e.g., terminal device 102, terminal device 103, or terminal device 104) and network devices can be Figure 1 Network device 101 in the middle.

[0112] Figure 4 A schematic flowchart of an example of the convolutional coding method of this application is shown.

[0113] S410, the terminal device generates the first bit sequence.

[0114] The first bit sequence consists of M bits. As an example, and not a limitation, the first bit sequence can be c0, c1, c2, ..., c M-1 In this sequence, the last L bits of the first M bits are CRC bits, where L = 8, 16, or 24. That is, c0, c1, c2, ..., c... M-L This is the bit sequence before adding CRC bits, where L CRC bits are c. M-L+1 c M-L+2 c M-L+3 c M-1 .

[0115] In the embodiments of this application, a bit sequence can also be referred to as a bit stream. For ease of description, this application will uniformly refer to it as a bit sequence.

[0116] S420, the terminal device determines the second bit sequence based on the first bit sequence. The second bit sequence includes M bits. The last N bits of the second bit sequence correspond one-to-one with the first N bits of the first bit sequence. Any bit in the last N bits of the second bit sequence has the same value as any bit in the first N bits that corresponds to it. Here, M and N are positive integers, and M is greater than N.

[0117] As one possible implementation, the last N bits of the second bit sequence correspond one-to-one with the N consecutive bits starting from a predefined position in the first (MLN) bits of the first bit sequence. Any bit in the last N bits of the second bit sequence has the same value as the N consecutive bits starting from a predefined position in the first (MLN) bits of the first bit sequence, where M and N are positive integers, and M is greater than (L+N).

[0118] Optionally, N can be 6 or other values, which are not limited in this application.

[0119] Optionally, the first MN bits of the second bit sequence are the (N+1)th to (M)th bits of the first bit sequence.

[0120] As an example, when N equals 6, the second bit sequence can be c6, c7, c8, ..., c M-1 The second bit sequence can be c0, c1, c2, c3, c4, c5; or, the second bit sequence can be c6, c7, c8, ..., c M-1 c5, c4, c3, c2, c1, c0; or, the second bit sequence could be c6, c7, c8, ..., c M-1 , c5, c3, c1, c2, c4, c0.

[0121] This approach avoids disrupting the order of bits other than the first N bits in the original bit sequence and does not increase the complexity of convolutional coding in low-power terminal devices.

[0122] As one possible implementation, the last N bits of the second bit sequence correspond one-to-one with the N consecutive bits starting from a predefined position in the first (MLN) bits of the first bit sequence. The predefined position is j, where j is an integer greater than or equal to 0 and less than or equal to (MLN). The second bit sequence can be c6, c7, c8, ..., c j-1 c j+6 c M-1 ,c j+5 c j+4 c j+3 c j+2 c j+1 c j .

[0123] S430, the terminal device performs convolutional encoding on the second bit sequence to obtain the third bit sequence. The initial value of the shift register of the convolutional encoder is equal to the value of the last N bits of the second bit sequence. The convolutional encoder includes N shift registers.

[0124] Specifically, the initial values ​​of the shift registers in the convolutional encoder include the values ​​of N shift registers, with the value of the i-th shift register being s. i Let i be a natural number less than N, and let the last N bits of the second bit sequence be x. M-N+i The first N bits of the first bit sequence have a value of c. i , where s i equals c i And x M-N+i equals c N-1-i Or, s i equals c N-1-i And x M-N+i equals c i .

[0125] Optionally, the initial values ​​of the shift registers of the convolution encoder include the values ​​of N shift registers, where the value of the i-th shift register is s. i Let i be a natural number less than N, and let the last N bits of the second bit sequence be x. M+N-i In the first bit sequence, the N consecutive bits starting from a predefined position in the first MLN bits take the value c. j+i , where s i equals c j+i And x M+N-i equals c j+N-1-i Or, s i Equals C N-1-i And x M+N-i equals c j+i .

[0126] The initial value of the shift register of the convolution encoder can also be referred to as the initial state of the shift register of the convolution encoder.

[0127] As an example, such as Figure 5 As shown, when N equals 6, the initial values ​​of the shift register of the convolution encoder can be set to c0, c1, c2, c3, c4, c5. Then, the second bit sequence can be c6, c7, c8, ..., c M-1 c0, c1, c2, c3, c4, c5, which are the 6 bits at the beginning of the first bit sequence, are moved to the end and arranged in ascending order of their numbers to obtain the second bit sequence.

[0128] As an example, such as Figure 6 As shown, when N equals 6, the initial values ​​of the shift register of the convolutional encoder can be set to c5, c4, c3, c2, c1, c0. Then, the second bit sequence can be c6, c7, c8, ..., c M-1 c5, c4, c3, c2, c1, c0, which are the 6 bits at the beginning of the first bit sequence, are moved to the end and arranged in descending order of their sequence numbers to obtain the second bit sequence.

[0129] As an example, such as Figure 7 As shown, when N equals 6 and j equals 2, the initial values ​​of the shift register of the convolution encoder can be set to c7, c6, c5, c4, c3, c2. Then, the second bit sequence can be c0, c1, ..., c8, c9, c 10 c M-1 c2, c3, c4, c5, c6, c7 are the six bits that start from the third bit c2 in the first bit sequence, moved to the end, and arranged in ascending order of their numbers to obtain the second bit sequence.

[0130] As an example, such as Figure 8 As shown, when N equals 6 and j equals 2, the initial values ​​of the shift register of the convolution encoder can be set to c2, c3, c4, c5, c6, c7. Then, the second bit sequence can be c0, c1, ..., c8, c9, c 10 c M-1 c7, c6, c5, c4, c3, c2, which are the 6 bits starting from the 3rd bit c2 in the first bit sequence, are moved to the end and arranged in descending order of their sequence numbers to obtain the second bit sequence.

[0131] It should be understood that Figures 5 to 8 The examples shown do not represent all possible situations of the embodiments of this application. Based on the technical solutions disclosed in this application, those skilled in the art can set the initial value of the shift register of the convolution encoder to N (e.g., 6) bits at the beginning position of the first bit sequence. The order of these N (e.g., 6) bits can be arbitrarily arranged. It is only necessary to ensure that the N (e.g., 6) bits at the beginning position of the first bit sequence are moved to the end and arranged in the same order to obtain the second bit sequence.

[0132] Optionally, based on the technical solutions disclosed in this application, those skilled in the art can set the initial value of the shift register of the convolution encoder to a consecutive N (e.g., 6) bits starting from a predefined position in the first (MLN) bits. The order of these N (e.g., 6) bits can be arbitrarily arranged, as long as it is ensured that the N (e.g., 6) bits starting from the predefined position of the first bit sequence are moved to the end, and the initial value of the shift register and the values ​​of the N bits are equal.

[0133] This method moves the first N bits of the first bit sequence to the end of the second bit sequence and sends them last, arranging them in ascending or descending order of sequence number. Convolutional coding has the characteristic of keeping the register's end state consistent with its initial state, ensuring the performance of convolutional coding in certain low-power terminal devices and effectively improving the coverage performance of communication between low-power terminal devices and network devices.

[0134] S440, the terminal device sends the third bit sequence.

[0135] One possible implementation is that the terminal device does not perform any first processing on the third bit sequence before sending it. The first processing includes block interleaving and rate matching, where rate matching includes at least one of bit collection, bit selection, and bit pruning. By sending the third bit sequence without any processing, the cache / storage overhead of the low-power terminal device using convolutional coding is effectively reduced, without increasing the power consumption of the low-power terminal device using convolutional coding.

[0136] As another possible implementation, before sending the third bit, the terminal device performs a second processing on the third bit sequence to obtain a processed third bit sequence. This second processing includes block interleaving where the number of rows multiplied by the number of columns in the matrix is ​​less than the length of the third bit sequence. The number of columns in the block interleaving matrix is ​​less than 32, and can be 4, 8, or 16. This block interleaving can also be called sub-block interleaving. The number of rows multiplied by the number of columns in the block interleaving equals the length of the sub-bit sequence. The third bit consists of P sub-bit sequences, where P is greater than or equal to 1. For example, if the length of the third bit sequence is 128, it can be divided into P = 4 sub-bit sequences, each with a length of 32. In this case, the block interleaving matrix can be set so that the number of rows multiplied by the number of columns equals the length of the sub-bit sequence; for example, the number of rows can be set to 4 and the number of columns can be set to 8. The terminal interleaves each sub-bit sequence in this block interleaving manner and then collects the bits to obtain the processed third bit sequence. The terminal device then sends the processed third bit sequence. By processing the third bit before sending the third bit sequence, this approach slightly increases the buffering / storage overhead of convolutional coding in low-power terminal devices, which helps improve the performance of convolutional coding and effectively enhances the coverage performance of communication between low-power terminal devices and network devices.

[0137] Optionally, the terminal device may also send first information to the network device. This first information indicates that the terminal device is a terminal device with a first capability. The first capability includes at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; and performing convolutional encoding on the first bit sequence using a convolutional encoder. Specifically, in this embodiment, terminal devices can be classified according to their capabilities, such as terminal devices with the first capability described above, or terminal devices with the second capability. Terminal devices with the first capability have lower capabilities, lower power consumption and storage levels, and are capable of encoding using the convolutional encoding method described in this application, but not capable of encoding using M-bit block interleaving and rate matching or a convolutional encoder. Terminal devices with the second capability have higher capabilities, higher power consumption and storage levels, and are capable not only of encoding using the convolutional encoding method described in this application, but also of encoding using M-bit block interleaving and rate matching or a convolutional encoder. Optionally, the terminal device with the second capability also has the ability to encode using methods such as Reed-Muller (RM) code encoding, cyclic redundancy check (CRC) code encoding, repetition encoding, and polar code encoding.

[0138] In this way, network devices can obtain the channel coding capabilities associated with the type of terminal device, and decode the information bits sent by the terminal device according to the different channel coding methods for different types of terminal devices. This enables terminal devices and network devices with different capabilities to complete effective channel coding transmission and reception, effectively improving the coverage performance of communication between different terminal devices and network devices.

[0139] According to the technical solution of this application, there is no need to wait for the original information bits to be added with CRC bits to obtain the complete first bit sequence before starting the convolutional encoder for encoding. This effectively reduces the cache / storage overhead of low-power terminal devices using convolutional encoding, which helps to further reduce the power consumption of low-power terminal devices using convolutional encoding. In addition, convolutional encoding has the characteristic of keeping the register end state consistent with the initial state, which ensures the performance of convolutional encoding in certain low-power terminal devices and effectively improves the coverage performance of communication between low-power terminal devices and network devices.

[0140] Figure 9 Another schematic flowchart of the convolutional coding method of this application is shown.

[0141] S910, the terminal device generates the first bit sequence, which includes M bits.

[0142] As an example, the first bit sequence can be c0, c1, c2, ..., c M-1 In this sequence, the last L bits of the first M bits are CRC bits, where L = 8, 16, or 24. That is, c0, c1, c2, ..., c... M-L This is the bit sequence before adding CRC bits, where L CRC bits are c. M-L+1 c M-L+2 c M-L+3 c M-1 .

[0143] S920, the terminal device determines the second bit sequence based on the first bit sequence. The second bit sequence includes M+N bits, where N bits are predefined bits and the values ​​of the N bits are not all equal to 0. The last N bits of the second bit sequence are predefined bits, and M and N are positive integers.

[0144] In this method, N predefined bits carry second information, which may include payload type information, service type information, or channel type information. This allows information to be carried on predefined bits, avoiding the bit rate loss caused by adding an extra N bits during actual data transmission due to convolutional coding.

[0145] Optionally, the first M bits of the second bit sequence are the same as the first bit sequence. This does not disrupt the bit order in the original bit sequence, which helps reduce the encoding complexity of the terminal device while ensuring the accuracy of information transmission.

[0146] Optional, N equals 6.

[0147] As an example, the second bit sequence can be c0, c1, c2, ..., c M-1 c M c M+1 c M+N-1 When N equals 6, the second bit sequence can be c0, c1, c2, ..., c M-1 c M c M+1 c M+5 .

[0148] S930, the terminal device performs convolutional encoding on the second bit sequence to obtain the third bit sequence. The initial value of the shift register of the convolutional encoder is equal to the value of the last N bits of the second bit sequence. The convolutional encoder includes N shift registers.

[0149] Specifically, such as Figure 8 As shown, the initial value of the shift registers in the convolution encoder includes the values ​​of N shift registers, where the value of the i-th shift register is s. i Where i is a natural number less than N, the initial value of the shift register of the convolution encoder can be s. i =c M+N-i The last N bits of the second bit sequence have a value of x. M+N-i , where s i equals c N-1-i And x M+N-i equals c i .

[0150] As an example, when N equals 6, the initial value of the shift register of the convolution encoder can be c. M c M+1 c M+5 The second bit sequence can be c0, c1, c2, ..., c M-1 c M c M+1 c M+5 .

[0151] S940, the terminal device sends the third bit sequence.

[0152] One possible implementation is that the terminal device does not perform any first processing on the third bit sequence before sending it. The first processing includes block interleaving and rate matching, where rate matching includes at least one of bit collection, bit selection, and bit pruning. By sending the third bit sequence without any processing, the cache / storage overhead of the low-power terminal device using convolutional coding is effectively reduced, without increasing the power consumption of the low-power terminal device using convolutional coding.

[0153] As another possible implementation, before sending the third bit, the terminal device performs a second processing on the third bit sequence to obtain a processed third bit sequence. This second processing includes block interleaving where the number of rows multiplied by the number of columns in the matrix is ​​less than the length of the third bit sequence. The number of columns in the block interleaving matrix is ​​less than 32, and can be 4, 8, or 16. This block interleaving can also be called sub-block interleaving. The number of rows multiplied by the number of columns in the block interleaving equals the length of the sub-bit sequence. The third bit consists of P sub-bit sequences, where P is greater than or equal to 1. For example, if the length of the third bit sequence is 128, it can be divided into P = 4 sub-bit sequences, each with a length of 32. In this case, the block interleaving matrix can be set so that the number of rows multiplied by the number of columns equals the length of the sub-bit sequence; for example, the number of rows can be set to 4 and the number of columns can be set to 8. The terminal interleaves each sub-bit sequence in this block interleaving manner and then collects the bits to obtain the processed third bit sequence. The terminal device then sends the processed third bit sequence. By processing the third bit before sending the third bit sequence, this approach slightly increases the buffering / storage overhead of convolutional coding in low-power terminal devices, which helps improve the performance of convolutional coding and effectively enhances the coverage performance of communication between low-power terminal devices and network devices.

[0154] Optionally, the terminal device may also send first information to the network device. This first information indicates that the terminal device is a terminal device with a first capability, which includes at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; and performing convolutional encoding on the first bit sequence using a convolutional encoder. Specifically, in this embodiment, terminal devices can be classified according to their capabilities, such as terminal devices with the first capability described above, or terminal devices with the second capability. Terminal devices with the first capability have lower capabilities, lower power consumption and storage levels, and are capable of encoding using the convolutional encoding method described in this application, but not capable of encoding using M-bit block interleaving and rate matching or a convolutional encoder. Terminal devices with the second capability have higher capabilities, higher power consumption and storage levels, and are capable not only of encoding using the convolutional encoding method described in this application, but also of encoding using M-bit block interleaving and rate matching or a convolutional encoder. Optionally, terminal devices with the second capability may also be capable of encoding using Reed-Muller RM codes, repetition codes, polar codes, etc. This allows network devices to determine the type of terminal device and decode the information bits sent by the terminal device based on that type, reducing the complexity of decoding for the network device.

[0155] According to the technical solution of this application, there is no need to wait for the original information bits to be added with CRC bits to obtain the complete first bit sequence before starting the convolutional encoder for encoding. This effectively reduces the cache / storage overhead of low-power terminal devices using convolutional encoding, which helps to further reduce the power consumption of low-power terminal devices using convolutional encoding. In addition, convolutional encoding has the characteristic of keeping the register end state consistent with the initial state, which ensures the performance of convolutional encoding in certain low-power terminal devices and effectively improves the coverage performance of communication between low-power terminal devices and network devices.

[0156] It should be understood that the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0157] It should also be understood that, in the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0158] It is understood that the method implemented by the communication device in the above embodiments of this application can also be implemented by a component (such as a chip or circuit) that can be configured inside the communication device.

[0159] The following, combined with Figure 11 and Figure 12 This application provides a detailed description of the convolutional coding apparatus provided in its embodiments. It should be understood that the descriptions of the apparatus embodiments correspond to the descriptions of the method embodiments; therefore, any content not described in detail can be found in the above method embodiments. For brevity, some content is omitted hereafter.

[0160] This application embodiment can divide the transmitting or receiving device into functional modules according to the above method examples. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the division of functional modules according to each function as an example.

[0161] The following, combined with Figure 11 and Figure 12 This application provides a detailed description of the convolutional coding apparatus provided in its embodiments. It should be understood that the descriptions of the apparatus embodiments correspond to the descriptions of the method embodiments; therefore, any content not described in detail can be found in the above method embodiments. For brevity, some content is omitted hereafter.

[0162] This application embodiment can divide the transmitting or receiving device into functional modules according to the above method examples. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the division of functional modules according to each function as an example.

[0163] Figure 11 This is a schematic block diagram of an example of the convolutional coding device 1100 provided in this application. Any device involved in any of the methods 400 and 900 described above, such as terminal devices and network devices, can be... Figure 11 The convolutional coding device shown is used to implement this.

[0164] It should be understood that the convolutional coding device 1100 can be a physical device, a component of a physical device (e.g., an integrated circuit, a chip, etc.), or a functional module within a physical device.

[0165] like Figure 11 As shown, the convolutional coding device 1100 includes one or more processors 1110. Optionally, the processor 1110 can call an interface to implement receiving and transmitting functions. The interface can be a logical interface or a physical interface, without limitation. For example, the interface can be a transceiver circuit, an input / output interface, or an interface circuit. The transceiver circuit, input / output interface, or interface circuit used to implement the receiving and transmitting functions can be separate or integrated together. The aforementioned transceiver circuit or interface circuit can be used for reading and writing code / data, or it can be used for transmitting or transmitting signals.

[0166] Optionally, the interface can be implemented using a transceiver. Optionally, the convolutional coding device 1100 may also include a transceiver 1130. The transceiver 1130 may also be referred to as a transceiver unit, transceiver, transceiver circuit, etc., and is used to implement transceiver functions.

[0167] Optionally, the convolutional coding device 1100 may further include a memory 1120. This application embodiment does not specifically limit the deployment location of the memory 1120; the memory can be integrated into the processor or be independent of the processor. In the case where the convolutional coding device 1100 does not include a memory, the convolutional coding device 1100 only needs to have processing capabilities, and the memory can be deployed in other locations (e.g., a cloud system).

[0168] The processor 1110, memory 1120 and transceiver 1130 communicate with each other through internal connection paths to transmit control and / or data signals.

[0169] It is understood that, although not shown, the convolutional coding device 1100 may also include other devices, such as input devices, output devices, batteries, etc.

[0170] Optionally, in some embodiments, memory 1120 may store execution instructions for performing the methods of the embodiments of this application. Processor 1110 may execute the instructions stored in memory 1120 in conjunction with other hardware (e.g., transceiver 1130) to complete the steps of the method execution described below. For specific working processes and beneficial effects, please refer to the description in the above method embodiments.

[0171] The methods disclosed in this application can be applied to or implemented by processor 1110. Processor 1110 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the instructions from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0172] It is understood that memory 1120 can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0173] Figure 12 This is a schematic block diagram of the convolutional coding device 1200 provided in this application.

[0174] Optionally, the specific form of the convolutional coding device 1200 may be a general-purpose computer device or a chip in a general-purpose computer device; this application embodiment does not limit this. Figure 12 As shown, the convolutional coding device includes a processing unit 1210 and a transceiver unit 1220.

[0175] Specifically, the convolutional coding device 1200 can be any of the devices involved in this application, and can implement the functions that the device can perform. It should be understood that the convolutional coding device 1200 can be a physical device, a component of a physical device (e.g., an integrated circuit, a chip, etc.), or a functional module in a physical device.

[0176] In one possible design, the convolutional coding device 1200 can be a terminal device as described in the above method embodiments, or it can be a chip used to implement the functions of the terminal device as described in the above method embodiments.

[0177] As an example, the communication device is used to perform the above. Figure 4 or Figure 7 The actions performed by the terminal device.

[0178] When execution Figure 4 When the terminal device performs an action, the processing unit 1210 executes S410, S420 and S430, and the transceiver unit 1220 executes S440.

[0179] For example, processing unit 1210 is used to generate a first bit sequence; determine a second bit sequence based on the first bit sequence, the second bit sequence including M bits, the last N bits of the second bit sequence corresponding one-to-one with the first N bits of the first bit sequence, and any bit in the last N bits of the second bit sequence having the same value as any bit in the first N bits that corresponds to it, where M and N are positive integers, and M is greater than N; perform convolution encoding on the second bit sequence using a convolution encoder to obtain a third bit sequence, the initial value of the shift register of the convolution encoder being equal to the value of the last N bits of the second bit sequence, the convolution encoder including N shift registers; and transceiver unit 1220 is used for the third bit sequence.

[0180] Optionally, the first MN bits of the second bit sequence are the (N+1)th to Mth bits of the first bit sequence. Optionally, the initial value of the shift registers of the convolutional encoder includes the values ​​of N shift registers, where the value of the i-th shift register is s. i Let i be a natural number less than N, and let the last N bits of the second bit sequence be x. M-N+i The first N bits of the first bit sequence have a value of c. i , where s i equals c i And x M-N+i equals c N-1-i Or, s i equals c N-1-i And x M-N+i equals c i .

[0181] Optional, N equals 6.

[0182] Optionally, the processing unit 1210 is further configured not to perform the first processing on the third bit sequence; the transceiver unit 1220 is further configured to transmit the third bit sequence. The first processing includes block interleaving and / or rate matching, and rate matching includes at least one of bit collection, bit selection, and bit trimming.

[0183] Optionally, the processing unit 1210 is further configured to perform a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes performing block interleaving where the number of rows multiplied by the number of columns of the matrix is ​​less than the length of the third bit sequence. The number of columns of the block interleaving matrix is ​​less than 32, wherein the number of columns of the block interleaving matrix is ​​4, 8, or 16. The transceiver unit 1220 is further configured to transmit the processed third bit sequence.

[0184] Optionally, the transceiver unit 1220 is further configured to transmit first information, which indicates that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0185] When execution Figure 9 When the terminal device performs an action, the processing unit 1210 executes S910, S920 and S930, and the transceiver unit 1220 executes S940.

[0186] For example, processing unit 1210 is used to generate a first bit sequence, which includes M bits; determine a second bit sequence based on the first bit sequence, which includes M+N bits, where N bits are predefined bits and their values ​​are not all equal to 0, and the last N bits of the second bit sequence are predefined bits, where M and N are positive integers; perform convolution encoding on the second bit sequence using a convolution encoder to obtain a third bit sequence, where the initial value of the shift register of the convolution encoder is equal to the value of the last N bits of the second bit sequence, and the convolution encoder includes N shift registers; and transceiver unit 1220 is used to transmit the third bit sequence.

[0187] Optionally, the first M bits of the second bit sequence are the M bits of the first bit sequence.

[0188] Optionally, a predefined N bits can be used to carry second information, which may include payload type information, service type information, or channel type information.

[0189] Optional, N equals 6.

[0190] Optionally, the processing unit 1210 is further configured to not perform the first processing on the third bit sequence, the first processing including block interleaving and / or rate matching, the rate matching including at least one of bit collection, bit selection, and bit trimming; the transceiver unit 1220 is configured to transmit the third bit sequence.

[0191] Optionally, the processing unit 1210 is further configured to perform a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes block interleaving that is less than the length of the third bit sequence. The number of columns in the block interleaving is less than 32, wherein the number of columns in the block interleaving is 4, 8, or 16. The transceiver unit is configured to transmit the processed third bit sequence.

[0192] Optionally, the transceiver unit 1220 is further configured to transmit first information, which indicates that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0193] It should also be understood that when the convolutional coding device 1200 is a terminal device, the transceiver unit 1220 in the convolutional coding device 1200 can be implemented through a communication interface (such as a transceiver or input / output interface), and the processing unit 1210 in the convolutional coding device 1200 can be implemented through at least one processor, for example, corresponding to... Figure 11 The processor 1110 is shown in the figure.

[0194] Optionally, the convolutional coding device 1200 may further include a storage unit, which can be used to store instructions or data. The processing unit can call the instructions or data stored in the storage unit to perform the corresponding operation.

[0195] It should be understood that the specific process of each unit performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0196] In another possible design, the convolutional coding device 1200 can be a network device in the above method embodiment, or it can be a chip used to implement the functions of the network device in the above method embodiment.

[0197] As an example, the communication device is used to perform the above. Figure 4 or Figure 9 The actions performed by network devices, for example, when the communication device is used to perform... Figure 4 When the network device performs the action, the transceiver unit 1220 is used to receive the third bit sequence; the processing unit 1210 is used to decode the third bit sequence according to the last N bits of the second bit sequence to obtain the second bit sequence, the second bit sequence includes M bits, and the N bits are the last N bits of the second bit sequence; the network device determines the first bit sequence according to the second bit sequence, the first N bits of the first bit sequence correspond one-to-one with the last N bits of the second bit sequence, and any bit in the first N bits of the first bit sequence has the same value as the bit that corresponds one-to-one with any bit in the last N bits of the second bit sequence, where M and N are positive integers, and M is greater than N.

[0198] Optionally, the N+1 to Mth bits of the first bit sequence are the first MN bits of the second bit sequence.

[0199] Optional, N equals 6.

[0200] Optionally, the processing unit 1210 is used to not perform the first processing on the third bit sequence, and to obtain the last N bits of the second bit sequence based on the third bit sequence. The first processing includes deblocking and / or derate matching, and the rate matching includes at least one of bit collection, bit selection, and bit pruning.

[0201] Optionally, the third bit sequence is subjected to a second processing to obtain a processed third bit sequence. The second processing includes deinterleaving blocks shorter than the length of the third bit sequence (or writing M), where the number of columns in the block interleaving is less than 32, and the number of columns in the block interleaving is 4, 8, or 16. The last N bits of the second bit sequence are determined based on the processed third bit sequence.

[0202] Optionally, the transceiver unit 1220 is further configured to receive first information, which indicates that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0203] For example, when the communication device is used to perform Figure 9 When the network device performs the following actions, the transceiver unit 1220 is used to receive the third bit sequence; the processing unit 1210 is used to determine the last N bits of the second bit sequence based on the third bit sequence; decode the third bit sequence based on the last N bits of the second bit sequence to obtain the second bit sequence, which includes M+N bits, where N bits are predefined bits and the values ​​of N bits are not all equal to 0, and the last N bits of the second bit sequence are predefined bits, and M and N are positive integers; and determine the first bit sequence based on the second bit sequence, which includes M bits.

[0204] Optionally, the first M bits of the second bit sequence are the M bits of the first bit sequence.

[0205] Optionally, a predefined N bits carry second information, which includes information about the load type, service type, or channel type.

[0206] Optional, N equals 6.

[0207] Optionally, the processing unit 1210 is used to not perform the first processing on the third bit sequence, and to obtain N bits based on the third bit sequence. The first processing includes deblocking and / or derate matching, and the rate matching includes at least one of bit collection, bit selection, and bit pruning.

[0208] Optionally, the processing unit 1210 is used to perform a second processing on the third bit sequence to obtain a processed third bit sequence. The second processing includes deinterleaving blocks shorter than the length of the third bit sequence (or writing the M), wherein the number of columns in the block interleaving is less than 32, and the number of columns in the block interleaving is 4, 8 or 16; and determining the last N bits of the second bit sequence based on the processed third bit sequence.

[0209] Optionally, the transceiver unit 1220 is further configured to receive first information, which indicates that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: not performing block interleaving on the third bit sequence, or performing block interleaving on the third bit sequence; not performing rate matching on the third bit sequence; performing convolutional encoding on the first bit sequence according to a convolutional encoder.

[0210] It should also be understood that when the convolutional coding device 1200 is a network device, the transceiver unit 1220 in the convolutional coding device 1200 can be implemented through a communication interface (such as a transceiver or input / output interface), and the processing unit 1210 in the convolutional coding device 1200 can be implemented through at least one processor, for example, corresponding to... Figure 11 The processor 1110 is shown in the figure.

[0211] Optionally, the convolutional coding device 1200 may further include a storage unit, which can be used to store instructions or data. The processing unit can call the instructions or data stored in the storage unit to perform the corresponding operation.

[0212] It should be understood that the specific process of each unit performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0213] It should also be understood that when the convolutional coding device 1200 is a network device, the transceiver unit 1220 in the convolutional coding device 1200 can be implemented through a communication interface (such as a transceiver or input / output interface), and the processing unit 1210 in the convolutional coding device 1200 can be implemented through at least one processor, for example, corresponding to... Figure 11 The processor 1110 is shown in the figure.

[0214] Optionally, the convolutional coding device 1200 may further include a storage unit, which can be used to store instructions or data. The processing unit can call the instructions or data stored in the storage unit to perform the corresponding operation.

[0215] It should be understood that the specific process of each unit performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0216] Furthermore, in this application, the convolutional coding device 1200 is presented in the form of a functional module. Here, "module" can refer to an application-specific integrated circuit (ASIC), circuit, processor and memory executing one or more software or firmware programs, integrated logic circuits, and / or other devices that can provide the aforementioned functions. In a simple embodiment, those skilled in the art will understand that the device 1200 can employ... Figure 10 The processing unit 1210 can be in the form shown. Figure 11 The processor 1110 shown is used for implementation. Optionally, if Figure 11 The computer device shown includes a memory 1120, and a processing unit 1210 can be implemented using a processor 1110 and a memory 1120. A transceiver unit 1220 can be implemented using... Figure 11 The transceiver 1130 shown is used for implementation. The transceiver 1130 includes receiving and transmitting functions. Specifically, the processor implements this by executing a computer program stored in memory. Optionally, when the device 1200 is a chip, the function and / or implementation process of the transceiver unit 1220 can also be implemented through pins or circuits, etc. Optionally, the memory can be a storage unit within the chip, such as a register or cache, or the storage unit can be a storage unit located outside the chip within a convolutional coding device, such as... Figure 11 The memory 1120 may be a storage unit deployed in other systems or devices, and is not located within the computer device.

[0217] Various aspects or features of this application can be implemented as methods, apparatus, or articles of manufacture using standard programming and / or engineering techniques. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical discs (e.g., compact discs (CDs), digital versatile discs (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). Furthermore, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to, various other media capable of storing, containing, and / or carrying instructions and / or data.

[0218] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: a computer program or a set of instructions, which, when executed on a computer, causes the computer to perform... Figure 4 and Figure 9 The method of any one of the embodiments shown.

[0219] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing a program or a set of instructions, which, when executed on a computer, causes the computer to perform... Figure 4 and Figure 9 The method of any one of the embodiments shown.

[0220] According to the method provided in the embodiments of this application, this application also provides a communication system, which includes the aforementioned apparatus or device.

[0221] The terms "component," "module," "system," etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0222] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0223] It should also be understood that the use of designations such as "first" and "second" in the embodiments of this application is only to distinguish different objects, such as different "information", "device", or "unit". The understanding of specific objects and the correspondence between different objects should be determined by their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0224] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0225] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.< / null> < / null> < / null> < / null>

Claims

1. A convolutional coding method, characterized in that, include: The terminal device generates a first bit sequence, which includes M bits; The terminal device determines a second bit sequence based on the first bit sequence. The second bit sequence includes M bits. The last N bits of the second bit sequence correspond one-to-one with the first N bits of the first bit sequence. Any bit in the last N bits of the second bit sequence has the same value as the bit in the first N bits that corresponds to that bit. The first MN bits of the second bit sequence are the (N+1)th to the Mth bits of the first bit sequence, where M and N are positive integers, and M is greater than N. The terminal device performs convolutional encoding on the second bit sequence according to the convolutional encoder to obtain a third bit sequence. The initial value of the shift register of the convolutional encoder is equal to the value of the last N bits of the second bit sequence. The convolutional encoder includes N shift registers. The terminal device transmits the third bit sequence without performing the first processing, wherein the first processing includes block interleaving.

2. The method according to claim 1, characterized in that, The initial value of the shift register of the convolutional encoder includes the values ​​of the N shift registers, where the value of the i-th shift register is... Where i is a natural number less than N, and the last N bits of the second bit sequence have the following values: The first N bits of the first bit sequence are... ,in, The equal And the equal ;or, The equal And the equal .

3. The method according to any one of claims 1 to 2, characterized in that, The value of N is 6.

4. The method according to any one of claims 1 to 3, characterized in that, The first process further includes rate matching, which includes at least one of bit collection, bit selection, and bit pruning.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: The terminal device sends first information, the first information indicating that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: No block interleaving is performed on the third bit sequence; No rate matching is performed on the third bit sequence.

6. A convolutional coding method, characterized in that, include: The network device receives a third bit sequence, and the network device does not perform the first processing on the third bit sequence, the first processing including deblocking and interleaving; The network device decodes the third bit sequence to obtain a second bit sequence, which includes M bits; The network device determines a first bit sequence based on the second bit sequence. The first bit sequence includes M bits. The first N bits of the first bit sequence correspond one-to-one with the last N bits of the second bit sequence. Any bit in the first N bits of the first bit sequence has the same value as the bit in the last N bits of the second bit sequence that corresponds to that bit. The (N+1)th to Mth bits of the first bit sequence are the first MN bits of the second bit sequence, where M and N are positive integers, and M is greater than N.

7. The method according to claim 6, characterized in that, The value of N is 6.

8. The method according to any one of claims 6 to 7, characterized in that, The first process further includes rate matching, which includes at least one of bit collection, bit selection, and bit pruning.

9. The method according to any one of claims 6 to 8, characterized in that, The method further includes: The network device receives first information, which indicates that the terminal device is a terminal device with a first capability, the first capability including at least one of the following: No block interleaving is performed on the third bit sequence; No rate matching is performed on the third bit sequence.

10. A communication device, characterized in that, include: Memory, used to store computer instructions; A processor for executing computer instructions stored in the memory, causing the communication device to perform the method as described in any one of claims 1 to 5, or... This causes the communication device to perform the method as described in any one of claims 6 to 9.

11. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a communication device, causes the method as described in any one of claims 1 to 9 to be performed.

12. A computer program product containing instructions, characterized in that, When it is run on a computer, it causes the method as described in any one of claims 1 to 9 to be performed.

13. A chip system, characterized in that, include: A processor for retrieving and executing computer programs or instructions from memory, causing a communication device on which the chip system is installed to implement the method as described in any one of claims 1 to 9.

14. A communication method, characterized in that, include: The terminal device generates a first bit sequence, which includes M bits. A second bit sequence is determined based on the first bit sequence, also including M bits. The last N bits of the second bit sequence correspond one-to-one with the first N bits of the first bit sequence. Any one of the last N bits of the second bit sequence has the same value as the bit that corresponds to that one-to-one bit in the first N bits of the first bit sequence. The (N+1)th to Mth bits of the first bit sequence are the first MN bits of the second bit sequence, where M and N are positive integers, and M is greater than N. A third bit sequence is obtained by convolutionally encoding the second bit sequence using a convolution encoder. The initial value of the shift register of the convolution encoder is equal to the value of the last N bits of the second bit sequence. The convolution encoder includes N shift registers. The terminal device transmits the third bit sequence without performing the first processing, where the first processing includes block interleaving. The network device receives the third bit sequence, and instead of performing the first processing on the third bit sequence, the network device decodes the third bit sequence to obtain the second bit sequence. The network device determines the first bit sequence based on the second bit sequence.

15. The communication method according to claim 14, characterized in that, The initial value of the shift register of the convolutional encoder includes the values ​​of the N shift registers, where the value of the i-th shift register is... Where i is a natural number less than N, and the last N bits of the second bit sequence have the following values: The first N bits of the first bit sequence are... ,in, The equal And the equal ;or, The equal And the equal .

16. A convolutional coding system, characterized in that, It includes a terminal device and a network device, wherein the terminal device is used to perform the method as described in any one of claims 1 to 5, and the network device is used to perform the method as described in any one of claims 6 to 9.

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