Memory structure

Abstract

A memory structure includes a substrate, a word line structure, a bit line contact, and a bit line. The substrate has a trench. The word line structure is disposed in the trench of the substrate. The word line structure includes a word line, a gate dielectric layer, and a cap layer. The word line is disposed in the trench. The gate dielectric layer is disposed between the word line and the substrate. The cap layer covers the word line. The cap layer includes a first material film, and a dielectric constant of the first material film is lower than a dielectric constant of silicon nitride. The bit line contact is disposed on a portion of the trench and a portion of the cap layer. The bit line is disposed over the bit line contact and is electrically connected with the bit line contact. The use of a low dielectric constant material to form the first material film of the cap layer can reduce the parasitic capacitance of the bit line, can reduce gate-induced drain leakage, and can increase the signal margin of the memory structure during operation.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure, and more particularly to a memory structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) elements are random access memory elements that store digital bit information in individual capacitors within a memory circuit. Generally, DRAM memory cells consist of capacitors and transistors arranged in an array. Vertical transistors have been developed.

[0003] As memory devices become increasingly integrated, parasitic capacitance and leakage current degrade their performance. For example, bit-line parasitic capacitance affects the signal margin of dynamic random access memory during operation due to charge-sharing effects. Therefore, a new structure is needed to reduce the parasitic capacitance and leakage current of memory devices. Summary of the Invention

[0004] Therefore, one object of this disclosure is to provide a memory structure in which a cover layer of the word line structure is formed using a low dielectric constant material, thereby reducing the parasitic capacitance of the bit lines and reducing the gate-induced drain current (GIDL), thereby increasing the signal margin of the memory structure during operation.

[0005] According to the above-mentioned objectives of this disclosure, a memory structure is proposed. This memory structure includes a substrate, a word line structure, bit line contacts, and bit lines. The substrate has trenches. The word line structure is disposed in the trenches of the substrate. The word line structure includes word lines, a gate dielectric layer, and a capping layer. The word lines are disposed in the trenches. The gate dielectric layer is disposed between the word lines and the substrate. The capping layer covers the word lines. The capping layer includes a first material thin film, and the dielectric constant of the first material thin film is lower than that of silicon nitride. Bit line contacts are disposed on a portion of the trenches and a portion of the capping layer. Bit lines are disposed above the bit line contacts and are electrically connected to the bit line contacts.

[0006] According to one embodiment of the present disclosure, the character line includes a first layer and a second layer located on the first layer, and the first layer and the second layer are made of different materials.

[0007] According to one embodiment of the present disclosure, the material of the first layer comprises a metal, and the material of the second layer comprises a semiconductor.

[0008] According to one embodiment of the present disclosure, the material of the first layer comprises tungsten, and the material of the second layer comprises polycrystalline silicon.

[0009] According to one embodiment of the present disclosure, the aforementioned gate dielectric layer conformally covers the bottom and side surfaces of the trench.

[0010] According to one embodiment of the present disclosure, the first material film of the aforementioned cover layer comprises silicon oxide.

[0011] According to one embodiment of the present disclosure, the aforementioned cover layer further includes a second material film disposed on the first material film, wherein the dielectric constant of the second material film is different from that of the first material film.

[0012] According to one embodiment of the present disclosure, the dielectric constant of the second material film is greater than that of the first material film.

[0013] According to one embodiment of this disclosure, the aforementioned second material film comprises silicon nitride.

[0014] According to one embodiment of the present disclosure, the thickness of the first material film is more than 20% of the thickness of the cover layer.

[0015] According to one embodiment of this disclosure, the first material film extends at least from the side of the bit line contact beyond the bottom surface of the bit line contact.

[0016] According to one embodiment of the present disclosure, the memory structure further includes an air gap disposed in the cover layer and adjacent to the side of the bit line contact, wherein the bottom of the air gap is lower than the bottom surface of the bit line contact.

[0017] According to the above-mentioned objectives of this disclosure, a memory structure is proposed. This memory structure includes a substrate, a word line structure, an isolation layer, bit line contacts, and bit lines. The substrate has trenches. The word line structure is disposed in the trenches of the substrate. The word line structure includes word lines, a gate dielectric layer, and a capping layer. The word lines are disposed in the trenches. The gate dielectric layer is disposed between the word lines and the substrate. The capping layer is disposed in the trenches and covers the word lines. The capping layer includes a first material film and a second material film disposed on the first material film, and the dielectric constant of the first material film is different from the dielectric constant of the second material film. The isolation layer is disposed on the capping layer and the gate dielectric layer. The bit line contacts are disposed in the isolation layer and on a portion of the trenches and a portion of the capping layer. The bit lines are disposed above the bit line contacts and are electrically connected to the bit line contacts.

[0018] According to one embodiment of the present disclosure, the character line includes a first layer and a second layer located on the first layer, and the first layer and the second layer are made of different materials.

[0019] According to one embodiment of the present disclosure, the material of the first layer comprises tungsten, and the material of the second layer comprises polycrystalline silicon.

[0020] According to one embodiment of the present disclosure, the dielectric constant of the first material film is lower than that of the second material film.

[0021] According to one embodiment of the present disclosure, the thickness of the first material film is more than 20% of the thickness of the cover layer.

[0022] According to one embodiment of this disclosure, the first material film extends at least from the side of the bit line contact beyond the bottom surface of the bit line contact.

[0023] According to one embodiment of the present disclosure, the memory structure further includes an air gap disposed in the cover layer and adjacent to the side of the bit line contact, wherein the bottom of the air gap is lower than the bottom surface of the bit line contact.

[0024] According to one embodiment of the present disclosure, the aforementioned air gap extends from the side of the isolation layer along the bit line contact beyond the bottom surface of the bit line contact. Attached Figure Description

[0025] The above and other objects, features, advantages, and embodiments of this disclosure can be more fully understood by referring to the following accompanying drawings and reading the following detailed description of the embodiments:

[0026] Figure 1 A partial cross-sectional schematic diagram of a memory structure according to some embodiments of the present disclosure is shown;

[0027] Figure 2 A partial cross-sectional schematic diagram illustrating a memory structure according to some embodiments of the present disclosure; and

[0028] Figure 3 A partial cross-sectional schematic diagram of a memory structure according to some embodiments of the present disclosure is shown. Detailed Implementation

[0029] The embodiments of this disclosure are discussed in detail below. However, it is understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of this disclosure. All embodiments of this disclosure reveal many different features that can be implemented individually or in combination as needed.

[0030] Furthermore, the terms “first,” “second,” and similar terms used herein are not intended to indicate order or sequence, but are used only to distinguish elements or operations described using the same technical terms.

[0031] The spatial relationship between the two components described in this disclosure applies not only to the orientation shown in the accompanying drawings, but also to orientations not shown in the drawings, such as inverted orientations. Furthermore, the terms "connection," "electrical connection," or similar expressions used in this disclosure to refer to the two components are not limited to direct or electrical connections between the two components, but may also include indirect or electrical connections as needed.

[0032] Please refer to Figure 1 , Figure 1 A partial cross-sectional schematic diagram of a memory structure according to some embodiments of the present disclosure is shown. The memory structure 100 may be a dynamic random access memory structure. The memory structure 100 may mainly include a substrate 110, word line structures 120, bit line contacts 130, and bit lines 140. In some embodiments, the memory structure 100 includes a plurality of word line structures 120, a plurality of bit line contacts 130, and a plurality of bit lines 140.

[0033] The substrate 110 may be, for example, a silicon substrate, a silicon-germanium substrate, a gallium arsenide substrate, or a semiconductor-on-insulator (SOI) substrate. The substrate 110 may include one or more channel regions 112. The channel regions 112 may be formed by implanting dopants into the substrate 110. The substrate 110 may have one or more trenches 114. For example, the trenches 114 may be formed by removing a portion of the substrate 110. In some exemplary embodiments, the trenches 114 extend into the channel regions 112.

[0034] The word line structure 120 is disposed in the trench 114 of the substrate 110, thus embedding the word line structure 120 into the substrate 110. For example, the top of the word line structure 120 may be substantially flush with the top of the substrate 110. In some embodiments, the word line structure 120 includes a word line 122, a gate dielectric layer 124, and a capping layer 126. The gate dielectric layer 124 may be formed on the bottom surface 114b and the side surface 114s of the trench 114. For example, the gate dielectric layer 124 may conformally cover the bottom surface 114b and the side surface 114s of the trench 114. The gate dielectric layer 124 may be formed using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The material of the gate dielectric layer 124 may comprise any suitable dielectric material, such as silicon oxide.

[0035] A word line 122 is disposed in a trench 114 on a gate dielectric layer 124, so that the gate dielectric layer 124 is located between the word line 122 and the substrate 110. The word line 122 may fill a portion of the trench 114. The word line 122 may be a single-layer structure or a multi-layer structure. In some embodiments, the word line 122 is a double-function operating line. The word line 122 may include a first layer 122a and a second layer 122b, wherein the second layer 122b is disposed on the first layer 122a, and the first layer 122a and the second layer 122b are made of different materials. In some embodiments, the material of the first layer 122a includes a metal, and the material of the second layer 122b includes a semiconductor. For example, the material of the first layer 122a may include tungsten, and the material of the second layer 122b may include polysilicon. The second layer 122b may be formed of polysilicon having a desired conductivity type. The second layer 122b may be formed of N-type polysilicon. +Polycrystalline silicon is formed. For example, the first layer 122a and the second layer 122b can be formed using chemical vapor deposition or physical vapor deposition techniques.

[0036] A capping layer 126 is disposed on and covers the word line 122. The average dielectric constant of the entire capping layer 126 is less than that of silicon nitride, which is used for capping layers in word line structures of conventional memory architectures. The capping layer 126 may contain at least one material with a dielectric constant less than that of silicon nitride. In some embodiments, the etch selectivity of the capping layer 126 is higher than that of silicon nitride. The capping layer 126 may be a single-layer structure or a multi-layer structure, such as a two-layer structure or a structure containing more than two layers stacked on top of each other.

[0037] exist Figure 1 In the illustrated embodiment, the capping layer 126 is a single-layer structure. Specifically, the capping layer 126 is composed of a first material film, the dielectric constant of which is less than that of silicon nitride. For example, the first material film of the capping layer 126 may comprise silicon oxide, or any suitable dielectric material with a dielectric constant less than that of silicon nitride. In some embodiments, the capping layer 126 may be formed using chemical vapor deposition or physical vapor deposition techniques.

[0038] Bit line contacts 130 are disposed on a portion of trench 114 and a portion of capping layer 126. Bit line contacts 130 are formed of a conductive material, such as silicon. In some embodiments, memory structure 100 further includes an isolation layer 150, wherein the isolation layer 150 is disposed on capping layer 126 and gate dielectric layer 124. Isolation layer 150 is formed of a dielectric material. For example, the material of isolation layer 150 may comprise silicon nitride or any suitable dielectric material. Isolation layer 150 may be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques. Bit line contacts 130 may be formed in isolation layer 150 and on portions of trench 114 and capping layer 126 using techniques such as photolithography, etching, and deposition techniques, such as CVD or PVD.

[0039] Bit line 140 is disposed above bit line contact 130. For example, bit line 140 is disposed on an isolation layer 150 above bit line contact 130. Bit line 140 is electrically connected to bit line contact 130. For example, bit line 140 may contact bit line contact 130. The material of bit line 140 may include metal, polysilicon, or any suitable conductive material. Bit line 140 may be formed using chemical vapor deposition or physical vapor deposition techniques.

[0040] The capping layer 126 of the word line structure 120 is formed of a material with a dielectric constant lower than that of conventional materials, thus reducing the parasitic capacitance of the bit lines and the electric field generated by the bit lines 140, thereby reducing the gate-induced drain current. Therefore, the signal margin of the memory structure 100 during operation can be increased.

[0041] Please refer to Figure 2 , Figure 2 A partial cross-sectional schematic diagram of a memory structure according to some embodiments of the present disclosure is shown. The memory structure 100a of this embodiment is similar in structure to Figure 1 The structure of memory structure 100 is shown. The difference between memory structure 100 and 100a is that the cover layer 128 of the word line structure 120a of memory structure 100a is a double-layer structure.

[0042] In memory structure 100a, the cover layer 128 of word line structure 120a includes a first material film 128a and a second material film 128b, wherein the second material film 128b is disposed on the first material film 128a. The material of the first material film 128a is different from the material of the second material film 128b. Specifically, the first material film 128a and the second material film 128b have different dielectric constants. In some exemplary embodiments, the average dielectric constant of the first material film 128a and the second material film 128b is less than the dielectric constant of silicon nitride.

[0043] In some embodiments, the dielectric constant of the first material film 128a is less than that of the second material film 128b. In such embodiments, the first material film 128a may comprise silicon oxide or any suitable low-dielectric-constant material, and the second material film 128b may comprise silicon nitride. Furthermore, the thickness t of the first material film 128a may be substantially 20% or more of the thickness T of the capping layer 128. For example, the thickness t of the first material film 128a may be substantially 20% to substantially 100% of the thickness T of the capping layer 128. In some exemplary embodiments, the first material film 128a extends at least from the side surface 130s of the bit line contact 130 beyond the bottom surface 130b of the bit line contact 130. Furthermore, the etch selectivity of the first material film 128a may be higher than that of silicon nitride.

[0044] In some specific embodiments, the dielectric constant of the first material film 128a is greater than the dielectric constant of the second material film 128b.

[0045] In embodiments where the capping layer 128 comprises several material films, one or more material films with a low dielectric constant in the capping layer do not need to be placed at the bottom of the capping layer, as long as the average dielectric constant of the capping layer is lower than that of a conventional capping layer in a memory structure.

[0046] Please refer to Figure 3 , Figure 3 A partial cross-sectional schematic diagram of a memory structure according to some embodiments of the present disclosure is shown. The memory structure 100b of this embodiment is similar in structure to Figure 2 The structure of memory structure 100a is shown. The difference between memory structure 100a and 100b is that memory structure 100b also includes an air gap 160.

[0047] In memory structure 100b, an air gap 160 is at least disposed in the cover layer 128 and adjacent to the side surface 130s of the bit line contact 130. In some embodiments, the bottom 160b of the air gap 160 is lower than the bottom surface 130b of the bit line contact 130. In some exemplary embodiments, the air gap 160 extends from the isolation layer 150 along the side surface 130s of the bit line contact 130 beyond the bottom surface 130b of the bit line contact 130. In such embodiments, the etch selectivity of the first material film 128a is greater than that of the dielectric material of the cover layer used in conventional memory structures, allowing the air gap 160 to successfully extend beyond the bottom surface 130b of the bit line contact 130.

[0048] The air gap 160 reduces the dielectric constant of the structure between word line 122 and bit line 140, thereby further reducing the parasitic capacitance of the bit line, reducing the electric field generated by bit line 140, and consequently reducing the drain current induced by the gate. Therefore, the signal margin of memory structure 100b can be increased.

[0049] Although this embodiment uses a cover layer 128 with a double-layer structure as an example, the air gap 160 can also be provided in the memory structure 100. In such an embodiment, please refer to... Figure 1 An air gap 160 is provided at least in the cover layer 126 and adjacent to the bit line contact 130. In some exemplary embodiments, the air gap 160 extends from the isolation layer 150 along the side 130s of the bit line contact 130 beyond the bottom surface 130b of the bit line contact 130.

[0050] As can be seen from the above embodiments, one advantage of this disclosure is that by using a low dielectric constant material to form the cover layer of the word line structure of the memory structure, the parasitic capacitance of the bit line can be reduced, and the drain current caused by the gate can be reduced, thereby increasing the signal margin of the memory structure during operation.

[0051] Although this disclosure has been described in detail above with reference to specific embodiments, the above embodiments are merely illustrative and not intended to limit the scope of this disclosure. It will be apparent to those skilled in the art that various modifications and alterations can be made to this disclosure without departing from its spirit and scope. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0052] [Symbol Explanation]

[0053] 100: Memory Structure

[0054] 100a: Memory Structure

[0055] 100b: Memory Structure

[0056] 110: Substrate

[0057] 112: Passage Area

[0058] 114: Ditch

[0059] 114b: Bottom surface

[0060] 114s: Side view

[0061] 120: Character Line Structure

[0062] 120a: Character Line Structure

[0063] 120b: Character Line Structure

[0064] 122: Character Line

[0065] 122a: First layer

[0066] 122b: Second layer

[0067] 124: Gate dielectric layer

[0068] 126: Covering layer

[0069] 128: Overlay

[0070] 128a: First Material Thin Film

[0071] 128b: Second material thin film

[0072] 130: Bit line contact

[0073] 130b: Bottom surface

[0074] 130s: Side view

[0075] 140: Bit Line

[0076] 150: Isolation layer

[0077] 160: Air gap

[0078] 160b: Bottom

[0079] T: Thickness

[0080] t: thickness.

Claims

1. A memory structure, characterized in that, This memory structure includes: The substrate has grooves; A character line structure is disposed in the trench of the substrate, wherein the character line structure includes: The character line is set in the ditch; A gate dielectric layer is disposed between the character line and the substrate; and A capping layer covering the character line, wherein the capping layer comprises a first material film, and the dielectric constant of the first material film is lower than that of silicon nitride; A bit line contact is disposed on a portion of the trench and a portion of the cover layer, wherein the first material film extends at least from the side of the bit line contact beyond the bottom surface of the bit line contact. A bit line is provided above the bit line contact and is electrically connected to the bit line contact; as well as An air gap is provided in the cover layer and adjacent to the side surface of the bit line contact, wherein the bottom of the air gap is lower than the bottom surface of the bit line contact.

2. The memory structure according to claim 1, characterized in that, The character line includes a first layer and a second layer located on the first layer, and the first layer and the second layer are made of different materials.

3. The memory structure according to claim 2, characterized in that, The first layer contains a metal, and the second layer contains a semiconductor.

4. The memory structure according to claim 2, characterized in that, The first layer contains tungsten, and the second layer contains polycrystalline silicon.

5. The memory structure according to claim 1, characterized in that, The gate dielectric layer conformally covers the bottom and sides of the trench.

6. The memory structure according to claim 1, characterized in that, The first material film of the cover layer contains silicon oxide.

7. The memory structure according to claim 1, characterized in that, The capping layer also includes a second material film disposed on the first material film, the dielectric constant of the second material film being different from that of the first material film.

8. The memory structure according to claim 7, characterized in that, The dielectric constant of the second material film is greater than the dielectric constant of the first material film.

9. The memory structure according to claim 8, characterized in that, The second material film contains silicon nitride.

10. The memory structure according to claim 8, characterized in that, The thickness of the first material film accounts for more than 20% of the thickness of the covering layer.

11. A memory structure, characterized in that, This memory structure includes: The substrate has grooves; A character line structure is disposed in the trench of the substrate, wherein the character line structure includes: The character line is set in the ditch; A gate dielectric layer is disposed between the character line and the substrate; and A cover layer is disposed in the trench and covers the character line, wherein the cover layer comprises a first material film and a second material film disposed on the first material film, and the dielectric constant of the first material film is different from the dielectric constant of the second material film; An isolation layer is disposed on the cover layer and the gate dielectric layer; A bit line contact is disposed in the isolation layer and on a portion of the trench and a portion of the cover layer, wherein the first material film extends at least from the side of the bit line contact beyond the bottom surface of the bit line contact. as well as A bit line is located above the bit line contact and is electrically connected to the bit line contact; as well as An air gap is provided in the cover layer and adjacent to the side surface of the bit line contact, wherein the bottom of the air gap is lower than the bottom surface of the bit line contact.

12. The memory structure according to claim 11, characterized in that, The character line includes a first layer and a second layer located on the first layer, and the first layer and the second layer are made of different materials.

13. The memory structure according to claim 12, characterized in that, The first layer contains tungsten, and the second layer contains polycrystalline silicon.

14. The memory structure according to claim 11, characterized in that, The dielectric constant of the first material film is lower than that of the second material film.

15. The memory structure according to claim 14, characterized in that, The thickness of the first material film accounts for more than 20% of the thickness of the covering layer.

16. The memory structure according to claim 11, characterized in that, The air gap extends from the side of the isolation layer that contacts the bit line beyond the bottom surface that contacts the bit line.

Images